AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S256 AT91SAM7S128 AT91

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AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S256 AT91SAM7S128 AT91

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High-performance 32-bit RISC Architecture High-density 16-bit Instruction Leader MIPS/Watt Embedded*ICEIn-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash kbytes, organized 1024 Pages Bytes (AT91SAM7S256) kbytes, organized Pages Bytes (AT91SAM7S128) kbytes, organized Pages Bytes (AT91SAM7S64) kbytes, organized Pages Bytes (AT91SAM7S321/32) Single Cycle Access Worst Case Conditions Prefetch Buffer Optimizing Thumb Instruction Execution Maximum Speed Page Programming Time: Including Page Auto-erase, Full Erase Time: 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Fast Flash Programming Interface High Volume Production Internal High-speed SRAM, Single-cycle Access Maximum Speed kbytes (AT91SAM7S256) kbytes (AT91SAM7S128) kbytes (AT91SAM7S64) kbytes (AT91SAM7S321/32) Memory Controller (MC) Embedded Flash Controller, Abort Status Misalignment Detection Reset Controller (RSTC) Based Power-on Reset Low-power Factory-calibrated Brown-out Detector Provides External Reset Signal Shaping Reset Source Status Clock Generator (CKGR) Low-power Oscillator, On-chip Oscillator Power Management Controller (PMC) Software Power Optimization Capabilities, Including Slow Clock Mode (Down Idle Mode Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources (AT91SAM7S256/128/64/321) (AT91SAM7S32) External Interrupt Sources Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART Support Debug Communication Channel interrupt, Programmable Access Prevention Periodic Interval Timer (PIT) 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) 12-bit key-protected Programmable Counter Provides Reset Interrupt Signals System Counter Stopped While Processor Debug State Idle Mode Real-time Timer (RTT) 32-bit Free-running Counter with Alarm Runs Internal Oscillator
AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32
Summary
6175BS-ATARM-04-Nov-05
Parallel Input/Output Controller (PIOA)
Thirty-two (AT91SAM7S256/128/64/321) twenty-one (AT91SAM7S32) Programmable Lines Multiplexed with Peripheral I/Os Input Change Interrupt Capability Each Line Individually Programmable Open-drain, Pull-up resistor Synchronous Output Eleven (AT91SAM7S256/128/64/321) Nine (AT91SAM7S32) Peripheral Controller (PDC) Channels Full Speed Mbits Second) Device Port (Except AT91SAM7S32). On-chip Transceiver, 328-byte Configurable Integrated FIFOs Synchronous Serial Controller (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer (AT91SAM7S256/128/64/321) (AT91SAM7S32) Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation Support ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Manchester Encoder/Decoder (AT91SAM7S256/128) Full Modem Line Support USART1 (AT91SAM7S256/128/64/321) Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three (AT91SAM7S32)-channel 16-bit Timer/Counter (TC) Three (AT91SAM7S256/128/64/321) (AT91SAM7S32) External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Four-channel 16-bit Controller (PWMC) Two-wire Interface (TWI) Master Mode Support Only, Two-wire Atmel EEPROMs Supported 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BABoot Assistant Default Boot program Interface with SAM-BA Graphic User Interface IEEE 1149.1 JTAG Boundary Scan Digital Pins 5V-tolerant I/Os, including Four High-current Drive lines, Each Power Supplies Embedded 1.8V Regulator, Drawing Core External Components 3.3V 1.8V VDDIO Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply 1.8V VDDCORE Core Power Supply with Brown-out Detector Fully Static Operation: 1.65V Worst Case Conditions Available 64-lead LQFP Green Package (AT91SAM7S256/128/64/321) 48-lead LQFP Green Package (AT91SAM7S32)
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Description
Atmel's AT91SAM7S series pincount Flash microcontrollers based 32-bit RISC processor. features high-speed Flash SRAM, large peripherals, including device (except AT91SAM7S32), complete system functions minimizing number external components. device ideal migration path 8-bit microcontroller users looking additional performance extended memory. embedded Flash memory programmed in-system JTAG-ICE interface parallel interface production programmer prior mounting. Built-in lock bits security protect firmware from accidental overwrite preserves confidentiality. AT91SAM7S Series system controller includes reset controller capable managing power-on sequence microcontroller complete system. Correct device operation monitored built-in brownout detector watchdog running integrated oscillator. AT91SAM7S Series general-purpose microcontrollers. Their integrated Device port makes them ideal devices peripheral applications requiring connectivity cellular phone. Their aggressive price point high level integration pushes their scope into cost-sensitive, high-volume consumer market.
Configuration Summary AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 AT91SAM7S32
AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321 AT91SAM7S32 differ memory size, peripheral package. Table summarizes configuration five devices. Except AT91SAM7S32, other AT91SAM7S devices package pinout compatible.
Table 2-1.
Configuration Summary
Device Port present External Interrupt Source Channels Channels
Device AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 AT91SAM7S32 Notes:
Flash 256K byte 128K byte byte byte byte
SRAM byte byte byte byte byte
USART 2(1)
Lines
Package LQFP LQFP LQFP LQFP LQFP
Manchester Encoder/Decoder, Fractional Baud Rate. Full modem line support USART1.
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Block Diagram
Figure 3-1. AT91SAM7S256/128/64/321 Block Diagram
JTAGSEL
JTAG SCAN
ARM7TDMI Processor
Voltage Regulator
VDDIN VDDOUT VDDCORE
System Controller
IRQ0-IRQ1
Memory Controller Embedded Flash Controller Address Decoder Misalignment Detection
VDDIO
SRAM
64/32/16/8 Kbytes
PCK0-PCK2 PLLRC XOUT
RCOSC
Abort Status
VDDFLASH
Flash
256/128/64/32 Kbytes
ERASE
VDDCORE
Reset Controller
Peripheral Bridge
VDDCORE NRST
Peripheral Data Controller
Channels
Fast Flash Programming Interface
DRXD DTXD
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN
SAM-BA
FIFO
Transceiver
DBGU
Device
PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG ADVREF
PWMC
USART0
USART1
Timer Counter
PWM0 PWM1 PWM2 PWM3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWCK
AT91SAM7S Series Summary
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AT91SAM7S Series Summary
Figure 3-2. AT91SAM7S32 Block Diagram
JTAGSEL
JTAG SCAN
ARM7TDMI Processor
Voltage Regulator
VDDIN VDDOUT
System Controller
IRQ0
Memory Controller Embedded Flash Controller Abort Status Misalignment Detection Address Decoder
VDDCORE VDDIO
SRAM Kbytes
PCK0-PCK2 PLLRC XOUT
VDDFLASH
RCOSC
Flash Kbytes
Peripheral Bridge
ERASE
VDDCORE
Reset Controller
VDDCORE
NRST
Peripheral Controller
Channels
Fast Flash Programming Interface
PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD7 PGMNCMD PGMEN0-PGMEN2
DRXD DTXD
DBGU PIOA
SAM-BA
PWMC
RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG ADVREF
USART0 Timer Counter
PWM0 PWM1 PWM2 PWM3 TCLK0
TIOA0 TIOB0 TIOA1 TIOB1
TWCK
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Signal Description
Table 4-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL
Voltage Regulator Power Supply Input Voltage Regulator Output Flash Power Supply Lines Power Supply Core Power Supply Ground
Power Power Power Power Power Power Ground
3.6V 1.85V nominal 3.0V 3.6V 3.0V 3.6V 1.65V 1.95V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT PLLRC PCK0 PCK2 Main Oscillator Input Main Oscillator Output Filter Programmable Clock Output Input Output Input Output JTAG JTAGSEL Test Clock Test Data Test Data Test Mode Select JTAG Selection Flash Memory ERASE Flash Configuration Bits Erase Command Reset/Test NRST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data IRQ0 IRQ1 External Interrupt Inputs Fast Interrupt Input PA31 Parallel Controller Pulled-up input reset PA20 only AT91SAM7S32 Input Input IRQ1 present Input Output Input High Open-drain with pull-Up resistor Pull-down resistor Input High Pull-down resistor Input Input Output Input Input pull-up resistor Pull-down resistor pull-up resistor pull-up resistor
AT91SAM7S32
AT91SAM7S Series Summary
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AT91SAM7S Series Summary
Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type Device Port Active Level Comments
Device Port Data Device Port Data USART
Analog Analog
present AT91SAM7S32 present AT91SAM7S32
SCK0 SCK1 TXD0 TXD1 RXD0 RXD1 RTS0 RTS1 CTS0 CTS1 DCD1 DTR1 DSR1
Serial Clock Transmit Data Receive Data Request Send Clear Send Data Carrier Detect Data Terminal Ready Data Ready Ring Indicator
Input Output Input Input Output Input Input Synchronous Serial Controller
SCK1 present
AT91SAM7S32
TXD1 present
AT91SAM7S32
RXD1 present
AT91SAM7S32
RTS1 present
AT91SAM7S32
CTS1 present
AT91SAM7S32
present AT91SAM7S32 present AT91SAM7S32 present AT91SAM7S32 present AT91SAM7S32
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync
Output Input Timer/Counter
TCLK0 TCLK2 TIOA0 TIOA2 TIOB0 TIOB2
External Clock Inputs Line Line
Input Controller
TCLK1 TCLK2 present
AT91SAM7S32
TIOA2 present
AT91SAM7S32
TIOB2 present
AT91SAM7S32
PWM0 PWM3
Channels
Output
MISO MOSI SPCK NPCS0 NPCS1-NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select
Output
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Table 4-1.
Signal Name
Signal Description List (Continued)
Function Type Two-Wire Interface Active Level Comments
TWCK
Two-wire Serial Data Two-wire Serial Clock
Analog-to-Digital Converter
AD0-AD3 AD4-AD7 ADTRG ADVREF
Analog Inputs Analog Inputs Trigger Reference
Analog Analog Input Analog Fast Flash Programming Interface
Digital pulled-up inputs reset Analog Inputs
PGMEN0-PGMEN2 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD
Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command
Input Input Output Output Input Input Input High PGMD0-PGMD7 only AT91SAM7S32
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Package Pinout
AT91SAM7S256/128/64/321 available 64-lead LQFP package. AT91SAM7S32 available 48-lead LQFP package.
64-lead LQFP Mechanical Overview
Figure shows orientation 64-lead LQFP package. detailed mechanical description given section Mechanical Characteristics full datasheet. Figure 5-1. 64-lead LQFP Package Pinout (Top View)
64-lead LQFP Pinout
AT91SAM7S256/128/64/321 Pinout 64-lead LQFP Package
ADVREF VDDIN VDDOUT PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA21/PGMD9 VDDCORE PA19/PGMD7/AD2 PA22/PGMD10 PA23/PGMD11 PA20/PGMD8/AD3 VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 PA24/PGMD12 VDDCORE PA25/PGMD13 PA26/PGMD14 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA27/PGMD15 PA28 NRST PA29 PA30 PA2/PGMEN2 VDDIO PA1/PGMEN1 PA0/PGMEN0 JTAGSEL PA31 VDDCORE ERASE VDDIO VDDFLASH XOUT XIN/PGMCK PLLRC VDDPLL
Table 5-1.
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48-lead LQFP Mechanical Overview
Figure shows orientation 48-lead LQFP package. detailed mechanical description given section Mechanical Characteristics product datasheet. Figure 5-2. 48-lead LQFP Package Pinout (Top View)
48-lead LQFP Pinout
AT91SAM7S32 Pinout 48-lead LQFP Package
ADVREF VDDIN VDDOUT PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA19/PGMD7/AD2 PA20/AD3 VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 VDDCORE PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD NRST PA2/PGMEN2 VDDIO PA1/PGMEN1 PA0/PGMEN0 JTAGSEL VDDCORE ERASE VDDFLASH XOUT XIN/PGMCK PLLRC VDDPLL
Table 5-2.
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Power Considerations
Power Supplies
AT91SAM7S Series types power supply pins integrates voltage regulator, allowing device supplied with only voltage. power supply types are: VDDIN pin. powers voltage regulator ADC; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDOUT pin. output 1.8V voltage regulator. VDDIO pin. powers lines transceivers; dual voltage range supported. Ranges from 3.0V 3.6V, 3.3V nominal from 1.65V 1.95V, 1.8V nominal. Note that supplying less than 3.0V VDDIO prevents transceivers. VDDFLASH pin. powers part Flash required Flash operate correctly; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDCORE pins. They power logic device; voltage ranges from 1.65V 1.95V, 1.8V typical. connected VDDOUT with decoupling capacitor. VDDCORE required device, including embedded Flash, operate correctly. During startup, core supply voltage (VDDCORE) slope must superior equal 6V/ms. VDDPLL pin. powers oscillator PLL. connected directly VDDOUT pin. separate ground pins provided different power supplies. Only pins provided should connected shortly possible system ground plane. order decrease current consumption, voltage regulator used, VDDIN, ADVREF, AD4, AD5, should connected GND. this case VDDOUT should left unconnected.
Power Consumption
AT91SAM7S Series static current less than VDDCORE 25°C, including oscillator, voltage regulator power-on reset. When brown-out detector activated, static current added. dynamic power consumption VDDCORE less than full speed when running Flash. Under same conditions, power consumption VDDFLASH does exceed
Voltage Regulator
AT91SAM7S Series embeds voltage regulator that managed System Controller. Normal Mode, voltage regulator consumes less than static current draws output current. voltage regulator also Low-power Mode. this mode, consumes less than static current draws output current. Adequate output supply decoupling mandatory VDDOUT reduce ripple avoid oscillations. best achieve this capacitors parallel: external capacitor must connected between VDDOUT close chip
6175BS-ATARM-04-Nov-05
possible. external capacitor must connected between VDDOUT GND. Adequate input supply decoupling mandatory VDDIN order improve startup stability reduce source voltage drop. input decoupling capacitor should placed close chip. example, capacitors used parallel: X7R.
Typical Powering Schematics
AT91SAM7S Series supports 3.3V single supply mode. internal regulator connected 3.3V source output feeds VDDCORE VDDPLL. Figure shows power schematics used bus-powered systems. Figure 6-1. 3.3V System Single Power Supply Schematic
VDDFLASH Power Source ranges from 4.5V (USB)
DC/DC Converter
VDDIO
VDDIN 3.3V VDDOUT Voltage Regulator
VDDCORE
VDDPLL
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Lines Considerations
JTAG Port Pins
TMS, schmitt trigger inputs. tolerant, not. TMS, integrate pull-up resistor. output, driven VDDIO, pull-up resistor. JTAGSEL used select JTAG boundary scan when asserted high level. JTAGSEL integrates permanent pull-down resistor about GND, that left unconnected normal operations.
Test
used manufacturing test, fast programming mode SAM-BA Boot Recovery AT91SAM7S Series when asserted high. integrates permanent pull-down resistor about GND, that left unconnected normal operations. enter fast programming mode, pins should tied high tied low. enter SAM-BA Boot Recovery, PA0, pins should tied high. Driving high level while driven leads unpredictable results.
Reset
NRST bidirectional with open drain output buffer. handled on-chip reset controller driven provide reset signal external components asserted externally reset microcontroller. There constraint length reset pulse, reset controller guarantee minimum pulse length. This allows connection simple push-button NRST system user reset, signal NRST reset components system. NRST integrates permanent pull-up resistor VDDIO.
ERASE
ERASE used re-initialize Flash content some bits. integrates permanent pull-down resistor about GND, that left unconnected normal operations.
Controller Lines
lines PA31 (PA0 PA20 AT91SAM7S32) 5V-tolerant integrate programmable pull-up resistor. Programming this pull-up resistor performed independently each line through controllers. 5V-tolerant means that lines drive voltage level according VDDIO, driven with voltage 5.5V. However, driving line with voltage over VDDIO while programmable pull-up resistor enabled will create current path through pull-up resistor from line VDDIO. Care should taken, particular reset, lines default input with pull-up resistor enabled reset.
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Line Drive Levels
lines high-drive current capable. Each these lines drive permanently. remaining lines draw only However, total current drawn lines cannot exceed (100mA AT91SAM7S32).
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Processor Architecture
ARM7TDMI Processor
RISC processor based ARMv4T Neumann architecture Runs MHz, providing MIPS/MHz instruction sets ARM® high-performance 32-bit instruction Thumb® high code density 16-bit instruction Three-stage pipeline architecture Instruction Fetch Instruction Decode Execute
Debug Test Integrated Embedded (embedded in-circuit emulator) watchpoint units Test access port accessible through JTAG protocol Debug communication channel Debug Unit Two-pin UART Debug communication channel interrupt handling Chip Register IEEE1149.1 JTAG Boundary-scan digital pins
Memory Controller
Arbiter Handles requests from ARM7TDMI Peripheral Controller Address decoder provides selection signals Three internal Mbyte memory areas Mbyte embedded peripheral area Abort Status Registers Source, Type parameters access leading abort saved Facilitates debug detection pointers Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap Command Remaps SRAM place embedded non-volatile memory Allows handling dynamic exception vectors Embedded Flash Controller Embedded Flash interface, three programmable wait states
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Prefetch buffer, buffering anticipating 16-bit requests, reducing required wait states Key-protected program, erase lock/unlock sequencer Single command erasing, programming locking operations Interrupt generation case forbidden operation
Peripheral Controller
Handles data transfer between peripherals memories Eleven channels: AT91SAM7S256/128/64/321 Nine channels: AT91SAM7S32 each USART Debug Unit Serial Synchronous Controller Serial Peripheral Interface Analog-to-digital Converter arbitration overhead Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory Next Pointer management reducing interrupt latency requirements
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Memory
AT91SAM7S256
Kbytes Flash Memory single plane 1024 pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, protecting sectors pages Protection Mode secure contents Flash Single-cycle access full speed
Kbytes Fast SRAM
AT91SAM7S128
Kbytes Flash Memory single plane pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, protecting sectors pages Protection Mode secure contents Flash Single-cycle access full speed
Kbytes Fast SRAM
AT91SAM7S64
Kbytes Flash Memory single plane pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, protecting sectors pages Protection Mode secure contents Flash Single-cycle access full speed
Kbytes Fast SRAM
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AT91SAM7S321/32
Kbytes Flash Memory single plane pages bytes Fast access time, single-cycle access Worst Case conditions Page programming time: including page auto-erase Page programming without auto-erase: Full chip erase time: 10,000 write cycles, 10-year data retention capability lock bits, protecting sectors pages Protection Mode secure contents Flash Single-cycle access full speed
Kbytes Fast SRAM
9.5.1
Memory Mapping
Internal SRAM AT91SAM7S256/128/64/321/32 embeds high-speed 64/32/16/8/8-Kbyte SRAM bank. After reset until Remap Command performed, SRAM only accessible address 0x0020 0000. After Remap, SRAM also becomes available address 0x0.
9.5.2
Internal AT91SAM7S Series embeds Internal ROM. contains FFPI SAM-BA program. internal mapped default.
9.5.3
Internal Flash AT91SAM7S256/128/64/321/32 features bank 256/128/64/32/32 Kbytes Flash. time, Flash mapped address 0x0010 0000. also accessible address after reset before Remap Command. Figure 9-1. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Flash Before Remap SRAM After Remap Internal Flash
Bytes
0x0010 0000 Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
Bytes
Undefined Areas (Abort)
Bytes
0x0FFF FFFF
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
9.6.1
Embedded Flash
Flash Overview Flash AT91SAM7S256 organized 1024 pages bytes. 262,144 bytes organized 32-bit words. Flash AT91SAM7S128 organized pages bytes. 131,072 bytes organized 32-bit words. Flash AT91SAM7S64 organized pages bytes. 65,536 bytes organized 32-bit words. Flash AT91SAM7S321/32 organized pages bytes. 32,768 bytes organized 32-bit words. Flash AT91SAM7S256/128 contains 256-byte write buffer, accessible through 32-bit interface. Flash AT91SAM7S64/321/32 contains 128-byte write buffer, accessible through 32-bit interface. Flash benefits from integration power reset cell from brownout detector. This prevents code corruption during power supply changes, even worst conditions. When Flash used (read write access), automatically placed into standby mode.
9.6.2
Embedded Flash Controller Embedded Flash Controller (EFC) manages accesses performed masters system. enables reading Flash writing write buffer. also contains User Interface, mapped within Memory Controller APB. User Interface allows: programming access parameters Flash (number wait states, timings, etc.) starting commands such full erase, page erase, page program, set, clear, etc. getting status last command getting error status programming interrupts last commands errors Embedded Flash Controller also provides dual 32-bit Prefetch Buffer that optimizes 16-bit access Flash. This particularly efficient when processor running Thumb mode.
9.6.3
Lock Regions Embedded Flash Controller manages 16/8 lock bits protect 16/8 regions flash against inadvertent flash erasing programming commands. Table summarizes configuration five devices.
Table 9-1.
Device
Flash Configuration Summary
Number Lock Bits Number Pages Lock Region Page Size bytes bytes bytes bytes
AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321/32
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locked-regions erase program command occurs, command aborted trigs interrupt. bits software programmable through User Interface. command "Set Lock Bit" enables protection. command "Clear Lock Bit" unlocks lock region. Asserting ERASE clears lock bits, thus unlocking entire Flash. 9.6.4 Security Feature AT91SAM7S Series features security bit, based specific NVM-Bit. When security enabled, access Flash, either through interface through Fast Flash Programming Interface, forbidden. This ensures confidentiality code programmed Flash. This security only enabled, through Command "Set Security Bit" User Interface. Disabling security only achieved asserting ERASE after full flash erase performed. When security deactivated, accesses flash permitted. important note that assertion ERASE should always longer than ERASE integrates permanent pull-down, left unconnected during normal operation. However, safer connect directly final application. 9.6.5 Non-volatile Brownout Detector Control general purpose (GPNVM) bits used controlling brownout detector (BOD), that even after power loss, brownout detector operations remain their state. These GPNVM bits cleared respectively through commands "Clear General-purpose Bit" "Set General-purpose Bit" User Interface. GPNVM used brownout detector enable bit. Setting GPNVM enables BOD, clearing disables BOD. Asserting ERASE clears GPNVM thus disables brownout detector default. GPNVM used brownout reset enable signal reset controller. Setting GPNVM enables brownout reset when brownout detected, Clearing GPNVM disables brownout reset. Asserting ERASE disables brownout reset default. 9.6.6 Calibration Bits Eight bits used calibrate brownout detector voltage regulator. These bits factory configured cannot changed user. ERASE effect calibration bits.
Fast Flash Programming Interface
Fast Flash Programming Interface allows programming device through either serial JTAG interface through multiplexed fully-handshaked parallel port. allows gang-programming with market-standard industrial programmers. FFPI supports read, page program, page erase, full erase, lock, unlock protect commands. Fast Flash Programming Interface enabled Fast Programming Mode entered when pins tied high tied low.
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
SAM-BA Boot Assistant
SAM-BABoot Recovery restores SAM-BA Boot first sectors on-chip Flash memory. SAM-BA Boot recovery performed when PA0, pins tied high. SAM-BA Boot Assistant default Boot Program that provides easy program situ on-chip Flash memory. SAM-BA Boot Assistant supports serial communication through DBGU through Device Port. (The AT91SAM7S32 Device Port.) Communication through DBGU supports wide range crystals from software auto-detection. Communication through Device Port limited 18.432 crystal. SAM-BA Boot provides interface with SAM-BA Graphic User Interface (GUI).
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System Controller
System Controller manages vital blocks microcontroller: interrupts, clocks, power, time, debug reset. Figure 10-1. System Controller Block Diagram (AT91SAM7S256/128/64/321)
System Controller
jtag_nreset
Boundary Scan Controller
irq0-irq1 periph_irq[2.14]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq
ice_nreset force_ntrst
periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis ice_nreset jtag_nreset
Debug Unit
dbgu_irq force_ntrst dbgu_txd security_bit
Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC bod_rst_en
pit_irq
flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.1]
Embedded Flash
proc_nreset
Reset Controller
periph_nreset proc_nreset
Memory Controller
flash_poe rstc_irq SLCK
NRST
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.14] pck[0-2]
UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend
XOUT
MAINCK
Power Management Controller
UDPCK
Device Port
PLLRC
PLLCK pmc_irq idle periph_clk[4.14] periph_nreset
periph_nreset usb_suspend
periph_nreset periph_clk[2] dbgu_rxd
periph_irq{2] irq0-irq1
Embedded Peripherals
periph_irq[4.14]
Controller
dbgu_txd
PA0-PA31 enable
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Figure 10-2. System Controller Block Diagram (AT91SAM7S32)
System Controller
jtag_nreset
Boundary Scan Controller
irq0 periph_irq[2.14]
nirq
Advanced Interrupt Controller
nfiq proc_nreset debug
ARM7TDMI
pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq
ice_nreset force_ntrst dbgu_irq
periph_nreset dbgu_rxd debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset gpnvm[0] gpnvm[1] flash_wrdis ice_nreset jtag_nreset
Debug Unit Periodic Interval Timer Real-Time Timer Watchdog Timer
wdt_fault WDRPROC bod_rst_en
force_ntrst dbgu_txd security_bit pit_irq
flash_poe rtt_irq flash_wrdis wdt_irq gpnvm[0.1]
Embedded Flash
proc_nreset
Reset Controller
periph_nreset proc_nreset
Memory Controller
flash_poe rstc_irq SLCK
NRST
Voltage Regulator Mode Controller
standby
Voltage Regulator
RCOSC
SLCK
periph_clk[2.14] pck[0-2]
XOUT
MAINCK
Power Management Controller
PLLRC
PLLCK pmc_irq idle periph_clk[4.14] periph_nreset
periph_nreset
periph_nreset periph_clk[2] dbgu_rxd
periph_irq{2] irq0
Embedded Peripherals
periph_irq[4.14]
Controller
dbgu_txd
PA0-PA20 enable
6175BS-ATARM-04-Nov-05
10.1
System Controller Mapping
System Controller peripherals mapped highest Kbytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Figure 10-3 shows mapping System Controller. Note that Memory Controller configuration user interface also mapped within this address space. Figure 10-3. System Controller Mapping
Address
0xFFFF F000
Peripheral
Peripheral Name
Size
0xFFFF F1FF 0xFFFF F200
Advanced Interrupt Controller
Bytes/128 registers
DBGU
0xFFFF F3FF 0xFFFF F400
Debug Unit
Bytes/128 registers
PIOA
0xFFFF F5FF 0xFFFF F600
Controller
Bytes/128 registers
Reserved
0xFFFF FBFF 0xFFFF FC00
0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00
Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller
Bytes/64 registers Bytes/4 registers Bytes/4 registers Bytes/4 registers Bytes/4 registers Bytes/1 register
RSTC Reserved Reserved VREG Reserved
0xFFFF FFFF
Memory Controller
Bytes/64 registers
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
10.2 Reset Controller
Reset Controller based power-on reset cell brownout detector. gives status last reset, indicating whether power-up reset, software reset, user reset, watchdog reset brownout reset. addition, controls internal resets NRST open-drain output. allows shape signal NRST line, guaranteeing that length pulse meets requirement. Note that NRST used reset output signal external devices during power-off, brownout detector must activated. 10.2.1 Brownout Detector Power-on Reset AT91SAM7S Series embeds brownout detection circuit power-on reset cell. Both supplied with monitor VDDCORE. Both signals provided Flash prevent code corruption during power-up power-down sequences brownouts occur VDDCORE power supply. power-on reset cell limited-accuracy threshold around 1.5V. output remains during power-up until VDDCORE goes over this voltage level. This signal goes reset controller allows full re-initialization device. brownout detector monitors VDDCORE level during operation comparing fixed trigger level. secures system operations most difficult environments prevents code corruption case brownout VDDCORE. Only VDDCORE monitored, voltage drop VDDFLASH other power supply device cannot affect Flash. When brownout detector enabled VDDCORE decreases value below trigger level (Vbot-, defined Vbot hyst/2), brownout output immediately activated. When VDDCORE increases above trigger level (Vbot+, defined Vbot hyst/2), reset released. brownout detector only detects drop voltage VDDCORE stays below threshold voltage longer than about 1µs. threshold voltage hysteresis about ensure spike free brownout detection. typical value brownout detector threshold 1.68V with accuracy factory calibrated. brownout detector low-power, consumes less than static current. However, deactivated save static current. this case, consumes less than 1µA. deactivation configured through GPNVM Flash.
6175BS-ATARM-04-Nov-05
10.3
Clock Generator
Clock Generator embeds low-power Oscillator, Main Oscillator with following characteristics: Oscillator ranges between Main Oscillator frequency ranges between Main Oscillator bypassed output ranges between provides SLCK, MAINCK PLLCK. Figure 10-4. Clock Generator Block Diagram
Clock Generator
Embedded Oscillator
Slow Clock SLCK
XOUT
Main Oscillator
Main Clock MAINCK
PLLRC
Divider
Clock PLLCK
Status
Control
Power Management Controller
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
10.4 Power Management Controller
Power Management Controller uses Clock Generator outputs provide: Processor Clock Master Clock Clock UDPCK (not present AT91SAM7S32) peripheral clocks, independently controllable three programmable clock outputs Master Clock (MCK) programmable from hundred maximum operating frequency device. Processor Clock (PCK) switches when entering processor idle mode, thus allowing reduced power consumption while waiting interrupt. Figure 10-5. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64 Peripherals Clock Controller ON/OFF Idle Mode
periph_clk[2.14]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,.,/64
pck[0.2]
Clock Controller ON/OFF PLLCK Divider /1,/2,/4
usb_suspend
UDPCK
10.5
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) Processor Individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control peripheral interrupts external interrupts Programmable edge-triggered level-sensitive internal sources Programmable positive/negative edge-triggered high/low level-sensitive external sources 8-level Priority Controller Drives normal interrupt processor Handles priority interrupt sources
6175BS-ATARM-04-Nov-05
Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes interrupt service routine branch execution 32-bit vector register interrupt source Interrupt vector register reads corresponding current interrupt vector Protect Mode Easy debugging preventing automatic operations Fast Forcing Permits redirecting interrupt source fast interrupt General Interrupt Mask Provides processor synchronization events without triggering interrupt
10.6
Debug Unit
Comprises: two-pin UART Interface Debug Communication Channel (DCC) support Chip Registers Interface providing Access Prevention Two-pin UART Implemented features compatible with USART Programmable Baud Rate Generator Parity, Framing Overrun Error Automatic Echo, Local Loopback Remote Loopback Channel Modes Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Chip Registers Identification device revision, sizes embedded memories, peripherals Chip 0x270B0940 AT91SAM7S256 (VERSION Chip 0x270A0740 AT91SAM7S128 (VERSION Chip 0x27090540 AT91SAM7S64 (VERSION Chip 0x27080342 AT91SAM7S321 (VERSION Chip 0x27080340 AT91SAM7S32 (VERSION
10.7
Periodic Interval Timer
20-bit programmable counter plus 12-bit interval counter
10.8
Watchdog Timer
12-bit key-protected Programmable Counter running prescaled SCLK Provides reset interrupt signals system Counter stopped while processor debug state idle mode
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
10.9 Real-time Timer
32-bit free-running counter with alarm running prescaled SCLK Programmable 16-bit prescaler SLCK accuracy compensation
10.10 Controller
Controller, controlling lines AT91SAM7S32) Fully programmable through set/clear registers Multiplexing peripheral functions line each line (whether assigned peripheral used general-purpose I/O) Input change interrupt Half clock period glitch filter Multi-drive option enables driving open drain Programmable pull-up each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
10.11 Voltage Regulator Controller
this controller select Power Mode Voltage Regulator between Normal Mode (bit cleared) Standby Mode (bit set).
6175BS-ATARM-04-Nov-05
Peripherals
11.1 Peripheral Mapping
Each peripheral allocated Kbytes address space. Figure 11-1. User Peripheral Mapping (AT91SAM7S256/128/64/321)
Peripheral Name
0xF000 0000
Size
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF 0xFFFA 4000
TC0, TC1,
Timer/Counter
Kbytes
Reserved
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
Device Port
Kbytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
Two-Wire Interface
Kbytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter
Kbytes
0xFFFC 4000
0xFFFC 7FFF 0xFFFC 8000
USART1
Kbytes
Reserved
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF 0xFFFD 0000
Controller
Kbytes
Reserved
0xFFFD 3FFF
0xFFFD 4000
0xFFFD 7FFF
Serial Synchronous Controller
Kbytes
0xFFFD 8000
0xFFFD BFFF 0xFFFD C000
Analog-to-Digital Converter
Kbytes
Reserved
0xFFFD FFFF
0xFFFE 0000
0xFFFE 3FFF 0xFFFE 4000
Serial Peripheral Interface
Kbytes
Reserved
0xFFFE FFFF
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Figure 11-2. User Peripheral Mapping (AT91SAM7S32)
Peripheral Name
0xF000 0000
Size
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF 0xFFFA 4000
TC0, TC1,
Timer/Counter
Kbytes
Reserved
0xFFFA FFFF
0xFFFB 0000 Reserved
0xFFFB 3FFF 0xFFFB 4000
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
Two-Wire Interface
Kbytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter
Kbytes
0xFFFC 4000 Reserved
0xFFFC 7FFF 0xFFFC 8000
Reserved
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF 0xFFFD 0000
Controller
Kbytes
Reserved
0xFFFD 3FFF
0xFFFD 4000
0xFFFD 7FFF
Serial Synchronous Controller
Kbytes
0xFFFD 8000
0xFFFD BFFF 0xFFFD C000
Analog-to-Digital Converter
Kbytes
Reserved
0xFFFD FFFF
0xFFFE 0000
0xFFFE 3FFF 0xFFFE 4000
Serial Peripheral Interface
Kbytes
Reserved
0xFFFE FFFF
6175BS-ATARM-04-Nov-05
11.2
Peripheral Multiplexing Lines
AT91SAM7S Series features controller, PIOA, that multiplexes lines peripheral set. Controller controls lines lines AT91SAM7S32). Each line assigned peripheral functions, Some them also multiplexed with analog inputs Controller. Table 11-1 page defines lines peripherals analog inputs multiplexed Controller columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. Note that some peripheral functions that output only duplicated table. pins reset their Parallel lines function configured input with programmable pull-up enabled, that device maintained static state soon reset detected.
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
11.3 Controller Multiplexing
Multiplexing Controller (AT91SAM7S256/128/64/321)
Controller Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral PWM0 PWM1 PWM2 TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DTR1 DSR1 IRQ1 NPCS1 Peripheral TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 IRQ0 PCK1 NPCS3 PWM0 PWM1 PWM2 TIOA2 TIOB2 TCLK1 TCLK2 NPCS2 PCK2 Comments High-Drive High-Drive High-Drive High-Drive Application Usage Function Comments
Table 11-1.
6175BS-ATARM-04-Nov-05
Table 11-2.
Multiplexing Controller (SAM7S32)
Controller Application Usage Comments High-Drive High-Drive High-Drive High-Drive Function Comments
Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20
Peripheral PWM0 PWM1 PWM2 TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK
Peripheral TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 IRQ0
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
11.4 Peripheral Identifiers
AT91SAM7S Series embeds wide range peripherals. Table 11-3 defines Peripheral Identifiers AT91SAM7S256/128/64/321. Table 11-4 defines Peripheral Identifiers AT91SAM7S32. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller.
Table 11-3.
Peripheral
Peripheral Identifiers (AT91SAM7S256/128/64/321)
Peripheral Mnemonic SYSIRQ PIOA Reserved ADC(1) PWMC Reserved Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 Analog-to Digital Converter Serial Peripheral Interface USART USART Synchronous Serial Controller Two-wire Interface Controller Device Port Timer/Counter Timer/Counter Timer/Counter
Peripheral Name Advanced Interrupt Controller System Interrupt Parallel Controller
External Interrupt
Note:
Setting SYSIRQ bits clock set/clear registers effect. System Controller continuously clocked. clock automatically started first conversion. Sleep Mode clock automatically stopped after each conversion.
6175BS-ATARM-04-Nov-05
Table 11-4.
Peripheral
Peripheral Identifiers (AT91SAM7S32)
Peripheral Mnemonic SYSIRQ PIOA Reserved ADC(1) Reserved PWMC Reserved Reserved Reserved Advanced Interrupt Controller IRQ0 Timer/Counter Timer/Counter Timer/Counter Synchronous Serial Controller Two-wire Interface Controller Analog-to Digital Converter Serial Peripheral Interface USART
Peripheral Name Advanced Interrupt Controller System Interrupt Parallel Controller
External Interrupt
Note:
Setting SYSIRQ bits clock set/clear registers effect. System Controller continuously clocked. clock automatically started first conversion. Sleep Mode clock automatically stopped after each conversion.
11.5
Serial Peripheral Interface
Supports communication with external serial devices Four chip selects with external decoder allow communication with peripherals Serial memories, such DataFlash® 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency Master Clock
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
11.6 Two-wire Interface
Master Mode only Compatibility with standard two-wire serial memories One, three bytes slave address Sequential read/write operations
11.7
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection first Optional break generation detection over-sampling receiver frequency Hardware handshaking Modem Signals Management DTR-DSR-DCD-RI USART1 (not present AT91SAM7S32) Receiver time-out transmitter timeguard Multi-drop Mode with address generation detection Manchester Encoder/Decoder AT91SAM7S256/128 RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo
11.8
Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
11.9
Timer Counter
Three 16-bit Timer Counter Channels
6175BS-ATARM-04-Nov-05
Three output compare input capture Wide range functions including: Frequency measurement Event counting Interval measurement Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs, defined Table 11-5 Table 11-5. Timer Counter Clocks Assignment
Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
multi-purpose input/output signals global registers that three channels
11.10 Controller
Four channels, 16-bit counter channel Common clock generator, providing thirteen different clocks Modulo counter providing eleven clocks independent linear dividers working modulo counter outputs Independent channel programming Independent enable/disable commands Independent clock selection Independent period duty cycle, with double bufferization Programmable selection output waveform polarity Programmable center left aligned output waveform
11.11 Device Port (Only AT91SAM7S256/128/64/321)
V2.0 full-speed compliant,12 Mbits second. Embedded V2.0 full-speed transceiver Embedded 328-byte dual-port endpoints Four endpoints
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Endpoint bytes Endpoint bytes ping-pong Endpoint bytes Ping-pong Mode (two memory banks) bulk endpoints Suspend/resume logic
11.12 Analog-to-digital Converter
8-channel 10-bit Ksamples/sec. Successive Approximation Register -3/+3 Integral Linearity, -2/+2 Differential Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference better accuracy voltage inputs Individual enable disable each channel Multiple trigger source Hardware software trigger External trigger Timer Counter outputs TIOA0 TIOA2 trigger Sleep Mode conversion sequencer Automatic wakeup trigger back sleep mode after conversions enabled channels Four eight analog inputs shared with digital signals
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Ordering Information
Table 12-1. Ordering Information
Package LQFP LQFP LQFP LQFP LQFP Package Type Green Green Green Green Green Code Revision Temperature Operating Range Industrial (-40° Industrial (-40° Industrial (-40° Industrial (-40° Industrial (-40°
Ordering Code AT91SAM7S256-AU-001 AT91SAM7S128-AU-001 AT91SAM7S64-AU-001 AT91SAM7S321-AU-001 AT91SAM7S32-AU-001
AT91SAM7S Series Summary
6175BS-ATARM-04-Nov-05
AT91SAM7S Series Summary
Revision History
Table 12-2. Revision History
Change Request Ref.
Doc. 6175AS 6175BS
Comments First issue Unqualified Intranet Corresponds 6175A full datasheet approval loop. Qualified Intranet. Section "Memory", page updated:
CSR05-529
6175BS-ATARM-04-Nov-05
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6175BS-ATARM-04-Nov-05

AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S256 AT91SAM7S128 AT91

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