Pierre Guillemin Alan Dunworth INTRODUCTION family offers micropr

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INITIALIZATION
Pierre Guillemin Alan Dunworth
INTRODUCTION family offers microprocessor designer wide variety architectural features configurable user's specific application requirements. Central these configurations multiple register based microcomputer core which added on-chip, powerful peripheral components including Convertors, Serial Communication Interface units (SCI's), 16-bit Multifunction timers with input capture/output compare capabilities. availability, on-chip, these application-specific units obviates need external interface design well offeringhigh-speed good reliability. particular peripherals incorporated on-chip themselves individually configured offer wide variety functional (architectural) alternatives. This configuration typically implemented simple software routines included power-on- system- reset routines. sole difficulty which user initially encounter stems, fact, from power versatility this approach system design. large number available options means that user must specify large number system parameters initializing control register contents specific peripheral units. objective this Application Note suggest user programming structure andphilosophy initial configuration system. approach illustrated number specific examples selected from wide range available ST9030, ST9040 families, applicable ST9s. System Reset After processor Reset control status registers, located group pages (0-63) forced preset values which define default Reset configuration system. example internal clock frequency (INTCLK) internal crystal oscillator externally applied clock frequency, supplied) divided without prescaling, individual pins Parallel Ports 0,1, bidirectional Pullup mode (for systems with on-chip ROM). releasing external RESET signal processor loaded with contents Reset Vector stored address locations This causes jump Reset routine which designer reconfigure system appropriate requirements particular application, loading suitable values into system registers. number registers initialized considerable representative system. Additionally, application-specific interrupt routines will, general, involve anipulation substantial system resources, e.g. read/write data registers, test/reset status, mask, control registers. associated programming task appear daunting prospect firstacquaintancewith system. Conceptually, organization associated software relatively simple straightforward recognized grouping under four headings programming steps involved initialization peripherals organization interrupt service routines.
AN413 1292
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Core System Configuration Certain core system resources common on-chip peripherals specified common routine which invoked System Reset. Such common resources include clock configuration, system user stack specification, global interrupt masking, processor priority setting, parallel port bit-by-bit specification, setting external memory wait-cycles. setting interrupt vector table, certain global masking enabling operations, also included under this heading. Individual On-chip Peripheral Configuration configuration on-chip peripherals, e.g. Multifunction Timers, Converters, etc., involves loading suitable bit-patterns into group page registers. This enables specification input output signals, determination peripheral's mode operation, selection internal external clock control signals. Individual On-chip Peripheral Initialization initialization particular on-chip peripheral involve setting clearing device-specific enable masking bits, specification interrupt priority levels, clearing status/flag values, loading data and/or limit registers. Organization Interrupt Service Routines This will normally include context-saving restoring system status, plus working-register page-pointer registers, together with values working registers used routine. routine proper include testingof status flag bits, reading writing data registers associated with particular device. Finally, interrupt pending bits should cleared, context restored, individual masking enabling bits restored appropriate values. practical programming terms there will normally single routine invoked system RESET which carries core system configurations listed under heading above. each individual peripheral there will typically single routine which carries configuration andinitialization operations listed under headingsb) There will also more interrupt routines associated with each peripheral, e.g. converter require general interrupt routines, Conversion, range operation (i.e. Analog Watchdog operation) channels example core-system configuration given Appendix Appendices C,D,E, give configuration/initialization examples, Interrupt routines Timer, Convertor, unit, Timer/Watchdog respectively. There space short note discuss these programmes detail line line basis. Instead approach will list, each device, resources which need taken into consideration when configuring, initializing, servicing particular device. example will then given specific each such resource. With this background, interested user should able follow detail those listings most relevant particular application area.
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BASIC SYSTEM CONFIGURATION Tables Appendix lists registers which should loaded with specified bit-patterns order initialize basic system configuration. demonstration routine which carries this representative system listed Appendix main routine, RESET_START, invoked system Reset. Also shown Appendix Assembler Declarations directives which enable Interrupt Vector Address Table program memory. Vector Address Table implements interrupt vectoring structure that allows on-chip peripheral identify location first instruction Interrupt Service Routine (ISR). Each interrupt module specific Interrupt Vector Register (IVR) mapped register file pages. When interrupt request acknowledged, peripheral interrupt module provides, IVR, vector point address Interrupt Service Routine Vector Table. Interrupt Vector table containing list addresses Interrupt Service Routine must located first locations program memory. first locations Program memory reserved follows:
Address Content Address high Power Reset routine Address Power Reset routine Address high Divide Zero Trap Subroutine Address Divide Zero Trap Subroutine Address high Level Address Level
Note that since above locations fixed hardware associated register involved. certain interrupt modules more than interrupt routine required. example Convertor separate interrupts Conversion Channel analog underflow/overflowconditions. such cases register specifies more significant, interrupt module hardware specifies less significant bits Vector Table address. following Assembler outline shows corresponding Vector table entries established. ADC_IT_VECT:= .org ADC_IT_VECT .word ADC_WDG .word ADC_EOC ADC_WDG: Code Analog Watchdog Routine included here Note that example Appendix System Reset routine invoked range conditions Channels iret ADC_EOC: conversion interrupt routine included here iret
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PORT INITIALIZATION maximum lines dedicated input/output. These lines, grouped into eight 8-bit ports, independently programmed provide parallel input/outputs with without handshake used connect in/out signals to/from peripherals (e.g. Core, Timers, units, etc.) present chip. functional allocation Ports support system tasks summarised follows:
Port Functions
Usable Port (without handshake) multiplexed low-address data lines external memory. Usable Port (without handshake)or high-address lines external memory. Usable Port (without handshake)or functions; Also INT1, INT2, INT3 inputs. Usable Port (without handshake)or Timer functions. Usable Port (with without handshake) Usable Port (with without handshake). Usable Port (without handshake) Usable Port (without handshake) functions. Also used INT4, INT5, INT6 inputs Control signals slow external memory
Ports automatically initialized system Reset correspond installed on-chip memory. Ports need initialized available) satisfy specific application requirements external I/O, plus alternative function assignments port pins, internal interconnections. Table A.3, Appendix lists complete Port Configuration registers together with their addresses. Example: P3C_PG P3C0R,#00000101b P3C1R,#00001111b P3C2R,#00000101b
this example Port pins configured bidirectional pins, with weak pull-up output inputs. Pins (T0INA) (T0INB) configured inputs, Pins (T0OUTA) (T0OUTB) configured Alternate Function Push-pull outputs.
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MULTIFUNCTION TIMER CONFIGURATION Multifunction Timer configured loading suitable control-bit patterns groupe page register TCR, TMR, ICR, OACR, OBCR (see Table Appendix Note that registers EIMR CICR provide global control functions common on-chip peripherals hence initialized conveniently basic system configuration routine. External Input Control Register, ICR, controls input source selection (internal/external), input mode selection (falling/rising edge sensitive, etc.), counter mode operation (continuous, one-shot, etc.), input function (Gate, Trigger, up/down control, etc.). Example: T_ICR,#01010100b This instruction selects external input falling-edge-sensitive Trigger input, input normal Port pin. Multifunction Timer Control Register, TCR, controls counter clear prescaler reload operations well providing counter enable control counter status flags. Example: T_TCR,#01001000b This instruction halts counter operation provides subsequent counting with counter clear Prescaler reload Reg0 Reg1 capture. Multifunction Timer Mode Register, TMR, selects clock source counter-prescaler input, enables Retrigger Continuous mode, controls register load/capture operations. Example: T_TMR,#10001100b This pattern enables output disables output disables bivalue modes, selects Reg0 capture Reg1 monitor. Retriggerable continuous mode selected. Output Control Register, OACR, links output T0OUTA counter overflow/underflow Compare events, provides subsequent Set, Reset, Toggle external output. on-chip event (OCE) linked COMP0 event. Example: T_OACR,#00011011b this example T0OUTA preset issubsequently COMP0, toggled COMP1, Reset OVF. signal generated successful CMP0 compare event. Output Control Register, OBCR, links output T0OUTB counter overflow/underflow Compare events, provides subsequent Set, Reset, Toggle external output. on-chip event (OCE) linked counter overflow/underflow event. Example: T_OBCR,#10000011b this example T0OUTB preset subsequentlyreset COMP0, COMP1. signal generated counter overflow/underflow event.
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MULTIFUNCTION TIMER INITIALIZATION Initialization Multifunction Timer requires loading Prescaler register Comparison registers. timer Status register should cleared, Vector Table entry should set, Multifunction Timer counter actions enabled. interrupt/DMA priority levels should mask bits should adjusted appropriate application. Further, operations specified, address counter registers will require initialization. Prescaler Register, PRSR, holds preset value 8-bit prescaler. Example: T_PRSR,#00h This defines division ratio maximum counter clock generated (INTCLK/3). Multifunction Timer Flags Register, FLAGR, contains flags which register successful capture comparison events together with OVF/UNF overrun conditions. Example: T_FLAGR,#~ocm0 This example resets overrun COMP0 operations. Interrupt Vector Register, IVR, should loaded with most significant bits Multifunction Timer's interrupt vector address program memory. interrupt source (compare, capture, OVF/UNF) provides least significant bits provide correct vector link. Example: T0_IVR,#T0_IT_VECT this example loaded with start address (10h) block words vector table allocated different Multifunction Timer interrupts.
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MULTIFUNCTION TIMER INITIALIZATION (Continued) Interrupt/DMA Control Register, IDCR, used Interrupt priority levels, transfer source destination. also enables Swap mode contains Block condition flags. Example: T0_IDCR,#11000110b this example priority level value Swap mode disabled. capture channel source REG0, compare channel source CMP0. Interrupt/DMA Mask Register, IDMR, contains global Multifunction Timer Interrupt enable plus individual DMAand Interrupt enable bits overflow well successful capture comparison events. Example: T_IDMR,#00000100b T_IDMR,#gtien
first instruction sets interrupt enable CMP0, second instruction globally enables Multifunction Timer interrupts. Counter Pointer Register, DCPR, defines area source, specifies location length register. Example: T0_DCPR,#CPT_LG_DMA length register rr12 RR76 transfer occurs to/from Program/Data memory. Address Pointer Register, DAPR, defines area source, specifies location address register. Example: T0_DAPR,#CPT_AD_DMA address register RR72. conjunction with DPCR value above example specifies Program memory buffer.
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CONVERTOR CONFIGURATION/INITIALIZATION Configuration convertor requires loading registers only, CLR, CRR, ICR, (Table A.6), initialization this device involves, apart from global masking, loading double reshold registers). Hence single routine written cover both configuration initialization aspects Convertor use. Control Logic Register, CLR, defines Analog channel conversion start address, selects internal/external triggers, enables continuous single conversion power up/down modes. This register also contains start/stop status/control bit. Example: AD_CLR,#00000100b this example, conversion scan starts with channel when enabled, powers convertor, halts conversion, specifies single conversion scan mode. Please note that before enabling conversion, mandatory Control Logic Register least 60µs before first conversion start. This order correctly bias analog section converter. Interrupt Vector Register, IVR, defines most significant bits vector table byte address. thus points first word addresses which correspond analog watchdog conversion interrupt routines. Example: AD_IVR,#ADC_ITEOC_VECT this example, address (decimal) loaded into IVR. Hence subsequent convertor interrupt will cause Vector Table access location Interrupt Control Register, ICR, contains priority level specification, source interrupt flags (Analog Watchdog EOC) their individual masking bits. Example: AD_ICR,#00100000b AD_ICR,#00000110b
this example, priority level first Conversion interrupts enabled, theAnalog Watchdog interrupt masked. second instruction then sets priority level Analog Watchdog enabled (bit ICR) will necessary load threshold registers channels this case access will made interrupt routine register CRR. Compare Result Register, CRR, contains flags showing results comparison operations between current values data registers upper lower threshold registers.
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UNIT CONFIGURATION list registers initialized when configuring unit given Table A.9. functions these registers, some illustrative examples their use, follows: Character Configuration Register, CHCR, used define serial frame format. Example: S_CHCR,#E3h This example defines serial frame follows: data bits, stop bit, even parity, address input character matches contents Address Register. Clock Configuration Register, CLCR, used specify transmitter, receiver, Baud Rate clock sources, clock divisor ratio. also enables Auto Echo Loopback test modes. Example: s_clcr,#txclk this example, Transmitter Receiver clocks provided Baud Rate Generator. Each data period will clock periods (asynchronous mode), Auto Loop Loopback modes disabled. Baud Rate Generator Register, BRGR, specifies 16-bit division ratio. Example: s_brgr,#DIV_9600 This example specifies division ratio yielding 9600 Bauds with external clock. Writing Baud Rate Generator Register immediately disables resets both Baud Rate generator, transmitter receiver circuitry. After writing remaining Baud Rate Generator Register, transmitter receiver circuits enabled. Baud Rate Generator will load value start counting. initialize SCI, user should first initialize Baud Rate Generator Divisor Register. This will reset circuitry. Initialize other registers desired operating mode. enable SCI, initialize remaining Baud Rate Generator Register. Address Compare Register, ACR, contains 8-bit value which used match against which received address tested Receive Address Pending bit. Example: s_acr,#RETURN This will cause Receive Address Pending Command character bit-pattern received.
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UNIT CONFIGURATION (Continued) Interrupt Vector Register, IVR, defines most significant bits vector table byte address. thus points first four vector table word address entries. Example: s_ivr,#SCI_IT this example, after external symbol been linked Vector Table entry address will beloaded into execution time. Interrupt Mask Register, IMR, contains five interrupt masking bits Block status bits. also selects shift register holding register source transmitter register empty interrupt. Example: s_imr,#00000101b this example interrupt pending bits reset, Transmitter data interrupt masked, Receiver data, data error, address interrupts unmasked. Interrupt/DMA Priority Register, IDPR, specifies Interrupt/DMA priority, selects four Address modes, controls emission Break characters enables address/9th data mode. also provides mask bits Receive Transmit transfers. Example: s_idpr,#04h this example priority level specified, Transmitter requests masked.
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UNIT INITIALIZATION list registers initialized when initializing unit given Table A.10. functions these registers, some illustrative examples their use, follows: Receiver Transaction Counter Pointer Register, RDCPR, contains register file address receiver transaction counter. addition determines whether transfers occur register file memory. Example: example this register provided below (see RDAPR example). Receiver Destination Address Pointer Register, RDAPR, contains register file address receiver data destination. addition, conjunction with RDCPR, determines whether transfers occur Program Data memory. Example: LNG-DMA_SCI DEPART_DMA_SCI 0A0h NUM_RDAP NUM_RDCP S_rdcpr,#NUM_RDCP S_rdapr,#NUM_RDAP R#NUM_RDCP,#(LNG_DMA_SCI) R#NUM_RDAP,#(DEPART_DMA_SCI)
this program sequence transaction counter Address Pointer register addresses defined respectively. These registers initialized block size bytes starting register address i.e. R160. Transmitter Transaction Counter Pointer Register, TDCPR, contains register file address transmitter transaction counter. addition determines whether transfers occur register file memory. Example: example this register provided below (see TDAPR example). Transmitter Destination Address Pointer Register, TDAPR, contains register file address transmitter data destination. addition, conjunction with TDCPR, determines whether transfers occur Program Data memory. Example: LNG-DMA_SCI DEPART_DMA_SCI 0A0h NUM_TDAP NUM_TDCP S_TDCPR,#NUM_TDCP S_TDAPR,#NUM_TDAP R#NUM_TDCP,#(LNG_DMA_SCI) R#NUM_TDAP,#(DEPART_DMA_SCI)
this program sequence transaction counter Address Pointer register addresses defined respectively. These registers initialized block size bytes starting register address i.e. R160.
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TIMER/WATCHDOG UNIT CONFIGURATION Configuration Timer/Watchdog requires loading registers listed Table A.11, Appendix Timer/Watchdog unit Configuration Timer/Watchdog Control Register, WDTCR, containsa start/stop bit, also used select input, output, counter modes, well input outputenable bits. Example: wdtcr,#80h this example Timer starts counting down continuous mode, input output sections disabled. Wait Control Register, WCR, well specifying number wait states access off-chip program data memory enables Watchdog function. Example: wcr,#wden this example Watchdog action disabled, number wait states zero. External Interrupt Vector Register, EIVR, contains bit, TLIS, which used control Level Interrupt source (Timer/Watchdog External NMI). second IAOS used select Timer/Watchdog interrupt source channel (INT0). This register also used supply most significant bits External Interrupt Vector. Example: eivr,#EXT_IT_VECT this example Timer/Watchdog generates interrupt channel each Count. Level Interrupt isolated from input used Software Trap. Timer/Watchdog Prescaler Register, WDTPR, contains 8-bit value which loaded into Prescaler register. Example: wdtpr specified Prescaler value zero leads minimum timer count period 333ns, assuming system clock running 12MHz. Timer/Watchdog High Register, WDTHR, Timer/Watchdog Register, WDTLR, together contain 16-bit value which loaded into counter each Count. Example: WDTR,#3003 specified count value leads count period about millisecond, (3003 333ns).
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TIMER/WATCHDOG UNIT INITIALIZATION External Interrupt Priority Level Register, EIPLR, specifies priority level four pairs external interrupts, A1,.D0, thus used priority Timer/Watchdog interrupt routine, called channel Example: eiplr,#0FEh this example priority levels specified pair INTA0, INTA1. External Interrupts PendingBit Register, EIPR, holds eight interruptpending bits external interrupts, including, present context, Watchdog/Timer interrupt. These bits hardware action reset software during service routine. Example: eipr this example external interrupt pending bits cleared. External Interrupts Mask-Bit Register, EIMR, holds eight interrupt mask bits external interrupts, including, present context, Timer/Watchdog interrupt. Example: eimr,#ia0 this example Timer/Watchdog Count Channel unmasked.
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INTERRUPT SERVICE ROUTINE ORGANIZATION When enabled interrupt acknowledged Interrupt machine cycle performs following actions: maskable interrupts disabled clearing register CICR. (ii) (two bytes) FLAGS register saved System stack. (iii) loaded with 16-bit vector stored Vector Table. exit from Interrupt service, using IRET instruction following operations carried out: (iv) FLAGR register restored from System stack. restored from System stack. (vi) unmasked interrupts enabled setting CICR.EI bit. general additional resources must saved restored apart from thosehandled automatically system listed above. typical case these additional resources will include Register pointer registers, Page-pointer register, working registers used Interrupt routine. outline suitable Interrupt service routine hence follows: Label_int: work_reg_page0 work_reg_page1 WDT_PG T0c_PG T0d_PG S_PG AD0_PG push push push srp0 srp1 push push push (0Dh*2) (0Dh*2)
#T0d_PG #work_reg_page0 #work_reg_page1 ;Interrupt Service routine ;appears here, including ;read/write data registers ;test status flags ;clear interrupt pending flags
iret
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SUMMARY This Application Note attempted formalize simplify programming task configuring initializing system. resources controlled have been listed with brief examples their use. Complete examples configuration, initialization, Interrupt Service routines presented Appendices. These programs have been written ST9030 readily adapted where necessary with other versions.
REFERENCES "ST9 Technical Manual", SGS-THOMSON Microelectronics. Application Note AN411, SYMBOLS.INC Standard Definitions Registers Register-bits.
APPENDICES Core Peripheral Configuration/Initialization Registers. A.1. System Configuration: System Registers. A.2. System Configuration: Paged Registers. A.3. Port Configuration Registers. A.4. Multifunction Timer Configuration/Initialization Registers. A.5. Multifunction Timer Data/Status Register. A.6. Configuration/Initialization Registers. A.7. Channel Registers. A.8. Threshold Registers A.9. Configuration Registers. A.10. Initialization Registers. A.11. Watchdog Timer Configuration/Initialization Registers. A.12. Init ialization. A.13. EEPROM Initialization. Examples System Configurations. Examples Multifunction Timer Configurations. Examples Converter Configurations. Examples Configurations. Examples Timer/Watchdog Configurations.
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APPENDIX CORE PERIPHERAL CONFIGURATION/INITIALIZATION A.1. System Configuration: System Registers
Mnem. CICR FLAGR RP0R RP1R MODER USPHR USPLR SSPHR SSPLR Name Central Interrupt Control Register Flags Register Register Pointer Register Pointer Page Pointer Register Mode Register User Stack Pointer (high) User Stack Pointer (low) System Stack Pointer (high) System Stack Pointer (low) Reg. R230 R231 R232 R233 R234 R235 R236 R237 R238 R239 Reset Value (Hex)
A.2. System Configuration: Page Registers
Mnem. EECR EITR EIPR EIMR EIPLR EIVR NICR Name EEPROM Control Register Mask Register External Interrupt Trigger-Event Register External Interrupt Pending Register External Interrupt Mask Register External Interrupt Priority Level Register External Interrupt Vector Register Nested Interrupt Control Register Wait Control Register Reg. R241 R242 R243 R244 R245 R246 R247 R252 Reset Value (Hex)
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A.3. Port Configuration Registers
Port Name Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Handshake Control Register Data Register Control Registers (PxC0-PxC2) Data Register Control Registers (PxC0-PxC2) Registers R224 R240-R242 R225 R244-R246 R226 R248-R250 R251 R227 R252-R254 R255 R228 R240-R242 R243 R229 R244-R246 R247 R251 R248-R250 R255 R252-R254 F0-F2 F4-F6 F8-FA FC-FE F0-F2 F4-F6 F8-FA FC-FE (Hex)
RESET Values: Ports
PcX0: 00000000 PcX1: 00000000 PcX2: 00000000 Handshake Control Registers: 111111111
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A.4. Multi-Function Timer Configuration/Initialization Registers (MFT0)
Mnem. CICR OACR OBCR IDMR DCPR DAPR IDCR Name Central Interrupt Control Register Timer Control Register Timer Mode Register External Interrupt Control Register Output Control Register Output Control Register Interrupt/DMA Mask Register Counter Pointer Register Address Pointer Register Interrupt Vector Register Interrupt/DMA Control Register Reg. R230 R248 R249 R250 R252 R253 R255 R240 R241 R242 R243 Reset Value (Binary) 10000111 00000XXX 00000000 0000XXXX XXXXXX0X XXXXXX0X 00000000 XXXXXXXX XXXXXXXX XXXXXXXX 11000111
A.5. Timer Data/Status Registers (MFT0)
Mnem. REG0HR REG0LR REG1HR REG1LR CMP0HR CMP0LR CMP1HR CMP1LR PRSR FLAGR Name Capture/Reload Register (High) Capture/Reload Register (Low) Capture/Reload Register (High) Capture/Reload Register (Low) Compare Register Register (High) Compare Register Register (Low) Compare Register Register (High) Compare Register Register (Low) Prescaler Register Timer Flags Register Reg. R240 R241 R242 R243 R244 R245 R246 R247 R251 R254 Reset Value (Binary) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000000 00000000
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A.6. Configuration/Initialization Registers
Mnem. Name Compare Result Register Control Logic Register Interrupt Control Register Interrupt Vector Register Reg. R252 R253 R254 R255 Reset Value (Binary) 00001111 00000000 00001111 XXXXXX10
A.7. Channel Registers
Mnem. AD_D0R AD_D1R AD_D2R AD_D3R AD_D4R AD_D5R AD_D6R AD_D7R Name Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Channel Data Register Reg. R240 R241 R242 R243 R244 R245 R246 R247
A.8. Threshold Registers
Mnem. AD_LT6R AD_UT6R AD_LT7R AD_UT7R Name Channel Lower Threshold Register Channel Upper Threshold Register Channel Lower Threshold Register Channel Upper Threshold Register Reg. R248 R249 R250 R251
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A.9. Configuration Registers
Mnem. IDPR CHCR BRGHR BRGLR Name Interrupt Vector Register Interrupt Mask Register Interrupt Status Register Interrupt/DMA Priority Register Character Recognition Register Clock Configuration Register Baud Rate Generator Divisor Register (High) Baud Rate Generator Divisor Register (Low) Reg. R244 R246 R247 R249 R250 R251 R252 R253 Reset Value (Binary) XXXXXXXX 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX 00000000 XXXXXXXX XXXXXXXX
A.10. Initialization
Mnem. Name Receiver Transaction Counter Register Receiver Address Pointer Register Transmit Transaction Counter Register Transmit Address Pointer Register Address Compare Register Receive Buffer Register (Read only) Transmitter Buffer Register (Write only) Reg. Reset Value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
RDCPR RDAPR TDCPR TDAPR RXBR TXBR
R240 R241 R242 R243 R245 R248 R248
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A.11. Watchdog Timer Configuration/Initialization
Mnem. EIPR EIMR EIPLR EIVR WDTLR WDTHR WDTPR WDTCR Name External Interrupt Pending Register External Interrupt Masking Register External Interrupt Priority Register External Interrupt Vector Register Watchdog Timer Register Watchdog Timer High Register Watchdog Timer Prescaler Register Watchdog Timer Control Register Wait Control Register Reg. R243 R244 R245 R246 R248 R249 R250 R251 R252 Reset Value (Binary) 00000000 00000000 11111111 XXXX0010 XXXXXXXX XXXXXXXX XXXXXXXX 00010010 01111111
A.12. Initialization
Mnem. SPIDR SPICR Name Data Register Control Register Reg. R253 R244 Reset Value (Binary) XXXXXXXX 00100000
A.13. EEPROM Initialization (ST9040 only)
Mnem. EECR Name EEPROM Control Register Reg. R241 Reset Value (Binary) 00000000
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS sbttl ST9030 registers addresses contents include "c:\st9\bin\symbols.inc" reader should refer file containing declaration bits registers ST9030 symbols used following listing. .nlist
This program demonstrates configuration peripherals* ;********************** ;*RAM Declaration* ;********************** prescal_t0 Value Timer Prescaler val_capt_t0 Value Timer Capture register nb_event_t0 Number Timer event lg_dma Length CPT_AD_DMA Address Register CPT_LG_DMA Counter Register ad_conv IT_T0_LEVEL IT_CAD_LEVEL conversion start address Timer priority level converter priority level
;**************************** ;*INTERRUPT VECTOR ADDRESSES* ;**************************** CORE_IT_VECT Core interrupt vectors T0_IT_VECT Timer interrupt vectors EXT_IT_VECT External interrupt vectors ADC_IT_VECT Converter interrupt vectors SCI_IT interrupt vector ;******************* ;*STACK Declaration* ;******************* SSTACK USTACK
System stack address group User stack address group
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS (Continued) ;******************** ;*Group number names* ;******************** BK_0 BK_BDT:= BK_CAD:= BK_T0 BK_SCI:= BK_F
free user group group group MFTimer group group. paged registers
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS (Continued) ;*Declaration interrupt vector table* .text start program .org CORE_IT_VECT Core interrupt vector ********************** .word DIV0 divide interrupt vector .word TOP_LEVEL_IT; level interrupt vector .org T0_IT_VECT Timer interrupt vector *********************** unused addresses Timer capture interrupt vector Timer compare interrupt vector External interrupt vector ************************* Watchdog Timer interrupt vector interrupt vector ******************** Analog Watchdog interrupt vector conv. interrupt vector interrupt vector ******************** unused addresses receiver interrupt Transmitter interrupt
.org T0_IT_VECT .word T0_CAP .word T0_COMP .org EXT_IT_VECT
WDT_IT:
.word
TEMPO
.org ADC_IT_VECT
.word RESET_START .word ADC_EOC .org SCI_IT .org SCI_IT .word REC_DATA .word TRA_HOLD
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS (Continued) ;********************** ;*Start main module* ;********************** .org 100h RESET_START: MODER,#11100000b start code
CLOCK MODE REGISTER internal stack prescaling external clock divided CENTRAL INTERRUPT CONTROL REGISTER priority level concurrent mode disable interrupt
CICR,#10000111b
FLAGR #WDT_PG WCR,#wden EIMR,#0
watch mode disabled, wait states. mask channel interrupts. reset,Global Counter Enable active.
SSPLR,#SSTACK USPLR,#USTACK call INIT_IO MAIN: MAIN
load system stack pointer load user stack pointer init ports
include your Main program here
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS (Continued) ;*Configuration TIMER pins Converter pins* proc INIT_IO [PPR] P3.0 (T0INA) P3.2 (T0INB) INPUT TRISTATE P3.1 (T0OUTA) P3.3 (T0OUTB) OUTPUT ALTERNATE FUNCTION PUSH_PULL #P3C_PG Port control register page P3C0R,#00001111b P3C1R,#00001010b P3C2R,#00000101b
init. INITIALIZATION CONVERTOR INPUTS P4.7 (AIN7) ALTERNATE FUNCTION OPEN DRAIN P4.6 (AIN6) ALTERNATE FUNCTION OPEN DRAIN #P4C_PG P4C0R,#11000000b P4C1R,#11000000b P4C2R,#11000000b Port control register page
init. INITIALIZATION P70: Input Sin. P71: Sout. P72: Txclck. P73: Rxclck. #P7C_PG P7C0R,#00001111b P7C1R,#11111110b P7C2R,#00000001b Port control page. (Sin): TRI, TTL. 1,2,3 (Sout, Txck, Rxck): AF,PP,TTL. Others OUT,PP,TTL.
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APPENDIX EXAMPLES PERIPHERAL CONFIGURATIONS (Continued) ;*SECTION CODE CORE INTERRUPT ROUTINE* ;-;*INTERRUPT ROUTINE ZERO DIVISION* ;-DIV0: ;*INTERRUPT ROUTINE TOP_LEVEL_IT* TOP_LEVEL_IT: iret ;*INTERRUPT ROUTINE TIMER WATCHDOG INT* TEMPO: iret
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APPENDIX EXAMPLES TIMER CONFIGURATIONS ;*********************** ;*DEFINE TIMER MACROS* ;*********************** .macroT0_START_IT start timer enable interrupts #T0D_PG select Timer data register page T_TCR,#ccl counter clear T_TCR,#cen counter enable T_IDMR,#gtien global interrupt mask .endm .macroT0_START_DMA_CAP .endm .macroSTOP_T0 .endm stop Timer select Timer data register page global interrupt mask counter enable
start timer enable interrupts #T0D_PG select Timer data register page T_IDMR,#( gtien cp0d global interrupt mask T_TCR,#cen counter enable
#T0D_PG T_IDMR,#gtien T_TCR,#cen
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APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) proc GEST_T0_ITCAPT{ ;Configuration Timer CAPTURE ;TCR: stop count clear capture count ;TMR: disable output internal clock disable bivalue mode disable retrigger mode disable REG1 mode continuous mode enable REG0 mode ;ICR: EXTA Trigger falling edge EXTA EXTB Operation ;OACR-OBCR: operation ;IDMR: Interrupt capture REG0 ;DCPR: reset value ;DAPR: ;IVR: Interrupt vector T0_IT_VECT ;IDCR: level #T0D_PG Timer data register page T_TCR,#01001000b T_TMR,#00001010b T_ICR,#01010100b T_PRSR,prescal_t0 PRESCALER T_OACR,#11111100b OACR T_OBCR,#11111100b OBCR T_FLAGR,#00h FLAGR T_IDMR,#00100000b IDMR #T0C_PG Timer control register page T0_DCPR,#00h DCPR T0_DAPR,#0 DAPR T0_IVR,#T0_IT_VECT interrupt vector T0_IDCR,#IT_T0_LEVEL priority level T0_START_IT start Timer enable interrupt
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) proc GEST_T0_EVENT{ Configuration Timer into EVENT COUNTER MODE COMPARE serviced when nb_event_t0 reached ;TCR: ;TMR: ;ICR: ;OACR-OBCR: ;FLAG: ;IDMR: ;DCPR: ;DAPR: ;IVR: ;IDCR: ;COMP0 #T0D_PG T_CMP0R,nb_event_t0 T_TCR,#00111000b T_TMR,#00000010b T_ICR,#01000010b T_PRSR,prescal_t0 T_OACR,#11111100b T_OBCR,#11111100b T_IDMR,#00000100b Stop count count Clear compare Disable output Bivalue mode Bicapture Internal clock Disable retrigger mode Continuous mode EXTB Ext.Clock Falling edge EXTB EXTA operation reset value compare interrupt vector T0_IT_VECT priority level
Timer data register page COMP0 PRESCALER OACR OBCR IDMR
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) #T0C_PG T0_DCPR,#0 T0_DAPR,#0 T0_IVR,#T0_IT_VECT T0_IDCR,#IT_T0_LEVEL T0_START_IT proc GEST_T0_DMA{ ;Configuration Timer0 CAPTURE associated mode ;the length given lg_dma ;TCR: ;TMR: ;ICR: ;OACR-OBCR: ;IDMR: ;DCPR: ;DAPR: ;IVR: ;IDCR: Stop count clear count disable interrupt bivalue mode capture external/internal clock disable retrigger mode continuous count EXTA TRIGGER Falling edge EXTA EXTA operation operation interrupt, CAPTURE REG0 ext. data/program memory counter external program memory address interrupt vector T0_IT_VECT interrupt priority level select Timer data register PRESCALER OACR OBCR Timer control register page DCPR DAPR IDCR
#T0D_PG T_TCR,#01001000b T_TMR,#00001010b T_ICR,#01010100b T_PRSR,prescal_t0 T_OACR,#11111100b T_OBCR,#11111100b
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) T_FLAGR,#00h T_IDMR,#00100000b #T0C_PG T0_DCPR,#CPT_LG_DMA T0_DAPR,#CPT_AD_DMA T0_IVR,#T0_IT_VECT T0_IDCR,#IT_T0_LEVEL FLAGR IDMR select Timer control register DCPR rr12 RR76 DAPR RR72 priority level
CPT_LG_DMA,lg_dma CPT_AD_DMA,#0ff00h T0_START_DMA_CAP
init counter address 0FF00h enable Interrupt.
Example Timer Timer parallel mode Toggle generated T0OUTB T1OUTB each overflow ;****************** ;initialize TIMER ;****************** TIMER0:: #T0D_PG #BK_F t_tcr,#00011000b t_tmr,#10001000b
select timer register page select working register Counter clear Software Enable output Disable output bivalue mode monitor counter value Capture Internal clock Retrigger mode Continuous mode
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued)
t_icr,#00 t_prsr,#00 t_oacr,#11111100b t_obcr,#11110100b t_flagr,#00 t_idmr,#00
action input pins prescaling action OUTPUT0 Toggle
.macroT0_START #T0D_PG t_tcr,#cen .endm
Start TIMER select Timer data register page counter enable
;****************** ;initialize TIMER ;****************** TIMER1:: #T1D_PG #BK_F t_tcr,#00011000b
select timer register page select working register Counter clear Software Enable output Disable output bivalue mode monitor counter value Capture Parallel mode Retrigger mode Continuous mode action input pins prescaling action T1OUTA Toggle T1OUTB
t_tmr,#10001100b
t_icr,#00 t_prsr,#00 t_oacr,#11111100b t_obcr,#11110100b t_flagr,#00 t_idmr,#00
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) .macroT1_START .endm loop Start TIMER select Timer data register page counter clear counter enable
#T1D_PG t_tcr,#ccl t_tcr,#cen
CICR,#10000000b
Global counter enable
INTERRUPT SUBROUTINES TIMER ;These subroutines serviced TIMER Interrupts. They come from: T0_IT_VECT both IT/CAPTURE IT/CAPTURE block T0_IT_VECT IT/COMPARE
Timer CAPTURE Interrupt subroutine: Capture event EXTA IT/CAPTURE block T0_CAP: #T0D_PG T_FLAGR,#ccp0 RESET_START
Timer data register page mask successful capture this CAPTURE overrun Capture RESET reset successful capture flags reset overrun capture flag return from interrupt
T_FLAGR,#ocp0 jxnz RESET_START T_FLAGR,#~cp0 T_FLAGR,#~ocp0 iret
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INITIALIZATION
APPENDIX EXAMPLES TIMER CONFIGURATIONS (Continued) ;Timer COMPARE interrupt subroutine: COMPARE T0_COMP: #T0D_PG T_FLAGR,#cm0 RESET_START Timer data register page mask successful compare RESET COMPARE overrun Compare RESET reset successful compare reset overrun compare return from interrupt
T_FLAGR,#ocm0 jxnz RESET_START T_FLAGR,#~cm0 T_FLAGR,#~ocm0 iret
;******** TIMER CONFIGURATION EXAMPLES ************
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INITIALIZATION
APPENDIX EXAMPLES CONVERTOR CONFIGURATIONS proc SG_CONV{ Converter configured follows: shot conversion power mode upon Conversion Start mode Autoscan from channel number AD_CONV upon Analog Compare #AD0_PG AD_CLR,#00000100b converter register page Control logic register power Stop Single mode Channel Compare result register Interrupt control register mask analog watchdog enable conversion Priority level Interrupt vector register
AD_CRR,#00h AD_ICR,#00100000b
swap
AD_ICR,#IT_CAD_LEVEL AD_IVR,#ADC_IT_VECT r0,ad_conv AD_CLR,r0
AD_CONV channel number
mask channel number start conversion address
R10, loop [R10] AD_CLR,#st
wait 60µs before start first conversion
start conversion
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INITIALIZATION
APPENDIX EXAMPLES CONVERTOR CONFIGURATIONS (Continued) CONVERSION INTERRUPT SUBROUTINE ADC_EOC: #AD0_PG
converter register page converter flags conversion pending flag analog watch_dog pending flag stop converter power down mode
AD_ICR,#~(ecv awd) AD_CLR,#~(st iret
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INITIALIZATION
APPENDIX EXAMPLES CONFIGURATIONS ;*********************** ;constant declarations. ;*********************** PRIORITY_SCI DIV_9600 DIV_4800 DIV_2400 DIV_1200 VC_9600 Return LNG_DMA_SCI DEPART_DMA_SCI 00dh 0A0h
priority level divisor 9600 baud clock with system clock. generate 4800 clock. generate 2400 clock. generate 1200 clock.
Character 9600 bauds. length. Start address BK_DMA_SCI reserved this. Contains transmit address pointer value. Contains transmit address counter value. data hold register
NUM_TDAP NUM_TDCP data rec_ptr rec_cpt
function: ports initialization. Speed frame initialization. Compare register initialization. Interrupt configuration. Interrupt request: Receive error. Receiver data. transmit. inputs: none outputs:none
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INITIALIZATION
APPENDIX EXAMPLES CONFIGURATIONS (Continued) proc INIT_SCI Communication format configuration. Communication format configured follows: data transmitted received character. stop included data format. Parity even. 9600 Baud communication rate. configuration. address included between parity stop bit. Address mode: Address interrupt character match. permits transmission from EEPROM memory serial line. Receiver data interrupt unmask detect received data item). Transmitter data interrupt unmask detect block). Receiver error interrupt unmask detect overrun, parity framing error). #SCI1_PG register page. #BK_F address registers with s_brglr,#00 Reset s_chcr,#( sb10 s_ccr,#txclk data bit. stop bit. Parity even. address bit. character match.
Xmit clock source BRG. Receiver clock source BRG. asynchronous mode. Command acquisition.
s_acr,#RETURN
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INITIALIZATION
APPENDIX EXAMPLES CONFIGURATIONS (Continued) Interrupt configuration. s_ivr,#SCI_IT Interrupt vector register. s_tdcpr,#NUM_TDCP counter register file. s_imr,#( rxdi Mask Transmitter data interrupt. Unmask Receiver data interrupt. Unmask Receiver data error interrupt. Unmask Receiver address interrupt. Reset pending bits. s_idpr,#PRIORITY_SCI s_brglr,#DIV_9600 Mask transmitter request. exeptions priority level. divisor 9600 bauds, start with external clock, 4800 external clock.)
proc. SYNC_COM: proc SYNC_COM #SCI1_PG #BK_F R#NUM_TDAP,#(DEPART_DMA_SCI) R#NUM_TDCP,#(LNG_DMA_SCI) s_idpr,#txd
pointer initialisation. counter initialisation. Unmask transmitter request. unmask transmitter data interrupt.
s_imr,#txdi Unmask Transmitter data interrupt. Mask Receiver data interrupt. Mask Receiver data error interrupt. proc.
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INITIALIZATION
APPENDIX EXAMPLES CONFIGURATIONS (Continued) REC_DATA: Receive interrupt. REC_DATA: pushu save page pointer. pushuw save register pointer pair. #SCI1_PG #BK_SCI data,S_RXBR data,#07Fh rec_ptr(rec_cpt),data incw rec_cpt rec_cpt,#7 S_ISR,#~rxdp popuw popu iret register page. registers reserved SCI. Read data received. Mask parity bit. Storage received data. table. Reset receiver data pending flag. restore register pointer pair restore page pointer
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INITIALIZATION
APPENDIX EXAMPLES CONFIGURATIONS (Continued) TRA_HOLD: transmitter Interrupt Function: Check Interrupt source. Disable mask Enable Receiver interrupt mask. TRA_HOLD: pushu pushuw save page pointer. save register pointer pair. register page. address registers with Transmitter Block interrupt. Dis. Transmit block pending bit. Reset transmit holding reg. empty rxe) Unmask Receiver data interrupt. Unmask Receiver data error interrupt. Mask Transmitter data interrupt. normal interrupt source.
#SCI1_PG #BK_F s_imr,#txeob [SETZ] bres S_txeob bres S_txhem s_imr,#~( rxdi
else RESET_START popuw popu iret
restore register pointer pair restore page pointer
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INITIALIZATION
APPENDIX EXAMPLES WATCHDOG TIMER CONFIGURATIONS ;INIT_WDT: This procedure initializes starts Watchdog Timer. Watchdog mode disabled. Timer will down count continuous mode. will generate interrupt channel each Count. external interrupt parameters initialization. proc INIT_WDT #WDT_PG wcr,#wden wdtpr WDTR,#3003 wdtcr,#stsp access paged registers with watch mode dis., wait states. ns(sys.clock=12 MHz) min. count, prescaler (3003 333) Timer starts down counting. Continuous mode. Watch disabled. Input section disabled. Output disabled. Interrupt Timer EOC. Level Interrupt TRAP.
proc. ;*Interrupt channel initialization* #WDT_PG #BK_F page reg. direct addressing mode. eipr eivr,#EXT_IT_VECT Dis. external int. pending bits. WARNING (Tech. manual-Chap. External interrupt vector. IAOS TLIS int. will Count.
eiplr,#0FEh eimr,#ia0sm Priority level: group INTA0,INTA1 4,5. Unmask Interrupt channel (WDT Count).
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INITIALIZATION
SOFTWARE INCLUDED THIS NOTE GUIDANCE ONLY. SGS-THOMSON SHALL HELD LIABLE DIRECT, INDIRECT CONSEQUENTIAL DAMAGES WITH RESPECT CLAIMS ARISING FROM SOFTWARE.
Information furnished believed accurate reliable. However, SGS-THOMSON Microelectronics assumes responsability consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights SGS-THOMSON Microelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. SGS-THOMSON Microelectronics products authorized critical components life support devices systems without express written approval SGS-THOMSON Microelectronics.
1994 SGS-THOMSON Microelectronics rights reserved. Purchase Components SGS-THOMSON Microelectronics conveys license under Philips Patent. Rights these components system granted provided that system conforms Standard Specification defined Philips. SGS-THOMSON Microelectronics Group Companies Australia Brazil France Germany Hong Kong Italy Japan Korea Malaysia Malta Morocco Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U.S.A.
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Pierre Guillemin Alan Dunworth INTRODUCTION family offers micropr

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