AFE1400X samsung analog front end(AFE) CCD/CIS image signal integ

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AFE1400X samsung analog front end(AFE) CCD/CIS image signal integ

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0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
samsung analog front end(AFE) CCD/CIS image signal integrated analog signal processor color image signal. converts CCD/CIS output signal digital data. includes three-channel CDS(Correlated Double Sampling) circuit, PGA(Programmable Gain Amplifier), 12-bit analog digital converter with reference generator. 12-bit digital output multiplexed into 8-bit output word that accessed using format read cycles. internal resgisters programmed through 3-wire serial interface, provide adjustment gain, offset, operating mode.
APPLICATIONS
Color Scanner Digital Copiers General Purpose CCD/CIS imager
FEATURES
12-bit MSPS Converter Integrated Triple Correlated Double Sampler 3-Channel MSPS Color Mode 6.25x Analog Programmable Gain Amplifier Internal Voltage Reference Missing Code Guaranteed Multiplexed Byte-Wide Output (8+4 Format) 3-Wire Serial Digital Interface Operation Single 3.3V Supply CMOS Power Dissipation 28-SOP-375 Package
SPECIFICATION
Resolution: 12-bit Conversion Rate: MHz(2 MHz*3) Supply Voltage: Power Dissipation: mW(Typical)
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
FUNCTIONAL BLOCK DIAGRAM
[7:0]
SLOAD DATA
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
CORE DESCRIPTION
Name AVDDA AVSSA AVDDD AVSSD AVBBA AVBBD REFT REFB VCOM R_VIN G_VIN B_VIN OFFSET CDS1_CLK CDS2_CLK ADCCLK SDATA SCLK SLOAD D[7:0] Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground Type vdda vssa vdda vssa vbba vbba poa_bb poa_bb poa_bb piar10_bb piar10_bb piar10_bb piar10_bb picc_bb picc_bb picc_bb poa_bb picc_bb picc_bb picc_bb pot4_bb Analog Ground Digital Supply Digital Ground Analog Substrate Digital Substrate Reference Decoupling Reference Decoupling Analog Common Voltage Analog Input; Analog Input; Green Analog Input; Blue Clamp Bias Level Decoupling Reset Clock Pulse Input Data Clock Pulse Input Converter Sample Clock Input Serial Interface Data Input/Output Serial Interface Clock Input Serial Interface Load Pulse Output Enable; Active Data Outputs Description Analog Supply
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
CODE CONFIGURATION
REFT AVSSD AVDDD AVSSA AVDDA
VCOM REFB
R_VIN G_VIN B_VIN OFFSET AVBBA AVBBD CDS1_CLK CDS2_CLK ADCCLK
afe_cip4
D[7:0] SDATA SCLK SLOAD
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Reference Voltage Storage Temperature Range Operating Temperature Range Symbol VOH, VRT/VRB Tstg Topr Value Unit
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5k resistor (Human body model)
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
ANALOG SPECIFICATIONS
(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz, Gain=1 unless otherwise noted) Characteristics Resolution Conversion Rate 3-Channel with 1-Channel with Signal-to-Noise Distortion Ratio 1MHz Input Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Analog Input Full-Scale Input Input Capacitance Reference Reference Bottom Amplifier Gain Resolution OFFSET Range OFFSET Resolution Power Supply Analog Voltage Digital Voltage Analog Current Digital Current Power Consumption Temperature Range VDDA1 VDDA2 IDD1 IDD2 0.04 -200 6.25 +200 SNDR Symbol Unit Bits MSPS MSPS %FSR %FSR Vp-p Bits Bits Operating 3.3V±5% 3.3V±5% Entire Signal Path Comment
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
DIGITAL SPECIFICATIONS
(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=20MHz, CDS1_CLK=6.666MHz, CDS2_CLK=6.666MHz, CL=20pF unless otherwise noted) Characteristics High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Voltage Level Output Voltage Symbol Unit 0.5mA -0.5mA Comment
TIMING SPECIFICATIONS
(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted) Characteristics CLOCK CHARACTERISTICS 3-Channel Conversion Rate 1-Channel Conversion Rate CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK2B Pulse Width CDSCLK1 Falling CDSCLK2 Rising CDSCLK2 Falling CDSCLK1 Rising ADCCLK Pulse Width CDSCLK2 Rising ADCCLK Rising CDSCLK2 Falling ADCCLK Falling ADCCLK Rising CDS2CLK Falling Aperture Delay SERIAL INTERFACE Maximum SCLK Frequency SLOAD SCLK Set-up Time SCLK SLOAD Hold Time SDATA SCLK Rising Set-up Time SCLK Rising SDATA Hold Time SCLK Falling SDATA Valid
fCLK tRDV
Symbol
Unit
tC1CLK tC2CLK tC2CLKB tC1C2A tC2C1A tADCLK tC2ADA tC2ADB tADC2A
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
TIMING SPECIFICATIONS
(VDDA1=3.3V, VDDA2=3.3V unless otherwise noted) Characteristics DATA OUTPUT Output Delay Tri-State Data Valid Output Enable High Tri-State Latency(Pipeline Delay)
tADDT tDEV ADCCLK Cycles
Symbol
Unit
NOTE: Aperture delay timing measurement between sampling clocks CDS. measured from falling edge CDS2_CLK input when input signal held data conversion
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
TIMING DIAGRAM
3-Channel Mode
Analog Input tC1C2A CDS1_CLK tC2ADA CDS2_CLK tADCLK ADCCLK tADDT
R0,G 0,B0 R1,G 1,B1 R2,G 2,B2
tC2C1A
tC1CLK
ADC2A
tC2CLKB
OUTPUT D[7:0]
3-Channel Mode
Analog Input tC2ADA CDS2_CLK tADCLK ADCCLK tADDT
R0,G 0,B0
R1,G 1,B1
R2,G 2,B2
tADC2A
tC2CLKB
OUTPUT D[7:0]
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
1-Channel Mode
Analog Input CDS1_CLK tC1CLK tC2CLK CDS2_CLK tC2ADA ADCCLK tC2ADB tADCLK tC1C2A tC2C1A
1-Channel Mode
Analog Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2CLK CDS2_CLK tC2ADA ADCCLK tC2ADB tADCLK
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
Digital Output Data Timing
ADCCLK
tADDT tADDT
Byte D5-D0 High High
OUTPUT D[7:0]
High Byte D13-D6
tDEV
Serial Write Operation Timing
SDATA
R/Wb
SCLK
SLOAD
Serial Read Operation Timing
SDATA
R/Wb
tRDV
SCLK
SLOAD
'Read' means microcontroller reads SDATA.
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
FUNCTIONAL DESCRIPTION
3-Channel Operation with This mode enables simultaneous sampling triple output CCD. waveforms coupled R_VIN, G_VIN B_VIN pins where they automatically biased appropriate voltage using onchip clamp. internal CDSs take samples incoming pixel data; first samples taken during reset time while second samples taken during data portion input pixels. 3-Channel Operation This mode enables simultaneous sampling triple output something like that. functions replaced with sample hold amplifiers. input waveforms either coupled restored R_VIN, G_VIN B_VIN pins. input reference voltage this mode will defined external OFFSET pin. 1-Channel Operation with This mode enables single channel monochrome sampling. waveforms coupled analog input where they automatically biased appropriate voltage using on-chip clamp. Bit4, bit5 bit6 register select desired input among red, green blue. 1-Channel Operation This mode enables single-channel monochrome sampling. function replaced with sample hold amplifier. input waveforms either coupled restored analog input pin. input reference voltage this mode will defined clamp level control register. Bit4, bit5 bit6 register select desired input among red, green blue.
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
MAIN BLOCK DESCRIPTION
Programmable Gain Amplifier analog programmable gain accommodate wide range input voltage spans. transfer function follows. H(X) 1/12*X where range Thus, minimum gain value equal maximum gain value equal 6.25. transfer function linearity linear scale. overall gain equal analog gain multiplied digital gain. multiplier should required back AFE.
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
BLOCK DIAGRAM
VDDA1 VSSA1
VDDA2 VSSA2
VDDDR VSSDR
REFT VCOM REFB
R_VIN
CLAMP
GREEN
CLAMP
R_OFFSET[8:0] R_GAIN[5:0]
G_VIN
12-bit
12:8
D[7:0]
BLUE
B_VIN
CLAMP
G_OFFSET[8:0] G_GAIN[5:0]
Configuration
B_OFFSET[8:0] B_GAIN[5:0]
Register
SDATA
Input Offset Register (R,G,B)
R_OFFSET[8:0] G_OFFSET[8:0] B_OFFSET[8:0]
PORT
SCLK SLOAD
OFFSET
R_GAIN[5:0] G_GAIN[5:0] B_GAIN[5:0]
Gain Register (R,G,B)
CDS1_CLK
CDS2_CLK
ADCCLK
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
INTERNAL REGISTER OVERVIEW internal register accessed through serial data SDATA's Register Register Configuration Green Blue Offset Green Offset Blue Offset Address RGB/ Data Bits 3Ch/ Green Blue
Configuration Register Channels 1=3-CH mode* 0=1-CH mode Operation 1=CDS Mode* 0=SHA Mode* Power Down 1=On 0=Off(Operation)*
NOTE: Power-on Default Value, Don't care
Register 3-CH Select 1=R-G-B* 0=B-G-R
NOTE: Power-on Default Value
1-CH 1=RED* 0=Off
1-CH 1=Green 0=Off*
1-CH 1=Blue 0=Off*
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
Gain Register (MSB) 6.167 6.25 15.801 15.918 (LSB) Gain (V/V) 1.083 1.167 Gain (dB) 0.693 1.341
NOTE: Power-on Default Value.
Offset Register D8(MSB) Sign -200 -0.781 -1.563 (LSB) Offset (mV) 0.781 1.563
NOTE: Power-on Default Value.
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
OVERALL TRANSFER FUNCTION
overall transfer function calculated follows. ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*4096, where equal (REFT-REFB) Input _Offset means value input offset register. analog offset range input offset register varied between 200mV -200 9-bit data format input offset register sign magnitude, with sign bit. maximize dynamic range input, necessary program input offset register code move code corresponding black level towards 'zero'. also PGA_gain maximize dynamic range 12-bit ADC's input. PGA_gain range varied between 6.25 gain register. 6-bit data format gain register straight binary coding.
INPUT COUPLING CAPACITOR
Because offset present output CCD, some kind restoration required. case enable mode, simplify input level shifting, decoupling capacitor used conjuction with internal input circuitry. capacitor charging discharging depends clamping time, analog input resistance output resistance circuit driving coupling capacitor. clamping time typically (n*T), where number periods CDSCLK1 asserted period assertion. CDSCLK2 should asserted during clamping time. analog input resistance AFE's Clamp equal recommended input coupling capacitor more than 0.1uF. time constant input clamp determined internal resistance external 0.1uF input capacitance. Thus, extend clamping time, time transport motor moves scanner carriage available, example.
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
POWER-ON INITIALIZATION
Write configuration register operation channel mode color pointer clamp mode
Write gain register gain one(000000)
Write input offset register 0mV(100000000)
another color
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
CALIBRATION
Decide clamp level mode (Refer next page) gain (Input offset
Scan dark line
Compute pixel offsets
input offset
odd/even offset back
another color
gain/offset size back
external pixel offset back
Scan white line
Compute pixel gains back
Adjust gain
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
CORE EVALUATION GUIDE
0.1u 0.1u 0.1u
AVSSD AVDDD AVSSA AVDDA R_VIN G_VIN B_VIN OFFSET AVBBA AVBBD CDS1_CLK CDS2_CLK ADCCLK REFT VCOM REFB
afe_cip4
D[7:0]
SDATA SCLK SLOAD
TIMING GENERATOR
INTERFACE
ASIC
Externally forced digital input/output
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
APPLICATIONS INFORMATION
Mode Applications recommended input coupling capacitor value 0.1uF. single ground plane recommended afe_cip4. Thus digital pins should well decoupled analog ground plane. possible, separate power supply should used VDDDR, this supply should still decoupled same ground plane rest afe_cip4. loading digital outputs should minimized. 0.1uF decoupling capacitors should located close possible afe_cip4 pins. When operating single channel mode, unused analog inputs must grounded.
CDSCLK CDSCLK ADCCLK VDDDR VSSDR D7(MSB) D0(LSB)
VDDA2 VSSA2 R_VIN OFFSET G_VIN VCOM
0.1u 0.01u
0.01u 0.1u 0.1u 1.0u 0.01u
0.1u
afe_cip4
B_VIN REFT REFB VSSA1 VDDA1 SLOAD SCLK SDATA
0.1u
0.1u 0.1u
0.1u
Data Outputs 3-Channel Mode Application Circuit Configuration
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
Mode Applications mode's considerations also apply this configuration, except that analog inputs directly connected afe_cip4 without coupling capacitors. OFFSET used application offset adjustment. connecting appropriate voltage OFFSET pin, signal will restored "zero".
CDSCLK CDSCLK ADCCLK VDDDR VSSDR D7(MSB) D0(LSB)
VDDA2 VSSA2 R_VIN OFFSET G_VIN VCOM
0.1u
0.1u
0.1u
afe_cip4
B_VIN REFT REFB VSSA1 VDDA1 SLOAD SCLK SDATA
0.1u
0.1u 0.1u
0.1u
Data Outputs 3-Channel Mode Application Circuit Configuration
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
PACKAGE DESCRIPTION
Name CDS1_CLK CDS2_CLK ADCCLK VDDDR VSSDR D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] SDATA SCLK SLOAD VDDA1 VSSA1 REFB REFT B_VIN VCOM G_VIN OFFSET R_VIN VSSA2 VDDA2 Type Description Reference Sampling Clock Data Sampling Clock Converter Clock Output Enable (Active Low) Output Buffer Power Output Buffer Ground Digital Output (MSB) High Byte: D13, Byte: Digital Output (D12, Digital Output (D11, Digital Output (D10, Digital Output (D9, Digital Output (D8, Digital Output (D7, Digital Output (LSB) High Byte: Byte: X(Don't care) Serial Interface Data Input/Output Serial Interface Clock Input Serial Interface Load Pulse Analog Power Aanlog Ground Reference Decoupling Reference Decoupling Analog Input: Blue Analog Common Voltage Analog Input: Green Clamp Bias Level Decoupling Analog Input: Digital Ground Digital Power
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
USER GUIDE
SYSTEM CONFIGURATION necessary that output signal analog front shading-compensated back logic block including subtracter multiplier.
(Shading-Compensation Block)
Memory
CCD/CIS
Subtracter Multiplier
Controller
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
QUESTIONNAIRE ANALOG CORE
Characteristics Resolution Signal-to-Noise Distortion Ratio Conversion Rate 3-Channel with 1-Channel with Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Power Consumption Temperature Range What want choose power supply voltages? example, analog needs 3.3V. digital 2.5V/3.3V. Which modes overall system (Refer page example: 3channel operation with 3channel SHI(CIS) operation 1channel operation with 1channel SHI(CIS) operation Would define gain range input offset range Could explain external/internal configurations required? possible, present other requirements below. VDDA VDDD SNDR Symbol Unit Bits Comment
MSPS MSPS %FSR %FSR Vp-p
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
AFE1400X
HISTORY CARD
Version Date 2001.07 Modified Items Original version published (preliminary) Comments
AFE1400X
0.35µm 12-BIT 20MSPS CCD/CIS SIGNAL PROCESSOR
NOTES

AFE1400X samsung analog front end(AFE) CCD/CIS image signal integ

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