SLAS386A JULY 2005 REVISED JUNE 2006 18-BIT, 1-MSPS, PSEUDO-BIPOL

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SLAS386A JULY 2005 REVISED JUNE 2006 18-BIT, 1-MSPS, PSEUDO-BIPOL

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ADS8482
SLAS386A JULY 2005 REVISED JUNE 2006
18-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
FEATURES
APPLICATIONS
Medical Instruments 1-MHz Sample Rate Optical Networking ±1.2 Typ, ±2.5 Transducer Interface +0.75/-0.6 Typ, +1.5/-1 High Accuracy Data Acquisition Systems 18-Bit Ensured Over Temperature Magnetometers ±0.05-mV Offset Error ±0.05-PPM/°C Offset Error Drift DESCRIPTION ±0.035 %FSR Gain Error ADS8482 18-bit, 1-MSPS converter ±0.5-PPM/°C Gain Error Drift with internal 4.096-V reference 99dB SNR, -121dB THD, 123dB SFDR pseudo-bipolar, fully differential input. device includes 18-bit capacitor-based converter Zero Latency with inherent sample hold. ADS8482 offers Power: MSPS full 18-bit interface, 16-bit option where data Unipolar Differential Input Range: Vref -Vref read using read cycles, 8-bit option using three read cycles. Onboard Reference with PPM/°C Drift Onboard Reference Buffer ADS8482 available 48-lead package characterized over industrial High-Speed Parallel Interface -40°C 85°C temperature range. Wide Digital Supply 5.25 8-/16-/18-Bit Transfer 48-Pin Package HIGH SPEED CONVERTER FAMILY
TYPE/SPEED ADS8383 ~600 ADS8381 ADS8380 ADS8481 1.25 4MHz
18-Bit Pseudo-Diff 18-Bit Pseudo-Bipolar, Fully Diff ADS8327 16-Bit Pseudo-Diff ADS8328 16-Bit Pseudo-Bipolar, Fully Diff ADS8406 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS7890 ADS7883 ADS8413 ADS7891 ADS7881 ADS8372 ADS8472 ADS8405 ADS8402 ADS8410 ADS8412 ADS8422 ADS8382 ADS8370 ADS8371 ADS8482 ADS8471 ADS8401 ADS8411
REFIN 4.096-V Internal Reference
CDAC Comparator
Output Latches 3-State Drivers
BYTE 16-/8-Bit Parallel Output 18/16 CONVST BUSY
REFOUT
Clock
Conversion Control Logic
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2005-2006, Texas Instruments Incorporated
ADS8482
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SLAS386A JULY 2005 REVISED JUNE 2006
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPER-ATURE RANGE ORDERING INFORMATION TRANS-PORT MEDIA QTY. Tape reel Tape reel 1000 Tape reel Tape reel 1000
ADS8482IRGZT ADS8482I +1.5 -40°C 85°C ADS8482IRGZR ADS8482IBRGZT ADS8482IB ±2.5 +1.5 -40°C 85°C ADS8482IBRGZR
most current specifications package information, refer website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE AGND AGND Voltage AGND +VBD BDGND +VBD Digital input voltage BDGND Digital output voltage BDGND Tstg Operating free-air temperature range Storage temperature range Junction temperature max) package Lead temperature, soldering Power dissipation thermal impedance Vapor phase sec) Infrared sec) -0.4 -0.4 -0.3 -0.3 -0.3 2.55 -0.3 +VBD -0.3 +VBD (TJMax TA)/JA °C/W UNIT
Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SLAS386A JULY 2005 REVISED JUNE 2006
SPECIFICATIONS
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Common-mode input range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution missing codes
TEST CONDITIONS
UNIT
(-IN)
-Vref -0.2 -0.2 (Vref)/2 (Vref)/2
Vref Vref Vref (Vref)/2
ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB (±0.2 around Vref/2) (-IN) Vref 4.096 Vref 4.096 -0.1 -0.1 -2.5 -0.5 -0.5 ±1.2 ±1.2 -0.6/0.75 -0.6/0.75 ±0.05 ±0.05 ±0.05 ±0.05 ±0.035 ±0.035 ±0.5 ±0.5 1FFFFh output code
Bits Bits bit) bit)
Integral linearity
Differential linearity Offset error
Offset error temperature drift Gain error
ppm/°C ppm/°C
Gain error temperature drift
Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Over voltage recovery
Ideal input span, does include gain offset error. This endpoint INL, best fit. means least significant Measured relative ideal full-scale input [+IN (-IN)] 8.192 This specification does include internal reference voltage error drift.
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SLAS386A JULY 2005 REVISED JUNE 2006
SPECIFICATIONS (Continued)
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER DYNAMIC CHARACTERISTICS ADS8482I ADS8482IB Total harmonic distortion (THD) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Signal noise ratio (SNR) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Signal noise distortion (SINAD) ADS8482I ADS8482IB ADS8482I ADS8482IB ADS8482I ADS8482IB Spurious free dynamic range (SFDR) ADS8482I ADS8482IB ADS8482I ADS8482IB -3dB Small signal bandwidth 97.5 97.5 -120 -121 -105 -110 -100 -103 98.6 98.5 98.5 TEST CONDITIONS UNIT
Calculated first nine harmonics input frequency.
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SLAS386A JULY 2005 REVISED JUNE 2006
SPECIFICATIONS (Continued)
-40°C 85°C, +VBD Vref 4.096 fSAMPLE MSPS (unless otherwise noted)
PARAMETER VOLTAGE REFERENCE INPUT Reference voltage REFIN, Vref Reference resistance Reference current drain INTERNAL REFERENCE OUTPUT Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift DIGITAL INPUT/OUTPUT Logic family -CMOS Logic level Data format Straight Binary POWER SUPPLY REQUIREMENTS Power supply voltage Supply current Power dissipation TEMPERATURE RANGE Operating free-air +VBD 4.75 5.25 5.25 loads loads +VBD -0.3 +VBD +VBD From (+VA), with 1-µF storage capacitor Static load 4.75 5.25 4.081 4.096 4.111 PPM/°C 4.096 TEST CONDITIONS UNIT
vary ±20% This includes only current. +VBD current typical with load capacitance output pins.
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SLAS386A JULY 2005 REVISED JUNE 2006
TIMING CHARACTERISTICS
specifications typical -40°C 85°C, =+VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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TIMING CHARACTERISTICS
specifications typical -40°C 85°C, +VBD
PARAMETER t(CONV) t(ACQ) t(HOLD) tpd1 tpd2 tpd3 tsu1 tsu2 tpd4 tsu3 tdis tsu5 Conversion time Acquisition time Sample capacitor hold time CONVST BUSY high Propagation delay time, conversion BUSY Propagation delay time, start convert state rising edge BUSY Pulse duration, CONVST Setup time, CONVST Pulse duration, CONVST high CONVST falling edge jitter Pulse duration, BUSY signal Pulse duration, BUSY signal high Hold time, first data transition low, read cycle, BYTE BUS18/16 input changes) after CONVST Delay time, Setup time, high high Pulse duration, Enable time, read cycle) data valid Delay time, data hold from high Delay time, BUS18/16 BYTE rising edge falling edge data valid Pulse duration, high Pulse duration, high Hold time, last read cycle rising edge CONVST falling edge Propagation delay time, BUSY falling edge next read cycle) falling edge Delay time, BYTE edge BUS18/16 edge skew Setup time, BYTE BUS18/16 transition falling edge Hold time, BYTE BUS18/16 transition falling edge Disable time, high high read cycle) 3-stated data Delay time, BUSY data valid delay Delay time, rising edge BUSY falling edge Delay time, BUSY falling edge rising edge BYTE transition setup time, from BYTE transition next BYTE transition, BUS18/16 transition setup time, from BUS18/16 next BUS18/16. t(ACQ)min
UNIT
tsu(ABORT) Setup time from falling edge CONVST (used start valid conversion) next falling edge CONVST (when CONVST used abort) next falling edge (when used abort).
input signals specified with (10% +VBD) timed from voltage level (VIL VIH)/2. timing diagrams. timing measured with equivalent loads data bits BUSY pins.
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SLAS386A JULY 2005 REVISED JUNE 2006
ASSIGNMENTS
PACKAGE (TOP VIEW)
+VBD BUS18/16 BYTE CONVST AGND AGND REFM REFM
REFOUT REFIN AGND AGND AGND AGND
BUSY BDGND +VBD DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 AGND AGND
internal connection NOTE: package thermal must soldered printed circuit board thermal mechanical performance.
TERMINAL FUNCTIONS
NAME AGND BDGND BUSY Analog ground Digital ground interface digital supply Status output. High when conversion progress. size select input. Used selecting 18-bit 16-bit wide transfer. Data bits output 18-bit data pins DB[17:0]. Last data bits D[1:0] from 18-bit wide output byte pins DB[9:2] BYTE high byte pins DB[17:10] BYTE Byte select input. Used 8-bit reading. fold back byte D[9:2] most significant bits folded back high byte most significant pins DB[17:10]. Convert start. falling edge this input ends acquisition period starts hold period. Chip select. falling edge this input starts acquisition period. 8-BIT Data BYTE BUS18/16 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 (MSB) BYTE BUS18/16 ones BYTE BUS18/16 ones ones ones ones ones ones (LSB) ones 16-BIT BYTE BUS18/16 (MSB) BYTE BUS18/16 ones ones ones ones ones ones ones ones ones 18-BIT BYTE BUS18/16 (MSB) DESCRIPTION
BUS18/16
BYTE CONVST
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SLAS386A JULY 2005 REVISED JUNE 2006
TERMINAL FUNCTIONS (continued)
NAME REFIN REFOUT REFM +VBD (LSB) ones ones ones ones ones ones ones ones ones ones ones ones ones ones ones ones ones ones DESCRIPTION (LSB) ones ones ones ones ones (LSB) ones ones (LSB)
Inverting input channel Noninverting input channel connection Reference input Reference output. 1-µF capacitor between REFOUT REFM when internal reference used. Reference ground Synchronization pulse parallel output. When low, this serves output enable puts previous conversion results bus. Analog power supplies, Digital power supply
TYPICAL CHARACTERISTICS
HISTOGRAM (8192 Conversion Outputs)
4000 3500 3000
+VBD 25C, MSPS, Vref 4.096 Input Midscale
3615
INTERNAL REFERENCE VOLTAGE FREE-AIR TEMPERATURE
4.098 4.0975 +VBD
Reference Voltage
INTERNAL REFERENCE VOLTAGE SUPPLY VOLTAGE
4.0972 25°C 4.09719 4.09718 4.09717 4.09716 4.09715 4.09714 4.09713 4.75
Reference Voltage
Frequency
2500 2000
1474
2383
4.097
4.0965
1500 1000
4.096 4.0955 4.095
Output Code
4.85
Free-Air Temperature
4.95 5.05 5.15 Supply Voltage
5.25
Figure
Figure
Figure
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SLAS386A JULY 2005 REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT FREE-AIR TEMPERATURE
SUPPLY CURRENT SUPPLY VOLTAGE
SUPPLY CURRENT SAMPLE RATE
+VBD 25°C, Vref 4.096
45.6
Supply Current
Supply Current
Supply Current
+VBD MSPS, Vref 4.096
45.6
25C, MSPS, Vref 4.096
45.2
45.2
44.8
44.8
44.4
44.4
Free-Air Temperature
4.75
4.85
4.95 5.05 Supply Voltage
5.15
5.25
Sample Rate KSPS
1000
Figure DIFFERENTIAL NONLINEARITY FREE-AIR TEMPERATURE
1.50
Figure INTEGRAL NONLINEARITY FREE-AIR TEMPERATURE
1.50
Figure DIFFERENTIAL NONLINEARITY SUPPLY VOLTAGE
+VBD MSPS, Vref 4.096
LSBs
-0.5
LSBs
0.50
LSBs
+VBD MSPS, Vref 4.096
0.50
-0.50
-1.5
+VBD 25°C, MSPS, Vref 4.096
-0.50
Free-Air Temperature
-2.5
Free-Air Temperature
4.75
4.95 5.15 Supply Voltage
Figure INTEGRAL NONLINEARITY SUPPLY VOLTAGE
2.50 1.50 1.50
Figure DIFFERENTIAL NONLINEARITY REFERENCE VOLTAGE
2.50 1.50
Figure INTEGRAL NONLINEARITY REFERENCE VOLTAGE
25°C, MSPS
LSBs LSBs
LSBs
0.50 -0.50 -1.50 -2.50 4.75
+VBD 25°C, MSPS, Vref 4.096
0.50
0.50 -0.50
25°C, MSPS
-0.50
-1.50
4.85
4.95 5.05 5.15 Supply Voltage
5.25
-2.50 Reference Voltage Reference Voltage
Figure
Figure
Figure
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SLAS386A JULY 2005 REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
OFFSET ERROR FREE-AIR TEMPERATURE
-0.01 -0.02 -0.03
OFFSET ERROR SUPPLY VOLTAGE
-0.01 -0.02
OFFSET ERROR REFERENCE VOLTAGE
-0.01 -0.02
+VBD MSPS, Vref 4.096
Offset Error
25°C, MSPS, Vref 4.096
Offset Error
25°C, MSPS
Offset Error
-0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09
-0.03 -0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.1
-0.04 -0.05 -0.06 -0.07 -0.08 -0.09 -0.1 Free-Air Temperature
-0.1 4.75
4.85
4.95 5.05 5.15 Supply Voltage
5.25
Reference Voltage
Figure GAIN ERROR SUPPLY VOLTAGE
-0.01 -0.02 -0.02
Figure GAIN ERROR FREE-AIR TEMPERATURE
-0.025 -0.03
Figure GAIN ERROR REFERENCE VOLTAGE
0.08 0.06 25°C, MSPS
Gain Error
25°C, MSPS, Vref 4.096
+VBD MSPS, Vref 4.096
Gain Error
Gain Error
-0.03 -0.04 -0.05 -0.06 -0.07
-0.035 -0.04 -0.045 -0.05 -0.055 -0.06 -0.065
0.04 0.02 -0.02 -0.04 -0.06 -0.08 -0.1
-0.08 4.75
4.85
4.95 5.05 5.15 Supply Voltage
5.25
-0.07 Free-Air Temperature
Reference Voltage
Figure
Figure
Figure TOTAL HARMONIC DISTORTION REFERENCE VOLTAGE
-119
OFFSET ERROR TEMPERATURE DRIFT DISTRIBUTION Samples)
GAIN ERROR TEMPERATURE DRIFT DISTRIBUTION Samples)
+VBD MSPS, Vref 4.096
Frequency
+VBD MSPS, Vref 4.096
-120
+VBD MSPS, 25°C,
Frequency
-121
-122
0.01 0.03 0.04 0.05 0.07 Offset Drift ppm/C 0.08 0.03 0.19 0.35 0.50 0.66 Gain Error Drift ppm/C 0.90 -123 Vref Reference Voltage
Figure
Figure
Figure
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SLAS386A JULY 2005 REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
SIGNAL-TO-NOISE RATIO REFERENCE VOLTAGE
SINAD Signal-to-noise Distortion
99.5
SIGNAL-TO-NOISE DISTORTION REFERENCE VOLTAGE
99.5
TOTAL HARMONIC DISTORTION FREE-AIR TEMPERATURE
-115
Total Harmonic Distortion
SNR- Signal-to-Noise Ratio
98.5
+VBD MSPS, 25°C,
98.5
+VBD MSPS, 25°C,
-116 -117 -118 -119 -120 -121
+VBD MSPS, Vref 4.096
97.5
97.5
96.5 Vref Reference Voltage
96.5
Vref Reference Voltage
-122
Free-Air Temperature
Figure SPURIOUS FREE DYNAMIC RANGE FREE-AIR TEMPERATURE
SFDR Spurious Free Dynamic Range
123.5 98.9 122.5 121.5 120.5 119.5 118.5
Figure SIGNAL-TO-NOISE RATIO FREE-AIR TEMPERATURE
SINAD Signal-to-Noise Distortion
Figure SIGNAL-TO-NOISE DISTORTION FREE-AIR TEMPERATURE
98.9
Signal-to-Noise Ratio
+VBD MSPS, Vref 4.096
98.8 98.7 98.6 98.5 98.4 98.3 98.2 98.1
+VBD MSPS, Vref 4.096
98.8 98.7 98.6 98.5 98.4 98.3 98.2
+VBD MSPS, Vref 4.096
Free-Air Temperature
Free-Air Temperature
98.1 Free-Air Temperature
Figure
Figure
Figure
+VBD 25C, MSPS, Vref 4.096
LSBs
-0.5 -1.5 -131072
-65536
Output Code
65536
131072
Figure
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SLAS386A JULY 2005 REVISED JUNE 2006
TYPICAL CHARACTERISTICS (continued)
-0.5 -1.5 -2.5 -131072 +VBD 25C, MSPS, Vref 4.096
LSBs
-65536
Output Code
65536
131072
Figure
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SLAS386A JULY 2005 REVISED JUNE 2006
TIMING DIAGRAMS
CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) t(ACQ) tsu(ABORT) BYTE 18/16 tpd4 tsu5 tsu2 tsu5 tsu(ABORT) t(CONV) tpd2
DB[17:12] Hi-Z
D[17:12] D[9:4]
tdis Hi-Z
Hi-Z Hi-Z
DB[11:10]
D[11:10]
D[3:2]
D[1:0]
DB[9:0]
Signal
Hi-Z
D[9:0]
Hi-Z
internal device
Figure Timing Conversion Acquisition Cycles With Toggling
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CONVST tpd1 BUSY tsu1 tpd3 CONVERT t(CONV) t(HOLD) SAMPLING (When Toggle) tpd2
t(CONV)
t(ACQ) tsu(ABORT) BYTE 18/16 tpd4 tsu5 tsu(ABORT)
DB[17:12] Previous Hi-Z D[17:12] tdis Hi-Z
D[17:12] D[9:4]
tdis Hi-Z
Repeated
D[17:12]
DB[11:10]
Hi-Z
Previous
D[11:10]
Hi-Z
D[11:10]
D[3:2]
D[1:0]
Hi-Z
Repeated
D[11:10]
DB[9:0]
Signal
Hi-Z
Previous
[9:0]
Hi-Z
D[9:0]
Hi-Z
Repeated
[9:0]
internal device
Figure Timing Conversion Acquisition Cycles With Toggling, Tied BDGND
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CONVST tpd1 BUSY tpd2
CONVERT t(CONV) t(HOLD) t(CONV)
SAMPLING (When tsu(ABORT) BYTE 18/16 tpd4
t(ACQ)
tsu(ABORT)
tsu5
tsu5
tdis
D[17:12] D[9:4]
DB[17:12]
Hi-Z
Hi-Z
DB[11:10]
Hi-Z
D[11:10]
D[3:2]
D[1:0]
Hi-Z
DB[9:0]
Hi-Z
D[9:0]
Hi-Z
Signal
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND, Toggling
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CONVST tpd1 BUSY tpd2
CONVERT tpd3 t(HOLD)
t(CONV) tpd3 t(HOLD) t(ACQ)
t(CONV)
SAMPLING (When
tsu(ABORT) BYTE tsu5 18/16 tsu5 DB[17:12]
D[17:12] D[9:4]
tsu(ABORT)
tsu5
tsu5
Next D[17:12]
DB[11:10]
Previous
D[11:10]
D[3:2]
D[1:0]
Next D[11:10]
DB[9:0]
Signal
D[9:0]
Next D[9:0]
internal device
Figure Timing Conversion Acquisition Cycles With Tied BDGND Auto Read
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BYTE tsu5 18/16
Hi-Z Valid tdis Hi-Z Valid
tdis Hi-Z
DB[17:0]
Valid
Figure Detailed Timing Read Cycles
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APPLICATION INFORMATION MICROCONTROLLER INTERFACING
ADS8482 8-Bit Microcontroller Interface Figure shows parallel interface between ADS8482 typical microcontroller using 8-bit data bus. BUSY signal used falling-edge interrupt microcontroller.
Analog
AGND Input Analog Input REFIN REFM AGND
Micro Controller GPIO GPIO GPIO GPIO AD[7:0]
Digital AD8482 BYTE BUS18/16 CONVST DB[17:10] BDGND BDGND +VBD
Data D[17:0]
Figure ADS8482 Application Circuitry
Analog
AGND
REFOUT REFM REFIN AGND
AGND
ADS8482
Figure ADS8482 Using Internal Reference
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PRINCIPLES OPERATION
ADS8482 high-speed successive approximation register (SAR) analog-to-digital converter (ADC). architecture based charge redistribution which inherently includes sample/hold function. Figure application circuit ADS8482. conversion clock generated internally. conversion time capable sustaining throughput. analog input provided input pins: -IN. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8482 operate with external reference with range from reference voltage input (REFIN) converter internally buffered. clean, noise, well-decoupled reference voltage this required ensure good performance converter. noise band-gap reference like REF3240 used drive this pin. 0.1-µF decoupling capacitor required between REFIN REFM pins (pin #12) converter. This capacitor should placed close possible pins device. Designers should strive minimize routing length traces that connect terminals capacitor pins converter. network also used filter reference voltage. 100- series resistor 0.1-µF capacitor, which also serve decoupling capacitor used filter reference voltage.
REFM
REF3240 REFIN
ADS8482
Figure ADS8482 Using External Reference ADS8482 also limited pass filtering capability built into converter. equivalent circuitry REFIN input shown Figure
REFIN REFM CDAC
CDAC
Figure Simplified Reference Input Circuit REFM input ADS8482 should always shorted AGND. 4.096-V internal reference included. When internal reference used, (REFOUT) connected (REFIN) with 0.1-µF decoupling capacitor 1-µF storage capacitor between (REFOUT) pins (REFM) (see Figure 36). internal reference converter double buffered. external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion. (REFOUT) left unconnected (floating) external reference used.
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PRINCIPLES OPERATION (continued) ANALOG INPUT
When converter enters hold mode, voltage difference between inputs captured internal capacitor array. Both input range -0.2 Vref input span [+IN (-IN)] limited -Vref Vref. input current analog inputs depends upon number factors: sample rate, input voltage, source impedance. Essentially, current into ADS8482 charges internal capacitor array during sample period. After this capacitance been fully charged, there further input current. source analog input must able charge input capacitance 18-bit settling level within acquisition time (320 device. When converter goes into hold mode, input impedance greater than Care must taken regarding absolute analog input voltage. maintain linearity converter, inputs span [+IN (-IN)] must within limits specified. Outside these ranges, converter's linearity meet specifications. minimize noise, bandwidth input signals with low-pass filters used. Care must taken ensure that output impedance sources driving inputs matched. this observed, inputs could have different setting times. This result offset error, gain error, linearity error which varies with temperature input voltage. analog input converter needs driven with noise, high-speed op-amp like THS4031. filter recommended input pins low-pass filter noise from source. input converter uni-polar input voltage range Vref. THS4031 used source follower configuration drive converter.
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SLAS386A JULY 2005 REVISED JUNE 2006
PRINCIPLES OPERATION (continued)
+VIN THS4031 (+)IN
2200
THS4031 +2.048 (-)IN
Figure Single-Ended Input, Differential Output Configuration systems, where input differential, THS4031 used inverting configuration with additional bias applied input keep input ADS8482 within rated operating voltage range. bias derived from REF3220 REF3240 reference voltage ICs. input configuration shown below capable delivering better than 97dB -103db input frequency kHz. case band-pass filters used filter input, care should taken ensure that signal swing input band-pass filter small keep distortion introduced filter minimal. such cases, gain circuit shown below increased keep input ADS8482 large keep system high. Note that gain system from input output THS4031 such configuration function gain signal. resistor divider used scale output REF3220 REF3240 reduce voltage input THS4031 keep voltage input converter within rated operating range.
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SLAS386A JULY 2005 REVISED JUNE 2006
PRINCIPLES OPERATION (continued)
+2.048 +VIN THS4031
(+)IN
Cascade System
-12V
2200
Cascade System Pattern Generator Platform SNR: SINAD: THD: -121 SFDR: ENOB(SINAD): 16.15 -VIN
+12V THS4031 (-)IN
+2.048
Figure Differential Input, Differential Output Configuration
DIGITAL INTERFACE
Timing Control timing diagrams specifications section detailed information timing signals their requirements. ADS8482 uses internal oscillator generated clock which controls conversion rate turn throughput converter. external clock input required.
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PRINCIPLES OPERATION (continued)
Conversions initiated bringing CONVST minimum (after minimum requirement been met, CONVST brought high), while low. ADS8482 switches from sample hold mode falling edge CONVST command. clean jitter falling edge this signal important performance converter. BUSY output brought high immediately following CONVST going low. BUSY stays high throughout conversion process returns when conversion ended. Sampling starts with falling edge BUSY signal when tied starts with falling edge when BUSY low. Both high during before conversion with exception must when CONVST goes initiate conversion). Both pins brought order enable parallel output with conversion. Reading Data ADS8482 outputs full parallel data straight binary format shown Table parallel output active when both low. There minimal quiet zone requirement around falling edge CONVST. This prior falling edge CONVST after falling edge. data read should attempted within this zone. other combination sets parallel output 3-state. BYTE BUS18/16 used multiword read operations. BYTE used whenever lower bits output higher byte bus. BUS18/16 used whenever last bits 18-bit output either bytes higher 16-bit bus. Refer Table ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full scale range Least significant (LSB) +Full scale Midscale Midscale Zero ANALOG VALUE +Vref (+Vref)/262144 (+Vref) -Vref BINARY CODE 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 CODE 1FFFF 00000 3FFFF 20000 DIGITAL OUTPUT STRAIGHT BINARY
output data full 18-bit word (D17-D0) DB17-DB0 pins (MSB-LSB) both BUS18/16 BYTE low. result also read 16-bit using only pins DB17-DB2. this case reads necessary: first before, leaving both BUS18/16 BYTE reading most significant bits (D17-D2) pins DB17-DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 high, lower bits (D1-D0) appear pins DB3-DB2. result also read 8-bit convenience. This done using only pins DB17-DB10. this case three reads necessary: first before, leaving both BUS18/16 BYTE reading most significant bits pins DB17-DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE high, medium bits (D9-D2) appear pins DB17-DB10. last read done bringing BUS18/16 high while holding BYTE high. When BUS18/16 high, lower bits (D1-D0) appear pins DB11-DB10. last read cycle necessary only first most significant bits interest. these multiword read operations performed with multiple active (toggling) with held simplicity. This referred AUTO READ operation. Table Conversion Data Read
DATA READ BYTE High BUS18/16 High High PINS DB17-DB12 One's One's PINS DB11-DB10 D1-D0 One's PINS DB9-DB4 One's One's PINS DB3-DB2 One's D1-D0 PINS DB1-DB0 One's One's
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Table Conversion Data Read (continued)
DATA READ BYTE High BUS18/16 PINS DB17-DB12 D9-D4 D17-D12 PINS DB11-DB10 D3-D2 D11-D10 PINS DB9-DB4 One's D9-D4 PINS DB3-DB2 One's D3-D2 PINS DB1-DB0 One's D1-D0
RESET
power-up, internal POWER-ON RESET circuitry generates reset required device. first three conversions after power-up used load factory trimming data specific device assure high accuracy converter. results first three conversions invalid should discarded. device also reset through combination CONVST. Since BUSY signal held high during conversion, either these conditions triggers internal self-clear reset converter. Issue CONVST when internal convert state high. falling edge CONVST starts reset. Issue (select device) while internal convert state high. falling edge causes reset. Once device reset, output latches cleared (set zeroes) BUSY signal brought low. sampling period started falling edge BUSY signal immediately after instant internal reset.
LAYOUT
optimum performance, care must taken with physical layout ADS8482 circuitry. ADS8482 offers single-supply operation, often used close proximity with digital logic, microcontrollers, microprocessors, digital signal processors. more digital logic present design higher switching speed, more difficult achieve good performance from converter. basic architecture sensitive glitches sudden changes power supply, reference, ground connections digital inputs that occur just prior latching output analog comparator. Thus, driving single conversion n-bit converter, there least windows which large external transient voltages affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. degree error digital output depends reference voltage, layout, exact timing external event. average, ADS8482 draws very little current from external reference reference voltage internally buffered. reference voltage external originates from amp, make sure that drive bypass capacitor capacitors without oscillation. 0.1-µF capacitor recommended from (REFIN) directly (REFM). REFM AGND must shorted same ground plane under device. AGND BDGND pins should connected clean ground point. cases, this should analog ground. Avoid connections which close grounding point microcontroller digital signal processor. required, ground trace directly from converter power supply entry point. ideal layout consists analog ground plane dedicated converter associated analog circuitry. with AGND connections, should connected power supply plane trace that separate from connection digital logic until they connected power entry point. Power ADS8482 should clean well bypassed. 0.1-µF ceramic bypass capacitor should placed close device possible. Table placement capacitor. addition, 1-µF 10-µF capacitor recommended. some situations, additional bypassing required, such 100-µF electrolytic capacitor even filter made inductors capacitors-all designed essentially low-pass filter supply, removing high frequency noise.
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Table Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS pairs that require shortest path decoupling capacitors Pins that require decoupling CONVERTER ANALOG SIDE (7,8), (9,10), (16,17), (20,21), (22,23), (25,26) CONVERTER DIGITAL SIDE (36,37)
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PACKAGE OPTION ADDENDUM
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20-Jun-2006
PACKAGING INFORMATION
Orderable Device ADS8482IBRGZR ADS8482IBRGZT ADS8482IRGZR ADS8482IRGZT
Status ACTIVE ACTIVE ACTIVE ACTIVE
Package Type
Package Drawing
Pins Package Plan 1000 1000
Lead/Ball Finish Call Call Call Call
Peak Temp Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
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SLAS386A JULY 2005 REVISED JUNE 2006 18-BIT, 1-MSPS, PSEUDO-BIPOL

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