SLAS512 JUNE 2006 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENT

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SLAS512 JUNE 2006 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENT

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ADS8422
SLAS512 JUNE 2006
16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE
FEATURES
Fully Differential Input with Pseudo-Bipolar Input Range 16-Bit MSPS 92dB SNR, -102dB with 100-kHz Input Internal 4.096-V Reference Reference Buffer REFIN/2 Available Setting Analog Input Common-Mode Voltage Zero Latency High-Speed Parallel Interface Single Supply Operation Capability Power: Typ, Flexible Power-Down Scheme Pin-Out Similar ADS8412/8402 48-Pin TQFP Package
APPLICATIONS
DWDM Instrumentation High-Speed, High-Resolution, Zero Latency Data Acquisition Systems Transducer Interface Medical Instruments Spectrum Analysis
DESCRIPTION
ADS8422 16-bit, 4-MHz converter with internal 4.096-V reference. device includes 16-bit capacitor-based multi-bit converter with inherent sample hold. This converter includes full 16-bit interface 8-bit option where data read using 8-bit read cycles necessary. ADS8422 fully differential, pseudo-bipolar input. available 48-lead TQFP package characterized over industrial -40°C +85°C temperature range.
HIGH-SPEED CONVERTER FAMILY
TYPE/SPEED 18-Bit Pseudo-Diff ADS8380 18-Bit Pseudo-Bipolar, Fully Diff ADS8327 16-Bit Pseudo-Diff ADS8328 16-Bit Pseudo-Bipolar, Fully Diff ADS8406 14-Bit Pseudo-Diff 12-Bit Pseudo-Diff ADS7886 ADS7890 ADS7883 ADS8413 ADS7891 ADS7881 ADS8372 ADS8472 ADS8405 ADS8402 ADS8410 ADS8412 ADS8422 ADS8382 ADS8370 ADS8371 ADS8471 ADS8401 ADS8411 ADS8422 ADS8383 ~600 ADS8381 ADS8481 1.25 4MHz
TEMPOUT COMMOUT REFIN REFOUT
Temp Sensor
CDAC Comparator Clock 4.096-V Internal Reference
Output Latches 3-State Drivers
BYTE 16-/8-Bit Parallel Data Output
Conversion Control Logic
RESET/PD1 CONVST BUSY
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
Copyright 2006, Texas Instruments Incorporated
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ADS8422
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SLAS512 JUNE 2006
These devices have limited built-in protection. leads should shorted together device placed conductive foam during storage handling prevent electrostatic damage gates.
ORDERING INFORMATION
MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ORDERING INFORMATION TRANSPORT MEDIA QTY. Small tape reel Tape reel 1000 Small tape reel Tape reel 1000
ADS8422IPFBT ADS8422I 48-Pin TQFP -40°C 85°C ADS8422IPFBR ADS8422IBPFBT ADS8422IB +1.5/-1 48-Pin TQFP -40°C 85°C ADS8422IBPFBR
most current specifications package information, refer website www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE AGND AGND Voltage AGND +VBD BDGND +VBD Digital input voltage BDGND Digital output voltage BDGND Tstg Operating free-air temperature range Storage temperature range Junction temperature max) TQFP 48-pin package Lead temperature, soldering Power dissipation thermal impedance Vapor phase sec) Infrared sec) -0.4 -0.4 -0.3 -0.3 -0.3 2.55 -0.3 +VBD -0.3 +VBD (TJMax TA)/JA °C/W UNIT
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Stresses beyond those listed under absolute maximum ratings cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under recommended operating conditions implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability.
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SLAS512 JUNE 2006
SPECIFICATIONS
-40°C 85°C, +VAREG +VBD fSAMPLE MSPS, Vref 4.096 (measured with internal reference reference buffer) (unless otherwise noted)
PARAMETER ANALOG INPUT Full-scale input voltage Absolute input voltage Common-mode input range Input capacitance Input leakage current SYSTEM PERFORMANCE Resolution missing codes
TEST CONDITIONS
UNIT
(-IN)
-Vref -0.2 -0.2 (Vref)/2 (Vref)/2
Vref Vref Vref (Vref)/2
ADS8422I ADS8422IB ADS8422I ADS8422IB ADS8422I ADS8422IB ADS8422I ADS8422IB ADS8422I ADS8422IB Vref 4.096 Vref 4.096 [+IN (-IN)]/2 mVpp MHz, [+IN (-IN)] 0000h output code 8000h output code -0.5 -0.5 -0.1 -0.1 ±0.7 ±0.7 ±0.25 ±0.25 ±0.05 ±0.05
Bits Bits bit) bit)
Integral linearity
Differential linearity
Offset error Gain error
Common-mode rejection ratio Noise Power supply rejection ratio SAMPLING DYNAMICS Conversion time Acquisition time Throughput rate Aperture delay Aperture jitter Step response Overvoltage recovery
0.180 0.070
Ideal input span, does include gain offset error. means least significant equal 2VREF/65536. This endpoint INL, best fit. Measured relative ideal full-scale input [+IN (-IN)] 8.192 This specification does include internal reference voltage error drift.
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ADS8422
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SLAS512 JUNE 2006
SPECIFICATIONS (Continued)
-40°C 85°C, +VAREG 5.25 +VBD fSAMPLE MSPS, Vref 4.096 (measured with internal reference reference buffer) (unless otherwise noted)
PARAMETER DYNAMIC CHARACTERISTICS ADS8422I Total harmonic distortion (THD) ADS8422IB ADS8422I ADS8422IB ADS8422I Signal noise ratio (SNR) ADS8422IB ADS8422I ADS8422IB ADS8422I Signal noise distortion (SINAD) ADS8422IB ADS8422I ADS8422IB ADS8422I Spurious free dynamic range (SFDR) ADS8422IB ADS8422I ADS8422IB -3dB Small signal bandwidth VOLTAGE REFERENCE INPUT Reference voltage REFIN, Vref Reference resistance INTERNAL REFERENCE OUTPUT Internal reference start-up time Reference voltage range, Vref Source current Line regulation Drift ANALOG COMMON-MODE, From (+V5A), with 1-µF capacitor REFOUT 25°C Static load 4.75 5.25 VREF/2 0.016 VREF/2 VREF/2 0.016 4.088 4.096 4.104 PPM/°C 4.096 1000 4.15 -104 -104 -102 -102 92.5 92.5 92.5 92.5 TEST CONDITIONS UNIT
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Calculated first nine harmonics input frequency.
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SLAS512 JUNE 2006
SPECIFICATIONS
-40°C 85°C, +VAREG +VBD fSAMPLE MSPS, Vref 4.096 (measured with internal reference reference buffer) (unless otherwise noted)
PARAMETER DIGITAL INPUT/OUTPUT Logic family CMOS Logic level Data format Twos Complement POWER SUPPLY REQUIREMENTS Power supply voltage +VAREG +VBD Supply current +VAREG +VAREG +VAREG 4.75 2.85 5.25 5.25 loads loads -0.3 +VBD +VBD TEST CONDITIONS UNIT
POWER DOWN Supply current +VA, power down 1-µF Storage capacitor from REFOUT AGND
Power-up time, from after 4.75 TEMPERATURE RANGE Operating free-air
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ADS8422
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SLAS512 JUNE 2006
TIMING CHARACTERISTICS FROM DIGITAL INPUTS
specifications typical -40°C 85°C, +VBD 5.25
PARAMETER CONVERSION ACQUISITION t(ACQ) Acquisition time, internal device, externally visible Pulse duration, CONVST Pulse duration, CONVST high Period, CONVST Quiet time, last toggle interface signals during acquisition before CONVST falling Quiet time, CONVST falling first toggle interface signals Pulse duration, only reset powerdown) Pulse duration, reset also powerdown Pulse duration, pulse duration REFOUT COMMOUT buffers powerdown Pulse duration, others unspecified 1500 1500
UNIT
POWER DOWN
input signals specified with (10% VDD) timed from after transition. digital output signals loaded with 10-pF capacitors +VBD 20-pF capacitor +VBD 5.25 timed reaching transition. Quiet time zones meeting performance functionality.
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TIMING CHARACTERISTICS DIGITAL OUTPUTS
specifications typical -40°C 85°C, +VBD 5.25
PARAMETER CONVERSION ACQUISITION t(CONV) Conversion time, internal device, externally visible Delay time, CONVST fall conversion start (aperture delay) Delay time, CONVST data valid Delay time, data valid BUSY Delay time, data valid Delay time, BYTE toggle data valid Delay time, data three-state after high Delay time, BUSY rising Delay time, high device operational (with held high) Delay time, high REFOUT/COMMOUT valid Delay time, power (after AVDD 4.75 Delay time, data three-state after
UNIT
DATA READ OPERATION
POWER DOWN
input signals specified with (10% VDD) timed from after transition. digital output signals loaded with 10-pF capacitors +VBD 20-pF capacitor +VBD 5.25 timed reaching transition.
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ASSIGNMENTS
Package (Top View)
REFM REFM AGND AGND CONVST BYTE RESET/PD1
connection Pins internally regulated outputs externally connected decoupling capacitors only. +VAREG connected supply. outputs REFIN/2 used powerdown analog output powerdown.
TERMINAL FUNCTIONS
NAME AGND BDGND BUSY BYTE Analog ground Digital ground interface digital supply Status output. High when conversion progress. Byte select input. Used 8-bit reading. fold back byte D[7:0] most significant bits folded back high byte most significant pins DB[15:8]. This outputs REFIN/2 used common-mode voltage differential analog input, (+IN -IN)/2. Convert start. This input true independent input. Chip select. Decoupling internally generated supply. 1-µF capacitor from these pins AGND. 8-BIT BYTE (MSB) BYTE (MSB) 16-BIT BYTE DESCRIPTION
COMMOUT CONVST CAP1, CAP2 Data DB15 DB14 DB13 DB12 DB11 DB10
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REFIN REFOUT COMMOUT AGND AGND CAP1 +VAREG AGND
BUSY BDGND +VBD BDGND
CAP2 AGND AGND DB15 DB14 DB13 DB12 DB11 DB10
+VBD
ADS8422
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SLAS512 JUNE 2006
TERMINAL FUNCTIONS (continued)
NAME REFIN REFOUT REFM RESET/PD1 +VAREG +VBD (LSB) Inverting input channel Noninverting input channel connection true signal. logic longer than applied this powers down only analog outputs that include REFOUT COMMOUT. powering down analog outputs total power dissipation reduced Reference input. 0.1-µF decoupling capacitor between REFIN REFM. Reference output. 1-µF capacitor between REFOUT REFM when internal reference used. Reference ground true signal. pulse applied this resets ADC; ongoing conversion aborted. pulse shorter than only resets, longer than resets also powers down ADC. Note that analog outputs REFOUT COMMOUT powered down PD2, necessary. Synchronization pulse parallel output. Analog power supplies, 4.75 5.25 Regulator supply, 5.25 Digital power supply (LSB) ones ones ones ones ones ones ones ones DESCRIPTION (LSB)
LSBs
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TYPICAL CHARACTERISTICS
+VAREG +VBD REFIN 4.096 -0.5 Code Figure 65534
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TYPICAL CHARACTERISTICS (continued)
+VAREG +VBD REFIN 4.096
LSBs
-0.5 -1.5 65534 Code
Figure
TIMING DIAGRAMS
CONVST
ACQUISITION Sample(N)
t(acq) Sample(N+1)
t(CONV) CONVERT Conversion(N) (Internal) DB(N-1) DB(N)
BUSY
shown here internal device output pins only when both (after ns). This shown Figure
Figure Conversion Control Timing
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ADS8422
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SLAS512 JUNE 2006
BYTE
Hi-Z Valid Data Hi-Z
Valid Data Valid Data
Hi-Z
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Data output pins only both low, after this condition satisfied.
Figure Data Read Timing
CONVST
BUSY Conversion(1) Hi-Z Undefined Data DB(1) DB(2) Conversion(2)
Data valid from first conversion initiated after pulled high analog outputs after pulled high.
Figure Power-Down Timing
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COMMOUT Valid Analog Outputs REFOUT
Data valid from first conversion initiated after pulled high analog outputs after pulled high.
Figure Analog Output Power-Down Timing
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ADS8422
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SLAS512 JUNE 2006
PRINCIPLES OPERATION
ADS8422 member family high-speed multi-bit successive approximation register (SAR) analog-to-digital converters (ADC). architecture based charge redistribution, which inherently includes sample/hold function. Figure application circuit ADS8422. conversion clock generated internally. conversion time maximum that capable sustaining 4-MHz throughput. analog input provided input pins: -IN. When conversion initiated, differential input these pins sampled internal capacitor array. While conversion progress, both inputs disconnected from internal function.
REFERENCE
ADS8422 built-in 4.096-V reference operate with external 4.096-V reference. When internal reference used, (REFOUT) should connected (REFIN) with 1-µF decoupling capacitor 10-µF storage capacitor between (REFOUT) pins (REFM). internal reference converter double buffered. external reference used, second buffer provides isolation between external reference CDAC. This buffer also used recharge capacitors CDAC during conversion. (REFOUT) left unconnected (floating) external reference used.
PRODUCT PREVIEW
When asserted analog outputs REFOUT COMMOUT powered down save approximately This requires external 4.096 REFOUT operating bias condition. When deasserted analog outputs (assuming 1-µF capacitor REFOUT load COMMOUT). order avoid powering down reference circuitry unintentional glitches facilitate common interface pins 37/38, power-down signal filtered internally such that pulse lesser than recognized power-down signal.
ANALOG INPUT
ADS8422 pseudo-bipolar, fully differential input. When input differential, amplitude input equals difference between -IN. peak-to-peak amplitude each input VREF. However since inputs 180° phase, peak-to-peak amplitude difference voltage [+IN (-IN)] equal 2VREF. common-mode input range from VREF/2 VREF/2 order avoid additional external circuitry board, ADS8422 outputs reference input REFIN divided (COMMOUT). This voltage used common-mode output from input driver. input current analog inputs depends upon number factors: sample rate, input voltage, source impedance. Essentially, current into ADS8422 charges internal capacitor array during sample period. After this capacitance been fully charged, there further input current. source analog input voltage must able charge input capacitance 16-bit settling level within acquisition time device. When converter goes into hold mode, input impedance greater than Care must taken regarding absolute analog input voltage. maintain linearity converter, both inputs should within limits specified. Outside these ranges, converter linearity meet specifications. minimize noise, bandwidth input signals with pass filters should used. Care should taken ensure that output impedances sources driving inputs matched. this observed, inputs could have different settling times. This result offset error, gain error, linearity error which change with temperature input voltage. When converter enters hold mode, voltage difference between inputs captured internal capacitor array.
DIGITAL INTERFACE
Timing Control timing diagrams detailed information timing signals their requirements.
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PRINCIPLES OPERATION (continued)
ADS8422 uses internal oscillator generated clock which controls conversion rate turn throughput converter. external clock input required. Conversions initiated bringing CONVST minimum (after minimum requirement been met, CONVST brought high). converter switches from sample hold mode falling edge CONVST command. clean jitter falling edge this signal important performance converter. BUSY brought high immediately following CONVST going low. BUSY stays high through conversion process returns when conversion ended data available pins. Once conversion started, cannot stopped except with asynchronous RESET logical PD1). CONVST detected high conversion, device immediately enters sampling mode analog input connected CDAC. Otherwise, CDAC connected analog input only when CONVST goes high. high duration CONVST should least There maximum high pulse duration specification CONVST. Reading Data ADS8422 outputs full parallel data complement format shown Table parallel output active when both low. There minimal quiet zone requirement around falling edge CONVST. This prior falling edge CONVST after falling edge. data read should attempted within this zone. other combination three-states parallel output. BYTE used multi-word read operation. BYTE used whenever lower bits output higher byte bus. Refer Table ideal output codes. Table Ideal Input Voltages Output Codes
DESCRIPTION Full scale range Least significant (LSB) +Full scale Midscale Midscale -Full scale ANALOG VALUE 2Vref 2Vref)/65536 (+Vref) -Vref+ BINARY CODE 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 CODE 7FFF 0000 FFFF 8000 DIGITAL OUTPUT STRAIGHT BINARY
output data read full 16-bit word pins DB15 (MSB-LSB) BYTE low. result also read 8-bit convenience. This done using only pins DB15-DB8. this case reads necessary: first before, leaving BYTE reading most significant bits pins DB15-DB8, then bringing BYTE high. When BYTE high, bits (D7-D0) appear pins DB15-DB8. These multi-word read operations performed with multiple active (toggling) signal with signal tied simplicity. Table Conversion Data Read
DATA READ BYTE High PINS DB15-DB8 PINS DB7-DB0 One's
RESET
RESET asynchronous active input signal. Maximum RESET time avoid powerdown. Current conversion aborted later than after converter reset mode. converter returns normal operation mode later than after RESET input brought high. converter provides power saving options: powerdown (using PD1) analog output powerdown (PD2).
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SLAS512 JUNE 2006
powerdown activated turning supply asserting longer than signal asserted less than only reset ongoing conversion aborted. Figure Device operation resumed from full powerdown either turning power supply de-asserting pin. Table Effects RESET, PD1,
COMMAND RESET APPLICATION TIME POWER WHEN APPLIED change RESUME TIME
LAYOUT
optimum performance, care should taken with physical layout ADS8422 circuitry. ADS8422 offers single-supply operation, often used close proximity with digital logic, microcontrollers, microprocessors, digital signal processors. more digital logic present design higher switching speed, more difficult achieve good performance from converter. basic architecture sensitive glitches sudden changes power supply, reference, ground connections, digital inputs that occur just prior latching output analog comparator. Thus, driving single conversion n-clock converter, there windows which large external transient voltages affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. period before BUSY falls should kept free supply glitches. degree error digital output depends reference voltage, layout, exact timing external event. average, ADS8422 draws very little current from external reference reference voltage internally buffered. reference voltage external originates from amp, make sure that drive bypass capacitor capacitors without oscillation. 0.1-µF bypass capacitor recommended from directly REFM (pin 48). REFM AGND should shorted same ground plane underneath device. AGND, BDGND, AGND pins should connected clean ground point. cases, this should analog ground. Avoid connections which close grounding point microcontroller digital signal processor. required, ground trace directly from converter power supply entry point. ideal layout consists analog ground plane dedicated converter associated analog circuitry. with AGND connections, should connected +5-V power supply plane trace that separate from connection digital logic, until they connected power entry point. Power ADS8422 should clean well bypassed. 0.1-µF ceramic bypass capacitor should placed close device possible. Table capacitor placement. addition, 1-µF 10-µF capacitor recommended. some situations, additional bypassing required, such 100-µF electrolytic capacitor even filter made inductors capacitors designed essentially low-pass filter +5-V supply, thus removing high frequency noise. Table Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE SUPPLY PINS pairs that require shortest path decoupling capacitors Pins that require decoupling CONVERTER ANALOG SIDE (4,5), (9,8), (10,12), (13,15), (43,44), (46,45) CONVERTER DIGITAL SIDE (24,25)
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APPLICATION INFORMATION MICROPROCESSOR INTERFACING
ADS8422 8-Bit Microcontroller Interface Figure shows parallel interface between ADS8422 typical microcontroller using 8-bit data bus. BUSY signal used falling edge interrupt microprocessor.
Analog
AGND Input Analog Input
REFIN REFM AGND Micro Controller AD[7:0] Data D[15:0]
Address Decoder
Supply +VBD +2.7
Digital Ground BDGND
Figure ADS8422 Application Circuitry
Analog
AGND
REFOUT REFM REFIN AGND
AGND
ADS8422
Figure ADS8422 Using Internal Reference
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PD1/RESET ADS8422 BYTE +VBD RESET BDGND CONVST BUSY DB[15:0]
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device ADS8422IBPFBR ADS8422IBPFBT ADS8422IPFBR ADS8422IPFBT PADS8422IBPFBT PADS8422IPFBT
Status PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW PREVIEW
Package Type TQFP TQFP TQFP TQFP TQFP TQFP
Package Drawing
Pins Package Plan 1000 1000
Lead/Ball Finish Call Call Call Call Call Call
Peak Temp Call Call Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MTQF019A JANUARY 1995 REVISED JANUARY 1998
(S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,50
0,27 0,17
0,08
0,13 5,50 7,20 6,80 9,20 8,80 0,05 1,05 0,95 Seating Plane 0,75 0,45 Gage Plane 0,25
1,20
0,08 4073176 10/96
NOTES: linear dimensions millimeters. This drawing subject change without notice. Falls within JEDEC MS-026
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SLAS512 JUNE 2006 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENT

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