512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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LP62E16512-T Series
512K VOLTAGE CMOS SRAM
Document Title 512K VOLTAGE CMOS SRAM Revision History
History
Initial issue Final version release Pb-Free package type
Issue Date
April 2002 July 2003 August 2004
Remark
Preliminary Final
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
512K VOLTAGE CMOS SRAM
Features
Operating voltage: 1.65V 2.2V Access times: (max.) Current: Very power version: Operating: 40mA (max.) Standby: 10µA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Data retention voltage: 1.2V (min.) Available 48-ball packages
General Description
LP62E16512-T operating current 8,388,608-bit static random access memory organized 524,288 words bits operates power voltage from 1.65V 2.2V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable input provided POWER-DOWN, device enable. byte enable inputs output enable input included easy interfacing. Data retention guaranteed power supply voltage 1.2V.
Product Family Product Family
LP62E16512 Operating Temperature Range
Power Dissipation Speed
Data Retention (ICCDR, Typ.) 0.1µA Standby (ISB1, Typ.) 0.5µA Operating (ICC2, Typ.)
Package Type
-25°C +85°C
1.65V~2.2V
70ns
Typical values measured 1.8V, 25°C 100% tested. Data retention current 1.2V.
Configurations
(Chip Size Package) 48-pin View
I/O9 I/O10 I/O15 I/O16
I/O11 I/O12 I/O13 I/O14
I/O2 I/O4 I/O5 I/O6
I/O1 I/O3 I/O7 I/O8
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Block Diagram
1024 8192 DECODER
MEMORY ARRAY
I/O1 COLUMN INPUT DATA CIRCUIT
I/O9
INPUT DATA CIRCUIT
I/O8
I/O16
CONTROL CIRCUIT
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Description
Symbol Description Address Inputs Symbol Description
Higher Byte Enable Input (I/O9 I/O16) Output Enable Power Supply Ground Connection
I/O1 I/O16
Chip Enable Data Input/Output Write Enable Input Byte Enable Input (I/O1 I/O8)
Recommended Operating Conditions
-25°C 85°C)
Symbol Parameter Min. Typ. Max. Unit
Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load
1.65 -0.3
+0.4
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Absolute Maximum Ratings*
-0.5V +3.0V IN/OUT Volt GND. -0.5V 0.5V Operating Temperature, Topr .-25°C +85°C Storage Temperature, Tstg.-55°C +125°C Power Dissipation, 0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics -25°C 85°C, 1.65V 2.2V,
Symbol Parameter LP62E16512-70LLT Min. Max. Unit Conditions
Input Leakage Current
Output Leakage Current
VI/O
Active Power Supply Current
II/O Min. Cycle, Duty 100%,
ICC1 Dynamic Operating Current ICC2
II/O 0.2V, VCC-0.2V
0.2V 0.2V 1MHz II/O
Standby Current ISB1
0.2V 0.2V
VCC-0.2V VCC-0.2V 0.2V
Output Voltage Output High Voltage
-1.0
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Truth Table
I/O1 I/O8 Mode
I/O9 I/O16 Mode High High High Read High Read Write High Write High High
Current ISB1, ISB1, ISB1, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2,
High High High Read Read High Write Write High High High
Note:
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Characteristics -25°C +85°C, 1.65V 2.2V)
Symbol Parameter LP62E16512-70LLT Min. Read Cycle tAcs1 tAcs2 tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1 tCHZ2 tBHZ tOHZ Write Cycle tCW1 tCW2 tWHZ Write Cycle Time Chip Enable Write Byte Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Output Valid Chip Enable Output Byte Enable Output Output Enable Output Chip Disable Output High Byte Disable Output High Output Disable Output High Output Hold from Address Change Max. Unit
Note: tCLZ1 tCLZ2 tBLZ tOLZ tCHZ1, tCHZ2 tBHZ tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Timing Waveforms
Read Cycle 1(1,
Address
DOUT
Read Cycle 2(1,
Address
tACS1 tACS2 tCLZ1 tCLZ2 tCHZ1 tCHZ2
tBLZ5
tBHZ5
tOHZ5
tOLZ5 DOUT
Notes:
high Read Cycle. Device continuously enabled VIL, and, VIL. Address valid prior coincident with and, transition transition High. VIL. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tWR3
tAS1
tWP2
DATA tWHZ4
DATA
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tAS1 tCW1 tCW2 tWR3
DATA tWHZ4
DATA
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Timing Waveforms (continued)
Write Cycle (Byte Enable Controlled)
Address
tCW1 tCW2 tWR3
tAS1
tBW2
DATA tWHZ4 DATA
Notes: measured from address valid beginning Write. Write occurs during overlap (tWP, tBW) high CS2. measured from earliest going high going Write cycle. level high low. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 0.2V VCC-0.2V 0.8V Figures
30pF
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ1, tCLZ2 tBHZ tBLZ tOLZ, tCHZ1, tCHZ2 tOHZ, tWHZ,
Data Retention Characteristics -25°C 85°C) Symbol Parameter Min. Max. Unit Conditions
0.2V 0.2V VCC-0.2V 1.2V, ICCDR Data Retention Current 0.2*
Data Retention
0.2V 0.2V VCC-0.2V VCC-0.2V 0.2V
tCDR
Chip Disable Data Retention Time Operation Recovery Time Rising Time from Data Retention Voltage Operating Voltage
Retention Waveform
LP62E16512 70LLT
ICCDR: max. 0.1µA 25°C (0.2µA 40°C
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Data Retention Waveform Controlled)
DATA RETENTION MODE 1.65V tCDR 1.2V 0.2V 1.65V
Data Retention Waveform (CS2 Controlled)
DATA RETENTION MODE 1.65V tCDR 1.2V 1.65V
0.2V
Ordering Information Part
LP62E16512U-70LLT LP62E16512U-70LLTF Pb-Free
Access Time(ns)
Operating Current Max.(mA)
Standby Current Max.(uA)
Package
(August, 2004, Version 1.1)
AMIC Technology, Corp.
LP62E16512-T Series
Package Information 48LD Outline Dimensions (48TFBGA)
VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 0.25 Ball*A1 CORNER (48X)
unit:
0.10 0.20(4X)
SIDE VIEW
SEATING PLANE
Symbol Notes:
Dimensions MIN. -0.20 0.48 7.90 9.90 -0.30 NOM. -0.25 0.53 8.00 10.00 3.75 5.25 0.75 0.35 MAX. 1.20 0.30 0.58 8.10 10.10 -0.40
BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE. BALL OPENING SUBSTRATE 0.3mm (SMD) SUGGEST DESIGN LAND SIZE 0.3mm (NSMD)
(August, 2004, Version 1.1)
AMIC Technology, Corp.

512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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