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Document Title DRAM Revision History DRAM History Initi


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A48P3616
Document Title DRAM Revision History
DRAM
History
Initial issue
Issue Date
September 2005
Remark
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Feature
Latency Frequency Latency Maximum Operating Frequency (MHz) DDR466 DDR400 DDR333 DDR266 (43) (5T) (6K) (75B) Differential clock inputs Four internal banks concurrent operation Data mask (DM) write data. aligns transitions with transitions. Commands entered each positive edge; data data mask referenced both edges DQS. Burst lengths: Latency: 6K/75B, Auto Precharge option each burst access Auto Refresh Self Refresh Modes 15.6µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 compatible) VDDQ 2.5V 0.2V (6K/75B) VDDQ 2.6V 0.1V (5T/43) Lead-free Halogen-free product available
DRAM
Double data rate architecture: data transfers clock cycle. Bidirectional data strobe (DQS) transmitted received with data, used capturing data receiver. edge-aligned with data reads centeraligned with data writes.
General Description
128Mb SDRAM high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. internally configured quad-bank DRAM based Nanya's 110nm process. 128Mb SDRAM uses double-data-rate architecture achieve high-speed operation. double data rate architecture essentially prefetch architecture with interface designed transfer data words clock cycle pins. single read write access 128Mb SDRAM effectively consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, one-half-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. strobe transmitted SDRAM during Reads memory controller during Writes. edgealigned with data Reads center-aligned with data Writes. 128Mb SDRAM operates from differential clock crossing going high going referred positive edge CK). Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges
Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed. address bits registered coincident with Read Write command used select bank starting column location burst access. SDRAM provides programmable Read Write burst lengths locations. Auto Precharge function enabled provide self-timed precharge that initiated burst access. with standard SDRAMs, pipelined, multibank architecture SDRAMs allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided along with power-saving Power Down mode. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation. functionality described timing specifications included this data sheet Enabled mode operation.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Configuration
TSOP (II)
DRAM
Column Address Table
Organization Address Column Address Refresh 4K/64ms
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Block Diagram
DRAM
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Input/Output Functional Description
Symbol Type Function Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge Output (read) data referenced crossings (both directions crossing). Clock Enable: HIGH activates, deactivates, internal clock signals device input buffers output drivers. Taking provides Precharge Power Down Self Refresh operation (all banks idle), Active Power Down (row Active bank). synchronous power down entry exit, self refresh entry. asynchronous self refresh exit. must maintained high throughout read write accesses. Input buffers, excluding disabled during Power Down. Input buffers, excluding CKE, disabled during self refresh. standard pinout includes pin. Optional pinouts might include CKE1 different pin, addition CKE0, facilitate independent power down control stacked devices. Chip Select: commands masked when registered high. provides external bank selection systems with multiple banks. considered part command code. standard pinout includes pin. Optional pinouts might include different pin, addition allow upper lower deck selection stacked devices. Command Inputs: (along with define command being entered. Input Data Mask: input mask signal write data. Input data masked when sampled high coincident with that input data during Write access. sampled both edges DQS. Although pins input only, loading matches loading. During Read, driven high, low, floated. Bank Address Inputs: define which bank Active, Read, Write Precharge command being applied. also determines mode register extended mode register accessed during EMRS cycle. Address Inputs: Provide address Active commands, column address Auto Precharge Read/Write commands, select location memory array respective bank. sampled during Precharge command determine whether Precharge applies bank (A10 low) banks (A10 high). only bank precharged, bank selected BA0, BA1. address inputs also provide op-code during Mode Register command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data. x16, LDQS corresponds data DQ0- DQ7; UDQS corresponds data DQ8-DQ15 Connect: internal electrical connection present. Electrical connection present. Should connected second level assembly. Supply Supply Supply Supply Supply Power Supply: 2.5V 0.2V. Ground Power Supply: 2.5V 0.2V. Ground SSTL_2 reference voltage: (VDDQ
DRAM
Input
CKE, CKE1, CKE1
Input
Input
Input
Input
BA0,
Input
Input
Input/Output
DQS, LDQS, UDQS Input/Output VDDQ VSSQ VREF
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Absolute Maximum Ratings*
Symbol VIN, VOUT VDDQ TATG IOUT Parameter Voltage pins relative Voltage Inputs relative Voltage supply relative Voltage VDDQ supply relative Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Unit
DRAM
-0.5 VDDQ+
-0.5 +3.6 -0.5 +3.6 -0.5 +3.6 +150
Notes: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
DQS/DQ/DM Slew Rate
DDR266 (75B) DQS/DQ/DM Slew Rate DCSLEW DDR333 (6K) DDR400 (5T) DDR466 (43) V/ns
Parameter
Symbol
Unit
Note
Notes: Measured between (DC), (DC), (DC), (DC). DQS, input slew rate specified prevent double clocking data preserve setup hold times. Signal transition through region must monotonic.
Capacitance
Parameter Input Capacitance: Delta Input Capacitance: Input Capacitance: Other Input-only pins (except Delta Input Capacitance: Other Input-only pins (except Input/Output Capacitance: DQS, Delta Input/Output Capacitance: DQS, Symbol Delta Delta CI/O Delta CI/O 0.25 Unit Note
Notes: VDDQ 2.5V 0.2V (minimum range maximum range), 100MHz, 25°C, VODC VDDQ/2, VOPeak -Peak 0.2V. Although input-only pin, input capacitance this must model input capacitance pins. This required match input propagation times system.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Electrical Characteristics Operating Conditions (0°C VDDQ 2.5V 0.2V, 2.5V 0.2V, Characteristics)
Symbol VDDQ VSS, VSSQ VREF (DC) (DC) (DC) (DC) (DC) VIRatio Supply Voltage Supply Voltage Supply Voltage Supply Voltage Reference Voltage Termination Voltage (System) Input High (Logic Voltage Input (logic Voltage Input Voltage Level, Inputs Input Differential Voltage, Inputs Input Crossing Point Voltage, Inputs Matching Pulup Current Puldown Current Ratio Input Leakage Current Input VOUT VDD; (All other pins under test Output Leakage Current (DQs disabled; VOUT VDDQ Output Current: Nominal Strength Driver High current (VOUT= VDDQ -0.373V, VREF, VTT) current (VOUT= 0.373V, VREF, VTT) Parameter 0.49 VDDQ VREF 0.04 VREF 0.15 0.30 0.30 0.71 16.8 16.8 0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ VDDQ Unit Note
DRAM
Notes: Inputs recognized valid until VREF stabilizes. VREF expected equal VDDQ transmitting device, track variations level same. Peak-to-peak noise VREF exceed value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level ratio pullup current pulldown current specified same temperature voltage, over entire temperature voltage range, device drain source voltages 0.25 volts volts. given output, represents maximum difference between pullup pulldown drivers process variation.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Electrical Characteristics Operating Conditions
(0°C VDDQ 2.5V 0.2V, 2.5V 0.2V, Characteristics) Symbol IOHW IOLW Parameter Output Current: Half- Strength Driver High current (VOUT= VDDQ -0.763V, VREF, VTT) current (VOUT= 0.763V, VREF, VTT) Unit Note
DRAM
Notes: Inputs recognized valid until VREF stabilizes. VREF expected equal VDDQ transmitting device, track variations level same. Peak-to-peak noise VREF exceed value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level ratio pullup current pulldown current specified same temperature voltage, over entire temperature voltage range, device drain source voltages 0.25 volts volts. given output, represents maximum difference between pullup pulldown drivers process variation.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Normal Strength Driver Pulldown Pullup Characteristics
full variation driver pulldown current from minimum maximum process, temperature voltage will within outer bounding lines curve. recommended that "typical" IBIS pulldown curve within shaded region curve. full variation driver pullup current from minimum maximum process, temperature voltage will within outer bounding lines curve. recommended that "typical" IBIS pullup curve within shaded region curve. full variation ratio maximum minimum pullup pulldown current will exceed 1.7, device drain source voltages from 1.0. full variation ratio "typical" IBIS pullup "typical" IBIS pulldown current should unity 10%, device drain source voltages from 1.0. This specification design objective only. guaranteed. These characteristics intended obey SSTL_2 class standard. This specification intended SDRAM only.
DRAM
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Normal Strength Driver Pulldown Pullup Currents
Pulldown Current (mA) Voltage Typical Tycpial High 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pullup Current (mA) Tycpial Tycpial High -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
DRAM
Normal Strength Driver Evaluation Conditions
typical Temperature (Tambient) VDDQ Process conditions 2.5V Typical process Minimum 2.3V Slow-slow process Maximum 2.7V Fast-fast process
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Characteristics
(Notes apply following Tables; Electrical Characteristics Operating Conditions, Operating Conditions, Specifications Conditions, Electrical Characteristics Timing.) voltages referenced VSS. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. Outputs measured with equivalent load. Refer Output Load Circuit below. timing tests swing 1.5V test environment, input timing still referenced VREF crossing point parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals 1V/ns range between (AC) (AC). input level specifications defined SSTL_2 Standard (i.e. receiver effectively switches result signal crossing input level, remains that state long signal does ring back above (below) input (high) level.
DRAM
Output Load Circuit Diagrams
Input Operating Conditions VDDQ 2.5V 0.2V (6K/75B); VDDQ 2.6V 0.1V (5T/43), Characteristics) Symbol (AC) (AC) (AC) (AC) Parameter/Condition Input High (Logic Voltage, DQS, Signals Input (Logic Voltage, DQS, Signals Input Differential Voltage, Inputs Input Crossing Point Voltage, Inputs 0.62 0.5*VDDQ VREF 0.31 VREF 0.31 VDDQ 0.5* VDDQ Unit Note
Notes: Input slew rate 1V/ns. Inputs recognized valid until VREF stabilizes. magnitude difference between input level input level value expected equal 0.5*VDDQ transmitting device must track variations level same.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Specifications Conditions
VDDQ 2.5V 0.2V(6K/75B); VDDQ 2.6V 0.1V (5T/43), Characteristics) Symbol Parameter/Condition Operating Current: bank; active precharge; (min); inputs changing twice clock cycle; address control inputs changing once clock cycle Operating Current: bank; active read precharge; Burst (min); 2.5; IOUT 0mA; address control inputs changing once clock cycle Precharge Power Down Standby Current: banks idle; Power Down mode; (max) Idle Standby Current: (min); banks idle; (min); address control inputs changing once clock cycle Active Power Down Standby Current: bank active; Power Down mode; (max) Active Standby Current: bank; active precharge; (min); (min); tRAS (max); inputs changing twice clock cycle; address control inputs changing once clock cycle Operating Current: bank; Burst reads; continuous burst; address control inputs changing once clock cycle; outputs changing twice clock cycle; 2.5; IOUT Operating Current: bank; Burst writes; continuous burst; address control inputs changing once clock cycle; inputs changing twice clock cycle; Auto-Refresh Current: tRFC (min) Self-Refresh Current: 0.2V Operating current: Four bank; four bank interleaving with address control inputs randomly changing; data changing every transfer; (min); IOUT 0mA. DDR266 (75B) DDR333 DDR400 DDR466 (6K) (5T) (43) Unit Note 5.0ns 4.3ns
DRAM
IDD0
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5 IDD6
IDD7
Notes: specifications tested after device properly initialized. Enables on-chip refresh address counters.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Electrical Characteristics Timing Absolute Specifications
VDDQ 2.5V 0.2V (6K/75B); VDDQ 2.6V 0.1V (5T/43), Characteristics) Symbol Parameter output access time from DDR266 DDR333 DDR400 DDR466 Unit +0.6 +0.5 0.55 0.55 +0.6 +0.6 +0.4
tCL, 1-4, 1-4, 2-4,12
DRAM
Note
-0.75 +0.75 -0.70 +0.70 -0.65 +0.65 -0.6 -0.75 +0.75 -0.60 +0.60 -0.55 +0.55 -0.5 0.45 0.45 0.55 0.55 0.45 0.45 0.45 0.45 1.75 +0.7 +0.7 +0.45
tCL,
tDQSCK output access time from high-level width low-level width Clock cycle time tIPW tDIPW tDQSQ tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD input hold time input setup time Input pulse width input pulse width (each input) Data-out high-impedance time from Data-out low-impedance time from DQS-DQ skew (DQS associated signals) TSOP Package
0.55 0.55
0.45 0.45 1.75 -0.6 -0.6
0.55 0.55
0.45 0.45 1.75
1.75
1-4,5 1-4,5 1-4,7 1-4,6
2-4,9,11,12 2-4,9,11,12
-0.75 +0.75 -0.7 -0.75 +0.75 -0.7 +0.5
tCL,
+0.6 +0.6 +0.4
-0.6 -0.6
Minimum half period given cycle; Defined high (tCH) (tCL) time. Data output hold time from Data hold Skew Factor TSOP Package
tCL,
tHP, tQHS 0.75 0.75 0.35 0.35 0.40 0.25 0.60 1.25
tHP, tQHS 0.55 0.75 0.35 0.35 0.40 0.25 0.75 0.75 0.60 1.25
tHP, tQHS 0.72 0.35 0.35 0.40 0.25 0.60 1.28
tHP, tQHS 0.72 0.35 0.35 0.40 0.25 0.60 1.28
Write command latching transition
input high pulse width (write cycle) input pulse width (write cycle) falling edge setup time (write cycle) falling edge hold time from (write cycle) Mode register command cycle time
tWPRES Write preamble setup time tWPST tWPRE Write postamble Write postamble
Address control input hold time (fast slew rate) Address control input hold time (fast slew rate)
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Preliminary DRAM
Electrical Characteristics Timing Absolute Specifications (continued)
VDDQ 2.5V 0.2V (6K/75B); VDDQ 2.6V 0.1V (5T/43), Characteristics) Symbol Parameter Address control input hold time (slow slew rate) Address control input setup time (slow slew rate) Read preamble Read postamble Active Precharge command Active Active/Auto-refresh command period Auto-refresh Active/Auto-refresh command period Active Read write dalay Active read command with Autoprecharge Precharge command period Active bank Active bank command Write vecovery time DDR266 DDR333 DDR400 DDR466 Unit Note
2-4,10,11, 12,14 2-4,10,11, 12,14
tRPRE tRPST tRAS tRFC tRCD tRAP tRRD tDAL tWTR tPDEX tXSNR tXSRD tREFI
0.40 0.60 0.40 0.60 0.40 0.60 0.40 0.60 120,000 120,000 120,000 120,000
1-4,13
(tWR/tCK tRP/tCK
(tWR/tCK tRP/tCK
(tWR/tCK tRP/tCK
(tWR/tCK Auto precharge write recovery precharge time tRP/tCK Intemal write read command delay Power down exit time Exit self-refresh non-read command Exit self-refresh read command Average Periodic Refresh Interval
1-4,8
Notes: Input slew rate 1V/ns. input reference level (for timing reference point which cross; input reference level signals other than VREF. Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (Note VTT. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. specific requirement that valid (high, low, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from Hi-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from high this time, depending tDQSS. maximum eight Autorefresh commands posted given SDRAM device. command/address input slew rate 1.0V/ns. Slew rate measured between (AC) (AC). command/address input slew rate 0.5V/ns 1.0V/ns. Slew rate measured between (AC) (AC).
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
slew rates 1.0V/ns. These parameters guarantee device timing, they necessarily tested each device, they guaranteed design tester characterization. each terms parentheses, already integer, round next highest integer. equal actual system clock cycle time. example, DDR266B 2.5, tDAL (15ns/7.5ns) (20ns/7.5ns) input setup hold time derating table used increase case where input slew rate below V/ns. Input Slew Rate V/ns V/ns V/ns Delta (tIS) +100 Delta (tIH) Unit Note
DRAM
Electrical Characteristics Timing Absolute Specifications (continued)
Input slew rate based lesser slew rates determined either (AC) (AC) (DC) (DC), similarly rising transitions. These derating parameters guaranteed design tester characterization necessarily tested each device.
input setup hold time derating table used increase case where slew rate below
V/ns. Input Slew Rate V/ns V/ns V/ns Delta (tDS) +150 Delta (tDH) +150 Unit Note
slew rate based lesser slew rates determined either (AC) (AC) (DC) (DC), similarly rising transitions. These derating parameters guaranteed design tester characterization necessarily tested each device.
Delta Rise, Fall Derating table used increase case where slew rates differ. Input Slew Rate V/ns 0.25 V/ns V/ns Delta (tDS) +100 Delta (tDH) +100 Unit Note
Input slew rate based lesser slew rates determined either (AC) (AC) (DC) (DC), similarly rising transitions. Input slew rate based larger delta rise, fall rate delta rise, fall rate. delta rise, fall rate calculated [1/(slew rate [1/(slew rate example: slew rate V/ns; slew rate V/ns Delta rise, fall (1/0.5) (1/0.4) [ns/V] -0.5 ns/V Using table above, this would result increase These derating parameters guaranteed design tester characterization necessarily tested each device.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Commands
Truth Tables prvide reference commands supported SDRAM device. verbal description each commands follows.
DRAM
Truth Table Commands
Name (Function) Deselect (Nop) Openration (Nop) Active (Select Bank Activate Row) Read (Select Bank Activate Column, Start Read Burst) Write (Select Bank Activate Column, Start Write Burst) Burst Terminate Precharge (Deactivate Bank Banks) Auto Refresh Self Refresh (Enter Self Refresh Mode) Mode Register
Address Bank/Row Bank/Col Bank/Col Code Op-Code
Read Write AR/SR
Note
Note: high commands shown except Self Refresh. BA0, select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A11 provide op-code written selected Mode Register.) BA0-BA1 provide bank address A0-A11 provide address. BA0, provide bank address; A0-A8 provide column address; high enables Auto Precharge feature (non-persistent), disables Auto Precharge feature. LOW: BA0, determine which bank precharged. HIGH: banks precharged BA0, "Don't Care." This command auto refresh high; Self Refresh low. Internal refresh counter controls bank addressing; inputs I/Os "Don't Care" except CKE. Applies only read bursts with Auto Precharge disabled; this command undefined (and should used) read bursts with Auto Precharge enabled write bursts Deselect functionally interchangeable.
Truth Table Operation
Name (Function) Write Enable Write Inhibit Valid Note
Note: Used mask write data; provided coincident with corresponding data.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Register Definition
Mode Register Mode Register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode. Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power (except which self-clearing). Mode Register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A11 specify operating mode. Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements results unspecified operation.
DRAM
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable. burst length determines maximum number column locations that accessed given Read Write command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When Read Write command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst wraps within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both Read Write bursts.
Mode Register Operation
Operating Mode A11-A9 A6-A0 Valid Valid VS** Type Normal operation reset Normal operation Reset Vendor-Specific Test Mode Reserved Latency Latency Type Reserved Reserved (Option) Reserved (Option) Reserved Burst Type Type Sequential Interleave Burst Length Burst Length Type Reserved Reserved Reserved Reserved Reserved
Operating Mode
Note: VS** Vendor Specific must select Mode Register (vs. Extended Mode Register).
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition page
DRAM
Read Latency
Read latency, latency, delay, clock cycles, between registration Read command availability first burst output data. latency programmed clocks. Read command registered clock edge latency clocks, data available nominally coincident with clock edge Reserved states should used unknown operation incompatibility with future versions result.
Burst Definition
Burst Length Starting Column Address Order Accesses Within Burst Type Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
Note: burst length two, A1-A selects two-data-element block; selects first access within block. burst length four, A2-A selects four-data-element block; A0-A1 selects first access within block. burst length eight, A3-A selects eight-data- element block; A0-A2 selects first access within block. Whenever boundary block reached within given sequence above, following access wraps within block.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Operating Mode
normal operating mode selected issuing Mode Register Command with bits A7-A11 zero, bits A0-A6 desired values. reset initiated issuing Mode Register command with bits A9-A11 each zero, one, bits A0-A6 desired values. Mode Register command issued reset should always followed Mode Register command select normal operating mode. other combinations values A7-A11 reserved future and/or test modes. Test modes reserved states should used unknown operation incompatibility with future versions result.
DRAM
Enable/Disable
must enabled normal operation. enable required during power initialization, upon returning normal operation after having disabled purpose debug evaluation. automatically disabled when entering self refresh operation automatically re-enabled upon exit self refresh operation. time enabled, clock cycles must occur allow time internal clock lock externally applied clock before Read command issued. This reason introducing timing parameter tXSRD SDRAM's (Exit Self Refresh Read Command). Non- Read commands issued clocks after enabled EMRS command (tMRD) clocks after enabled self refresh exit command (tXSNR, Exit Self Refresh Non-Read Command).
Extended Mode Register
Extended Mode Register controls functions beyond those controlled Mode Register; these additional functions include enable/disable, output drive strength selection, output enable/disable, (NTC optional). These functions controlled settings shown Extended Mode Register Definition. Extended Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power. Extended Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements result unspecified operation.
Output Drive Strength
normal drive strength outputs specified SSTL_2, Class
Enable/Disable
signal optional DRAM output control used isolate module loads (DIMMs) from system memory means external switches when given module (DIMM) being accessed. function optional feature NANYA included SDRAM devices.
Extended Mode Register Definition
Operating Mode
Operating Mode A11-A3 A2-A0 Valid Type Normal Operation Other States Reserved
Type Disable Enable (Optional)
Drive Strength Type Normal Reserved
Type Enable Disable
Note: must select Extended Mode Register (vs. base Mode Register)
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Device Operations Deselect
Deselect function prevents commands from being executed SDRAM. SDRAM effectively deselected. Operations already progress affected.
DRAM
Precharge
Precharge command used deactivate (close) open particular bank open row(s) banks. bank(s) will available subsequent access specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank. precharge command treated there open that bank, previously open already process precharging.
Operation (NOP)
Operation (NOP) command used perform SDRAM. This prevents unwanted commands from being registered during idle wait states. Operations already progress affected.
Mode Register
mode registers loaded inputs A0-A11, while issuing Mode Register Command. mode register descriptions Register Definition section. Mode Register command only issued when banks idle bursts progress. subsequent executable command cannot issued until tMRD met.
Auto Precharge
Auto Precharge feature which performs same individual-bank precharge function described above, without requiring explicit command. This accomplished using enable Auto Precharge conjunction with specific Read Write command. precharge bank/row that addressed with Read Write command automatically performed upon completion Read Write burst. Auto Precharge non-persistent that either enabled disabled each individual Read Write command. Auto Precharge ensures that precharge initiated earliest valid stage within burst. This determined explicit Precharge command issued earliest possible time without violating tRAS(min). user must issue another command same bank until precharge (tRP) completed. SDRAM devices supports optional tRAS lockout feature. This feature allows Read command with Auto Precharge issued bank that been activated (opened) satisfied tRAS(min) specification. tRAS lockout feature essentially delays onset auto precharge operation until conditions occur. One, entire burst length data been successfully prefetched from memory array; two, tRAS(min) been satisfied. means specify whether SDRAM device supports tRAS lockout feature, parameter been defined, tRAP (RAS Command Read Command with Auto Precharge better stated Bank Activate Read Command with Auto Precharge). devices that support tRAS lockout feature, tRAP tRCD(min). This allows Read Command (with without Auto Precharge) issued open bank once tRCD(min) satisfied.
Active
Active command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A11 selects row. This remains active open) accesses until Precharge Read Write with Auto Precharge) issued that bank. Precharge Read Write with Auto Precharge) command must issued completed before opening different same bank.
Read
Read command used initiate burst read access active (open) row. value BA0, inputs selects bank, address provided inputs A0-A8 selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Read burst; Auto Precharge selected, remains open subsequent accesses.
Write
Write command used initiate burst write access active (open) row. value BA0, inputs selects bank, address provided inputs A0-A8 selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Write burst; Auto Precharge selected, remains open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered low, corresponding data written memory; signal registered high, corresponding data inputs ignored, Write executed that byte/column location.
Burst Terminate
Burst Terminate command used truncate read bursts (with Auto Precharge disabled). most re-cently registered Read command prior Burst Terminate command truncated, shown Operation section this data sheet. Write burst cycles terminated with Burst Terminate command.
Preliminary (September 2005, Version 0.0)
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A48P3616
Auto Refresh
Auto Refresh used during normal operation SDRAM analogous Before (CBR) Refresh previous DRAM types. This command nonpersistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during Auto Refresh command. 128Mb SDRAM requires Auto Refresh cycles average periodic interval 7.8µs (maximum). starting column bank addresses provided with Read command Auto Precharge either enabled disabled that burst access. Auto Precharge enabled, that accessed starts precharge completion burst, provided tRAS been satisfied. generic Read commands used following illustrations, Auto Precharge disabled. During Read bursts, valid data-out element from starting column address available following latency after Read command. Each subsequent data-out element valid nominally next positive negative clock edge (i.e. next crossing following timing figure entitled "Read Burst: Latencies (Burst Length=4)" illustrates general timing each supported latency setting. driven SDRAM along with output data. initial state known read preamble; state coincident with last data-out element known read postamble. Upon completion burst, assuming other commands have been initiated, goes High-Z. Data from Read burst concatenated with truncated with data from subsequent Read command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst which being truncated. Read command should issued cycles after first Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown timing figure entitled "Consecutive Read Bursts: Latencies (Burst Length 8)". Read command initiated positive clock cycle following previous Read command. Nonconsecutive Read data shown timing figure entitled "Non-Consecutive Read Bursts: Latencies (Burst Length 4)". Full-speed Random Read Accesses: Latencies (Burst Length within page pages) performed shown page
DRAM
Self Refresh
Self Refresh command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. Self Refresh command initiated Auto Refresh command coincident with transitioning low. automatically disabled upon entering Self Refresh, automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before Read command issued). Input signals except (low) "Don't Care" during Self Refresh operation. procedure exiting self refresh requires sequence commands. (and must stable prior returning high. Once high, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command.
Bank/Row Activation
Before Read Write commands issued bank within SDRAM, that bank must "opened" (activated). This accomplished Active command addresses A0-A11, (see Activating Specific Specific Bank), which decode select both bank activated. After opening (issuing Active command), Read Write command issued that row, subject tRCD specification. subsequent Active command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive Active commands same bank defined tRC. subsequent Active command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive Active commands different banks defined tRRD.
Latencies
Data from Read burst truncated with Burst Terminate command, shown timing figure entitled Terminating Read Burst: Latencies (Burst Length page Burst Terminate latency equal read (CAS) latency, i.e. Burst Terminate command should issued cycles after Read command, where equals number desired data element pairs. Data from Read burst must completed truncated before subsequent Write command issued. truncation necessary, Burst Terminate command must used, shown timing figure entitled Read Write: Latencies (Burst Length page example shown tDQSS(min). tDQSS(max) case, shown here, longer idle time. tDQSS(min) tDQSS(max) defined section Writes.
Reads
Subsequent programming mode register with latency, burst type, burst length, Read bursts initiated with Read command.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Read burst followed truncated with, Precharge command same bank (provided that Auto Precharge activated). Precharge command should issued cycles after Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown timing figure Read Precharge: Latencies (Burst Length page37 Read latencies 2.5. Following Precharge command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data elements. case Read being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same Read burst with Auto Precharge enabled. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
DRAM
first data element from burst applied after either last element completed burst last desired data element longer burst which being truncated. Write command should issued cycles after first Write command, where equals number desired data element pairs (pairs required prefetch architecture). Timing figure Write Write (Burst Length page shows concatenated bursts example nonconsecutive Writes shown timing figure Write Write: DQSS, Non-Consecutive (Burst Length page Fullspeed random write accesses within page pages performed shown timing figure Random Write Cycles (Burst Length page Data Write burst followed subsequent Read command. follow Write without truncating write burst, tWTR (Write Read) should shown timing figure Write Read: Non-Interrupting (CAS Latency Burst Length page Data Write burst truncated subsequent (interrupting) Read command. This illustrated timing figures "Write Read: Interrupting (CAS Latency Burst Length 8)", "Write Read: Minimum DQSS, Number Data Write), Interrupting (CAS Latency Burst Length 8)", "Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length 8)". Note that only data-in pairs that registered prior tWTR period written internal array, subsequent data-in must masked with shown diagrams noted previously. Data Write burst followed subsequent Precharge command. follow Write without truncating write burst, should shown timing figure Write Precharge: Non-Interrupting (Burst Length page Data Write burst truncated subsequent Precharge command, shown timing figures Write Precharge: Interrupting (Burst Length page Write Precharge: Nominal DQSS Write), Interrupting (Burst Length page Note that only data-in pairs that registered prior period written internal array, subsequent data should masked with Following Precharge command, subsequent command same bank cannot issued until met. case Write burst being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same burst with Auto Precharge. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
Writes
Write bursts initiated with Write command, shown timing figure Write Command page starting column bank addresses provided with Write command, Auto Precharge either enabled disabled that access. Auto Precharge enabled, being accessed precharged completion burst. generic Write commands used following illustrations, Auto Precharge disabled. During Write bursts, first valid data-in element registered first rising edge following write command, subsequent data elements registered successive edges DQS. state between Write command first rising edge known write preamble; state following last data-in element known write postamble. time between Write command first corresponding rising edge (tDQSS) specified with relatively wide range (from 125% clock cycle), most Write diagrams that follow drawn extreme cases (i.e. tDQSS(min) tDQSS(max)). Timing figure Write Burst (Burst Length page shows extremes tDQSS burst four. Upon completion burst, assuming other commands have been initiated, enters High-Z additional input data ignored. Data Write burst concatenated with truncated with subsequent Write command. either case, continuous flow input data maintained. Write command issued positive edge clock following previous Write command.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Precharge
Precharge command used deactivate open particular bank open banks. bank(s) available subsequent access some specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank.
DRAM
Power Down
Power Down entered when registered accesses progress). Power Down occurs when banks idle, this mode referred Precharge Power Down; Power Down occurs when there active bank, this mode referred Active Power Down. Entering Power Down deactivates input output buffers, excluding CKE. still running Power Down mode, maximum power savings, user option disabling prior entering Power Down. that case, must enabled after exiting Power Down, clock cycles must occur before Read command issued. Power Down mode, stable clock signal must maintained inputs SDRAM, other input signals "Don't Care". However, Power Down duration limited refresh requirements device, most applications, self refresh mode preferred over DLL-disabled Power Down mode. Power Down state synchronously exited when registered high (along with Deselect command). valid, executable command applied clock cycle later.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Latencies
DRAM
tRAP Definition
Note: above timing diagrams show effects tRAP devices that support tRAS lockout. these cases, Read with Auto Precharge command (RDA) issued with tRCD(min) dataout available with shortest latency from Bank Activate command (ACT). internal precharge operation, however, does begin until after tRAS(min) satisfied.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Activating Specific Specific Bank
DRAM
tRCD tRRD Definition
Read Command
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Precharge Command
DRAM
Power Down
Preliminary (September 2005, Version 0.0)
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A48P3616
Clock Enable (CKE)
Current Self Refresh Self Refresh Power Down Power Down Banks Idle Banks Idle Bank(s) Active
Previous Cycle
DRAM
Previous Cycle
Command Deselect Deselect Deselect Auto Refresh Deselect "Truth Table Current State Bank Command Bank (Same Bank)" page
Action Maintain Self-Refresh Exit Self-Refresh Maintain Power Down Exit Power Down Precharge Power Down Entry Self Refresh Entry Active Power Down Entry
Note
Note: logic state clock edge state previous clock edge. Current state state SDRAM immediately prior clock edge Command command registered clock edge action result command states sequences shown illegal reserved. Deselect commands should issued clock edges occurring during Self Refresh Exit (tXSNR) period. minimum clock cycles needed before applying read command allow lock input clock.
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Current State Bank Command Bank (Same Bank) Current State
DRAM
Command Deselect Operation Active Auto Refresh Mode Register Read Write Precharge Read Precharge Burst Terminate Read Write Precharge Action
NOP. Continue previous operation NOP. Continue previous operation
Note 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6,
Select Activate
Idle
Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Select column start Read Burst Select column start Write Burst
Deactivate bank(s)
Select column start Read Burst
Burst Terminate
Select column start Read Burst Select column start Write Burst
Truncate Write burst, start Precharge
Note: This table applies when high high (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table bank-specific, except where noted, i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. following states must interrupted command issued same bank. Precharging: Starts with registration Precharge command ends when met. Once met, bank idle state. Activating: Starts with registration Active command ends when tRCD met. Once tRCD met, bank "row active" state. Read w/Auto Precharge Enabled: Starts with registration Read command with Auto Precharge enabled ends when been met. Once met, bank idle state. Write w/Auto Precharge Enabled: Starts with registration Write command with Auto Precharge enabled ends when been met. Once met, bank idle state. Deselect commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state according Truth Table following states must interrupted executable command; Deselect commands must applied each positive clock edge during these states. Refreshing: Starts with registration Auto Refresh command ends when tRFC met. Once tRFC met, SDRAM "all banks idle" state. Accessing Mode Register: Starts with registration Mode Register command ends when tMRD been met. Once tMRD met, SDRAM "all banks idle" state. Precharging All: Starts with registration Precharge command ends when met. Once met, banks idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; all/any banks precharged, all/any must valid state precharging. bank-specific; Burst terminate affects most recent Read burst, regardless bank. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking.
Preliminary (September 2005, Version 0.0)
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A48P3616
Current State Bank Command Bank (Different bank) Current State Idle Activating, Active, Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
DRAM
Command Deselect Operation Command Otherwise Allowed Bank Active Read Write Precharge Active Read Precharge Active Read Write Precharge Action
NOP/Continue previous operation NOP/Continue previous operation
Note
Select Activate Select column start Read Burst Select column start Write Burst
Select Activate
Select column start Read Burst
Select Activate
Select column start Read Burst Select column start Write Burst
Note: This table applies when high high (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table describes alternate bank operation, except where noted, i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: note Write with Auto Precharge Enabled: note Auto Refresh Mode Register commands only issued when banks idle. Burst Terminate command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. Write command applied after completion data output. Read with Auto Precharge enabled Write with Auto Precharge enabled states each broken into parts: access period precharge period. Read with Auto Precharge, precharge period defined same burst executed with Auto Precharge disabled then followed with earliest possible Precharge command that still accesses data burst. Write with Auto Precharge, precharge period begins when ends, with measured Auto Precharge disabled. access period starts with registration command ends where precharge period tRP) begins. During precharge period Read with Auto Precharge Enabled Write with Auto Precharge Enabled states, Active, Precharge, Read, Write commands other bank applied; during access period, only Active Precharge commands other bank applied. either case, other related limitations apply (e.g. contention between Read data Write data must avoided).
Preliminary (September 2005, Version 0.0)
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A48P3616
Current State Bank Command Bank (Different bank) (continued)
Current State Read (With Auto Precharge) Write (With Auto Precharge)
DRAM
Command Active Read Write Precharge Active Read Write Precharge
Action
Select Activate
Note 1-7, 1-7, 1-7, 1-7,
Select column start Read Burst Select column start Write Burst
Select Activate
Select column start Read Burst Select column start Write Burst
Note: This table applies when high high (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table describes alternate bank operation, except where noted, i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: note Write with Auto Precharge Enabled: note Auto Refresh Mode Register commands only issued when banks idle. Burst Terminate command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. Write command applied after completion data output. Read with Auto Precharge enabled Write with Auto Precharge enabled states each broken into parts: access period precharge period. Read with Auto Precharge, precharge period defined same burst executed with Auto Precharge disabled then followed with earliest possible Precharge command that still accesses data burst. Write with Auto Precharge, precharge period begins when ends, with measured Auto Precharge disabled. access period starts with registration command ends where precharge period tRP) begins. During precharge period Read with Auto Precharge Enabled Write with Auto Precharge Enabled states, Active, Precharge, Read, Write commands other bank applied; during access period, only Active Precharge commands other bank applied. either case, other related limitations apply (e.g. contention between Read data Write data must avoided).
Preliminary (September 2005, Version 0.0)
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A48P3616
Simplified State Diagram
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Read Burst: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Consecutive Read Bursts: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Non-Consecutive Read Bursts: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Random Read Accesses: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Terminating Read Burst: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Read Write: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Read Precharge: Latencies (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Write Command
DRAM
Preliminary (September 2005, Version 0.0)
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Write Burst (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Write Write (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Write Write: DQSS, Non-Consecutive (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Random Write Cycles (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Write Read: Non-Interrupting (CAS Latency Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Write Read: Interrupting (CAS Latency Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Preliminary DRAM
Write Read: Minimum DQSS, Number Data Write), Interrupting(CAS Latency Burst Length
Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.
A48P3616
Write Precharge: Non-Interrupting (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Write Precharge: Interrupting (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
(Burst Length
DRAM
Write Precharge: Minimum DQSS, Number Data Write), Interrupting
Write Precharge: Nominal DQSS Write), Interrupting (Burst Length
Preliminary (September 2005, Version 0.0)
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Data Input (Write) (Timing Burst Length
DRAM
Data Output (Read) (Timing Burst Length
Preliminary (September 2005, Version 0.0)
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Initialize Mode Register Sets
DRAM
Preliminary (September 2005, Version 0.0)
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Power Down Mode
DRAM
Preliminary (September 2005, Version 0.0)
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Auto Refresh Mode
DRAM
Preliminary (September 2005, Version 0.0)
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Self Refresh Mode
DRAM
Preliminary (September 2005, Version 0.0)
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Read without Auto Precharge (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Read with Auto Precharge (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Bank Read Access (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Write without Auto Precharge (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Write with Auto Precharge (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Bank Write Access (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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A48P3616
Write Operation (Burst Length
DRAM
Preliminary (September 2005, Version 0.0)
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Package Dimensions (400mil; lead TSOP Package)
DRAM
Preliminary (September 2005, Version 0.0)
AMIC Technology, Corp.

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