Standard Definition Video Reconstruction Filter Buffer MAX7428 lo
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Standard Definition Video Reconstruction Filter Buffer
MAX7428 low-cost, high-performance replacement standard discrete filter buffer solutions. MAX7428 ideal anti-aliasing smoothing video applications, when analog video reconstructed from digital data stream. MAX7428 requires single supply filter cutoff frequency optimized NTSC, PAL, standard definition digital (SDTV) video signals. MAX7428 features Maxim's single (MSPBTM) interface digitally control channel selection (INA INB), adjust high-frequency boost, bypass filter, configure luma versus chroma operation, control output disable. single capacitor allows program MAX7428 chip address. devices with unique addresses connected same bus. MAX7428 single channel filter ideal composite (CVBS) video signals. Multiple MAX7428s combined filter S-Video (Y/C) component video signals. MAX7428 available tiny 8-pin SOT23 package fully specified over -40°C +85°C extended temperature range. MAX7428EVKIT available reduce design time.
Features
Ideal CVBS, (S-Video), Outputs NTSC, PAL, SDTV 6th-Order Continuous Time Lowpass Filter Drives Video Loads Four Levels Passband High-Frequency Boost Control Input Multiplexer Output Disable Filter Bypass Single-Supply Voltage Tiny 8-pin SOT23 Package
MAX7428
Ordering Information
PART MAX7428EKA TEMP. RANGE -40°C +85°C PINPACKAGE SOT23 MARK AAIU
Applications
Set-Top Boxes Players Hard-Disk Recorders Camcorders
MSPB trademark Maxim Integrated Products Configuration appears data sheet.
Functional Diagram
SYNCIO SERIAL INTERFACE CONTROL DATA
SYNC MAX7428
6TH-ORDER FILTER +6dB
LEVEL SHIFT
ENCODER BIAS GENERATOR REXT
INPUT
*OPTIONAL
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Standard Definition Video Reconstruction Filter Buffer MAX7428
ABSOLUTE MAXIMUM RATINGS
.+6V Other Pins .-0.3V (VCC 0.3V) Maximum Current Into .±50mA Continuous Power Dissipation +70°C) 8-Pin SOT23 (derate 9.52mW/°C above +70°C).762mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-65°C +150°C Junction Temperature .+150°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC ±10%, RREXT 300k ±1%, CREXT (1nF 1µF) ±1%, CLOAD 20pF; BOOST0, BOOST1 TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Passband Response Stopband Attenuation Boost Relative Step Size, Four Levels Differential Gain Differential Phase Harmonic Distortion Signal-to-Noise Ratio Group Delay Deviation Line Time Distortion Field Time Distortion Clamp Settling Time Output Clamp Level Frequency Gain Output Short-Circuit Current Input Leakage Current Input Dynamic Swing Supply Range Supply Current Power-Supply Rejection INA/INB Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage YINPP CINPP load 100mVp-p, 7MHz 100mVp-p, 7MHz CLEVEL CLEVEL Hdist Vdist tclamp SYMBOL CONDITIONS 4.2MHz relative 100kHz 4.2MHz 5.5MHz relative 4.2MHz 25MHz 4.2MHz 5MHz 5-step modulated staircase 5-step modulated staircase 100kHz 5MHz Peak signal (2Vp-p) noise (100Hz 50MHz band) Deviation from 100kHz 3.58/4.43MHz 18µs lines, 18µs, (Note (Note CLEVEL CLEVEL Gain 100kHz shorted ground 1.35 1.75 ±0.1 ±0.1 UNITS Degrees Lines Vp-p
Standard Definition Video Reconstruction Filter Buffer
ELECTRICAL CHARACTERISTICS (continued)
(VCC ±10%, RREXT 300k ±1%, CREXT (1nF 1µF) ±1%, CLOAD 20pF; BOOST0, BOOST1 TMIN TMAX, unless otherwise noted. Typical values +25°C.)
PARAMETER Logic Input Voltage Logic Input Current Logic Output High Voltage Logic Output Voltage SYMBOL (source) (sink) ISOURCE 500µA ISINK 500µA CONDITIONS UNITS
MAX7428
MSPB TIMING SPECIFICATIONS
(VCC ±10%, RREXT 300k ±1%, CREXT (1nF 1µF) ±1%; TMIN TMAX, unless otherwise noted. Typical values +25°C.) (Figures through
PARAMETER MSPB TIMING Logic Zero/Prompt Pulse Width Logic Pulse Width Transaction Pulse Width Separation Between Pulses Release Time Host After Prompt Pulse Reclaim Time Host After Prompt Pulse Read Back Data Valid Window After Prompt Pulse tSEP tRELEASE tRECLAIM tREAD SYMBOL CONDITIONS UNITS
Note horizontal line 63.5µs.
Standard Definition Video Reconstruction Filter Buffer MAX7428
Typical Operating Characteristics
(VCC +5V, RREXT 300k; BOOST0, BOOST1 1VP-P, +25°C, unless otherwise noted.)
AMPLITUDE FREQUENCY
MAX7428 toc01
PASSBAND AMPLITUDE FREQUENCY
AMPLITUDE (dB)
MAX7428 toc02
PHASE RESPONSE FREQUENCY
MAX7428 toc03
AMPLITUDE (dB)
PHASE (DEGREES) -120 -180
BOOST1, BOOST0 BOOST1, BOOST0 BOOST1, BOOST0 BOOST1, BOOST0 FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
GROUP DELAY FREQUENCY
MAX7428 toc04
RESPONSE (1IRE 7.14mV)
MAX7428 toc05
MODULATED 12.5T RESPONSE (1IRE 7.14mV)
MAX7428 toc06
GROUP DELAY (ns) FREQUENCY (MHz)
200mV/div
200mV/div
200mV/div
200mV/div
200ns/div
400ns/div
SUPPLY CURRENT TEMPERATURE
MAX7428 toc07
DIFFERENTIAL GAIN DIFFERENTIAL PHASE
MAX7428 toc08
SUPPLY CURRENT (mA) LOAD
DIFFERENTIAL GAIN
-0.1 -0.2 -0.3
0.00 -0.01 -0.04 -0.08 -0.10 -0.06
DIFFERENTIAL PHASE (DEGREES)
0.20 0.15 0.10 0.05 0.00 -0.05
0.00 0.04
0.06
0.06
0.04 0.02
1st.
2nd.
3rd.
4th.
5th.
6th.
TEMPERATURE (°C)
Standard Definition Video Reconstruction Filter Buffer
Typical Operating Characteristics (continued)
(VCC +5V, RREXT 300k; BOOST0, BOOST1 1VP-P, +25°C, unless otherwise noted.)
OUTPUT IMPEDANCE FREQUENCY
IMPEDANCE FREQUENCY (MHz) 200ns/div 500mV/div
MAX7428 toc09
MAX7428
OUTPUT TRANSIENT INPUT SWITCHING
MAX7428 toc10
Description
NAME SYNCIO DATA REXT Video Input Supply Voltage Video Input Ground Sync Pulse Input Output Serial Data Interface External Resistor. Connect 300k resistor from REXT internal biasing. Connect capacitor from REXT chip address programming (see Table Buffer Output FUNCTION
Standard Definition Video Reconstruction Filter Buffer MAX7428
220µF
OPTIONAL
0.1µF ENCODER 0.1µF INPUT DATA SYNCIO REXT
220µF
OPTIONAL
MAX7428
300k
SERIAL SYNC PULSE
(SEE TABLE *NEEDED ONLY FILTER BYPASS MODE
Figure MAX7428 Typical Application Circuit
Detailed Description
MAX7428 filters buffers outputs DACs encoder chipsets that process digital video information applications such boxes, hard-disk recorders, players, recorders, digital VCRs. These devices also filter "clean-up" analog video signals. MAX7428 includes input select input channel, 6th-order Sallen-Key filter with four adjustable high-frequency boost levels, output buffer with gain, sync separator clamp, external resistor internal bias levels. Output disable adds additional multiplexing wiredOR configuration. Filter bypass, conjunction with inputs, used provide filtered unfiltered video signal processing. Maxim's single (MSPB) interface controls above features. external capacitor used assign each device unique address which allows control devices same bus. Figure shows typical application circuit.
Filter
Filter Response reconstruction filter consists 6th-order Butterworth filter three second-order stages. Butterworth filter features maximally flat passband NTSC bandwidths. stopband offers typically 50dB attenuation sampling frequencies 25MHz above (see Typical Operating Characteristics). corner frequency critical since response filter meets both stopband passband specifications. MAX7428 incorporates autotrimming feature that reduces corner frequency variation digitally. possible, although likely, that discrete shift corner frequency occur external environmental change. autotrimming operates continuously that corner frequency remains centered over full operating temperature range. High-Frequency Boost high-frequency boost compensates signal degradation roll-off signal path prior MAX7428. High-frequency boost programmable four steps increase image sharpness.
Input Considerations
0.1µF ceramic capacitor AC-couple input MAX7428. This input capacitor stores level level-shift input signal optimal point between GND. ABSEL Control Register sets which channel (INA INB) selected (Control Register section). inputs have typical input resistance 50k.
Output Buffer
output buffer able drive video loads with 2VP-P signal. +6dB gain output buffer independent filter bypass input selection. output buffer drives backmatch resistors
Standard Definition Video Reconstruction Filter Buffer MAX7428
Table Control Register
(MSB) NAME DEFAULT SYNCIO ABSEL BYPASS CLEVEL BOOST1 BOOST0 OUTDISABLE FIRST (LSB)
series capacitor (typically 220µF). OUTDISABLE control register disables output (mute) (Control Register section). MAX7428 able drive video load directly without using 220µF capacitor. This feature very viable SCART applications.
Filter Bypass
MAX7428 offers selectable filter bypassing that allows either video inputs filtered unfiltered. optional input resistors needed only filter bypass mode. This ensures proper discharge input coupling capacitors.
SYNCIO: SYNCIO Select bit. logic sets SYNCIO function output while logic sets SYNCIO function input. ABSEL: Channel Select bit. logic selects input processed while logic selects input processed. BYPASS: Filter Bypass Select bit. logic selects filter while logic bypasses filter. CLEVEL: Clamp Level bit. logic selects clamp level (luma) video signal while logic selects clamp level 1.5V (chroma) video signal. [BOOST1, BOOST0]: High-Frequency Boost Control bits. adjust bits select amount high frequency boost filter. Table defines levels adjustment (see Typical Operating Characteristics). OUTDISABLE: Output Disable bit. logic selects normal operation while logic places output high-impedance state.
Serial Interface
Maxim's Single (MSPB) interface uses DATA transfer data from microprocessor (µP) MAX7428. This negative logic protocol uses three different pulse widths represent logic "1", logic "0", control commands. MSPB allows devices connected same assigning unique 4-bit identification address each device. communicate each device individually sending "broadcast" message devices. unique address each device means time constant external capacitor connected parallel with external 300k resistor (Initializing MAX7428 section).
Applications Information
Maxim's Single (MSPB) Serial Interface
MSPB interface uses three pulses different widths represent commands data bits. Figure shows pulses that single interface uses communicate with device. combination pulse (t1), zero pulse (t0), transaction pulse (tT), prompt pulse writes reads back from, sends broadcast data devices bus. Note: zero pulse prompt pulse same. Initialization pulses significantly longer used only power-up software reset.
Control Register
Table defines structure 8-bit control register programmed MSPB. This register controls selection input SYNCIO functionality, filter bypassing, clamp level selection, high-frequency boost control, output disable. Maxim's Single Interface (MSPB) Serial Interface section detailed programming instructions.
Table Boost Level Programming
BOOST1 BOOST0 RELATIVE HIGH FREQUENCY BOOST 0.3db 0.5db 0.6db 1.0db 0.9db 1.5db
Standard Definition Video Reconstruction Filter Buffer MAX7428
Table Initialization Capacitor Values Pulse Widths (CREXT ±10% Tolerance, RREXT Tolerance)
CAPACITOR VALUE (nF) 1000 INITIALIZING WAIT PERIOD (ms) (tINTWAIT) 20.000 13.600 9.400 4.400 3.000 2.000 1.360 0.940 0.440 0.300 0.200 0.136 0.094 0.044 0.030 0.020 INITIALIZING TIME PERIOD (ms) WITH RREXT 300k (tINT) (136.8) 52.6 (44.1) 35.90 23.90 (13.7) 16.25 11.21 (4.4) 5.26 3.59 2.39 1.625 (1.37) 1.121 0.526 (0.441) 0.359 0.239 0.162 (0.137) (144) 55.4 (46.4) 37.80 25.20 (14.4) 17.10 11.80 (4.64) 5.54 3.78 2.52 1.710 (1.44) 1.180 0.554 (0.464) 0.378 0.252 0.171 (0.144) (151.2) 58.2 (48.72) 39.70 26.50 (15.1) 17.95 12.39 (4.9) 5.82 3.97 2.65 1.795 (1.51) 1.239 0.582 (0.487) 0.397 0.265 0.179 (0.151)
Note: Indicates time periods associated with capacitors. This limits total number devices seven.
Initializing MAX7428
Initialization performed only after power-up software reset. assigns unique address each device bus. time constant capacitor connected REXT parallel with 300k resistor determines order which devices initialized (address assigned). device with largest time constant initialized first descending order. Table shows "Initialize Wait" "Initialize Time" pulse widths needed specific capacitor value tolerance. Program each device with this command sequence starting with device with biggest capacitor. reinitialize device, cycle power software reset. following command sequence timing diagram (Figure initialization.
Initialization Command Sequence: Initialize wait T011 Initialize Chip 4-bits T111
ZERO/PROMPT PULSE
PULSE
30µs
TRANSACTION PULSE
100µs
INTIALIZATION PULSE
tINT
tINT TABLE
Figure MSPB Interface Pulses
Programming MAX7428
address sequence precedes write read operation determine with which device communicate. address transmitted this mode matches with
device's address, device initiate data transfer. following command sequence timing diagram (Figure address command sequence.
Standard Definition Video Reconstruction Filter Buffer MAX7428
tSEP tINTWAIT tINT EXAMPLE ADDRESS: 0001
Figure Initialization Timing Diagram
tSEP
EXAMPLE ADDRESS: 0001
Figure Address Timing Diagram
tSEP
EXAMPLE DATA: 1***000
Figure Write Timing Diagram
Address Command Sequence: T010 Address 4-bits T111
Read Command Sequence: T101 Prompts T111
write sequence load data into data register device. must follow address sequence. Transmit minimum eight data bits make this sequence valid starting with first. last 8bits used more than eight bits transmitted. following command sequence timing diagram (Figure writing.
Write Command Sequence: T001 Data 8-bits (See Table T111
broadcast sequence writes data control registers devices same time. Write data with again. following command sequence timing diagram (Figure broadcast transaction. address required.
Broadcast Command Sequence: T000 Data 8-bits T111
During read sequence, sends prompt pulse causing device output data word first. Similar write transaction, readback transaction must preceded address sequence. more than eight prompts available, device outputs same data starting with again. following command sequence timing diagram (Figure readback.
Executing software reset solves same function hardware reset achieved transmitting data bits (eight more) ones. reset individual device, send address sequence that specific device followed writing eight ones register.
Standard Definition Video Reconstruction Filter Buffer MAX7428
tSEP tREF tREAD
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
READS
READS
REPEAT READ MORE BITS
(tRELEASE): WILL RELEASE TIME START READING TIME
UNTIL TIME FINISH READING (tRECLAIM): DEVICE WILL RELEASE TIME
NOTE: TIME REFERENCED
Figure Read Timing Diagram
tSEP
DATA: 1***000
Figure Broadcast Timing Diagram
Software Reset Command Sequence: T000 T010 T001 Eight more ones Address 4-bits Eight more ones T111 T111 T111
(CLEVEL clamping level signal should +1.5V (CLEVEL
Composite Video Filtering
MAX7428 ideally suited filtering composite video signals. Program SYNCIO output when processing composite video signals. rare occasion where external sync pulse needed process composite video, program SYNCIO input. When processing composite video clamp level (CLEVEL
Video Filtering
MAX7428s video filtering. Since only signal contains sync, typical video-filtering application requires master-slave configuration SYNCIO. MAX7428 processing signal should have SYNCIO configured output, which drives SYNCIO second MAX7428, processing signal that SYNCIO configured input (Figure Clamping level signal should
Component video consists three separate signals. Typically three signals separate red, green, blue (RGB) signals (luma) color difference signals: which blue minus luma which minus luma. Sync information included with signal component video, case RGB, sync information carried green with separate sync line. component video-filter application requires three MAX7428s with SYNCIO master-slave configuration. MAX7428 processing signal SYNCIO configured output, which drives SYNCIO inputs other MAX7428s (Figure video signal filtering with separate horizontal sync signal, configure MAX7428s SYNCIO input (Figure 10). clamping levels component video MAX7428 processes clamps (CLEVEL remaining MAX7428s clamps +1.5V (CLEVEL video with external sync, three MAX7428s clamps +1.0V (CLEVEL
Component Video (RGB Filtering
Standard Definition Video Reconstruction Filter Buffer MAX7428
(LUMA) (INCLUDES SYNC SIGNAL) SYNCIO (CLEVEL
(LUMA)
SYNCIO (CLEVEL
MAX7248
MAX7248
(CHROMA)
SYNCIO (CLEVEL
(CHROMA)
SYNCIO (CLEVEL
(CHROMA)
MAX7248
SYNCIO (CLEVEL
MAX7248
MAX7248
Figure Video Filter Application
Figure Video Filter Application
Power-Supply Bypassing Layout
MAX7428 operates from single supply. Bypass with 0.1µF capacitor. Place external components close MAX7428 possible. Refer MAX7428EVKIT typical board layout example.
SYNCIO (CLEVEL
MAX7248
Chip Information
TRANSISTOR COUNT: 4955 PROCESS: BiCMOS
SYNCIO (CLEVEL
Configuration
MAX7248
VIEW
REXT DATA SYNCIO
EXTERNAL SYNC SYNCIO (CLEVEL
MAX7428
MAX7248
SOT23-8
Figure Video Filter with External Sync Application
Standard Definition Video Reconstruction Filter Buffer MAX7428
Package Information
SOT23, 8L.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2001 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
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