August 2001, ver. Features Preliminary Information 16-M

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EPC16 Configuration Device
August 2001, ver.
Features
Preliminary Information
16-Mbit Flash memory device that configures APEXII, APEX 20K, MercuryTM, ACEX1K, FLEX® devices Compression increases effective configuration density this device Mbits Available 88-pin Ultra FineLine BGAand 100-pin plastic quad flat pack (PQFP) package Standard Flash (Sharp LHF16J06) controller combined into package VCCINT VCCIO both Supports true N-bit programmable logic device (PLD) parallel programming mode Configures multiple PLDs parallel Supports 8-bit parallel data output every DCLK cycle Pin-selectable 2-ms 100-ms power-on reset (POR) time Programmable clock speed with three clock modes faster configuration time Internal oscillator defaults Programmable internal oscillator higher frequencies External clock source with frequencies Allows processor access unused Flash memory locations external flash interface Flash memory hold eight pages configuration files, enabling systems reconfigure PLDs with different configuration files Flash block/sector protection capability Compliant with IEEE Std. 1532 in-system programmability (ISP) specification Supports JamStandard Test Programming Language (STAPL) Supports Joint Test Action Group (JTAG) boundary scan nINIT_CONF allows private JTAG instruction initiate configuration Programmable configuration done error detection capability Internal programmable weak pull-ups pins Standby mode with reduced power consumption
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Altera Corporation
A-DS-EPC16-02
EPC16 Configuration Device
Preliminary Information
Architecture Description
Altera® EPC16 configuration device supports single-chip solution very high density PLDs while decreasing configuration time. core EPC16 configuration device divided into major blocks, Flash memory (Sharp LHF16J06) controller. Flash memory used APEX APEX 20K, Mercury, ACEX, FLEX device configuration, unused locations used memory storage processor. Figure shows block diagram EPC16 configuration device's core blocks, their connection PLD, their interface with JTAG/ISP interface.
Figure EPC16 Configuration Device Block Diagram
JTAG/ISP Interface
EPC16 Device
Flash
Controller
EPC16 Configuration Device Controller Units
controller unit EPC16 configuration device 3.3-V core interface. controller synchronous system that includes following:
Power-on reset circuitry (POR) Internal oscillator (IOSC) Clock divider unit (CDU) Decompression engine configuration unit (PCU) JTAG interface unit (JIU)
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Figure shows block diagram EPC16 configuration device controller unit. Figure EPC16 Configuration Device Controller Unit Block Diagram
Page Mode Select TCI, TDO, EXTCLK
EPC16 Configuration Device Controller
A[20:0] Divide IOSC Oscillator INTOSC
nCONFIG
DCLK DQ[15:0] Decompression Engine Flash Data SYSCLK Flash Data
Divide
Flash Memory
DCLK Pause [7:0]
DATA[7:0]
DCLK
Development Tools
Unit RD/BY# Counter Flash Reset Reset [15:8]
DATA[7:0] CONF_DONE
nSTATUS
PORSEL
Notes Figure
EXTCLK should connected being used. should connected programming bottom boot block, which required when programming device from Quartus software.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Power-On Reset Unit
circuit keeps system reset until power supply voltage levels have stabilized. EPC16 configuration device options time: user either keep time 100-ms default value reduce time through selectable input applications that require fast power-up. PORSEL input controls reduction time from (See Table page more information.) unit responsible managing controller's reset scheme. When counter expires, unit releases pin. time further extended from external source driving low. execute JTAG instructions until complete.
EPC16 device reset divided into three categories:
reset starts initial power-up reset during ramp drops anytime after stabilized. initiates re-configuration driving nSTATUS low, which occurs detects cyclic redundancy check (CRC) error nCONFIG input asserted PLD. controller detects error asserts initiate reconfiguration APEX APEX 20K, Mercury, ACEX FLEX devices when auto restart upon error option enabled software.
Internal Oscillator
internal oscillator (IOSC) EPC16 configuration device, which supports four modes internal clock frequencies, shown Table user program oscillator, which controlled option bits through software. Table Internal Oscillator Frequencies Mode
(MHz)
21.0 32.0 42.0
(MHz)
26.5 40.0 53.0
(MHz)
10.0 33.0 50.0 66.0
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Clock Divider Unit
generates SYSCLK DCLK controller dividing internal oscillator clock (INTOSC) external clock (EXCLK). CDU's clock division architecture parts. first divider divides down selected reference clock generate DCLK. second divider divides down DCLK generate SYSCLK. Each divider contains integer divider. Both divider divider also implemented first divider (N), second divider only divide integers. default from power-up, INTOSC mode first divider divide generate DCLK, second divider divide generate SYSCLK (see Figure default duty cycle clock divisions, other than non-integer divisions, (for non-integer dividers, duty cycle will 50%). integer divisions, allows duty cycle DCLK SYSCLK programmable setting appropriate option bits through software. DCLK frequency limited maximum DCLK frequency PLD, SYSCLK frequency limited maximum Flash performance (about MHz). Therefore, DCLK SYSCLK might different frequencies. Figure details CDU. DCLK frequency each device family specified Application Note (Configuring SRAM-Based Devices).
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Figure Clock Divider Unit
INTOSC EXCLK
Divide DCLK
Divide SYSCLK
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Decompression Engine
EPC16 configuration device supports decompression. Configuration data compressed QuartusII software stored EPC16 device. During configuration, decompression engine inside EPC16 device will decompress expand data. This feature increases effective configuration density EPC16 device Mbits. EPC16 configuration device also supports parallel data reduce configuration time. However, some cases, data transfer limited Flash data transfer rate. With parallel programming mode (when DCLK frequency MHz), data output bandwidth faster than data input bandwidth reading from Flash. Because configuration time depends ratio data bits read bandwidth, compression will improve configuration time. decompression engine decompresses compressed configuration data before sending configuration unit (PCU) configuration.
Configuration Unit
function transmit decompressed data PLD, depending configuration mode. EPC16 configuration device supports four parallel configuration modes, with Depending data width, shifts data transmit appropriate data valid data pins. Unused data pins drive low. addition transmitting data PLD, responsible delaying DCLK whenever there insufficient decompressed data, e.g., when waiting decompression engine decompress data. This technique called "Pausing DCLK." manages CONF_DONE error detection logic. CONF_DONE error occurs when de-asserted within certain number clock cycles after last data transmitted PLD. When CONF_DONE error detected, asserts signals unit, which asserts nRESET (OE) start re-configuring PLD. This done only when auto-restart upon error option enabled software.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
JTAG Interface Unit
IEEE Std. 1149.1 JTAG Boundary Scan implemented EPC16 configuration device facilitate testing interconnection functionality. EPC16 device also supports mode. EPC16 device's compliant with IEEE Std. 1532 draft specification. addition programming, erasing, verifying Flash, EPC16 configuration device also supports block/sector protection through IEEE Std. 1532-compliant instructions. JTAG interface unit (JIU) communicates directly with Flash (see Figure Direct access Flash will enable maximum JTAG frequency MHz. Figure JTAG/ISP Interface
JTAG/ISP Interface
Controller
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Flash Memory
Before JTAG/ISP interface programs Flash memory, JTAG instruction (PENDCFG) asserts PLD's nCONFIG (connected INIT_CONFIG pin), which will terminate access Flash. When mode starts, JTAG/ISP interface becomes bus-master. mode starts during configuration, configuration terminates immediately.
Flash Memory
Sharp LHF16J06 used EPC16 configuration devices megabit Flash memory with boot block located bottom. Flash memory divided into three types blocks: boot block, parameter block, main block. Each block protection capability erased individually. EPC16 configuration device also program erase Flash lock bits through JTAG interface. lock bits protect Flash against inadvertent erase; block cannot erased when lock set.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
boot block replace dedicated boot PROM microprocessor found Excaliburembedded processor solutions). also store other system (not configuration) data. boot block features hardware-controllable write protection protect crucial microprocessor boot code from accidental modification using combination pins block lock bit. Each block contains lock that disables program erase operation block. bottom boot blocks Flash memory, should connected VCC. connected GND, bottom boot block cannot programmed erased. Quartus software version 1.1, should connected VCC, otherwise configuration file cannot stored main block.
Parameter blocks used storing small, frequently updated parameters. There parameter blocks words, each 16-Mbit Flash block. Parameter block protection controlled using combination block lock bits. main blocks fill remainder Flash memory contain configuration user memory space. 16-Mbit Flash block, there blocks words. Similar parameter block, protection main block controlled using combination block lock bits.
Memory
EPC16 configuration device memory divided into main sections: controller memory space user memory space. controller memory space consists controller's option bits maximum eight pages configuration data. memory space starts with address 008000h (after words boot/parameter blocks) continues upward. bits reside from address 008000h 00801fh, they reserved option bits (see Figure
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Figure Flash Memory EPC16 Configuration Device (Bottom Boot)
FFFFFh
Empty locations that used PLD/processor
Used
used PLD/processor
Page
Main Block Page mode section
Development Tools
Page 08020h 0801Fh
Option Bits Controller's option bits
08000h Bottom words reserved processor
Boot/Parameter Block
Reserved Bottom Boot/Parameter
00000h
Altera Corporation
EPC16 Configuration Device
Preliminary Information
boot block parameter block located bottom 32K-word blocks. lock flexibility available with blocks feature boot block, user want bottom 32K-word block processor memory space. Altera recommends using bottom 32K-word blocks (Boot/Parameter blocks). However, processor will boot from 32K-word blocks, user should re-map address bottom block using glue logic. systems that processor memory space, then system user bottom 32K-word blocks configuration data memory space.
Page Mode Selection
Page Mode Selection feature allows EPC16 configuration device store eight different designs PLD. user chooses which design will configure configuration. Three input pins (PGM[2:0]) select eight pages configuration files that configure PLDs. Page defined default page (see Figure Connect these pins board select user-specified page Quartus software when generating EPC16 file. PGM2 most significant (MSB).
Operating Modes
operating modes define EPC16 configuration device's process flow data control signals. data process flow explains data transferred between blocks during read write cycles. control process flow explains control signals handshake between blocks facilitate data transfer. main modes are:
Normal Mode Programming Mode
Normal Mode
Normal mode controls configuration process using compressed data Flash memory. process involves reading data from Flash memory, data decompression, sending data PLD.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Upon power-up, unit generates reset signals. unit resets EPC16 configuration device's control units using 10MHz default internal clock main clock source. After counter expires, unit de-asserts holding low, time extended. Upon start configuration process, device samples PGM[] select pins determine which page configuration files Flash memory should used configuration. will switch internal clock clock settings according option setting. device starts read Flash configuration data. When goes high, starts DCLK configures PLD. When last configuration data bits have been read from Flash memory, page counter expires stops reading from Flash memory. CONF_DONE error detection occurs, DCLK will continue toggling until goes high. configuration cycle successful. CONF_DONE error detection detects error, unit will assert start reconfiguration. After configuration process complete, stops DCLK. keep Flash memory idle state, device enables pull-ups, pulldowns, and/or bus-keepers flash interface pins.
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Programming Mode
During mode, JTAG interface becomes bus-master access Flash memory. system executes instructions access Flash memory through JIU. After receiving instruction, will decode instruction perform necessary Flash cycle. programming mode, interfaces with initiate reconfiguration cycle. When JTAG interface takes bus-mastership, starts reconfigure PLD. During configuration, JTAG interface should issue instruction that interfere with configuration. After re-configuration cycle successfully completed, asserts CONF_DONE high. Upon this assertion, DCLK will drive DATA[7:0] remains last logic state.
Device Configuration
control signals from EPC16 configuration device (DATA[], DCLK, nCS, nINIT_CONF, interface directly with APEX APEX 20K, Mercury, ACEX, FLEX devices' control signals. more information parallel configuration, refer Application Note (Configuring SRAM-Based Devices).
Altera Corporation
EPC16 Configuration Device
Preliminary Information
DCLK pin, which driven from EPC16 configuration device PLD, acts configuration cycle reference clock. functions configuration data "write-enable" strobe signal. open-drain driven when complete. built-in 2-ms 100-ms counter will hold release during initial power permit voltage levels stabilize. After expires, time extended externally driving low. When driven low, EPC16 configuration device resets address counters. EPC16 configuration device connected CONF_DONE PLD. checks successful configuration after last configuration data been transmitted PLD. always drives when pulled low. Both pins have programmable weak internal pull-up resistor. EPC16 configuration device allows user initiate configuration APEX APEX 20K, Mercury, ACEX, FLEX devices nINIT_CONF pin, which tied nCONFIG LUT-based PLDs. JTAG instruction causes EPC16 configuration device drive nINIT_CONF low, which turn pulls nCONFIG low. EPC16 configuration device then drives nINIT_CONF high start configuration. When JTAG state machine exits this state, nINIT_CONF releases nCONFIG, configuration initiated.
Serial Configuration Mode
APEX APEX 20K, Mercury, ACEX, FLEX devices configured through EPC16 configuration device serial programming mode. this mode, EPC16 configuration device sends serial bit-stream configuration data DATA0 pin, which routed DATA0 input LUT-based PLDs. Figure shows APEX APEX 20K, Mercury, ACEX, FLEX devices configured with EPC16 configuration device serial programming mode.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Figure Serial Configuration
EPC16 Configuration Device DCLK DATA0 nINIT_CONF EXCLK Optional External Clock Source
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
Notes Figure
pull-up resistors except APEX 20KE devices; APEX 20KE device pull-up resistors nCS, nINIT_CONF pins EPC16 configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, nCONFIG must connected VCCINT through pull-up resistor. more information, refer Application Note (Configuring SRAM-Based Devices). EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com).
Development Tools
EPC16 configuration device, Flash memory stores configuration data, controller transfers configuration data through DATA0 LUT-based PLDs. DATA0, DCLK, nCS, nINIT_CONF, pins interface with EPC16 configuration device PLD.
Parallel Configuration Multiple Devices Serial Mode
EPC16 configuration device supports parallel configuration multiple devices their serial configuration mode (see Figure EPC16 configuration device simultaneously output parallel DATA outputs multiple LUT-based PLDs. user selects configuration modes software.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Figure Parallel Configuration Multiple Devices Serial Mode (Different Data with
PLD0
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
EPC16 Configuration Device
DCLK DATA0 nINIT_CONF EXCLK DATA1
PLD1
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
DATA[2.6] DATA7
External Clock Source
PLD7
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
Notes Figure
pull-up resistors except APEX 20KE devices; APEX 20KE device pull-up resistors nCS, nINIT_CONF pins EPC16 configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. nINIT_CONF internal pull-up resistor which always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, nCONFIG must connected VCCINT through pull-up resistor. more information, refer Application Note (Configuring SRAM-Based Devices). EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com).
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Table summarizes configuration modes EPC16 configuration device. Table EPC16 Configuration Mode Mode Name
Passive Serial Mode Passive Multi-Device Parallel Synchronous Mode Passive Multi-Device Parallel Synchronous Mode Passive Multi-Device Parallel Synchronous Mode Note Table
mode category gives number valid DATA outputs each configuration mode.
Mode Used Outputs
DATA0 DATA[1.0]
Unused Outputs
DATA[7.1] drive DATA[7.2] drive
DATA[3.0]
DATA[7.4] drive
DATA[7.0]
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Figure shows parallel configuration multiple devices serial mode with same DATA.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Figure Parallel Configuration Multiple Devices Serial Mode (Same Data with
PLD0
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
EPC16 Configuration Device
DCLK DATA0 nINIT_CONF EXCLK
PLD1
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
External Clock Source
PLD7
DCLK DATA0 CONF_DONE nSTATUS nCONFIG MSEL1 MSEL0
Notes Figure
pull-up resistors except APEX 20KE devices; APEX 20KE device pull-up resistors nCS, nINIT_CONF pins EPC16 configuration devices have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins, user option turning these resistors through software. nINIT_CONF internal pull-up resistor that always active. nINIT_CONF available used, nCONFIG must pulled either directly through resistor. When configuring APEX 20KE device, nCONFIG must connected VCCINT through pull-up resistor. more information, refer Application Note (Configuring SRAM-Based Devices). EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com).
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Multiple Devices Configuration Chain
Because significant amount Flash memory EPC16 configuration device, need cascade multiple EPC16 configuration devices together configure large devices. EPC16 configuration device configure chain PLDs cascaded together. Figure shows EPC16 configuration device configuring chain multiple PLDs serial mode. Figure Multiple Device Configuration Chain
PLD7 DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
PLD0 DCLK DATA0 nSTATUS CONF_DONE nCEO nCONFIG MSEL0 MSEL1
EPC16 Configuration Device DCLK DATA0 nINIT_CONF EXCLK Optional External Clock Source
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Notes Figure
pull-up resistors except those used with APEX 20KE devices. Circuitry using APEX 20KE devices should 10-k pull-up resistors. pins have internal pull-up resistors. internal pull-up resistor nINIT_CONF always active. However, pins user option turning these resistors through software. nINIT_CONF internal pull-up resistor which always active. When configuring APEX 20KE device, nCONFIG must connected VCCINT through pull-up resistor. more information, refer Application Note (Configuring SRAM-Based Devices). EXCLK input only. Quartus software, user select EXCLK internal oscillator clock source. nSTATUS should have external pull-up resistor ACEX FLEX devices. Instead, programmable internal resistor should used. direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com).
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Figure shows timing waveform configuration device scheme. Figure Configuration Device Scheme Timing Waveform
nINIT_CONF VCC/nCONFIG OE/nSTATUS tLOE
Note
nCS/CONF_DONE DCLK DATA User INIT_DONE
Driven High
bit/byte bit/byte
bit/byte
User Mode
Notes Figure
timing information, refer Table page configuration device will drive DATA after configuration. APEX APEX devices enter user mode clock cycles after CONF_DONE goes high. Mercury devices enter user mode clock cycles after CONF_DONE goes high. ACEX FLEX 10K, FLEX 6000 devices enter user mode clock cycles after CONF_DONE goes high.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Table defines EPC16 device timing parameters when using EPC16 devices Table EPC16 Configuration Device Configuration Parameters (PLD Interface) Symbol
fDCLK tDCLK tCAC tLOE fECLK tECLK tECLKH tECLKL tECLKR tECLKF Note Table
This parameter used CONF_DONE error detection EPC16 device. Contact Altera Applications detailed information. This parameter used cyclic redundancy check (CRC) error detection CPLD.
Parameter
DCLK frequency DCLK period DCLK duty cycle high time DCLK duty cycle time first DCLK delay first DATA available DCLK rising edge DATA change assert DCLK disable delay assert DATA disable delay DATA hold time from last DCLK rising edge DCLK rising edge assert time assure reset EXCLK input frequency EXCLK input period EXCLK input duty cycle high time EXCLK input duty cycle time EXCLK input rise time EXCLK input fall time
Condition
duty cycle
66.7
Unit
duty cycle duty cycle
Development Tools
133.3
duty cycle duty cycle duty cycle
3.375 3.375
Power Sequencing
Altera recommends that power-up before EPC16 device's expires. detailed information, refer Application Note (Configuring SRAM-Based Devices).
Altera Corporation
EPC16 Configuration Device
Preliminary Information
EPC16 configuration device powered order with respect other devices. EPC16 device configures devices successfully regardless power sequencing.
EPC16 Configuration Device Pin-Outs
Tables through describe definitions EPC16 configuration device. These tables include interface pins, Flash interface pins, JTAG interface pins, other pins. Table Interface Pins with Respect Controller Name
DATA[7.0] DCLK
Type
Output Output Input
Description
This configuration output data bus. DATA changes each rising edge DCLK. DCLK always output. EPC16 configuration device drives DCLK signal configuration clock. input EPC16 configuration device used input PLD's CONF_DONE signal error detection after last configuration data transmitted PLD. will always drive when asserted. This contains programmable internal weak pull-up. nINIT_CONF connected nCONFIG LUT-based PLDs initiate configuration EPC16 configuration device private JTAG instruction. This contains programmable internal weak pull-up. This driven when complete. user-selectable 2-ms 100-ms counter will hold release during initial power permit voltage levels stabilize. time extended externally driving low. After EPC16 controller releases will wait sense high before starting configuration process. This contains programmable internal weak pull-up.
nINIT_CONF
Output
Open-Drain
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Table Flash Interface Pins Name
A[20:0](2)
Note Description
These pins address input Flash memory read write operations. addresses internally latched during write cycle. These pins Data that interface with Flash memory controller. controller external source drives DQ[15:0] during Flash command data write cycles. During data read cycle, Flash memory drives DQ[15:0] controller. When asserted, activates Flash memory. When high, deselects device reduces power consumption standby levels. When asserted, resets Flash memory. When high, enables normal operation. When low, inhibits write operation Flash memory, which provides data protection during power transitions. controller asserts this during Flash read cycles. When asserted, enables drivers Flash output pins. controller asserts during Flash write cycle. When asserted, controls writes Flash memory. Flash memory, addresses data latched rising edge pulse. This usually tied ground board. controller does drive this because could cause contention. Block erase, full chip erase, word write, lock configuration power supply. Flash asserts this when write erase operation complete. This Flash only pin.
Type
Input
DQ[15:0]
Input/Output
Input
Input
Input Input
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VCCW RY/BY# Notes Table
Input Supply Output
EPC16 device being used strictly configuration device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com). (A20) used Flash EPC16 device. should left no-connect (NC) pin. symbol means active low. These pins driven during Flash testing. Because controller cannot tolerate 12-V level, connection these pins from controller Flash will bonded internally package they will available separate pins. user required connect pins board level (for example, PCB, connect from controller from Flash memory, shown Figure page 23). should connected board when using Quartus software version 1.1.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Table JTAG Interface Pins Other Pins with Respect Controller Name
PGM[2.0]
Type
Input Output Input Input Input
Description
This JTAG data input pin. Connect this JTAG circuitry used. This JTAG data output pin. connect this JTAG circuitry used. This JTAG clock pin. Connect this ground JTAG circuitry used. This JTAG mode select pin. Connect this JTAG circuitry used. These three input pins used select eight pages configuration files configure PLD. Connect these pins board select page specified designer Quartus software when generating EPC16 file. PGM/2 MSB. During Normal mode, EXCLK operates external clock source. This selects 2-ms 100-ms counter delay during power When PORSEL Low, time When PORSEL High, time Test mode that used select different test modes. operating mode, this should connected Test mode that used select different test modes. operating mode, this should connected
EXCLK PORSEL
Input Input
Input Input
Note Table
ramp rate should less than POR, should less than POR.
Package
EPC16 configuration device available 88-pin Ultra FineLine package 100-pin PQFP package. Ultra FineLine package, which based 0.8-mm pitch, maximizes board space efficiency. board laid this package using only layer. Figure shows EPC16 configuration device's package ball assignment 88-pin Ultra FineLine package. Refer Tables through starting page descriptions each pin. four pins four corner edges no-connect (NC) pins.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Figure Package Ball Assignments 88-Pin Ultra FineLine Package
Note
DCLK
DATA7
DQ15
PGM0
DQ14
DATA5
DATA6
RY/BY#
nINIT CONF
PGM1
DQ13
DATA4
DQ12
DATA3
VCCW
DQ11
DQ10
DATA2
PGM2
PORSEL
DATA1
DATA0
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EXCLK
Notes Figure
direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#, which shown Figure page Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com). RP#F WE#F pins Flash die. RP#C WE#C pins controller die. WE#C WE#F should connected together PCB. RP#F RP#C should also connected together PCB.
Figure shows routing 88-pin Ultra FineLine package. find Gerber file this layout Altera site http://www.altera.com.
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Figure Routing 88-Pin Ultra FineLine Package
Note
DCLK
DATA7
DQ15
PGM0
DQ14
DATA5
DATA6
RY/BY#
nINIT CONF
PGM1
DQ13
DATA4
DQ12
VCCND
DATA3
VCCW
DQ11
DQ10
DATA2
PGM2
PORSEL
DATA1
DATA0
EXCLK
Notes Figure
direct Flash interface used EPC16 device, then Flash pins should left unconnected because they internally connected controller unit. only pins that need external connection WP#, WE#, RP#. Flash being used external memory source, then Flash pins should connected. more information, consult Flash Data Sheet Altera site (http://www.altera.com). RP#F WE#F pins Flash die. RP#C WE#C pins controller die. WE#C WE#F should connected together PCB. RP#F RP#C should also connected together PCB. should connected able program bottom boot block, which required when programming device from Quartus software.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Programming Configuration File Support
Quartus MAX+PLUS development software provide programming support EPC16 configuration device automatically generate programming files EPC16 configuration devices. multi-device project, software combine programming files multiple APEX APEX 20K, Mercury, ACEX, FLEX devices into EPC16 configuration device. EPC16 configuration devices programmed in-system through industry-standard 4-pin JTAG interface. EPC16 device provides ease prototyping updating APEX APEX 20K, Mercury, ACEX, FLEX device functionality. EPC16 configuration devices also programmed third-party Flash programmers. After programming EPC16 configuration device in-system, LUT-based configuration initiated including EPC16 device's JTAG initiate configuration instruction. Table
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Altera Corporation
EPC16 Configuration Device
Preliminary Information
circuitry EPC16 configuration device compliant with IEEE Std. 1532 specification. IEEE Std. 1532 standard developed allow concurrent between devices from multiple vendors. Table EPC16 JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Description
Allows snapshot state EPC16 device pins captured examined during normal device operation permits initial data pattern output device pins. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing results input pins. Places 1-bit bypass register between pins, which allow data pass synchronously through selected device adjacent devices during normal device operation. Selects device IDCODE register places between TDO, allowing device IDCODE serially shifted TDO. device IDCODE EPC16 device shown below: 0100A0DDh Selects USERCODE register places between TDO, allowing USERCODE serially shifted TDO. 32-bit USERCODE programmable user-defined pattern. This function allows user initiate re-configuration process tying nINIT_CONF PLD(s) nCONFIG pin(s). After this instruction updated, nINIT_CONF released starts configuration. This function will used assert nINIT_CONF before accessing Flash memory, PLD/processor connected Flash. This used avoid Flash contention when both JTAG/ISP PLD/processor want access Flash. Before JTAG/ISP access Flash, CPLD/processor needs reset asserting INIT_CONF, which puts PLD/processor "reset" state waits de-assertion INIT_CONF.
EXTEST
BYPASS
IDCODE
USERCODE
INIT_CONF
PENDCFG
Note Table
EPC16, instruction register length boundary scan length 174.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing
EPC16 configuration device provides JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundaryscan testing performed before after configuration, during configuration. Table shows timing parameters values EPC16 configuration device. Table JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register highimpedance valid output Update register valid output high impedance
Unit
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Altera Corporation
EPC16 Configuration Device
Preliminary Information
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, supply current values, capacitance, configuration parameters EPC16 configuration device.
Table EPC16 Configuration Device Absolute Maximum Rating Symbol
IMAX IOUT TSTG TAMB
Parameter
Supply voltage input voltage ground current output current, Power dissipation Storage temperature Ambient temperature Junction temperature
Condition
With respect ground With respect ground
-0.5 -0.5
Unit
bias Under bias Under bias
Table EPC16 Configuration Device Recommended Operating Conditions Symbol
Parameter
Supplies voltage 3.3-V operation Input voltage Output voltage Operating temperature
Condition
Unit
With respect ground commercial industrial
-0.3
Input rise time Input fall time
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Table EPC16 Configuration Device Operating Conditions Symbol
Parameter
Supplies voltage core High-level input voltage Low-level input voltage 3.3-V mode high-level output voltage
Condition
Unit
0.45
3.3-V mode high-level CMOS -0.1 output voltage Low-level output voltage Low-level output voltage -0.1 CMOS Input leakage current Tri-state output off-state current Configuration pins ground ground Internal pull (OE, nCS, nINIT, CONF)
RCONF
Development Tools
Table EPC16 Configuration Device Supply Current Values Symbol
ICC0 ICC1
Parameter
supply current (standby) supply current (during configuration)
Condition
Unit
Table EPC16 Configuration Device Capacitance Symbol
COUT
Parameter
Input capacitance Output capacitance
Condition
Unit
Altera Corporation
EPC16 Configuration Device
Preliminary Information
Table EPC16 Configuration Device Configuration Parameters (Flash Interface) Symbol
fSCLK tSCLK tSCLKH tSCLKL tAVQV(F) tGLQV(F) tWLWH(F) tWHR0(F)
Parameter
SYSCLK frequency SYSCLK period SYSCLK duty cycle high time SYSCLK duty cycle time Flash address data DQ[15:0] delay Flash data DQ[15:0] delay Flash pulse width Flash high ready
Condition
Unit
Device Pin-Outs
Altera site (http://www.altera.com) Altera Digital Library pin-out information.
Altera Corporation
Preliminary Information
EPC16 Configuration Device
Notes:
Altera Corporation
EPC16 Configuration Device
Preliminary Information
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Altera Corporation

August 2001, ver. Features Preliminary Information 16-M

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