HYM7V63401B R-Series DESCRIPTION Hynix HYM7V63401B R-Series 4Mx64

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

HYM7V63401B R-Series DESCRIPTION Hynix HYM7V63401B R-Series 4Mx64

Datasheet Thumbnail

Top Searches for this datasheet

4Mx64 bits PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series DESCRIPTION
Hynix HYM7V63401B R-Series 4Mx64bits Synchronous DRAM Modules. modules composed four 4Mx16bit CMOS Synchronous DRAMs 400mil 54pin TSOP-II package, 2Kbit EEPROM 8pin TSSOP package 168pin glass-epoxy printed circuit board. 0.33uF 0.1uF decoupling capacitors each SDRAM mounted PCB. HYM7V63401B R-Series Dual In-line Memory Modules suitable easy interchange addition 32Mbytes memory. HYM7V63401B R-Series offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth.
FEATURES
PC133/100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.375" (34.93mm) Height with Single Sided components Single 0.3V power supply devices pins compatible with LVTTL interface Data mask function SDRAM internal banks four banks Module bank physical bank Auto refresh self refresh 4096 refresh cycles 64ms Programmable Burst Length Burst Type Full Page Sequential Burst Interleave Burst Programmable /CAS Latency Clocks
ORDERING INFORMATION
PART HYM7V63401BTRG-75 MAX. FREQUENCY 133MHz INTERNAL BANK Banks REF. POWER Normal SDRAM PACKAGE TSOP-II PLATING Gold
This document general product description subject change without notice. Hyundai Electronics does assume responsibility circuits described. patent licenses implied. Rev. 0.1/APr.01 ©1999 Hyundai Electronics
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series DESCRIPTION
NAME CK0~CK3 Clock Inputs DESCRIPTION System Clock Input. other inputs registered SDRAM rising edge CLK. Controls internal clock signal when deactivated, SDRAM will states among power down, suspend self refresh. Enables disables inputs except DQM. Select bank activated during /RAS activity. Select bank read/written during /CAS activity address RA0~RA11, Column address CA0~CA7 Auto-precharge flag /RAS define operation. Refer function truth table details. /CAS define operation. Refer function truth table details. define operation. Refer function truth table details. Controls output buffers read mode masks input data write mode. Multiplexed data input/output pins Power supply internal circuits input/output buffers Ground Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address input Write Protect Serial Presence Detect DIMM Connect Don't
CKE0 /S0, BA0,
Clock Enable Chip Select SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Address Strobe
/CAS
Column Address Strobe
DQM0~DQM7 DQ0~DQ63 SA0~SA2
Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground Clock Input Data Input/Output Address Input Write Protect Connect
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series ASSIGNMENTS
FRONT SIDE NAME BACK SIDE NAME DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 FRONT SIDE NAME DQM2 DQM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BACK SIDE NAME *CK1 CKE0 DQM6 DQM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 *CK3
Architecture
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM0 DQM1 A10/AP DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS DQM4 DQM5 /RAS
Voltage
Note CK1, connected with termination R/C. (Refer Block Diagram.)
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series BLOCK DIAGRAM
Note serial resistor values Ohms. padding capacitance termination CK1, 10pF.
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 FUNCTION DESCRIBED Bytes Written into Serial Memory Module Manufacturer Total Bytes Memory Device Fundamental Memory Type Addresses This Assembly Column Addresses This Assembly Module Banks This Assembly Data Width This Assembly Data Width This Assembly (Continued) Voltage Interface Standard This Assembly SDRAM Cycle Time /CAS Latency=3 Access Time from Clock /CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back Back Random Column Address Burst Lengths Supported Banks Each SDRAM Device SDRAM Device Attributes, Latency SDRAM Device Attributes, Latency SDRAM Device Attributes, Write Latency SDRAM Module Attributes FUNCTION Bytes Bytes SDRAM Banks Bits LVTTL 7.5ns 5.4ns None 15.625µs Self Refresh Supported None tCCD 1,2,4,8,Full Page Banks /CAS Latency=2,3 Latency=0 Latency=0 Neither Buffered Registered +/-10% voltage tolerance, Burst Read Single Write, Precharge All, Auto Precharge, Early Precharge 10ns 20ns 15ns 20ns 45ns 32MB 1.5ns 0.8ns 1.5ns 0.8ns JEDEC Hynix JEDEC Unused Hynix (Korea Area) BYTE72 Manufacturing Location (United States Area) (Europe Area) (Japan Area) Asia Area VALUE NOTE
BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 BYTE62 BYTE63 BYTE64 BYTE65
SDRAM Device Attributes, General SDRAM Cycle Time /CAS Latency=2 Access Time from Clock /CAS Latency=2 SDRAM Cycle Time /CAS Latency=1 Access Time from Clock /CAS Latency=1 Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Minimum /RAS /CAS Delay (tRCD) Minimum /RAS Pulse width (tRAS) Module Bank Density Command Address Signal Input Setup Time Command Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may used future) Revision Checksum Bytes 0~62 Manufacturer JEDEC Code .Manufacturer JEDEC Code
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series
Continued
BYTE NUMBER BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256 FUNCTION DESCRIBED Manufacturer's Part Number (Component) Manufacturer's Part Number (Voltage Interface) Manufacturer's Part Number (Data Width) .Manufacturer Part Number (Data Width) Manufacturer's Part Number (Memory Depth) Manufacturer's Part Number (Refresh) Manufacturer's Part Number (Internal Banks) Manufacturer's Part Number (Generation) Manufacturer's Part Number (Package Type) Manufacturer's Part Number (Module Type) Manufacturer's Part Number (Plating Type) Manufacturer's Part Number (Hyphen) Manufacturer's Part Number (Min. Cycle Time) .Manufacturer Part Number (Min. Cycle Time) Manufacturer's Part Number Revision Code (for Component) .Revision Code (for PCB) Manufacturing Date .Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may used future) Reserved Intel specification details 100MNZ support FUNCTION (SDRAM) (3.3V, LVTTL) Refresh) Banks) (TSOPII) (x16 based Unbuffered DIMM) (Gold) (Hyphen) Blanks Process Code Process Code Work Week Year Serial Number None Refer Note8 Refer Note8 VALUE NOTE
Unused Storage Locations
Note: bank address excluded. 1,2,4,8 Interleave Burst Type adopted. Refer most recent version Intel JEDEC Specification. ASCII adopted. Basically Hynix writes Part except Byte 73-90 limited bytes from byte efficiently. fixed dependent. These values apply PC100 applications only, Intel SDRAM specification. Refer Hynix Site
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series ABSOLUTE MAXIMUM RATINGS
PARAMETER Ambient Temperature Storage Temperature Voltage relative Voltage relative Short Circuit Output Current Power Dissipation Soldering Temperature Time TSTG VIN, VOUT VDD, VDDQ TSOLDER SYMBOL RATING -1.0 -1.0 UNIT
Note Operation above absolute maximum adversely affect device reliability.
OPERATING CONDITION
70°C) PARAMETER Power Supply Voltage Input High Voltage Input Voltage SYMBOL TYP. UNIT NOTE
Note voltage referenced (max) acceptable 5.6V pulse width with duration. (min) acceptable -2.0V pulse width with duration.
OPERATING CONDITION
70°C, 0.3V, PARAMETER Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement SYMBOL Vtrip Voutref VALUE *Note UNIT
Note Output load measure access time equivalent gates capacitor (50pF). details, refer AC/DC output circuit.
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series CAPACITANCE
25°C, 1MHz) PARAMETER CK0, CKE0 Input Capacitance /S0, A0~A11, BA0, /RAS, /CAS, DQM0~DQM7 Data Input/Output Capacitance DQ0~DQ63 SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CI/O TYP. UNIT
OUTPUT LOAD CIRCUIT
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series CHARACTERISTICS
70°C, 0.3V) PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Voltage SYMBOL UNIT NOTE -4mA +4mA
Note 3.6V. other pins tested under DOUT disabled. VOUT 3.6V.
CHARACTERISTICS
70°C, 0.3V, SPEED ARAMETER SYMBOL TEST CONDITION Operating Current IDD1 IDD2P IDD2PS Burst Length bank active tRC(min), VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins 0.2V 0.2V VIH(max), Input signals stable. VIL(max), VIL(max), VIH(min), VIH(min), Input signals changed time during 2clks. other pins 0.2V 0.2V VIH(max), Input signals stable. tCK(min), banks active IDD5 IDD6 UNIT NOTE
Precharge Standby Current Power Down Mode
IDD2N Precharge Standby Current Power Down Mode IDD2NS IDD3P IDD3PS
Active Standby Current Power Down Mode
IDD3N Active Standby Current Power Down Mode IDD3NS
Burst Mode Current
Operating
IDD4
Auto Refresh Current Self Refresh Current
tRRC tRRC(min), banks active 0.2V
Note IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open. Min. tRRC (Refresh /RAS cycle time) shown CHARACTERISTICS
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series CHARACTERISTICS
operating conditions unless otherwise noted) ARAMETER SYMBOL System Clock Cycle Time /CAS Latency /CAS Latency tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOLZ tOHZ3 tOHZ2 1000 /CAS Latency /CAS Latency UNIT NOTE
Clock High Pulse Width Clock Pulse Width Access Time from Clock /CAS Latency
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time Data Output Low-Z time Data Output High-Z time /CAS Latency
Note Assume (input rise fall time) 1ns. Access times measured with input signals 1v/ns edge rate.
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series CHARACTERISTICS
ARAMETER SYMBOL /RAS Time Cycle Operation Auto Refresh tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 100K /CAS Latency UNIT NOTE
/RAS /CAS Delay /RAS Active Time /RAS Precharge Time /RAS /RAS Bank Active Delay /CAS /CAS Delay Write Command Data-in Delay Data-in Precharge Command Data-in Active Command Data-out Hi-Z Data-in Mask Command Precharge Data Output Hi-Z /CAS Latency
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note command given tRRC after self refresh exit.
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series OPERATING OPTION TABLE
HYM7V63401BTRG-75
/CAS LATENCY 133MHz (7.5ns) 125MHz (8.0ns) 100MHz (10.0ns) 3CLKS 3CLKS 2CLKS tRCD 3CLKS 3CLKS 2CLKS tRAS 6CLKS 6CLKS 4CLKS 9CLKS 9CLKS 7CLKS 3CLKS 3CLKS 2CLKS 5.4ns 2.7ns
COMMAND TRUTH TABLE
CKEn-1 Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge Selected Bank Burst Stop Auto Refresh Entry Self Refresh Exit Entry Precharge Power Down Exit Entry Clock Suspend Exit CKEn /RAS /CAS ADDR A10/ NOTE
code
Note Existing Self Refresh occurs asynchronously bringing from high. Don't care, Logic High, logic Low, Bank Address, Column Address, code Operand code, operation
Rev. 0.1/Apr.01
PC133 SDRAM Unbuffered DIMM
HYM7V63401B R-Series PACKAGE DIMENSIONS
Rev. 0.1/Apr.01

HYM7V63401B R-Series DESCRIPTION Hynix HYM7V63401B R-Series 4Mx64

Top Searches for this datasheet

Other recent searches