Motherboard Clock Generator 440BX Type with 133MHz Generates cloc
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PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
Generates clock frequencies Pentium systems with INTEL 440BX Apollo Pro133 Promedia chip sets, requiring multiple clocks high speed SDRAM buffers. Support clocks, 6PCI high-speed SDRAM buffers 3-DIMM applications. 24MHz clock 48MHz clock. 2.5V IOAPIC clock. Two14.318MHz reference clocks. Built-in programmable watchdog timer secs with 0.5-second interval. will generate reset output when timer expired. Support 2-wire serial interface with builtin Vendor Device Revision Single byte micro-step linear Frequency Programming with Glitch free smooth switching. Spread Spectrum ±0.25% center. duty cycle with jitter. Available SSOP.
CONFIGURATION
VDD1 REF0//PCI_STOP#^ XOUT VDD2 PCI_F/MODE*^ PCI0/FS3* PCI1 PCI2 PCI3 PCI4 VDD2 SDRAMIN SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 SDATA SCLK
VDDL1 IOAPIC REF1/FS2*^ CPU_F CPU_1 VDDL2 WDRESET# SDRAM_F SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0*^ 24MHz/FS1*^
Note: Pull Active Bi-directional latched power-up
MODE CONFIGURATION
MODE (Pin REF0 PCI_STOP (OUTPUT) (INPUT)
PLL202-11
BLOCK DIAGRAM
VDDL1 XOUT XTAL IOAPIC VDD1 REF(0:1) VDDL2 (0:3)* CPU1 CPU_F PLL1 Control Logic VDD2 PCI(0:4) PCI_F VDD4 24Mhz PLL2 48Mhz SDATA SCLK Logic Watch WDRESET#
POWER GROUP
VDD1: REF, XIN, XOUT, CORE VDD2: PCI_F, PCI(0:4) VDD3: SDRAM_F, SDRAM(0:11) VDD4: 48MHz, 24MHz, SDATA, SCLK VDDL1: IOAPIC VDDL2: CPU_F, CPU1
SPECIFICATIONS
Cycle Cycle jitter: 250ps. Cycle Cycle jitter: 250ps. SDRAM SDRAM skew: 500ps. skew: 500ps. skew 250ps skew: 4ns, typical SDRAMIN SDRAM skew: 4ns, typical 3.5ns.
10/19/00 Page
VDD3 SDRAM (0:11) SDRAMIN SDRAM_F
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
DESCRIPTIONS
Name
VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 XOUT PCI0/F3* REF1/F2* 24MHz/F1* 48MHz/F0* PCI_F, PCI(0:4) CPU_F, CPU1 SDRAM (0:11), SDRAM_F SDATA SCLK REF0//PCI_STOP WDRESET PCI_F/MODE 48MHz 24MHz REF1/FS2 SDRAMIN IOAPIC
Number
6,14 19,30,36 3,9,16,22, 33,39,45 8,46,25,26
Type
Description
Power supply REF0, REF1, crystal oscillator. Power supply PCI_F, PCI(0:4). Power supply SDRAM(0:11), SDRAM_F. Power supply 24MHz 48MHz. Power supply IOAPIC (2.5V). Power supply CPU_F CPU1 (2.5V). Ground. 14.318MHz crystal input connected crystal. 14.318MHz crystal output. power these pins input pins will determine clock frequency. After input sampling, these pins will generate output clocks. FS0, have internal pull (high default) while internal pull down (low default). clocks with frequencies defined Frequency Table. These pins except PCI_F will when PCI_STOP LOW. clocks with frequencies defined Frequency Table. 3.3V SDRAM Clocks with frequencies defined Frequency Selection table. SDRAM_F free running output. Serial data input serial interface port. Multiplexed controlled MODE signal. PCI_STOP will stop clock except PCI_F when LOW. This open drain output. Will watchdog timer expiration. power-on, MODE function will activated. When MODE Low, input PCI_STOP. When high, Pin2 output REF0. After input data latched, this will generate free running clock. 48MHz output after input data latched during power-on. 24MHz output SUPER after input data latched during power-on. Buffered reference clock output after input data latched during power-on. Buffer input pin: signal provided this input buffered SDRAM outputs. 2.5V Buffered reference clock.
7,8,10,11,12, 44,43 38,37,35,34,32, 31,29,28,21,20, 18,17,40
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
POWER MANAGEMENT
PCI_SOTP CPU1 Running Running Running PCI_F,CPU_F,SDRAM_F Running Running SDRAM Running Running IOAPIC Running Running XTAL,VCO Running Running
FREQUENCY (MHz) SELECTION TABLE
Byte0 Bit2
83.3 66.8 100.2 133.3
40.0 37.5 41.7 33.4 34.3 37.3 34.0 33.4 40.0 38.3 36.3 35.0 35.0 37.5 31.0 33.3 33.8 32.5 31.5 39.3 38.4 31.7 30.0 28.3 41.5 40.0 38.8 37.0 36.5 36.0 35.5 34.5
(default)
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
CONFIGURATION SETTING
Address Assignment Slave Receiver/Transmitter Data Transfer Rate
Provides both slave write readback functionality Standard mode 100kbits/s serial bits will read sent clock driver following order Byte Bits Byte Bits Byte Bits This serial protocol designed allow both blocks write read from controller. bytes must accessed sequential order from lowest highest byte. Each byte transferred must followed acknowledge bit. byte transferred without acknowledged will terminate transfer. write read block both begins with master sending slave address write condition (0xD2) read condition (0xD3). Following acknowledge this address byte, Write Mode: Command Byte Byte Count Byte must sent master ignored slave, Read Mode: Byte Count Byte will read master then other Data Byte. Byte Count Byte default power-up (0x09).
Serial Bits Reading
Data Protocol
CONTROL REGISTERS
BYTE Functional Frequency Select Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection Table Frequency selection control 1=Via I2C, 0=Via External jumper Selection Frequency selection Table 0=Normal 1=Spread Spectrum enable, ±0.25% Center Spread 0=Normal 1=Tristate Mode outputs
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Inverted Power latched value (Read only) Reserved Reserved Reserved SDRAM_F Active/Inactive Reserved CPU1 Active/Inactive CPU_F (Active/Inactive)
BYTE Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved PCI_F Active/Inactive Reserved PCI4 Active/Inactive PCI3 Active/Inactive PCI2 Active/Inactive PCI1 Active/Inactive PCI0 Active/Inactive
BYTE SDRAM Clock Register (1=Enable, 0=Disable)
Pin#
21,20,18,17 32,31,29,28 38,37,35,34
Default
Description
Reserved Inverted Power latched value (Read only) 48MHz 24MHz Reserved SDRAM 8:11 Active/Inactive SDRAM Active/Inactive SDRAM Active/Inactive
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
BYTE Control Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved Reserved Reserved Reserved Inverted Power latched value (Read only) Reserved Inverted Power latched value (Read only) Reserved
BYTE Peripheral Clock Register (1=Enable, 0=Disable)
Pin#
Default
Description
Reserved Reserved Reserved IOAPIC Active/Inactive Reserved Reserved REF1 Active/Inactive REF0 Active/Inactive
BYTE Fall-Back Frequency Revision Vendor Register (1=Enable, 0=Disable)
Pin#
Default
Description
Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Fall-back Frequency selection Vendor Vendor Vendor Revision Revision Revision Revision Vendor
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
BYTE Linear Programming Register (1=Enable, 0=Disable)
Pin#
Default
Description
Linear programming sign "+", Linear programming magnitude (MSB) Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude Linear programming magnitude (LSB)
Note: This register will initialized following WATCHDOG RESET.
BYTE WATCHDOG TIMER Device Register (1=Enable, 0=Disable)
Pin#
Default
Device
Description
Watchdog Timer Enable Bit. 1=Enable, 0=Disable Watchdog Time Interval (MSB) Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval Watchdog Time Interval (LSB) Device Device Device Device Device Device
Note: Default value power-up
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
PROGRAMMING FREQUENCY simplify traditional loop counter setting, PLL202-11 device incorporates SMART-BYTE technology with single byte programming better optimize clock jitter spread spectrum performance. Detail PLL202-11's dual mode frequency programming method described below: ROM-table Frequency Programming: pre-defined frequencies found Frequency table accessed either through external jumpers setting internal register BYTE0. Micro-step Linear Frequency Programming: Frequency programmed fine linear positive negative stepping around selected frequency Frequency table. highest step either +127 -127. Other frequencies will changed proportionally with rate that frequency change. formula follow:
CPU.ROM-Table (=0.22)
Where: magnitude factor defined Byte 7.bit(0:6) (sign bit) defined Byte7.bit constant 0.22
FREQUENCY PROGRAMMING EXAMPLE: Procedures program target frequency 139.0 Mhz:
Locate closest frequency from Frequency-ROM table: 0.22 Solve (Linear Magnitude factor) integer: ROMTABLE (139 135) 0.22 Program register:
Setting I2C.BYTE0 Setting I2C.BYTE7
Sign
(0.22) 138.96 frequency increased 33.8 (1+2.9%) 34.8
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
BUILT-IN WATCHDOG TIMER (WDT) Watchdog timer used perform safe recovery frequency switching causes system enter into "Hang-up" state within reasonable period time Watchdog time interval). While disabled, watchdog time interval programmed between seconds with increment second setting value I2C.Byte8.Bit(5:0). Once Enabled, disabled within period that shorter than programmed watchdog interval; otherwise will generate 500ms watchdog reset pulse provoke system reset. After system restarts, PLL202-11 will start from predefined Fall-back Frequency (the value Byte6,bits(7:3)). system reason fails again Fall-back Frequency, internal hardware will then generate watchdog reset restart system from value external hardware jumper setting ensure safe recovery. Example usage: System power-up CPU= 66.8MHz where external jumpers used. Switch target CPU=100.0MHz frequency with following register setting:
FSEL
Setting I2C.BYTE0
Setting I2C.BYTE7
Sign
WD-Timer
Setting I2C.BYTE8
FBSEL
Setting I2C.BYTE6
fall-back frequency same location that FSEL since frequency switching between different timing groups will cause system hang After timer expired seconds, system will restart properly target 100.0MHz capable; otherwise will perform another reset action restart system from 66.8 Switch target CPU=78Mhz within same timing Group fall-back frequency recommended most safe comfortable level ensure successful reboot such 75.3 system unable switch 78Mhz.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
OPERATIONAL FLOW CHART START Register Loading: Fall-Back, WD-TIMER, WD-ENABLE Register Loading: FSEL
Disable WDEnable Target Setting
SUCCESS
Wait System Response
Copy Fall-Back Frequency Setting Frequency Setting Disable WDEnable Fall-Back Frequency Setting
FAIL After specified WD-Timer Expired
SUCCESS
System Restart Fall-back Frequency
FAIL After specified WD-Timer Expired
System Restart Jumper-Setting Frequency
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, Output Voltage, Storage Temperature Ambient Operating Temperature Junction Temperature Voltage
SYMBOL
MIN.
MAX.
UNITS
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
AC/DC Electrical Specifications PARAMETERS
Input High Voltage Input Voltage Input High Current Input Current Input Current Pull-up resistor Pull-down resistor Input frequency Input Capacitance
SYMBOL
CONDITIONS
Inputs except inputs except Inputs with pull-up resistors Inputs with pull-up resistors 2,7,25,26,41,46 3.3V Logic Inputs XOUT pins
MIN.
-0.3
TYP.
MAX.
+0.3
UNITS
-200 14.318
Kohm
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
Output Buffer Electrical Specifications
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
CPU_F, CPU1 REF, 48MHz, 24MHz
CONDITIONS
Measured 0.4V 2.0V, =10-20pf, 2.5V±5% Measured 0.4V 2.4V, =10-20pf Measured 0.4V 2.4V, =10-30pf Measured 0.4V 2.0V, =10-30pf, 2.5V±5% Measured 0.4V, =10-20pf, 2.5V±5% Measured 2.4V 0.4V, =10-20pf Measured 2.4V 0.4V, =10-30pf Measured 2.0V 0.4V, =10-30pf, 2.5V±5% Measured 1.5V =20pf Measured 1.5V, =20~30pf
MIN.
TYP.
MAX.
UNITS
Output Rise time
SDRAM, SDRAM_F, PCI_F,PCI IOAPIC CPU_F, CPU1 REF, 48MHz, 24MHz
V/ns
V/ns
Output Fall time
SDRAM, SDRAM_F, PCI_F, IOAPIC CPU_F,CPU1,SDRAM, PCI_F,PCI, 48MHz, 24MHz IOAPIC,REF SDRAM SDRAM
Duty Cycle
Clock Skew
SKEW
SDRAM SDRAMIN SDRAM CPU_F,CPU1
Measured 1.5V, equal loads =3.3V(2.5V)±5% =3.3V±5% =3.3V(2.5V)±5%
Output Impedance
REF0,48MHz,24MHz, PCI_F,PCI SDRAM,SDRAM_F, REF1 IOAPIC
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
Output Buffer Electrical Specifications, continued
Unless otherwise stated, power supplies 3.3V±5%, ambient temperature range 70°C
PARAMETERS
SYMBOL
OUTPUTS
SDRAM,SDRAM_F PCI_F,PCI
CONDITIONS
MIN.
TYP.
MAX.
UNITS
1.5V
Output High Current
48MHz,24MHz CPU1 CPU_F IOAPIC SDRAM,SDRAM_F PCI_F,PCI 1.5V 1.25V 2.5V±5%)
Output Current
48MHz,24MHz CPU1 CPU_F IOAPIC Measured 1.25V 1.25V 2.5V±5%)
Jitter, Sigma
sigma
IOAPIC REF,48MHz,24MHz
Measured 1.5V -0.25 -0.5
Jitter, Absolute
IOAPIC REF,48MHz,24MHz
Measured 1.25V
0.25
Measured 1.5V Measured 1.25V Measured 1.5V
Jitter (cycle cycle)
cyc-cyc
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
PLL202-11 rev.
Motherboard Clock Generator 440BX Type with 133MHz
PACKAGE INFORMATION
0.400 0.410 10.160 10.414
0.292 0.299 7.417 7.595
0.008 0.0135 0.203 0.343
0.025 0.635
0.015 (0.381) 0.010 0.016 (0.254 0.406) 0.620 0.630 (15.75 16.00)
0.088 0.096 (2.235 2.438)
0.097 0.104 (2.464 2.642) 30-6 0.050 (1.27) 0.008 0.016 (0.203 0.406)
48PIN SSOP
ORDERING INFORMATION
part ordering, please contact Sales Department:
47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PLL202-11
PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished PhaseLink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991
10/19/00 Page
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