SN54 74LS113A offers individual set, clock inputs. These monolithic du
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SN54/74LS113A DUAL NEGATIVE EDGE-TRIGGERED FLIP-FLOP
SN54 74LS113A offers individual set, clock inputs. These monolithic dual flip-flops designed that when clock goes HIGH, inputs enabled data will accepted. logic level inputs allowed change when clock pulse HIGH bistable will perform according truth table long minimum setup times observed. Input data transferred outputs negative-going edge clock pulse.
DUAL NEGATIVE EDGE-TRIGGERED FLIP-FLOP
POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
SUFFIX CERAMIC CASE 632-08
5(9) 6(8)
SUFFIX PLASTIC CASE 646-06
3(11) 1(13) CLOCK (CP)
(SD) 4(10) 2(12)
SUFFIX SOIC CASE 751A-02
ORDERING INFORMATION MODE SELECT TRUTH TABLE
INPUTS OPERATING MODE Toggle Load (Reset) Load (Set) Hold OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
LOGIC SYMBOL
HIGH Voltage Level Voltage Level Don't Care Lower case letters indicate state referenced input output) set-up time prior HIGH clock transition.
FAST DATA
SN54/74LS113A
GUARANTEED OPERATING RANGES
Symbol Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Parameter 4.75 5.25 Unit
CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol Parameter Input HIGH Voltage Input Voltage Input Clamp Diode Voltage Output HIGH Voltage Output Voltage Clock Input HIGH Current Clock Set, Clock 0.35 0.65 0.25 Unit Test Conditions Guaranteed Input HIGH Voltage Inputs Guaranteed Input Voltage Inputs MIN, MIN, MAX, MIN, MAX, Truth Table MIN, Truth Table
MAX,
MAX,
Input Current
MAX,
Short Circuit Current (Note Power Supply Current
Note more than output should shorted time, more than second.
CHARACTERISTICS 25°C,
Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay, Clock Output Unit Test Conditions
SETUP REQUIREMENTS 25°C,
Limits Symbol Parameter Clock Pulse Width High Pulse Width Setup Time Hold Time Unit Test Conditions
FAST DATA
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