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PENTIUM® PROCESSOR WITH CACHE
Separate dedicated external system bus, dedicated internal full-speed cache KB/8 separate data instruction, nonblocking, level cache Data integrity reliability features include ECC, Fault Analysis/Recovery, Functional Redundancy Checking Fits Intel Pentium processor 387-Pin Socket Meets timings levels Pentium processor lighter package ceramic Scratch resistant anodized aluminum heat spreader Designed sockets
Large integrated cache multiprocessing systems Binary compatible with applications running previous members Intel microprocessor family Optimized 32-bit applications running advanced 32-bit operating systems Dynamic Execution microarchitecture Single package includes Pentium® processor CPU, cache system interface Scaleable four processors memory
Pentium® processor with cache designed high-end multiprocessor capable server systems. Pentium processor with cache delivers more performance than previous generation processors through innovation called Dynamic Execution. This next step beyond superscalar architecture implemented Pentium processor. This makes possible advanced visualization interactive capabilities required today's high-end commercial technical applications tomorrow's emerging applications. Pentium processor with cache also includes advanced data integrity, reliability, serviceability features mission critical applications.
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION 1995 January 1998 Order Number: 243570-001
PENTIUM® PROCESSOR WITH CACHE
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com Copyright Intel Corporation 1996, 1997. Third-party brands names property their respective owners.
PENTIUM® PROCESSOR WITH CACHE
CONTENTS
PAGE PAGE 5.1.2. MEASURING CASE TEMPERATURE 5.1.3. THERMAL RESISTANCE. 5.2. Thermal Analysis. 5.2.1. TYPICAL PASSIVE HEAT SINK DESIGNS. 5.2.2. TABLES CURVES PASSIVE HEAT SINKS FLOW RATES 5.2.3. HEAT SINK DESIGNS 5.2.4. EFFECT THERMAL GREASE PEDESTAL SIZE THERMAL PERFORMANCE. 6.0. MECHANICAL SPECIFICATIONS 6.1. Pinout 6.2. Introduction Flatness. 6.3. Critical Zone Pedestal Area 6.3.1. BACKPLATE PRESSURE SPECIFICATION 6.4. Heat Sink Design Recommendations 6.4.1. HEAT SINK. 6.5. Strength Specification. 6.6. Coplanarity Specification. 6.7. Predicted Storage Failure Rates A.0. ALPHABETICAL LISTING SIGNALS A.1. A[35:3]# (I/O) A.2. A20M# A.3. ADS# (I/O) A.4. AERR# (I/O). A.5. AP[1:0]# (I/O). A.6. ASZ[1:0]# (I/O). A.7. ATTR[7:0]# (I/O) A.8. BCLK A.9. BE[7:0]# (I/O). A.10. BERR# (I/O). A.11. BINIT# (I/O) A.12. BNR# (I/O) A.13. BP[3:2]# (I/O). A.14. BPM[1:0]# (I/O).
1.0. INTRODUCTION 1.1. Terminology. 1.2. References. 2.0. ELECTRICAL SPECIFICATIONS 2.1. Pentium® Processor VREF 2.2. Power Management: Stop Grant Auto HALT. 2.3. Power Ground Pins. 2.4. Decoupling Recommendations 2.4.1. GTL+ DECOUPLING. 2.4.2. PHASE LOCK LOOP (PLL) DECOUPLING. 2.5. BCLK Clock Input Guidelines. 2.5.1. SETTING CORE CLOCK CLOCK RATIO. 2.6. Voltage Identification 2.7. JTAG Connection. 2.8. Signal Groups 2.8.1. ASYNCHRONOUS SYNCHRONOUS. 2.9. PWRGOOD. 2.10. THERMTRIP# 2.11. Unused Pins. 2.12. Maximum Ratings 2.13. Specifications. 2.14. GTL+ Specifications 2.15. Specifications. 3.0. GTL+ INTERFACE SPECIFICATION. 4.0. TOLERANT SIGNAL QUALITY SPECIFICATIONS 4.1. Overshoot/Undershoot Guidelines. 4.2. Ringback Specification. 4.3. Settling Limit Guideline. 5.0. THERMAL SPECIFICATIONS. 5.1. Thermal Parameters 5.1.1. AMBIENT TEMPERATURE.
PENTIUM® PROCESSOR WITH CACHE
A.15. BPRI# A.16. BR0#(I/O), BR[3:1]# A.17. BREQ[3:0]# (I/O) A.18. D[63:0]# (I/O) A.19. DBSY# (I/O). A.20. DEFER# A.21. DEN# (I/0). A.22. DEP[7:0]# (I/O) A.23. DID[7:0]# (I/O) A.24. DRDY# (I/O) A.25. DSZ[1:0]# (I/O) A.26. EXF[4:0]# (I/O). A.27. FERR# (O). A.28. FLUSH# (I). A.29. FRCERR (I/O) A.30. HIT# (I/O), HITM# (I/O). A.31. IERR# (O). A.32. IGNNE# (I). A.33. INIT# (I). A.34. INTR A.35. LEN[1:0]# (I/O). A.36. LINT[1:0] (I). A.37. LOCK# (I/O). A.38. (I). A.39. PICCLK A.40. PICD[1:0] (I/O). A.41. PWRGOOD (I). A.42. REQ[4:0]# (I/O). A.43. RESET# A.44. (I/O). A.45. RS[2:0]# A.46. RSP# A.47. SMI# A.48. SMMEM# (I/O). A.49. SPLCK# (I/O). A.50. STPCLK# A.51. A.52. TDI(I). A.53. (O). A.54. (I). A.55. TRDY (I). A.56. TRST FIGURES
Figure Pentium® Processor with Cache Block Diagram. Figure GTL+ Topology. Figure Transient Types Figure Timing Diagram Clock Ratio Signals Figure Example Schematic Clock Ratio Sharing Figure PWRGOOD Relationship Power-On. Figure Tolerant Group Derating Curve Figure Generic Waveform Figure Valid Delay Timings Figure Setup Hold Timings. Figure Mode BCLK PICCLK Timing Figure High GTL+ Receiver Ringback Tolerance Figure Reset Configuration Timings. Figure Power-On Reset Configuration Timings Figure Test Timings (Boundary Scan) Figure Test Reset Timings Figure Tolerant Signal Overshoot/Undershoot Ringback. Figure Technique Measuring Processor. Figure Location Measurement Back Plate (not scale). Figure Thermal Resistance Relationships Figure Typical Heat Sink Dimensions (View from Side-X). Figure Typical Heat Sink Dimensions (View from Side-Y). Figure Different Heat Sink Sizes Flow Rates. Figure Pentium® Processor with Cache Side Figure View Package Figure Pentium® Processor View with Power Locations. Figure Processor View with Back Plate Warpage Mapping. Figure Pedestal Shape Bottom Side View
TABLES
PENTIUM® PROCESSOR WITH CACHE
Table Typical Heat Sink Designs (View from Side-Y). Table Different Passive Heat Sink Sizes Flow Rates. Table Different Passive Heat Sink Sizes Flow Rates. Table Different Passive Heat Sink Sizes Flow Rates. Table Different Heat Sinks Flow Rates. Table Pentium® Processor with Cache Package Table Listing Order. Table Listing Alphabetic Order. Table Flatness Specification Table Pedestal Specification. Table Dimensions Figure Table Request Phase Decode Table Clock Ratios Versus Logic Levels. Table ASZ[1:0]# Signal Decode. Table ATTR[7:0]# Field Descriptions Table Special Transaction Encoding BE[7:0]# Table BR[3:0]# Signals Rotating Interconnect Table BR[3:0]# Signal Agent Table DID[7:0]# Encoding Table EXF[4:0]# Signal Definitions. Table LEN[1:0]# Data Transfer Lengths Table Transaction Types Defined REQa#/REQb# Signals Table Transaction Response Encodings
Figure Heat Sink with Pedestal Placement Processor Side View Figure Example Heat Sink Figure Coplanarity Specification Figure Expected Storage Failure Rates Stringent Storage Conditions.
Table Voltage Identification Definition Table Signal Groups Table Absolute Maximum Ratings Table Power Voltage Specifications (Option Table Power Voltage Specifications (Option Table GTL+ Signal Groups Specifications. Table Non-GTL+ Signal Groups Specifications. Table GTL+ Voltage Specifications Table Clock Specifications Table Supported Clock Ratios Table GTL+ Signal Groups Specifications. Table GTL+ Signal Groups Ringback Tolerance Table Tolerant Signal Groups Specifications. Table Reset Conditions Specifications Table APIC Clock APIC Specifications. Table Boundary Scan Interface Specifications. Table Signal Ringback Specifications. Table Typical Heat Sink Designs (View from Side-X).
1.0.
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example, D[3:0] `HLHL' refers `A', D#[3:0] `LHLH' also refers `A'. High logic level, logic level) word Preliminary appears occasionally. Check with your local Field Applications Engineer recent information.
INTRODUCTION
Pentium processor with cache multichip module targeted high-end 4-way multiprocessor capable server systems. component package contains Intel Pentium processor core, cache. cache built using SRAM found version Pentium processor. While version uses conventional ceramic package, Pentium processor with cache integrates three plastic package with aluminum heat spreader. This 387-pin package compatible with current Pentium processor footprint. Pentium processor with cache routes processor's high-speed cache interface through balanced nets thin film interconnect substrate SRAMs. This allows internal component operation speeds between Pentium processor cache die. Figure shows typical processor system implemented. Pentium
1.2.
References
referenced within this
following specification:
Pentium® Processor Buffer Models- IBIS Format World Wide page http://www.intel.com)
AP-523, Pentium® Processor Power Distribution Guidelines (Order Number 242764) AP-524, Pentium® Processor GTL+ Layout Guidelines (Order Number 242765) AP-525, Pentium® Processor Thermal Design Guidelines (Order Number 242766)
1.1.
Terminology
Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690) Pentium® Processor Family Developer's Manual, Volume Programmer's Reference Manual (Order Number 242691) Pentium® Processor Family Developer's Manual, Volume Operating System Writer's Guide (Order Number 242692) Pentium® Specification Update (Order Number 242689)
symbol after signal name refers active signal. This means that signal active state (based name signal) when driven low. example, when FLUSH# flush been requested. When Nonmaskable Interrupt (NMI) high, nonmaskable interrupt occurred. case lines where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted.
PENTIUM® PROCESSOR WITH CACHE
3570-01
Pentium® Processor
Pentium Processor
Pentium Processor
Pentium Processor
System Interface
High Speed Interface
Memory Interface
Figure Pentium® Processor with Cache Block Diagram
2.0. 2.1.
ELECTRICAL SPECIFICATIONS Pentium® Processor VREF
Most Pentium processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Pentium processor specification similar specification been enhanced provide larger noise margins reduced ringing. This accomplished increasing termination voltage level controlling edge rates. Because this specification different from standard specification, referred GTL+ this document.
GTL+ signals open-drain require external termination supply that provides high signal level. GTL+ inputs differential receivers which require reference signal (VREF). Termination (usually resistor each signal trace) used pull high voltage level control reflections stubfree transmission line. VREF used receivers determine signal logical logical Table termination voltage specifications GTL+, Section 4.0. GTL+ Interface Specification. There VREF pins Pentium processor ensure that internal noise will affect performance buffers. Pins (VREF[3:0]) must tied together pins A47, U41, AE47 AG45 (VREF[7:4]) must tied together. groups also tied each other desired.
1.5V
1.5V
stubs
ASIC ASIC
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Figure GTL+ Topology
GTL+ depends incident wave switching. Therefore timing calculations GTL+ signals based flight time opposed capacitive deratings. Analog signal simulation Pentium processor including trace lengths highly recommended when designing system with heavily loaded GTL+ bus. Intel's World Wide page (http://www.intel.com) download buffer models Pentium processor IBIS format.
2.2.
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required die. These have been added cleanly support voltage specification variations Pentium processor future processors. Section 2.6. explanation voltage identification pins. clean on-chip power distribution, Pentium processor (power) (ground) inputs. circuit board, VCCP pins must connected voltage island. Similarly, pins must connected system ground plane. Figure locations power ground pins.
Power Management: Stop Grant Auto HALT
2.4.
Decoupling Recommendations
Pentium processor allows Stop Grant Auto HALT modes immediately reduce power consumed device. When enabled, these cause clock stopped most CPU's internal units thus significantly reduces power consumption whole. Stop Grant entered asserting STPCLK# Pentium processor. When STPCLK# recognized Pentium processor, will stop execution will service interrupts. will continue snooping bus. Stop Grant power specified assuming snoop hits occur. Auto HALT low-power state entered when Pentium processor executes halt (HLT) instruction. this state, Pentium processor behaves executed halt instruction, additionally powers-down most internal units. Auto HALT, Pentium processor will recognize interrupts snoops. Auto HALT power specified assuming snoop hits interrupts occur. low-power stand-by mode Stop Grant Auto HALT defined Low-Power Enable configuration either lowest power achievable Pentium processor (Stop Grant power), power state which clock distribution left running (Idle power). "Low-power stand-by" disabled leaves core logic running, while "Low-power stand-by" enabled allows Pentium processor enter lowest power mode.
large number transistors high internal clock speeds, Pentium processor create large, short duration transient (switching) current surges that occur internal clock edges which cause power planes spike above below their nominal value properly controlled. Pentium processor also capable generating large average current swings between full power states, called Load-Change Transients, which cause power planes below their nominal value bulk decoupling adequate. Figure example these current fluctuations. Care must taken board design guarantee that voltage provided Pentium processor remains within specifications listed this volume. Failure result timing violations and/or reduced lifetime component. Adequate decoupling capacitance should placed near power pins Pentium processor. inductance capacitors such 1206 package surface mount capacitors recommended best high frequency electrical performance. Forty (40) 1206-style capacitors with ±22% tolerance make good starting point simulations this recommended decoupling when using Pentium Processor Voltage Regulator Module. Inductance should reduced connecting capacitors directly VCCP planes with minimal trace length between component pads vias plane. sure include effects board inductance within simulation. Also, when choosing capacitors use, bear mind operating temperatures they will tolerance that they rated Type better recommended (±22% tolerance over temperature range °C).
2.3.
Power Ground Pins
There pins defined package voltage identification (VID). These pins specify voltage
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Current Current Averaged Current
Load-Change Transient
Switching Transient
Switching Transient
3570-03
Figure Transient Types Bulk capacitance with Effective Series Resistance (ESR) should also placed near Pentium processor order handle changes average current between low-power normal operating states. About 4000 capacitance with makes good starting point simulations, although more capacitance needed bring down this level current technology industry. Pentium Processor Voltage Regulator Modules already contain this bulk capacitance. sure determine what available market before choosing parameters models. Also, include power supply response time cable inductance full simulation. AP-523, Pentium® Processor Power Distribution Guidelines (Order Number 242764), power modeling Pentium processor. 2.4.1. GTL+ DECOUPLING methodologies processor. Notice that existence external power entering through buffers causes current higher than current evidenced Figure 2.4.2. PHASE LOCK LOOP (PLL) DECOUPLING
Isolated analog decoupling required internal PLL. This should equivalent ceramic capacitance. capacitor should type better should across PLL1 PLL2 pins Pentium processor. ("Y5R" implies ±15% tolerance over temperature range °C.)
2.5.
BCLK Clock Input Guidelines
Although Pentium processor GTL+ receives power external Pentium processor, should noted that this power supply will also require same diligent decoupling
BCLK input directly controls operating speed GTL+ interface. GTL+ external timing parameters specified with respect rising edge BCLK input. Clock multiplying within processor provided internal Phase Lock Loop (PLL) which requires constant frequency BCLK input. Therefore BCLK frequency cannot
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Using CRESET# (CMOS reset), circuit Figure used share pins. pins processors bussed together allow them compatibility processor. component used multiplexer must have outputs that drive higher than order meet Pentium processor's tolerant buffer specifications. multiplexer output current should limited maximum, case VCCP supply processor ever fails. pull-down resistors between multiplexer processor force ratio into processor event that Pentium processor powers before multiplexer and/or chip set. This prevents processor from ever seeing ratio higher than final ratio. multiplexer were powered VCCP, CRESET# would still unknown until supply came power CRESET# driver. pull-down used CRESET# instead four between multiplexer Pentium processor. this case, multiplexer must designed such that compatibility inputs truly ignored their state unknown. case, compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible. mode processors, multiplexer will needed pair, multiplexer will need clocked using BCLK meet setup hold times processors. This require high speed programmable logic.
changed dynamically. however changed when RESET# active assuming that reset specifications clock configuration signals. Pentium processor core frequency must configured during reset using A20M#, IGNNE#, LINT1/NMI, LINT0/INTR pins. value these pins during RESET#, until clocks beyond RESET# pulse, determines multiplier that will internal core clock. Appendix definition these pins during reset. other times their functionality defined compatibility signals that pins named after. These signals tolerant driven existing logic devices. This important both functions pins. Supplying clock multiplier this required order increase processor performance without changing processor design, maintain frequency such that system boards designed function properly frequencies increase. 2.5.1. SETTING CORE CLOCK CLOCK RATIO
Table lists configuration pins values that must driven reset time order core clock clock ratio. Figure shows timing relationship required clock ratio signals with respect RESET# BCLK. CRESET# from 82453GX 82453KX 82440FX) shown since timing useful controlling multiplexing function that required sharing pins.
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Compatibility
BCLK RESET#
CRESET#
Ratio pins#
Final Ratio
Final Ratio
3570-04
Figure Timing Diagram Clock Ratio Signals
3.3V
A20M# IGNNE# LINT1/NMI LINT0/INTR
3.3V
Pentium®
Ratio:
CRESET#
Processor
3570-05
Figure Example Schematic Clock Ratio Sharing
2.6.
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possibility Pentium processor supply running event failure supply lines. Note that specification Pentium Processor Voltage Regulator Modules allows these signals either compatible levels opens shorts. Using them compatible levels will require pull-up resistors input voltage regulator voltage divider input voltage regulator resistors chosen should cause current through exceed specification Table There must other components these signals uses them opens shorts.
Voltage Identification
There four Voltage Identification Pins Pentium processor package. These pins used support automatic selection power supply voltage. These pins signals each either open circuit package short circuit VSS. opens shorts define voltage required processor. This been added cleanly support voltage specification variations future Pentium processors. These pins named VID0 through VID3 definition these pins shown Table this table refers open refers short ground. VCCP power supply should supply voltage that requested disable itself. Table Voltage Identification Definition VID[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 Voltage Setting VID[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 Voltage Setting Present
2.7.
JTAG Connection
debug port described Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), should start JTAG chain with first component coming from Debug Port from last component going Debug Port. recommended pull-up value Pentium processor pins voltage levels supported Pentium processor JTAG logic, recommended that Pentium processors other logic level components within system first JTAG chain. translation buffer should used connect rest chain unless component used next that capable accepting input. Similar considerations must made TCK, TRST#. Components need these signals buffered match required logic levels. multiprocessor system, cautious when including empty Pentium processor sockets scan chain. sockets scan chain must have processor installed complete chain system must support method bypass empty sockets. Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), full information putting debug port JTAG chain.
NOTES: Nominal setting requiring regulation Pentium® processor VCCP pins under conditions. Support expected V-2.3 Open circuit; Short
Support wider range settings will benefit system meeting power requirements future Pentium processors. Note that `1111' opens) used detect absence processor given socket long power supply used does affect these lines. these pins, they need pulled external resistor another power source. power source chosen should that guaranteed stable whenever supply voltage regulator stable. This will prevent
2.8.
Signal Groups
order simplify following discussion, signals have been combined into groups buffer type. outputs open drain require external
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high-level source provided externally termination pull-up resistor.
GTL+ input signals have differential input buffers which VREF their reference signal. GTL+ output signals require termination Later this document, term "GTL+ Input" refers GTL+ input group well GTL+ group when receiving. Similarly, "GTL+ Output" refers GTL+ output group well GTL+ group when driving. tolerant, Clock, APIC JTAG inputs each driven from ground tolerant, APIC, JTAG outputs each pulled high much Table specifications. groups signals contained within each group shown Table Note that signals ASZ[1:0]#, ATTR[7:0]#, BE[7:0]#, BREQ#[3:0], DEN#, DID[7:0]#, DSZ[1:0]#, EXF[4:0]#, LEN[1:0]#, SMMEM#, SPLCK# GTL+ signals that shared onto another pin. Therefore they appear this table. 2.8.1. ASYNCHRONOUS SYNCHRONOUS
PICCLK with respect BCLK. With enabled, PICCLK must BCLK synchronized with respect BCLK. PICCLK must always BCLK least more than
2.9.
PWRGOOD
PWRGOOD tolerant input. expected that this signal will clean indication that clocks system VCCP supplies stable within their specifications. Clean implies that signal will remain (capable sinking leakage current) without glitches, from time that power supplies turned until they come within specification. signal will then transition monotonically high (3.3 state. Figure illustrates relationship PWRGOOD other system signals. PWRGOOD driven inactive time, power clocks must again stable before rising edge PWRGOOD. must also meet minimum pulse width specification Table followed RESET# pulse, Table This signal must supplied Pentium processor used protect internal circuits against voltage sequencing issues. this signal recommended added reliability. This signal does need synchronized operation. should remain high throughout boundary scan testing.
GTL+ signals synchronous. tolerant signals applied asynchronously, except when running processors mode. mode, synchronization logic required signals (except PWRGOOD) going both processors. Also note timing requirements
Group Name GTL+ Input GTL+ Output GTL+ Tolerant Input Tolerant Output Clock4 APIC Clock4 APIC I/O4 JTAG Input4 JTAG Output4 Power/Other5 PRDY# BCLK PICCLK
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Table Signal Groups Signals BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#, STPCLK# FERR#, IERR#, THERMTRIP#3
PICD[1:0] TCK, TDI, TMS, TRST# CPUPRES#, PLL1, PLL2, TESTHI, TESTLO, UP#, VCCP, VCC5, VID[3:0], VREF[7:0],
NOTES: BR0# only BREQ# signal that bi-directional. internal BREQ# signals mapped onto pins after agent determined. PWRGOOD Section 2.9. THERMTRIP# Section 2.10. These signals tolerant pull-up resistor PICD[1:0] TDO. CPUPRES# ground defined allow designer detect presence processor socket. (preliminary) PLL1 PLL2 decoupling internal (see Section 2.4.2.). TESTHI pins should tied VCCP. pull-up used. Section 2.11. TESTLO pins should tied VSS. pull-down used. Section 2.11. open Pentium® processor. VCCP primary power supply. VCC5 unused Pentium processor. VID[3:0] lines described Section 2.6. VREF [7:0] reference voltage pins GTL+ buffers. ground.
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Figure PWRGOOD Relationship Power-On
2.10.
THERMTRIP#
Pentium processor protects itself from catastrophic overheating internal thermal sensor. This sensor well above normal operating temperature ensure that there false trips. processor will stop execution when junction temperature exceeds ~135 This signaled system THERMTRIP# pin. Once activated, signal remains latched, processor stopped, until RESET# goes active. There hysteresis built into thermal sensor itself, long temperature drops below trip level, RESET# pulse will reset processor execution will continue. temperature dropped beyond trip level, processor will continue drive THERMTRIP# remain stopped.
reliable operation, always connect unused inputs appropriate signal level. Unused GTL+ inputs should pulled-up VTT. Unused active tolerant inputs should connected with resistor unused active high inputs should connected ground (VSS). resistor must also used when tying bi-directional signals power ground. When tying signal power ground, resistor will also allow fully testing processor after board assembly. unused pins, suggested that resistors used pull-ups (except PICD[1:0] discussed above), resistors used pull-downs. Never directly supply other than processor's VCCP supply VSS.
2.12. 2.11. Unused Pins
RESERVED pins must remain unconnected. pins named TESTHI must pulled higher than VCCP, tied directly VCCP. pins named TESTLO must pulled tied directly VSS. PICCLK must driven with clock input, PICD[1:0] lines must each pulled-up with separate resistor, even when APIC will used.
Maximum Ratings
Table contains Pentium processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. Pentium processor should receive clock while subjected these conditions. Functional operating conditions given tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Symbol TStorage TBias VCCP(Abs) VIN3 IVID
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Table Absolute Maximum Ratings1 Parameter Storage Temperature Case Temperature under Bias Primary Supply Voltage with respect GTL+ Buffer Input Voltage with respect Tolerant Buffer Input Voltage with respect Maximum input current Maximum current -0.5 -0.5 -0.5 Operating Voltage VCCP+ exceed VCCP+ exceed Unit
Notes
NOTES: Functional operation absolute maximum minimum implied guaranteed. Operating voltage voltage that component designed operate Table Table Parameter applies GTL+ signal groups only. Parameter applies tolerant, APIC, JTAG signal groups only. Current flow through buffer diodes when VCCP+1.1 power supply fault condition while power supplies sequencing. Thermal stress should minimized cycling power VCCP supply fails.
2.13.
Specifications
Table through Table list specifications associated with Pentium processor. Specifications valid only while meeting processor specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter. Pentium processor with cache dissipates more power than Pentium processor with cache. DC-DC converter Pentium processor with cache Pmax limit, need re-designed Pmax values well values. There options this redesign. (Table Table list specifications these options.) first option increase current available from DC-DC converter "ICCP1" while keeping normal VCCP. second option ignore VID[0:3] value from processor, supply VCCP (typical) instead. This will require lower
"ICCP2" current tighter limit undershoot overshoot values power supply range benefit second option lower "Pmax2" power dissipation requirement compared "Pmax1", which required from first option. Pentium processor with cache tested satisfy either solution. Most signals Pentium processor GTL+ signal group. These signals specified terminated specifications these signals listed Table Care should taken read notes associated with each parameter. allow compatibility with other devices, some signals tolerant therefore terminated driven specifications these tolerant inputs listed Table Care should taken read notes associated with each parameter.
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Unit Notes
Table Power Voltage Specifications (Option Symbol VCCP1 Pmax1 ICCP1 ISGntP Parameter Primary Thermal Design Power VCCP1 Current Stop Grant Current Operational Case Temperature 3.135 Typical 3.465 15.0
Table Power Voltage Specifications (Option Symbol VCCP2 Pmax2 ICCP2 ISGntP Parameter Primary Thermal Design Power VCCP2 Current Stop Grant Current Operational Case Temperature Typical 14.25 Unit
Notes
NOTES: other specifications, specifications timings identical Pentium® processor with cache components. meet this tolerance, equivalent forty (40) capacitors (1206 packages) should placed near power pins device. least capacitance should exist power planes, with less than inductance resistance between capacitance pins processor, assuming regulator setting +/-1%. current measured VCC, CMOS pins driven with VIH= VCCP VIL=0V during execution ICC-StopGrant/AutoHalt Tests. Maximum values measured typical take into account thermal time constant package. Typical values tested, suggest maximum power expected system during actual operation. designing system typical power level, fail safe mechanism should used guarantee component Tcase specification case workload anomalies. Values measured typical VCCP asserting STPCLK# executing HALT instruction, with Low_Power_Enable enabled. values tested guaranteed design.
Symbol IREF CGTL+
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Table GTL+ Signal Groups Specifications Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Output Current Leakage Current Reference Voltage Current GTL+ Capacitance -0.3 VREF 0.30 VREF -0.2 VCCP 0.60 ±100 Unit
Notes Table
Table
NOTES: VREF worst case, nominal. Noise VREF should accounted for. Parameter measured into resistor Min. max. guaranteed design/characterization. VPIN VCCP) Total current VREF pins. Section 2.1. details VREF connections. Total buffer, package parasitics socket. Capacitance values guaranteed design GTL+ buffers.
Table Non-GTL+1 Signal Groups Specifications Symbol CTOL CCLK CTCK Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage Input Leakage Current Tol. Capacitance BCLK Input Capacitance Input Capacitance -0.3 ±100 Unit
Notes
Outputs Open-Drain
Except BCLK TCK,
NOTES: Table applies tolerant, APIC, JTAG signal groups. Parameter measured (for with inputs). Parameter guaranteed design (for with CMOS inputs). Vpin VCCP) Total buffer, package parasitics socket. Capacitance values guaranteed design.
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2.14.
GTL+ Specifications
GTL+ must routed daisy-chain fashion with termination resistors each every signal trace. These termination resistors placed between ends signal trace voltage supply generally chosen approximate board impedance. valid high levels determined input buffers using reference voltage called VREF. Table lists
nominal specifications GTL+ termination voltage (VTT) GTL+ reference voltage (VREF). important that printed circuit board impedance specified held ±20% tolerance, that intrinsic trace capacitance GTL+ signal group traces known. more details GTL+, GTL+ interface specification Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690).
Notes ±10% ±2%,
Table GTL+ Voltage Specifications Symbol VREF Parameter Termination Voltage Input Reference Voltage 1.35 VTT-2% Typical 1.65 Units
NOTE: VREF should created from voltage divider resistors.
2.15.
Specifications
covers APIC timing, Table covers Boundary Scan timing. specifications GTL+ signal group relative rising edge BCLK input. GTL+ timings referenced VREF both logic levels unless otherwise specified. Care should taken read notes associated with particular timing parameter.
Table through Table list specifications associated with Pentium processor. Timing Diagrams begin with Figure specifications broken into categories. Table contains clock specifications, Table Table contain GTL+ specifications, Table tolerant Signal group specifications, Table contains timings reset conditions, Table
Table Clock Specifications Parameter Core Frequency Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 50.00 66.67 Unit
Figure
Notes MHz,1
@>2.0 @<0.8 (0.8 (2.0
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NOTES: internal core clock frequency derived from clock. clock ratio must driven into Pentium processor signals LINT[1:0], A20M# IGNNE# reset. descriptions these signals Appendix 100% tested. Guaranteed design/characterization. Measured rising edge adjacent BCLKs jitter present must accounted component BCLK skew between devices. Clock jitter measured from rising edge clock signal next rising edge remain within clock jitter specifications, clock periods must within ideal clock period given frequency. example, 66.67 clock with nominal period must have single clock period that greater than 15.3 less than 14.7 ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between MHz. spectrum analyzer display frequency spectrum clock driver your system.
Table Supported Clock Ratios1 Component 5/2X 7/2X
NOTE: Only those indicated tested during manufacturing test process.
Table GTL+ Signal Groups Specifications T7A: T7B: T10: Parameter GTL+ Output Valid Delay GTL+ Output Valid Delay GTL+ Input Setup Time GTL+ Input Hold Time RESET# Pulse Width 0.80 0.80 0.70 Unit Figure Notes
NOTES: Valid delay timings these signals specified into idealized resistor with Minimum values guaranteed design. GTL+ interface specification Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), actual test configuration. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification takes into account V/ns edge rate allowable VREF variation. Guaranteed design. After VCC, VTT, VREF, BCLK clock ratio become stable.
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Figure Notes
Table GTL+ Signal Groups Ringback Tolerance Parameter Overshoot Minimum Time High Amplitude Ringback Duration Square wave Ringback Final Settling Voltage -100 Unit
NOTE: Specified edge rate 0.3-0.8 V/ns. GTL+ interface specification Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), definition these terms, generic waveforms. values determined design/characterization.
Table Tolerant Signal Groups Specifications Parameter Unit BCLKs BCLKs Figure Notes
T11: Tolerant Output Valid Delay T12: Tolerant Input Setup Time T13: Tolerant Input Hold Time T14: Tolerant Input Pulse Width, except PWRGOOD T15: PWRGOOD Inactive Pulse Width
Both levels
NOTES: Valid delay timings these signals specified into Figure capacitive derating curve. These inputs driven asynchronously. However, guarantee recognition specific clock, setup hold times with respect BCLK must met. These signals must driven synchronously mode. A20M#, IGNNE#, INIT# FLUSH# asynchronous inputs, guarantee recognition these signals following synchronizing instruction such write instruction, they must valid with active RS[2:0]# signals corresponding synchronizing transaction. INTR only valid APIC disable mode. LINT[1:0]# only valid APIC enabled mode. When driven inactive, after Power, REF, BCLK, ratio signals stable. Specified over clock rise time fall time ranges these signals, between defined Figure
12.00 11.50 11.00 10.50 10.00 9.50 9.00 8.50 8.00 7.50 7.00
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Figure Tolerant Group Derating Curve
Table Reset Conditions Specifications T16: T17: T18: T19: T20: Parameter Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time Unit BCLKs BCLKs BCLKs BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
NOTE: reset, clock ratio defined these signals must safe value (their final lower multiplier) within this delay unless PWRGOOD being driven inactive.
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Figure Notes
Table APIC Clock APIC Specifications Parameter 33.3 Unit
T21A: PICCLK Frequency T21B: Mode BCLK PICCLK offset T22: T23: T24: T25: T26: T27: T28: T29: PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time PICD[1:0] Valid Delay
NOTES: With enabled PICCLK must BCLK synchronized with respect BCLK. PICCLK must always BCLK least more than Referenced PICCLK Rising Edge. open drain signals, Valid Delay synonymous with Float Delay. Valid delay timings these signals specified into Specified over rise time fall time ranges these signals, between defined Figure
Parameter T30: Frequency T31: Period T32: High Time T33: Time T34: Rise Time T35: Fall Time T36: TRST# Pulse Width T37: TDI, Setup Time T38: TDI, Hold Time T39: Valid Delay T40: Float Delay
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Table Boundary Scan Interface Specifications 62.5 Unit @2.0 @0.8 (0.8 V-2.0 (2.0 V-0.8
Figure
Notes
Asynchronous
T41: Nontest Outputs Valid Delay T42: Nontest Outputs Float Delay T43: Nontest Inputs Setup Time T44: Nontest Inputs Hold Time
NOTES: 100% tested. Guaranteed design/characterization. added maximum rise fall times every below MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified into terminated Nontest Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. PWRGOOD should driven high throughout boundary scan testing. During Debug Port operation, normal specified timings rather than boundary scan timings. Specified over rise time fall time ranges these signals, between defined Figure
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Rise Time Fall Time High Time Time Period
Figure Generic Waveform
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Valid Delay Pulse Width GTL+ signal group; Tolerant, APIC, JTAG signal groups GTL+ signals must achieve high level least GTL+ signals must achieve level most
Figure Valid Delay Timings
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Setup Time Hold Time GTL+ signal group; Tolerant, APIC JTAG signal groups
Figure Setup Hold Timings
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T21B (FRC Mode BCLK PICCLK offset)
Figure Mode BCLK PICCLK Timing
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VREF
0.3-0.8
VREF
VREF
Vstart
+0.05ns
Clock
Time
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Case analogous. Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage
Figure High GTL+ Receiver Ringback Tolerance
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3570-13
(GTL+ Input Hold Time) (GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Delay Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Setup Time)
Figure Reset Configuration Timings
3570-14
(PWRGOOD Inactive Pulse Width) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time)
Figure Power-On Reset Configuration Timings
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(All Nontest Inputs Setup Time) (All Nontest Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold Time) (TDO Valid Delay) (All Nontest Outputs Valid Delay) (All Nontest Outputs Float Delay)
Figure Test Timings (Boundary Scan)
3570-16
(TRST# Pulse Width)
Figure Test Reset Timings
3.0.
GTL+ INTERFACE SPECIFICATION
generic GTL+ interface specification, Pentium® Processor Family Developer's Manual Volume Specifications (Order Number 242690), Chapter
They Overshoot/Undershoot, Ringback Settling Limit. three signal quality parameters shown Figure Pentium® Processor Buffer Models-IBIS Format World Wide page http://www.intel.com) contain models simulating tolerant signal distribution.
4.1. 4.0. TOLERANT SIGNAL QUALITY SPECIFICATIONS
Overshoot/Undershoot Guidelines
signals that tolerant should also meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect long term reliability component. There three signal quality parameters defined tolerant signals.
Overshoot undershoot) absolute value maximum voltage allowed above nominal high voltage below VSS. overshoot/undershoot guideline limits transitions beyond VCCP fast signal edge rates. Figure processor damaged repeated overshoot events tolerant buffers charge large
enough (i.e., overshoot great enough). However, excessive ringback dominant harmful effect resulting from overshoot undershoot (i.e., violating overshoot/undershoot guideline will make satisfying ringback specification difficult). overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without on-chip protection diodes present because diodes will begin clamping tolerant signals beginning approximately above VCCP below VSS. signals reaching clamping voltage, then this issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
4.2.
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back after achieving farthest excursion. Figure illustration ringback. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal Ringback specification allowed under circumstances. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications Non-GTL+ signals. Table Signal Ringback Specifications Transition Maximum Ringback (with input diodes present)
Ringback Specification
Ringback refers amount reflection seen after signal undergone transition. ringback specification voltage that signal rings
3570-17
Figure Tolerant Signal Overshoot/Undershoot Ringback
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4.3.
Settling Limit Guideline
5.1.1.
AMBIENT TEMPERATUR
Settling Limit defines maximum amount ringing receiving that signal must limited before next transition. amount allowed total signal swing -VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify Settling Limit done either with without input protection diodes present. Violation Settling Limit guideline acceptable simulations 5-10 successive transitions show amplitude ringing increasing subsequent transitions.
Ambient temperature, temperature ambient surrounding package. system environment, ambient temperature temperature upstream from package close vicinity; active cooling system, inlet active cooling device. 5.1.2. MEASURING CASE TEMPERATUR
5.0.
THERMAL SPECIFICATIONS
This section defines thermal specification Pentium processor with cache.
ensure functionality reliability, Pentium processor with cache specified proper operation when (case temperature) within specified range Table Special care required when measuring case temperature ensure accurate temperature measurement. Thermocouples, which must calibrated prior measurement, often used measure When measuring temperature surface which different temperature from surrounding ambient air, errors could introduced measurements conducted properly. measurement errors could having poor thermal contact between thermocouple junction surface, heat loss radiation, conduction through thermocouple heads. verify that proper maintained, should measured package heat spreader (package side, opposite pins). measurement made same with without heat sink attached. When heat sink attached, hole (smaller than .150" diameter) should drilled through heat sink allow probing package surface. Figure illustration measure Figure shows location measure
5.1.
Thermal Parameters
This section defines terms used Pentium processor with cache thermal analysis.
Probe Heat Sink
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Figure Technique Measuring Processor
1.23"
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2.66"
2.46"
0.59"
3570-19
Figure Location Measurement Back Plate (not scale)
minimize measurement recommends following approach:
errors,
Intel
gauge finer diameter type thermocouples. Attach thermocouple bead junction center package surface using high thermal conductivity cements. thermocouple should attached angle shown Figure hole size should smaller than 0.150" diameter hole should filled with grease. Make sure there contact between thermocouple cement heat sink base. contact will affect thermocouple reading. THERMAL RESISTANC
bottom thermal cooling solution. This value strongly dependent material, conductivity, thickness thermal interface used. values depend material, thermal conductivity, geometry thermal cooling solution well airflow rates. parameters defined following relationships. Where: Case-to-Ambient thermal resistance (°C/W) Case-to-Sink thermal resistance (°C/W) Sink-to-Ambient thermal resistance (°C/W)
5.1.3.
thermal resistance value case-toambient, used measure cooling solution's thermal performance. comprised case-to-sink thermal resistance, sinkto-ambient thermal resistance, measure thermal resistance along heat flow path from package
Case temperature defined location (°C) Ambient temperature (°C) Device power dissipation
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5.2.
5.2.1.
Thermal Analysis
TYPICAL PASSIVE HEAT SINK DESIGNS
Table Table provide dimensions three heat sinks used generate data Table Table These heat sinks designs reference only. definition pedestal, refer Section 6.2.
Ambient Heat Sink Thermal Interface Material
Ceramic Package
Heat Spreader
3570-20
Figure Thermal Resistance Relationships
X-Fin Space
X-Fin Width
Base Thickness Z-Height
X-Pedestal Width X-Length
3570-21
(not scale, does reflect actual number fins)
Figure Typical Heat Sink Dimensions (View from Side-X)
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Y-Fin Space
Y-Fin Width
Pedestal Thickness
Y-Pedestal Length Y-Length
3570-22
(not scale, does reflect actual number fins)
Figure Typical Heat Sink Dimensions (View from Side-Y)
Table Typical Heat Sink Designs (View from Side-X) Heat Sink Design Z-Height 1.00" 1.32" 1.32" X-Length 2.5" 3.0" 3.6" Base Thickness 0.155" 0.170" 0.165" X-Fin Width 0.085" 0.050" 0.060" X-Fin Space 0.183" 0.218" 0.212" X-Pedestal Width 1.2" 1.2" 1.2"
Table Typical Heat Sink Designs (View from Side-Y) Heat Sink Design Y-Length 3.15" 3.15" 3.15" Y-Fin Width 0.090" 0.200" 0.200" Y-Fin Space 0.127" 0.126" 0.131" Y-Pedestal Length 2.1" 2.1" 2.1" Pedestal Thickness 0.020" 0.020" 0.020" 0.25" 0.25" 0.25" 0.24" 0.34" 0.30"
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5.2.2. TABLES CURVES PASSIVE HEAT SINKS FLOW RATES
1.09 0.86 0.76 0.83 0.69 0.61
Table Different Passive Heat Sink Sizes Flow Rates CA[°C/W] Flow Rate [LFM] Heat Sink Size 2.5" 3.15" 1.00" 3.0" 3.15" 1.32" 3.6" 3.15" 1.32" 2.09 1.50 1.30 1.70 1.26 1.10 1.50 1.13 0.99 1.32 1.01 0.89 1.19 0.92 0.81
Table Different Passive Heat Sink Sizes Flow Rates [°C/W] Flow Rate [LFM] Heat Sink Size 2.5" 3.15" 1.00" 3.0" 3.15" 1.32" 3.6" 3.15" 1.32" 1.02 0.82 0.72 0.96 0.78 0.69 0.92 0.75 0.67 0.88 0.73 0.64 0.85 0.70 0.62
Table Different Passive Heat Sink Sizes Flow Rates [°C/W] Flow Rate [LFM] Heat Sink Size 2.5" 3.15" 1.00" 3.0" 3.15" 1.32" 3.6" 3.15" 1.32" 0.81 0.67 0.59 0.79 0.66 0.58 0.77 0.64 0.57 0.76 0.63 0.56
NOTE: calculated based following formula: (TC-TA) where package case temperature, ambient temperature, total power dissipation from processor. values shown this table typical values. actual values depend heat sink design, interface between heat sink package, flow system, thermal interactions between processor surrounding components, through PCB, ambient temperature.
Theta [C/W]
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2.50" 3.15" 1.00" 3.0" 3.15" 1.32" 3.6" 3.15" 1.32"
Flow Rate [LFM]
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Figure Different Heat Sink Sizes Flow Rates Table Different Heat Sinks Flow Rates [°C/W] External Flow Rate [LFM] Heat Sink Design Single Dual Overall Size 2.50" 3.15" 1.25" 2.55" 3.20" 1.00" 1.25 0.81 1.25 0.79 1.22 0.80 1.19 0.80 1.17 0.80
5.2.3.
HEAT SINK DESIGNS
5.2.4.
heat sink also used cooling Pentium processor. Table shows single-fan design design with small fans. small fans more effective than larger fan. Also, notice minimal impact external airflow over heat sinks.
EFFECT THERMAL GREASE PEDESTAL SIZE THERMAL PERFORMANC
Thermal performance interface material between package surface heat sink base determined following factors:
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Thermal conductivity interface material contact area interface material between package surface heat sink base interface material thickness after heat sink assembly
higher thermal resistance, less efficient interface transferring heat. That higher thermal resistance, higher temperature drop across interface. Thermal resistance increases with interface material thickness. higher thermal conductivity interface material, lower thermal resistance addition, larger pedestal size corresponding larger contact area results lower thermal
resistance assuming interface thickness remains same. However, interface thickness determined flatness package surface heat sink base. higher flatness, thicker interface. Although pedestal will result smaller contact area, pedestal with thinner interface thickness. package surface with less flatness around package edge, pedestal significantly reduce interface thickness, resulting better thermal performance despite reducing contact area.
6.0.
MECHANICAL SPECIFICATIONS
following figures table show package dimensions Pentium processor with cache.
Chamfer Places
+/-0.005
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Figure Pentium® Processor with Cache Side
+/-0.005
1.76"
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2.66"
0.165" Body
2.46"
Tooling Holes
0.70"
0.298"
0.13" Tooling Holes 2.36"
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Figure View Package
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Table Pentium® Processor with Cache Package Parameter Package Type Total Pins Array Length Diameter Finish Package Length Package Width Package Body (not including pins) Flatness Heat Spreader Size Tooling Holes Diameter Weight Value Plastic with integrated Anodized Aluminum heat spreader Modified Staggered (Pentium® processor footprint) 0.130" 0.005" fillet) 0.018" 0.002" (rounded end) Gold plated, sockets only 2.66" +/-0.005" (7.76 0.013) 2.46" +/-0.005" (6.25 0.013) 0.165" 0.010" (0.419 0.025) Section 6.2. 2.66" 2.46" (7.76 6.25 with four through package tooling holes 0.062" diameter1 grams
NOTE: tooling holes heat sink attach component hold down mechanics. Intel will guarantee position, size existence these holes.
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VccP Vcc5 Other
2H2O
3520-26
Figure Pentium® Processor View with Power Locations
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6.1.
Pinout
CPUPRES# VCCP VCCP VCCP VCCP VCCP VCCP VCCP A35# IERR# BERR# VREF1 FRCERR INIT# FERR# PLL1 TESTLO PLL2
Table listing number order. Table listing name order. Please Section 2.8. determine signal's type. signals described Appendix other pins described Section 2.0. Table Table Listing Order Signal Name VREF0 STPCLK# TRST# IGNNE# A20M# FLUSH# THERMTRIP# BCLK RESERVED TESTHI TESTHI D14# D10# D11# D13# D16# VREF4
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Table Listing Order (Continued) D12# D15# D17# D20# D18# D19# D21# A29# A30# A32# A33# A34# D22# D23# D25# D24# D26# VCCP VCCP VCCP VCCP A22# A24# A27#
A26# A31# D27# D29# D30# D28# D31# A19# A21# A20# A23# A28# D32# D35# D38# D33# D34# VCCP VCCP RESERVED A16# A15# A18# A25# D37# D40#
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VREF2 AP1# D59# D57# D54# D53# D50# VCCP VCCP AP0# RSP# BPRI# BNR# BR3# DEP7# VREF6 D60# D56# D55# SMI# BR1# REQ4# REQ1#
Table Listing Order (Continued) D43# D36# D39# A12# A14# A11# A13# A17# D44# D45# D47# D42# D41# VCCP VCCP VCCP VCCP A10# D51# D52# D49# D48# D46#
AA39 AA41
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Table Listing Order (Continued) REQ0# DEP2# DEP4# D63# D61# D58# VCCP VCCP REQ3# REQ2# DEFER# VREF3 TRDY# PRDY# RESET# DEP1# DEP6# D62# BR2# DRDY# DBSY# HITM# LOCK# BPM1# PICD0
AA43 AA45 AA47 AB40 AB42 AB44 AB46 AC39 AC41 AC43 AC45 AC47 AE39 AE41 AE43 AE45 AE47
PICCLK PREQ# DEP5# VCCP VCCP RESERVED HIT# BR0# RS0# BP3# BPM0# BINIT# DEP0# DEP3# RESERVED ADS# RS1# RS2# AERR# TESTHI PICD1 BP2# RESERVED VREF5
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VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VID0 VID1 VID2 VID3 RESERVED TESTLO
Table Listing Order (Continued) AF40 AF42 AF44 AF46 AG39 AG41 AG43 AG45 AG47 AJ39 AJ41 AJ43 AJ45 AJ47 VCC5 RESERVED PWRGOOD RESERVED RESERVED LINT1/NMI LINT0/INTR VREF7 RESERVED VCCP VCCP VCCP VCCP VCCP VCCP
AL39 AL41 AL43 AL45 AL47 AN39 AN41 AN43 AN45 AN47 AQ39 AQ41 AQ43 AQ45 AQ47 AS39
AS41 AS43 AS45 AS47 AU39 AU41 AU43 AU45 AU47 AW39 AW41 AW43 AW45 AW47 AY39 AY41
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Table Listing Order (Continued) TESTLO TESTLO TESTLO RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
AY43 AY45 AY47 BA11 BA13 BA15 BA17 BA19 BA21 BA23 BA25 BA27 BA29 BA31 BA33 BA35 BA37 BA39 BA41 BA43 BA45 BA47
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TESTLO TESTLO VCCP VCCP VCCP VCCP TESTLO RESERVED TESTLO RESERVED RESERVED
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Table Listing Order (Continued) BC11 BC13 BC15 BC17 BC19 BC21 BC23 BC25 BC27 BC29 BC31 BC33 BC35 BC37 BC39 BC41 BC43 BC45 BC47 RESERVED TESTLO TESTLO RESERVED RESERVED RESERVED RESERVED TESTLO RESERVED TESTLO
Table Listing Alphabetic Order Signal Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29#
Signal Name A30# A31# A33# A34# A35# ADS# AERR# AP0# AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1# BR2# BR3# CPUPRES#
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Table Listing Alphabetic Order (Continued)
D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# AC43 D20# D21# AE43 D22# AC39 D23# AC41 D24# AA39 D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37#
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AC47 AA47 AG43 AG41 AA43 AA41 AE41 AA45
Table Listing Alphabetic Order (Continued) Signal Name D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0#
DEP1# DEP2# DEP3# DEP4#
DEP5# DEP6# DEP7# DRDY# FERR# FLUSH# FRCERR HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# AC45 REQ4#
Signal Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
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Table Listing Alphabetic Order (Continued)
RESERVED RESERVED RESERVED RESERVED RESERVED
AY45 AY47 BA11 BA35 BA41 BA45 BC11 BC19 BC23 BC27 BC31 BC35 AE39 AS39 AS41 AS43
RESERVED RESERVED AE45 RESERVED RESERVED RESERVED AG39 RESERVED AG47 RESERVED RESERVED AS47 RESERVED RESET# RS0# AU39 RS1# AU43 RS2# AU47 RSP# SMI# STPCLK# AW41 AW45 TESTHI TESTHI TESTHI TESTLO AY39 TESTLO AY41 TESTLO AY43 TESTLO
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AB44 AJ41 AJ45 AL39 AL43 AL47 AN41 AN45 AQ39 AQ43 AQ47 BA17 BA21 BA25
Table Listing Alphabetic Order (Continued) Signal Name TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO TESTLO THERMTRIP# TRDY# TRST# VCC5 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP AS45
VCCP VCCP VCCP VCCP
BA13 VCCP BA15 VCCP BA33 VCCP BA37 VCCP BC13 VCCP BC15 VCCP BC33 VCCP BC37 VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
Signal Name VCCP VID0 VID1 VID2 VID3 VREF0 VREF1 VREF2 VREF3 VREF4 VREF5 VREF6 VREF7
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Table Listing Alphabetic Order (Continued) BA29
AB40 AB42 AB46 AF40 AF42 AF44 AF46
AE47 AG45
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BA19 BA23 BA27 BA31 BA39 BA43 BA47 BC17 BC21 BC25 BC29 BC39 BC41 BC43 BC45 BC47
Table Listing Alphabetic Order (Continued) Signal Name
AJ39 AJ43 AJ47 AL41 AL45 AN39 AN43 AN47 AQ41 AQ45 AU41 AU45 AW39 AW43 AW47
6.2.
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Introduction Flatness
6.3.
Critical Zone Pedestal Area
Pentium processor with cache characterized flatness packaging technology. flatness defined variance from planar homogenous surface. this document, warpage flatness often used interchangeably. warpage describes depth nonflat surface. warpage measured mils, reference point highest variation along axis. example, precise file along surface back plate processor from corner other corner. There will between file back plate. processor back plate shows homogenous warpage which shown Figure (The lowest spot center highest spot corners.)
reference point center back plate, warpage increases towards sides corners. flatness specification defined ways: Critical zone flatness Overall back plate flatness critical zone defined optimal heat sink contact area given flatness associated with this product. This been based several test results optimizations. critical area defined 2.1" 1.3" rectangular area which centers area processor. heat sink pedestal shape shown Figure
package side Backplate
Area Area
Processor Side View 9mil
Area
Reference Point Warpage
3570-27
Figure Processor View with Back Plate Warpage Mapping
PENTIUM® PROCESSOR WITH CACHE
Fins Pedestal Area
Fins
2.1" 1.3"
Heatsink Pedestal part heat sink) Side View Bottom View
3570-28
Figure Pedestal Shape Bottom Side View thickness pedestal vary depending heat sink vendor. System designers need consider their system issues order optimize their thermal solution. Pedestal size specified Table optimal performance. Flatness direction Z-axis specified Table Table Flatness Specification Area (Centered) 2.1" 1.3" 2.66" x2.46" (Total package area) Maximum Warpage 0.0070" 0.012"
Table Pedestal Specification Dimensions Length Width Thickness (step) Minimum Specification inches) 0.015
Heat sink with pedestal Backplate Processor
PENTIUM® PROCESSOR WITH CACHE
Fins
Pedestal
Grease
3570-29
Figure Heat Sink with Pedestal Placement Processor Side View 6.3.1. BACKPLATE PRESSURE SPECIFICATION OEMs choose design their heat sink solutions various ways. Figure shows heat sink with pedestal attaches processor. OEMs choose pedestal type heat sink solution thermal analysis shows that case temperature stays under maximum operating temperature given Table 6.4.1. HEAT SINK
Table Dimensions Figure Dimension Table
specified pedestal area 2.1" 1.3" (which critical zone), maximum backplate pressure exceed lbs.
3.5" .25/-0.0 2.0" .25/ -0.0 3.20" maximum 3.00" maximum 1.30" maximum 0.185" .015" (clip spacing) 0.015" minimum, .050" maximum 1.475" maximum 0.950" clip attachment spacing
6.4.
Heat Sink Design Recommendations
Another option design heat sink along with pedestal thermal solution. Figure demonstrates example heat sink. dimensions possible 2-fan heat sink listed Table location fans attachment clips depend system requirements.
PENTIUM® PROCESSOR WITH CACHE
3570-30
Figure Example Heat Sink
6.5.
Strength Specification
6.6.
Coplanarity Specification
Pentium processor with cache sustain pounds force. Exceeding this limit puts part risk makes behavior unpredictable. side cover.
Coplanarity, here, defined variation along z-axis, between lower most (located middle package) highest (located corners package). Coplanarity specified exceed mils. Refer Figure details.
3570-31
Figure Coplanarity Specification
6.7.
Time (Years)
PENTIUM® PROCESSOR WITH CACHE
humidity. diamond line shows estimated failure rate over time based HAST °C/85% relative humidity monitors activation energy 0.777 square line offers worst case estimation from same monitor data using lower confidence interval 60%.
Predicted Storage Failure Rates
anticipated failure rate, based storage temperature relative humidity, shown Figure graph. This graph reflects moisture storage predictions °C/85% relative
Estimate based Monitor Data Worst Case (Monitor C.l.)
Confidence Interval
Fail
3570-32
Figure Expected Storage Failure Rates Stringent Storage Conditions
PENTIUM® PROCESSOR WITH CACHE
APPENDIX SIGNAL LISTING
This appendix provides alphabetical listing Pentium processor signals. Pins that appear here considered signals described Table
A.0. ALPHABETICAL LISTING SIGNALS A.1. A[35:3]# (I/O)
deferred reply transactions defined REQa[4:0]# 00000, Aa[23:16]# carry deferred This signal same deferred supplied request initiator original transaction Ab[23:16]#/DID[7:0]# signals. Pentium processor agents that support deferred replies sample deferred perform internal match against outstanding transactions waiting deferred replies. During deferred reply, Aa[35:24]# Aa[15:3]# reserved. branch-trace message transaction defined REQa[4:0]# 01001 special interrupt acknowledge transactions, defined REQa[4:0]# 01000, Aa[35:3]# signals reserved undefined. During second clock Request Phase, Ab[35:3]# signals perform identical signal functions transactions. ease description, these functions described using signal names. Ab[31:24]# renamed attribute signals ATTR[7:0]#. Ab[23:16]# renamed Deferred signals DID[7:0]#. Ab[15:8]# renamed eightbyte enable signals BE[7:0]#. Ab[7:3]# renamed extended function signals EXF[4:0]#. Table Request Phase Decode Ab[31:24]# Ab[23:16]# Ab[15:8]# BE[7:0]# Ab[7:3]# EXF[4:0]#
A[35:3]# signals address signals. They driven during two-clock Request Phase request initiator. signals clocks referenced Aa[35:3]# Ab[35:3]#. During both clocks, A[35:24]# signals protected with AP1# parity signal, A[23:3]# signals protected with AP0# parity signal. Aa[35:3]# signals interpreted based information carried during first Request Phase clock REQa[4:0]# signals. memory transactions defined REQa[4:0]# {XX01X,XX10X,XX11X}, Aa[35:3]# signals define 236-byte physical memory address space. cacheable agents system observe Aa[35:3]# signals begin internal snoop. memory agents system observe Aa[35:3]# signals begin address decode determine they responsible transaction completion. Aa[4:3]# signals define critical word, first data chunk transferred data bus. Cache line transactions burst order described Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), transfer remaining three data chunks. Pentium processor transactions defined REQa[4:0]# 1000X, signals Aa[16:3]# define 64K+3 byte physical space. agents system observe signals begin address decode determine they responsible transaction completion. Aa[35:17]# always zero. Aa16# zero unless space being accessed first three bytes KByte address range.
ATTR[7:0]# DID[7:0]#
active-to-inactive transition RESET#, each Pentium processor agent samples A[35:3]# signals determine power-on configuration.
A.2.
A20M#
A20M# signal address-20 mask signal Compatibility group. A20M# input signal asserted, Pentium processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap around Mbyte boundary. Only assert A20M# when processor real mode. effect asserting
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Phase only begin In-order Queue less than maximum number entries defined power-on configuration Request Phase being stalled active BNR# sequence ADS# associated with previous Request Phase sampled inactive. Along with ADS#, request initiator drives A[35:3]#, REQ[4:0]#, AP[1:0]#, signals clocks. During second Request Phase clock, ADS# must inactive. provides parity protection REQ[4:0]# ADS# signals during both clocks. transaction part locked operation, LOCK# must active with ADS#. request initiator continues after first Request Phase, issue request every three clocks. request initiator needs release ownership after Request Phase, deactivate BREQn#/BPRI# arbitration signal early with activation ADS#. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. sampling asserted ADS#, agents load transaction In-order Queue update internal counters. Error, Snoop, Response, Data Phase transaction defined with respect ADS# assertion.
A20M# protected mode undefined implemented differently future processors. Snoop requests cache-line write back transactions unaffected A20M# input. Address masked when processor samples external addresses perform internal snooping. A20M# asynchronous input. However, guarantee recognition this signal following write instruction, A20M# must valid with active RS[2:0]# signals corresponding Write transaction. mode, A20M# must synchronous BCLK. During active RESET#, Pentium processor begins sampling A20M#, IGNNE#, LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. After PLL-lock time, core clock becomes stable locked external clock. active-to-inactive transition RESET#, Pentium processor latches A20M#, IGNNE#, LINT[1:0] freezes frequency ratio internally. Table
A.3.
ADS# (I/O)
ADS# signal address Strobe signal. asserted current owner clock indicate Request Phase. Request
Table Clock Ratios Versus Logic Levels Ratio Core Clock Clock RESERVED RESERVED RESERVED RESERVED LINT[1]/NMI LINT[0]/INTR IGNNE# A20M#
OTHER COMBINATIONS
PENTIUM® PROCESSOR WITH CACHE
A.4.
AERR# (I/O)
AERR# signal address parity error signal. Assuming AERR# driver enabled during power-on configuration, agent drive AERR# active exactly clock during Error Phase transaction. AERR# must inactive minimum clocks. Error Phase always three clocks from beginning Request Phase. observing active ADS#, agents begin parity protocol checks signals valid Request Phase clocks. Parity checked AP[1:0]# signals. AP1# protects A[35:24]#, AP0# protects A[23:3]# protects REQ[4:0]#. parity error without protocol violation signaled AERR# assertion. AERR# observation enabled during power-on configuration, AERR# assertion valid Error Phase aborts transaction. agents remove transaction from In-order Queue update internal counters. Snoop Phase, Response Phase, Data Phase transaction aborted. signals these phases must deasserted clocks after AERR# asserted, even signals have been asserted before AERR# been observed. Specifically Snoop Phase associated with aborted transaction driven next clock, snoop results, including STALL condition (HIT# HITM# asserted clock), ignored. agents must also begin arbitration reset sequence deassert BREQn#/BPRI# arbitration signals sampling AERR# active. current owner middle lock operation must keep LOCK# asserted assert arbitration request BPRI#/BREQn# after keeping inactive clocks retain ownership guarantee lock atomicity. other agents, including current owner middle lock operation, must wait least clocks before asserting BPRI#/BREQn# beginning arbitration. AERR# observation enabled, request initiator retry transaction times until reaches retry limit defined implementation. (The Pentium processor retries once.) After retries, request initiator treats error hard error. request initiator asserts BERR# enters Machine Check Exception handler, defined system configuration.
AERR# observation disabled during power-on configuration, AERR# assertion ignored agents except central agent. Based Machine Check Architecture system, central agent ignore AERR#, assert execute handler, assert BINIT# reset units agents execute handler.
A.5.
AP[1:0]# (I/O)
AP[1:0]# signals address parity signals. They driven request initiator during Request Phase clocks along with ADS#, A[35:3]#, REQ[4:0]#, RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This rule allows parity high when covered signals high. Provided "AERR# drive" enabled during poweron configuration, agents begin parity checking observing active ADS# determine there parity error. observing parity error Request Phase clocks, agent asserts AERR# during Error Phase transaction.
A.6.
ASZ[1:0]# (I/O)
ASZ[1:0]# signals memory addressspace size signals. They driven request initiator during first Request Phase clock REQa[4:3]# pins. ASZ[1:0]# signals valid only when REQa[1:0]# signals equal 01B, 10B, 11B, indicating memory access transaction. ASZ[1:0]# decode defined Table Table ASZ[1:0]# Signal Decode ASZ[1:0]# Description A[35:3]# A[35:3]# Reserved
memory access within 0-to-(4GByte-1) address space, ASZ[1:0]# must 00B. memory access within 4Gbyte-to-(64 GByte-1) address space, ASZ[1:0]# must 01B.
ATTR[7:3]# XXXXX Reserved
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Table ATTR[7:0]# Field Descriptions ATTR[2]# Potentially Speculatable Write-Back Write-Protect ATTR[1:0]# Write-Through UnCacheable
observing agents that support 4Gbyte bit) address space must respond transaction only when ASZ[1:0]# equals observing agents that support 64GByte (36-bit) address space must respond transaction when ASZ[1:0]# equals 01B.
memory transactions (REQa[4:0]# {10000B, 10001B, XX01XB, XX10XB, XX11XB}) byte-enable signals indicate that valid data requested being transferred corresponding byte data bus. BE0# indicates D[7:0]# valid, BE1# indicates D[15:8]# valid,., BE7# indicates D[63:56]# valid. Special transactions ((REQa[4:0]# 01000B) (REQb[1:0]# 01B)), BE[7:0]# signals carry special cycle encodings defined Table other encodings reserved. Table Special Transaction Encoding BE[7:0]# BE[7:0]# 0000 0000 Special Cycle Reserved Shutdown Flush Halt Sync Flush Acknowledge Stop Clock Acknowledge Acknowledge Reserved
A.7.
ATTR[7:0]# (I/O)
ATTR[7:0]# signals attribute signals. They driven request initiator during second Request Phase clock Ab[31:24]# pins. ATTR[7:0]# signals valid transactions. ATTR[7:3]# reserved undefined. ATTR[2:0]# driven based Memory Range Register attributes Page Table attributes. Table defines ATTR[3:0]# signals.
A.8.
BCLK
0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 00000 0110 00000 0111 Other
BCLK (clock) signal Execution Control group input signal. determines frequency. agents drive their outputs latch their inputs BCLK rising edge. BCLK signal indirectly determines Pentium processor's internal clock frequency. Each Pentium processor derives internal clock from BCLK multiplying BCLK frequency ratio defined allowed power-on configuration. Table external timing parameters specified with respect BCLK signal.
Deferred Reply, Interrupt Acknowledge, Branch Trace Message transactions, BE[7:0]# signals undefined.
A.9.
BE[7:0]# (I/O) A.10. BERR# (I/O)
BERR# signal Error group Error signal. asserted indicate unrecoverable error without protocol violation.
BE[7:0]# signals byte-enable signals. They driven request initiator during second Request Phase clock Ab[15:8]# pins. These signals carry various information depending REQ[4:0]# value.
PENTIUM® PROCESSOR WITH CACHE
BERR# protocol follows: agent detects unrecoverable error which BERR# valid error response BERR# sampled inactive, asserts BERR# three clocks. agent assert BERR# only after observing that signal inactive. agent asserting BERR# must deassert signal clocks observes that another agent began asserting BERR# previous clock. BERR# assertion conditions defined system configuration. Configuration options enable BERR# driver follows: Enabled disabled Asserted optionally internal errors along with IERR# Optionally asserted request initiator transaction after observes error Asserted agent when observes error transaction
BINIT# observation disabled during power-on configuration, BINIT# ignored agents except central agent that must handle error manner appropriate system architecture.
A.12. BNR# (I/O)
BNR# signal Block Next Request signal Arbitration group. BNR# signal used assert stall agent unable accept transactions avoid internal transaction queue overflow. During stall, current owner cannot issue transactions. Since multiple agents might need request stall same time, BNR# wire-OR signal. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, BNR# activated specific clock edges sampled specific clock edges. valid stall involves assertion BNR# clock well-defined clock edge (T1), followed deassertion BNR# clock next clock edge (T1+1). BNR# first sampled second clock edge (T1+1) must always ignored third clock edge (T1+2). extension stall requires clock active (T1+2), clock inactive (T1+3) BNR# sequence with BNR# sampling points every clocks (T1+1, T1+3,.). After RESET# active-to-inactive transition, agents might need perform hardware initialization their unit logic. agents intending create request stall must assert BNR# clock after RESET# sampled inactive. After BINIT# assertion, agents through similar hardware initialization create request stall asserting BNR# four clocks after BINIT# assertion sampled. first BNR# sampling clock that BNR# sampled inactive, current owner allowed issue request. agent immediately reassert BNR# (four clocks from previous assertion clocks from previous de-assertion) create stall. This throttling mechanism enables independent control every request generation.
BERR# sampling conditions also defined system configuration. Configuration options enable BERR# receiver enabled disabled. When central agent samples active BERR# signal, forward BERR# BINIT# processors. Pentium processor does support BERR# sampling (always disabled).
A.11. BINIT# (I/O)
BINIT# signal initialization signal. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# protocol follows: agent detects error which BINIT# valid error response, BINIT# sampled inactive, asserts BINIT# three clocks. agent assert BINIT# only after observing that signal inactive. agent asserting BINIT# must deassert signal clocks observes that another agent began asserting BINIT# previous clock. BINIT# observation enabled during power-on configuration, BINIT# sampled asserted, state machines reset. agents reset their rotating arbitration state after reset, internal count information lost. caches affected.
Signal BREQ0# BREQ1# BREQ2# BREQ3#
PENTIUM® PROCESSOR WITH CACHE
Table BR[3:0]# Signals Rotating Interconnect Agent Pins BR0# BR1# BR2# BR3# Agent Pins BR3# BR0# BR1# BR2# Agent Pins BR2# BR3# BR0# BR1# Agent Pins BR1# BR2# BR3# BR0#
BNR# deasserted consecutive sampling points, requests freely generated bus. After receiving transaction, agent require address stall anticipated transaction-queue overflow condition. response, agent assert BNR#, three clocks from active ADS# assertion create stall. Once stall created, remains stalled until BNR# sampled asserted subsequent sampling points.
A.13. BP[3:2]# (I/O)
BP[3:2]# signals System Support group Breakpoint signals. They outputs from Pentium processor that indicate status breakpoints.
priority agent further reduce arbitration latency clocks samples active ADS# inactive LOCK# clock which BPRI# driven active three clocks samples active ADS# inactive LOCK# clock which BPRI# sampled active. LOCK# sampled active, priority agent must wait LOCK# deasserted gains ownership clocks after LOCK# sampled deasserted. priority agent keep BPRI# asserted until requests completed release de-asserting BPRI# early same clock edge which issues last request. observation active AERR#, RESET#, BINIT#, BPRI# must deasserted next clock. BPRI# reasserted clock after sampling RESET# active-to-inactive transition three clocks after sampling BINIT# active RESET# inactive. AERR# assertion, priority agent middle bus-locked operation, BPRI# must re-asserted after clocks, otherwise BPRI# must stay inactive least clocks. After RESET# inactive transition, Pentium processor agents begin BPRI# BNR# sampling BNR# sample points. When both BNR# BPRI# observed inactive BNR# sampling point, APIC units Pentium processors common APIC synchronized.
A.14. BPM[1:0]# (I/O)
BPM[1:0]# signals more System Support group breakpoint performance monitor signals. They outputs from Pentium processor that indicate status breakpoints programmable counters used monitoring Pentium processor performance.
A.15. BPRI#
BPRI# signal Priority-agent Request signal. priority agent arbitrates asserting BPRI#. priority agent always next owner. Observing BPRI# active causes current symmetric owner stop issuing requests, unless such requests part ongoing locked operation. LOCK# sampled inactive clocks from BPRI# driven asserted, priority agent issue request within four clocks asserting BPRI#.
A.16. BR0#(I/O), BR[3:1]#
BR[3:0]# pins physical request pins that drive BREQ[3:0]# signals system. BREQ[3:0]# signals interconnected rotating manner individual processor pins. Table gives rotating interconnect between processor signals. During power-up configuration, central agent must assert BR0# signal. symmetric
PENTIUM® PROCESSOR WITH CACHE
agents sample their BR[3:0]# pins active-toinactive transition RESET#. which agent samples active level determines agent agents then configure their pins match appropriate signal protocol, shown Table Table BR[3:0]# Signal Agent Sampled Active RESET# BR0# BR3# BR2# BR1# Agent
bus. symmetric owner stops issuing requests that part existing locked operation upon observing BPRI# active. symmetric agent deassert BREQn# until becomes symmetric owner. symmetric agent reassert BREQn# after keeping inactive clock. observation active AERR#, RESET#, BINIT#, BREQ[3:0]# signals must deasserted next clock. BREQ[3:0]# reasserted clock after sampling RESET# active-toinactive transition three clocks after sampling BINIT# active RESET# inactive. AERR# assertion, agent middle buslocked operation, BREQn# must re-asserted after clocks, otherwise BREQ[3:0]# must stay inactive least clocks.
A.17. BREQ[3:0]# (I/O)
BREQ[3:0]# signals Symmetric-agent Arbitration signals (called request). symmetric agent arbitrates asserting BREQn# signal. Agent drives BREQn# output receives remaining BREQ[3:0]# signals inputs. symmetric agents support distributed arbitration based round-robin mechanism. rotating internal state used symmetric agents track agent with lowest priority next arbitration event. power-on, rotating initialized three, allowing agent highest priority symmetric agent. After arbitration event, rotating symmetric agents updated agent symmetric owner. This update gives symmetric owner lowest priority next arbitration event. arbitration event occurs either when symmetric agent asserts BREQn# Idle (all BREQ[3:0]# previously inactive), current symmetric owner de-asserts BREQm# release ownership owner arbitration event, based BREQ[3:0]#, rotating symmetric agents simultaneously determine symmetric owner. symmetric owner park (hold bus) provided that other symmetric agent requesting use. symmetric owner parks keeping BREQn# signal active. sampling active BREQm# asserted another symmetric agent, symmetric owner de-asserts BREQn# soon possible release
A.18. D[63:0]# (I/O)
D[63:0]# signals data signals. They driven during Data Phase agent responsible driving data. These signals provide 64-bit data path between various Pentium processor agents. 32-byte line transfers require four data transfer clocks with valid data eight bytes. Partial transfers require data transfer clock with valid data byte(s) indicated active byte enables BE[7:0]#. Data signals valid particular transfer must still have correct data selected). BE0# asserted, D[7:0]# transfers least significant byte. BE7# asserted, D[63:56]# transfers most significant byte. data driver asserts DRDY# indicate valid data transfer. Data Phase involves more than clock data driver also asserts DBSY# beginning Data Phase de-asserts DBSY# earlier than same clock that performs last data transfer.
A.19. DBSY# (I/O)
DBSY# signal Data-bus Busy signal. indicates that data busy. asserted agent responsible driving data during Data Phase, provided Data Phase involves more than clock. DBSY# asserted beginning Data Phase deasserted after clock which last data driven. data
PENTIUM® PROCESSOR WITH CACHE
clock after DBSY# response, requesting agent must retry transaction. defer agent returns deferred response, requesting agent must freeze snoop state transitions associated with deferred transaction issues order-dependent transactions until corresponding deferred reply transaction. meantime, ownership deferred address transferred defer agent must guarantee management conflicting transactions issued same address. DEFER# active response newly issued bus-lock transaction, entire bus-locked operation re-initiated regardless HITM#. This feature useful bridge agent response split buslocked operation. recommended that bridge agent extend Snoop Phase first transaction split locked operation until either guarantee ownership system resources enable successful completion split sequence assert DEFER# followed Retry Response abort split sequence.
released deasserted.
When normal read data being returned, Data Phase begins with Response Phase. Thus agent returning read data assert DBSY# when transaction reaches In-order Queue ready return response RS[2:0]# signals. response write request, agent driving write data must drive DBSY# active after write transaction reaches In-order Queue sees active TRDY# with inactive DBSY# indicating that target ready receive data. implicit write back response, snoop agent must assert DBSY# active after target memory agent implicit write back asserts TRDY#. Implicit write back TRDY# assertion begins after transaction reaches In-order Queue, TRDY# de-assertion associated with write portion transaction, completed. this case, memory agent guarantees assertion implicit write back response same clock which snooping agent asserts DBSY#.
A.20. DEFER#
DEFER# signal defer signal. asserted agent during Snoop Phase indicate that transaction cannot guaranteed in-order completion. Assertion DEFER# normally responsibility addressed memory agent agent. systems that involve resources system other than Pentium processor bus, bridge agent accept DEFER# assertion responsibility behalf addressed agent. When HITM# DEFER# both active during Snoop Phase, HITM# given priority transaction must completed with implicit write back response. HITM# inactive, DEFER# active, agent asserting DEFER# must complete transaction with Deferred Retry response. DEFER# inactive, HITM# active, then transaction committed in-order completion snoop ownership transferred normally between requesting agent, snooping agents, response agent. DEFER# active with HITM# inactive, transaction commitment deferred. defer agent completes transaction with retry
A.21. DEN# (I/0)
DEN# signal defer-enable signal. driven second clock Request Phase EXF1#/Ab4# pin. DEN# asserted indicate that transaction deferred responding agent.
A.22. DEP[7:0]# (I/O)
DEP[7:0]# signals data protection signals. They driven during Data Phase agent responsible driving D[63:0]#. DEP[7:0]# signals provide optional protection data bus. During power-on configuration, DEP[7:0]# signals enabled either checking checking. error correcting code detect correct single-bit errors detect double-bit nibble errors. Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), provides more information about ECC. DEP[7:0]# provide valid entire data each data clock, regardless which bytes valid. checking enabled, receiving agents check signals data signals.
PENTIUM® PROCESSOR WITH CACHE
A.23. DID[7:0]# (I/O)
DID[7:0]# signals Deferred Identifier signals. They transferred using A[23:16]# signals request initiator. They transferred Ab[23:16]# during second clock Request Phase transactions, only defined deferrable transactions (DEN# asserted). DID[7:0]# also transferred Aa[23:16]# during first clock Request Phase Deferred Reply transactions. deferred identifier defines token supplied request initiator. DID[7:4]# carry request initiators' agent identifier DID[3:0]# carry transaction identifier associated with request. This configuration limits specification masters with each masters capable making requests. Every deferrable transaction issued Pentium processor which been guaranteed completion (has successfully passed Snoop Result Phase) will have unique Deferred This includes outstanding transactions which have their snoop result reported, have their snoop results deferred. After deferrable transaction passes Snoop Result Phase without DEFER# asserted, Deferred reused. Similarly, deferred transaction which deferred reused after completion snoop window deferred reply. DID[7]# indicates agent type. Symmetric agents Priority agents DID[6:4]# indicates agent Symmetric agents their arbitration Pentium processor four symmetric agents, does assert DID[6]#. DID[3:0]# indicates transaction agent. transaction must unique transactions issued agent which have reported their snoop results. Table DID[7:0]# Encoding DID[7] Agent Type DID[6:4] Agent DID[3:0] Transaction
Deferred Reply agent transmits DID[7:0]# (Ab[23:16]#) signals received during original transaction Aa[23:16]# signals during Deferred Reply transaction. This process enables original request initiator make identifier match wake original request waiting completion.
A.24. DRDY# (I/O)
DRDY# signal Data Phase data-ready signal. data driver asserts DRDY# each data transfer, indicating valid data data bus. multicycle data transfer, DRDY# deasserted insert idle clocks Data Phase. During line transfer, DRDY# active four clocks. During partial 1-to-8 byte transfer, DRDY# active clock. data transfer exactly clock, then entire Data Phase consist only clock active DRDY# inactive DBSY#. DBSY# asserted 1-to-8 byte transfer, then data released until clock after DBSY# deasserted.
A.25. DSZ[1:0]# (I/O)
DSZ[1:0]# signals data-size signals. They transferred REQb[4:3]# signals second clock Request Phase requesting agent. DSZ[1:0]# signals define data transfer capability requesting agent. Pentium processor, DSZ#= always.
A.26. EXF[4:0]# (I/O)
EXF[4:0]# signals Extended Function signals transferred Ab[7:3]# signals request initiator during second clock Request Phase. signals specify special functional requirement associated with transaction based requester mode capability. signals defined Table
EXF4# EXF3# EXF2# EXF1# EXF0# NAME SMMEM# SPLCK# Reserved DEN# Reserved
PENTIUM® PROCESSOR WITH CACHE
Table EXF[4:0]# Signal Definitions External Functionality Mode Split Lock Reserved Defer Enable Reserved single "logical" processor, then checker processor asserts FRCERR detects mismatch between internally sampled outputs master processor's outputs. checker's FRCERR output connected master's FRCERR input pin. point-to-point connections, checker always compares against master's outputs. bussed single-driver signals, checker compares against signal when master only allowed driver. bussed multiple-driver Wire-OR signals, checker compares against signal only master expected drive signal low. FRCERR also toggled during Pentium processor's reset action. Pentium processor asserts FRCERR approximately second after RESET's active-to-inactive transition executes built-in self-test (BIST). When BIST execution completes, Pentium processor de-asserts FRCERR BIST completed successfully continues assert FRCERR BIST fails. Pentium processor does execute BIST action, then keeps FRCERR asserted approximately clocks then de-asserts transactions which Defer Retry Response acceptable. When Activated After entering mode first transaction split lock operation
A.27. FERR#
FERR# signal Compatibility group Floating-point Error signal. Pentium processor asserts FERR# when detects unmasked floating-point error. FERR# included compatibility with systems using DOS-type floatingpoint error reporting.
A.28. FLUSH#
When FLUSH# input signal asserted, Pentium processor agent writes back internal cache lines Modified state invalidates internal cache lines. completion flush operation, Pentium processor issues Flush Acknowledge transaction indicate that cache flush operation complete. Pentium processor stops caching data while FLUSH# signal remains asserted. FLUSH# asynchronous input. However, guarantee recognition this signal following write instruction, FLUSH# must valid along with RS[2:0]# Response Phase corresponding Write transaction. mode, FLUSH# must synchronous BCLK. active-to-inactive transition RESET#, each Pentium processor agent samples FLUSH# determine power-on configuration. Table
Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), describes Pentium processor configured master checker.
A.30. HIT# (I/O), HITM# (I/O)
HIT# HITM# signals Snoop-hit Hitmodified signals. They snoop results asserted Pentium processor agent Snoop Phase.
A.29. FRCERR (I/O)
FRCERR signal Error group Functionalredundancy-check Error signal. Pentium processors configured pair,
PENTIUM® PROCESSOR WITH CACHE
agent assert both HIT# HITM# together clock Snoop Phase indicate that requires snoop stall. When stall condition sampled, agents extend Snoop Phase clocks. stall continued reasserting HIT# HITM# together every other clock clock. caching agent must assert HITM# clock Snoop Phase transaction hits Modified line, snooping agent must perform implicit write back update main memory. snooping agent with Modified line makes transition Shared state original transaction Read Line Read Partial, otherwise transitions Invalid state. Deferred Reply transaction have HITM# asserted indicate return unexpected data. snooping agent must assert HIT# clock during Snoop Phase line does Modified line write back cache transaction plans keep line Shared state. Multiple caching agents assert HIT# same Snoop Phase. requesting agent observes HIT# active during Snoop Phase cache line Exclusive Modified state. observing snoop stall, agents asserting HIT# HITM# independently reassert signal after inactive clock that correct snoop result available, case Snoop Phase terminates after clock extension.
A.32. IGNNE#
IGNNE# signal Intel Architecture Compatibility group Ignore Numeric Error signal. IGNNE# asserted, Pentium processor ignores numeric error continues execute noncontrol floating-point instructions. IGNNE# deasserted, Pentium processor freezes noncontrol floating-point instruction previous instruction caused error. IGNNE# effect when control register set. IGNNE# asynchronous input. However, guarantee recognition this signal following write instruction, IGNNE# must valid along with RS[2:0]# Response Phase corresponding Write transaction. mode, IGNNE# must synchronous BCLK. During active RESET#, Pentium processor begins sampling A20M#, IGNNE# LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. Table After PLLlock time, core clock becomes stable locked external clock. active-toinactive transition RESET#, Pentium processor latches A20M# IGNNE# freezes frequency ratio internally. Normal operation signals continues clocks after RESET# inactive sampled.
A.31. IERR#
IERR# signal Error group Internal Error Signal. Pentium processor asserts IERR# when observes internal error. keeps IERR# asserted until turned part Machine Check Error handler, with RESET# BINIT# assertion. handler software indirectly accomplish deassertion IERR# RESET# BINIT# assertion.An internal error handled several ways inside processor based power-on configuration. Machine Check Exception (MCE) enabled, IERR# causes entry. IERR# also directed BERR# indicate error. Usually BERR# sampled back processors enter redirected central agent.
A.33. INIT#
INIT# signal Execution Control group initialization signal. Active INIT# input resets integer registers inside Pentium processors without affecting their internal caches their floating-point registers. Each Pentium processor begins execution power-on reset vector configured during power-on configuration regardless whether INIT# gone inactive. processor continues handle snoop requests during INIT# assertion. INIT# used help performance MS-DOS* extenders written Intel 80286 processor. INIT# provides method switch from protected mode real mode while maintaining contents internal caches floating-point state. INIT# used lieu RESET# after power-up.
PENTIUM® PROCESSOR WITH CACHE
active-to-inactive transition RESET#, each Pentium processor agent samples INIT# signals determine power-on configuration. clocks after RESET# sampled deasserted, these signals begin normal operation. INIT# asynchronous input. mode, INIT# must synchronous BCLK.
Table LEN[1:0]# Data Transfer Lengths LEN[1:0]# Request Initiator's Data Transfer Length Bytes Bytes Bytes Reserved
A.34. INTR
INTR signal Interrupt Request signal. INTR input indicates that external interrupt been generated. interrupt maskable using EFLAGS register. set, Pentium processor vectors interrupt handler after current instruction execution completed. Upon recognizing interrupt request, Pentium processor issues single Interrupt Acknowledge (INTA) transaction. INTR must remain active until INTA transaction guarantee recognition. INTR sampled every rising BCLK edge. INTR asynchronous input recognition INTR guaranteed specific clock asserted synchronously meets setup hold times. INTR must also deasserted minimum clocks guarantee inactive recognition. mode, INTR must synchronous BCLK. power-up LINT[1:0] signals used poweron-configuration clock ratios. Both these signals must software configured programming APIC register space used either NMI/INTR LINT[1:0] BIOS. Because APIC enabled after reset, LINT[1:0] default configuration.
A.36. LINT[1:0]
LINT[1:0] signals Execution Control group Local Interrupt signals. When APIC disabled, LINT0 signal becomes INTR, maskable interrupt request signal, LINT1 becomes NMI, nonmaskable interrupt. INTR backward compatible with same signals Pentium processor. Both signals asynchronous inputs. mode, LINT[1:0] must synchronous BCLK. During active RESET#, Pentium processor continuously samples A20M#, IGNNE# LINT[1:0] values determine ratio core-clock frequency bus-clock frequency. Table After PLL-lock time, core clock becomes stable locked external clock. active-to-inactive transition RESET#, Pentium processor latches ratio internally. Both these signals must software configured programming APIC register space used either NMI/INTR LINT[1:0] BIOS. Because APIC enabled after reset, LINT[1:0] default configuration.
A.35. LEN[1:0]# (I/O)
LEN[1:0]# signals data-length signals. They transmitted using REQb[1:0]# signals request initiator second clock Request Phase. LEN[1:0]# define length data transfer requested request initiator defined Table LEN[1:0]#, HITM#, RS[2:0]# signals together define length actual data transfer.
A.37. LOCK# (I/O)
LOCK# signal Arbitration group lock signal. locked sequence transactions, LOCK# asserted from first transaction's Request Phase through last transaction's Response Phase. locked operation prematurely aborted (and LOCK# deasserted) AERR# DEFER# asserted during first transaction sequence. sequence also prematurely aborted hard error (such hard failure response AERR# assertion beyond retry limit) occurs transactions during locked operation.
PENTIUM® PROCESSOR WITH CACHE
When priority agent asserts BPRI# arbitrate ownership, waits until observes LOCK# deasserted. This enables symmetric agents retain ownership throughout locked operation guarantee atomicity lock. AERR# asserted retry limit during ongoing locked operation, arbitration protocol ensures that lock owner receives ownership after arbitration logic reset. This result accomplished requiring lock owner reactivate arbitration request clock ahead other agents' arbitration request. LOCK# kept asserted throughout arbitration reset sequence.
processor synchronous operation APIC bus. PICCLK must synchronous BCLK mode.
A.40. PICD[1:0] (I/O)
PICD[1:0] signals Execution Control group APIC Data signals. They used bidirectional serial message passing APIC bus.
A.41. PWRGOOD
PWRGOOD driven Pentium processor system indicate that clocks power supplies within their specification. Section 2.9. additional details. This signal will affect operation.
A.38.
signal Nonmaskable Interrupt signal. state LINT1 signal when APIC disabled. Asserting causes interrupt with internally supplied vector value external interrupt-acknowledge transaction generated. asserted during execution service routine, remains pending recognized after IRET executed service routine. most, assertion held pending. rising-edge sensitive. Recognition guaranteed specific clock asserted synchronously meets setup hold times. asserted asynchronously, active inactive pulse widths must minimum clocks. mode, must synchronous BCLK.
A.42. REQ[4:0]# (I/O)
REQ[4:0]# signals Request Command signals. They asserted current owner both clocks Request Phase. first clock, REQa[4:0]# signals define transaction type level detail that sufficient begin snoop request. second clock, REQb[4:0]# signals carry additional information define complete transaction type. REQb[4:2]# reserved. REQb[1:0]# signals transmit LEN[1:0]# (the data transfer length information). both clocks, REQ[4:0]# ADS# protected parity RP#. receiving agents observe REQ[4:0]# signals determine transaction type participate transaction necessary, shown Table
A.39. PICCLK
PICCLK signal Execution Control group APIC Clock signal. input clock Pentium
Deferred Reply Rsvd (Ignore) Interrupt Acknowledge Special Transactions Rsvd (Central agent response) Branch Trace Message Rsvd (Central agent response) Rsvd (Central agent response) Read Write Rsvd (Ignore) Memory Read Invalidate Rsvd (Memory Write) Memory Code Read Memory Data Read Memory Write (may retried) Memory Write (may retried)
PENTIUM® PROCESSOR WITH CACHE
Table Transaction Types Defined REQa#/REQb# Signals REQa[4:0]# REQb[4:0]# Transaction ASZ# ASZ# ASZ# ASZ# ASZ# ASZ# D/C#=0 D/C#=1 W/WB#=0 W/WB#=1 LEN# LEN# LEN# LEN# LEN# LEN# LEN# LEN#
DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ# DSZ#
A.43. RESET#
RESET# signal Execution Control group reset signal. Asserting RESET# resets Pentium processors known states invalidates their caches without writing back Modified state) lines. power-on type reset, RESET# must stay active least millisecond after VCCP have reached their proper specifications. observing active RESET#, agents must deassert their outputs within clocks. number signals sampled activeto-inactive transition RESET# power-on configuration. configuration options described Pentium® Processor Family Developer's Manual, Volume Specifications (Order Number 242690), pertinent signal descriptions this appendix.
Unless outputs tristated during power-on configuration, after active-to-inactive transition RESET#, Pentium processor optionally executes built-in self-test (BIST) begins program execution reset-vector 0_000F_FFF0H 0_FFFF_FFF0H.
A.44. (I/O)
signal Request Parity signal. driven request initiator both clocks Request Phase. provides parity protection ADS# REQ[4:0]#. When Pentium processor agent observes parity error Request Phase clocks, must assert AERR# Error Phase, provided "AERR# drive" enabled during power-on configuration.
PENTIUM® PROCESSOR WITH CACHE
correct parity signal high even number covered signals number covered signals low. This definition allows parity high when covered signals high.
response agent returns Normal with data response read transaction with HITM# DEFER# deasserted Snoop Phase, when addressed agent ready return data samples inactive DBSY#. response agent returns Normal without data response write transaction with HITM# DEFER# deasserted Snoop Phase, when addressed agent samples TRDY# active DBSY# inactive, ready complete transaction. response agent must return Implicit write back response next clock read transaction with HITM# asserted Snoop Phase, when addressed agent samples TRDY# active DBSY# inactive. addressed agent must return Implicit write back response clock after following sequence sampled write transaction with HITM# asserted: TRDY# active DBSY# inactive Followed TRDY# inactive Followed TRDY# active DBSY# inactive
A.45. RS[2:0]#
RS[2:0]# signals Response Status signals. They driven response agent (the agent responsible completion transaction In-order Queue). Assertion RS[2:0]# nonzero value clock completes Response Phase transaction. response encodings shown Table Only certain response combinations valid, based snoop result signaled during transaction's Snoop Phase. RS[2:0]# assertion transaction initiated when following conditions met: agents have observed Snoop Phase completion transaction. transaction In-order Queue. RS[2:0]# sampled Idle state
response driven depends transaction described below: response agent returns hard-failure response transaction which response agent observes hard error.
defer agent return Deferred, Retry, Split response anytime read transaction with HITM# deasserted DEFER# asserted. defer agent return Deferred, Retry, Split response when samples TRDY# active DBSY# inactive write transaction with HITM# deasserted DEFER# asserted.
RS[2:0] Idle State Reserved Normal with data
PENTIUM® PROCESSOR WITH CACHE
Table Transaction Response Encodings Description HITM# DEFER#
Retry Response. transaction canceled must retried initiator. Defer Response. transaction suspended. defer agent will complete with defer reply
Hard Failure. transaction received hard error. Exception handling required. Normal without data Implicit Write Back Response. Snooping agent will transfer modified cache line data bus.
A.46. RSP#
RSP# signal Response Parity signal. driven response agent during assertion RS[2:0]#. RSP# provides parity protection RS[2:0]#. correct parity signal high even number covered signals number covered signals low. During Idle state RS[2:0]# (RS[2:0]#=000), RSP# also high since driven agent guaranteeing correct parity. Pentium processor agents check RSP# times parity error observed, treat protocol violation error. BINIT# driver enabled during configuration, agent observing RSP# parity error assert BINIT#.
Request Phase EXF4#/Ab7# signal. asserted Pentium processor indicate that processor System Management Mode executing SMRAM space.
A.49. SPLCK# (I/O)
SPLCK# signal Split Lock signal. driven second clock Request Phase EXF3#/Ab6# signal first transaction locked operation. driven indicate that locked operation will consist four locked transactions. Note that SPLCK# asserted only locked operations only first transaction locked operation.
A.50. STPCLK#
STPCLK# signal Stop Clock signal. When asserted, Pentium processor enters lowpower state, stop-clock state. processor issues Stop Clock Acknowledge special transaction, stops providing internal clock signals units except unit APIC unit. processor continues snoop transactions service interrupts while stop clock state. When STPCLK# deasserted, processor restarts internal clock units resumes execution. assertion STPCLK# effect clock. STPCLK# asynchronous input. mode, STPCLK# must synchronous BCLK.
A.47. SMI#
System Management Interrupt asserted asynchronously system logic. accepting System Management Interrupt, Pentium processor saves current state enters mode. issues Acknowledge transaction then begins program execution from handler.
A.48. SMMEM# (I/O)
SMMEM# signal System Management Mode Memory signal. driven second clock
PENTIUM® PROCESSOR WITH CACHE
A.51.
signal System Support group Test Clock signal. provides clock input test (also known test access port). Make certain that active before initializing TAP.
transaction reaches top-of-the-In-order Queue. minimum clock after RS[2:0]# active assertion transaction "n-1" (after transaction reaches In-order Queue).
A.52. TDI(I)
signal System Support group testdata-in signal. transfers serial test data into Pentium processor. provides serial input needed JTAG support.
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