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Pentium® Processor With On-die Cache Mobile Module Connector (MMC-1)
Core frequencies MHz, MHz, MHz, MHz, 256K on-die
level cache
Processor core voltage regulation supports input voltages from Above percent peak efficiency Thermal transfer plate Intel® 82433DX provides heat dissipation Intel® 82443DX Host Bridge system controller DRAM controller supports SDRAM 3.3V Supports CLKRUN# protocol SDRAM clock support self refresh SDRAM during Suspend mode 3.3V only control, compliant
66-MHz processor system speed Integrated Active Thermal Feedback (ATF) system ACPI Rev. compliant Internal A/D-digital signaling (SMBus) across module interface Programmable trip point interrupt poll mode temperature reading
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel. INTEL CORPORATION 1999, 2000 February 2000 Order Number: 245109-003
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel' Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life-saving, life-sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked reserved" undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium processor with on-die cache mobile modules contain design defects errors known errata. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature, obtained calling 1-800548-4725 visiting Intel' site http://www.intel.com Copyright Intel Corporation1999, 2000. *Third-party brands names property their respective owners.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
CONTENTS
3.1.1 3.1.2 3.1.3. 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 4.3.1 4.3.2 4.3.3 4.3.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 INTRODUCTION Revision History ARCHITECTURE OVERVIEW.5 MODULE CONNECTOR INTERFACE Signal Definition Signal List Memory (108 Signals).9 Signals) Processor PIIX4E/M Sideband Signals) Power Management Signals) Clock Signals) Voltages Signals).14 JTAG Signals).14 Miscellaneous Signals).15 Connector Assignments Assignments.18 FUNCTIONAL DESCRIPTION Pentium Processor With On-Die Cache Mobile Module MMC-1.19 Cache 82443DX Host Bridge System Controller Memory Organization.19 Reset Strap Options.20 Interface.20 Feature Set.20 Power Management.20 Clock Control Architecture Normal State.22 Auto Halt State Stop Grant State.22 Quick Start State HALT/Grant Snoop State Sleep State Deep Sleep State 4.7.3 4.6.1 Typical POS/STR Power. Electrical Requirements Requirements Requirements BCLK Signal Quality Specifications Measurement Guidelines Voltage Regulator Voltage Regulator Efficiency
4.6.2 4.6.2.1 4.7.1
4.7.2. 4.7.2.1
Control Voltage Regulator. Voltage Signal Definition Sequencing Power Planes: Bulk Capacitance Requirements
Surge Current Guidelines. Slew-rate Control: Circuit Description. Undervoltage Lockout: Circuit Description (V_uv_lockout) 4.7.4.3 Overvoltage Lockout: Circuit Description (V_ov_lockout). 4.7.4.4 Overcurrent Protection: Circuit Description Active Thermal Feedback Thermal Sensor Configuration Register MECHANICAL SPECIFICATION. Module Dimensions. 5.1.1 MMC-1 Connector Location. 5.1.2 5.1.3 5.3.1 5.3.2 Printed Circuit Board Thickness. Height Restrictions Thermal Transfer Plate. Physical Support. Mounting Requirements Module Weight. THERMAL SPECIFICATION Thermal Design Power. Thermal Sensor Setpoint LABELING INFORMATION ENVIRONMENTAL STANDARDS.
4.7.4 4.7.4.1 4.7.4.2
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
FIGURES
Figure Block Diagram Pentium Processor With On-die Cache Mobile Module MMC-1.6 Figure 280-Pin Connector Footprint Numbers, Module Secondary Side Figure Clock Control States Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Figure Power-on Sequence Timing Figure Instantaneous In-rush Current Model.30 Figure Instantaneous In-rush Current.31 Figure Over Current Protection Circuit Figure Spice Simulation Using In-rush Protection (Example Only) Figure Board Dimensions.35 Figure Board Dimensions- Orientation.36 Figure Printed Circuit Board Thickness Figure Keep-out Zone Figure Thermal Transfer Plate Figure Thermal Transfer Plate Figure Standoff Holes, Board Edge Clearance, Containment Ring.40 Figure Product Tracking Code
TABLES
Table Module Connector Signal Summary Table Memory Signal Descriptions Table Signal Description Table Processor/PIIX4E/M Sideband Signal Descriptions. Table Power Management Signal Descriptions. Table Clock Signal Descriptions Table Voltage Descriptions Table JTAG Pins. Table Miscellaneous Pins. Table Connector Assignments. Table Connector Specifications Table Configuration Straps 82443DX Host Bridge System Controller. Table Clock State Characteristics. Table POS/STR Power. Table Power Supply Design Specifications Table Specifications (BCLK) Processor Core Pins. Table BCLK Signal Quality Specifications Processor Core. Table Typical Voltage Regulator Efficiency Table Voltage Signal Definitions Sequences Table VR_ON In-rush Current. Table Capacitance Requirements Power Plane Table Thermal Sensor SMBus Address Table Table Thermal Sensor Configuration Register Table Thermal Design Power Specifications. Table Environmental Standards.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
INTRODUCTION PIIX4E/M PCI/ISA Bridge large-scale integrated devices Intel 440DX PCIset. notebook' system electronics must include PIIX4E/M device connect Pentium processor with on-die cache mobile module. PIIX4E/M provides extensive power management capabilities supports second integrated device, Intel® 82443DX Host Bridge. features Intel 82443DX Host Bridge system controller include DRAM controller, which supports volts with burst read 7-2-2-2 nanoseconds) SDRAM volts with burst read 8-1-1-1 megahertz, CL=2). 82443DX Host Bridge also regulates clock bus. 82443DX clock enables Self Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management. E_SMRAM mode supports write-back cacheable SMRAM megabyte. thermal transfer plate (TTP) 82443DX Host Bridge provides heat dissipation thermal attach point notebook manufacturer' thermal solution. on-board voltage regulator converts system voltage processor' core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single notebook system. Supporting input voltages from volts volts, processor core voltage regulator enables above percent peak efficiency decouples processor voltage requirements from system. Pentium processor with on-die cache mobile module MMC-1 also incorporates Active Thermal Feedback (ATF) sensing, compliant ACPI Specification 1.0. system management (SMBus) supports internal external temperature sensing with programmable trip points.
This document provides technical information integrating Pentium® Processor Mobile Module Connector (MMC-1) into latest notebook systems today' notebook market. Building around this modular design gives system manufacturer these advantages: Avoids complexities associated with designing highspeed processor core logic boards. Provides upgrade path from previous Intel® Mobile Modules using standard interface.
Date 1999 1999
Revision History Revision Updates Initial release Updates include: Addition 400-MHz processor speed POS/STR measurement corrections specification clarification VR_ON VR_PWRGD specification correction cache specification correction Power sequence clarification Revised Table
2000
ARCHITECTURE OVERVIEW
Pentium processor with on-die cache mobile module MMC-1 highly integrated assembly containing mobile Pentium processor with on-die cache immediate system-level support. Pentium processor with on-die cache mobile module MMC-1 offers speeds megahertz,366 megahertz, megahertz, megahertz, megahertz. processor speeds have 66megahertz processor system (PSB) speed.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Figure illustrates block diagram Pentium processor with on-die cache mobile module MMC-1.
Processor Core Voltage
Mobile Celeron Processor Core
Sense
V_DC 5V-21V
V_CPUIO 2.5V
443DX
280-Pin Connector
Figure Block Diagram Pentium Processor With On-die Cache Mobile Module MMC-1
Memory SMBus
GCLKO GCLKI
PCLK1
SMBus
DCLKRD DCLKWR DCLKO
PIIX4E/M Sidebands
HCLK0
Volt. Reg.
R_GTL
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
CONNECTOR INTERFACE
Signal Definition
This section provides signal groups connector information. signals defined compatibility with future Intel mobile modules.
Table provides list signals category corresponding number signals each category. proper signal termination, contact your Intel sales representative further information.
Table Module Connector Signal Summary
Signal Group
Memory Processor/PIIX4E/M Sideband Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: V_CPUIO JTAG Miscellaneous Module Ground Reserved Total
Number Pins
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output pin, this requires pullup resistor Bi-directional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals CMOS buffers voltage compatible signals with 3.3-volt outputs 5.0-volt tolerant inputs.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.2
Memory (108 Signals)
Table lists memory interface signals. Table Memory Signal Descriptions
Name
MECC[7:0]
Type
CMOS
Voltage
Description
Memory Data: These signals carry Memory data during access DRAM. supported Pentium processor with on-die cache mobile module.
RASA[5:0]# CSA[5:0]#
CMOS
Address Strobe (EDO): These pins select DRAM row. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low.
CASA[7:0]# DQMA[7:0]
CMOS CMOS
Column Address Strobe (EDO): These pins select DRAM column. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle.
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWE[A, SRAS[A,
Memory Address (EDO/SDRAM): This column address DRAM. 82443DX Host Bridge system controller identical sets address lines (MAA MAB#). module supports only address lines. additional addressing features, please refer Intel® 440DX PCIset Datasheet.
CMOS CMOS
Memory Write Enable (EDO/SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access precharge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. This signal also allows Column access. SDRAM Clock Enable (SDRAM): When these signals deasserted, SDRAM enters power-down mode. CKEB used system electronics. Memory Data: These signals connected DRAM data bus. They terminated module.
SCAS[A,
CMOS
CKE[A, MD[63:0]
CMOS CMOS
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.3.
Signals)
Table lists interface signals. Table Signal Description Description Address/Data: standard address data lines. address driven with FRAME# assertion data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: 82443DX Host Bridge drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 82443DX supports lock initiated cycles only. initiated locked cycles supported. Request: master requests PCI. Grant: Permission given master PCI. Hold: This signal comes from expansion bridge; bridge request PCI. 82443DX Host Bridge will drain DRAM write buffers, drain processor-to-PCI posting buffers, acquire host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: 82443DX Host Bridge drives this signal grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#. System Error: 82443DX asserts this signal indicate error condition. Please refer Intel® 440BX PCIset Datasheet further information. Clock Run: open-drain output input. 82443DX Host Bridge requests central resource (PIIX4E/M) start maintain clock asserting CLKRUN#. 82443DX Host Bridge tri-states CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 82443DX Host Bridge. signals also tri-state, compliant with specifications.
Name AD[31:0] C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# PLOCK#
Type
Voltage
REQ[4:0]# GNT[4:0]# PHOLD#
PHLDA#
SERR# CLKRUN#
PCI_RST#
CMOS
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.4
Processor PIIX4E/M Sideband Signals)
Table lists processor PIIX4E/M sideband interface signals. voltage level these signals determined V_CPUIO.
Table Processor/PIIX4E/M Sideband Signal Descriptions
Name
FERR#
Type
CMOS
Voltage Description
V_CPUIO Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor driven processor PIIX4E/M. Processor Reset: signal used module. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E/M. Initialization: INIT# asserted PIIX4E/M processor system initialization. This signal open-drain. Processor Interrupt: INTR driven PIIX4E/M signal processor that interrupt request pending needs serviced. This signal open-drain. Non-Maskable Interrupt: used force non-maskable interrupt processor. PIIX4E/M bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal open-drain. Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound which occurs Intel 8086 processor. System Management Interrupt: SMI# active synchronous output from PIIX4E/M that asserted response many enabled hardware software events. SMI# open-drain signal asynchronous input processor. However, this chip SMI# synchronous PCLK. Stop Clock: STPCLK# active synchronous open-drain output from PIIX4E/M that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, responds entering power state (Quick Start). processor will only exit this mode when this signal deasserted.
CPURST IGNNE# INIT# INTR
CMOS CMOS CMOS CMOS CMOS
V_CPUIO V_CPUIO V_CPUIO V_CPUIO V_CPUIO
A20M# SMI#
CMOS CMOS
V_CPUIO V_CPUIO
STPCLK#
CMOS
V_CPUIO
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.5
Power Management Signals) solely digital thermal sensor, SMBus contains reserved serial addresses future use. section more details.
Table lists power management interface signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used
Table Power Management Signal Descriptions
Name
OEM_PU L2_ZZ SUS_STAT# VR_ON
Type
CMOS CMOS CMOS
Voltage
V_CPUIO V_3ALWAYS
Description
Pullup: This pullup resistor required module. Low-Power Mode Cache SRAM: This signal used module. Suspend Status: This signal connects SUS_STAT1# outputs PIIX4E/M. provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3-V (5.0-V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E/M SUSB# signal, which used controlling Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal (VIL(max)=0.4V, VIH(min)=3.0V.) Figure Power-on Sequence Timing" proper sequencing VR_ON. VR_PWRGD: This signal driven high indicate that voltage regulator stable pulled using 100K resistor when inactive. used some combination generate system PWRGOOD signal. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Ensure proper termination based upon System Management Specification, Revision 1.0. Serial Data: open-drain data signal SMBus interface digital thermal sensor. Ensure proper termination based upon System Management Specification, Revision 1.0. Interrupt: This signal open-drain output signal digital thermal sensor.
VR_PWRGD
SM_CLK
CMOS
SM_DATA
CMOS
ATF_INT#
NOTE:
CMOS
V_3ALWAYS: 3.3V supply. generated whenever V_DC available supplied PIIX4E/M resume well.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.6
Clock Signals)
Table lists clock interface signals. Table Clock Signal Descriptions
Name
OEM_PD PCLK
Type
CMOS
Voltage
V_3S
Description
Pulldown: renamed from PCI_REF required module. Clock PCLK input module from CKDM66-M clock source system' clocks. This clock used 82443DX Host Bridge logic clock domain. This clock stopped when PIIX4E/M PCI_STP# signal asserted and/or during suspend states. Host Clock These clocks inputs module from CKDM66-M clock source used processor 82443DX Host Bridge system controller. This clock stopped when PIIX4E/M CPU_STP# signal asserted and/or during suspend states. Suspend Clock: This signal used module. Frequency Status: This signal provides status host clock frequency system electronics. These signals static pulled either high V_3S voltage supply through 10-K resistor. This module designed 66-MHz strapping option shown below. FQS1 FQS0 Frequency Reserved Reserved
HCLK[1:0]
CMOS
V_CPUIO
SUSCLK FQS[1:0]
CMOS CMOS
V_3S
CPU3.3_2.5#
CMOS
V_CPUIO
Clock Voltage Select: Provides status system electronics about voltage level which CKDM66-M clock generator should operating. This signal pulled module.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.7
Voltages Signals)
Table lists voltage signal definitions. Table Voltage Descriptions
Name
V_DC V_3S V_CPUIO
Type
Number Pins
Input: 5V-21V.
Description
SUSB# controlled 3.3V: V_3S supplied system electronics. This 3.3V power supply that turned during suspend during system states STR, STD, Soff. SUSC# controlled Power managed 5.0-V supply. output voltage regulator system electronics. This rail during Soff. SUSC# controlled 3.3V: Power managed 3.3-V supply. output voltage regulator system electronics. This rail during Soff. Processor Ring: Powers processor interface signals such PIIX4E/M open-drain pullups processor/PIIX4E/M sideband signals CKDM66-M clock source.
3.1.8
JTAG Signals) since definition interface changed between generations mobile Pentium processor mobile Pentium processor with on-die cache.
Table lists JTAG signals, which system electronics implement JTAG chain port, desired. JTAG signals provided cannot used port,
Table JTAG Pins
Name
TCLK TRST# ITP(1:0) ITP1 ITP0
NOTE:
Type
Voltage
V_CPUIO V_CPUIO V_CPUIO V_CPUIO V_CPUIO V_CPUIO
Description
JTAG Test Data Out: Serial output port. instructions data shifted processor from this port. JTAG Test Data Serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: estability clock clocking JTAG boundary scan sequence. JTAG Test Reset: Asynchronously resets controller processor. Debug Port Signals: These signals used module should connected.
DBREST# (reset target system) debug port logically ANDed"with VR_PWRGD PIIX4E/M' PWROK.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
3.1.9
Miscellaneous Signals)
Table lists miscellaneous signals. Table Miscellaneous Pins
Name
Module ID[3:0]
Type
CMOS
Number
Description
Module Revision These pins track revision level Pentium processor with on-die cache mobile module. 100-K pullup resistor V_3S required these signals should placed system electronics. Section 7.0, Labeling Information"for more detail. Mobile Pentium processor with on-die cache mobile Pentium processor present: high this signal indicates PIIX4E/M bridge CONFIG1 that module based Pentium architecture. indicates that module Pentium processor family. This signal allowed float Pentium processor with on-die cache mobile module MMC-1 requires 100-K pullup resistor V_3S system electronics. This signal grounded. Ground. Unallocated Reserved pins should connected.
PPP_PP#
CMOS
Ground Reserved
RSVD
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Connector Assignments Assignments"for assignments pads connector.
Table lists signals each MMC-1 system electronics. Refer Section 3.3,
Table Connector Assignments
Number
MD31 MD30 MD29 MD27 V_3S MD28 MD26 MD25 MD24 CAS3#/DQM3 CAS6#/DQM6 MA00 CKEA V_3S MA02 MA03 MD55 MD54 MD51 MD52 MD53 MD49 V_3S MD48 MD50 SRASA# SRASB# MWEA# MWEB# RAS0#/CS0# RAS1#/CS1# V_3S MD14 MD11 MD15 MD10 MD13 MD09 MD08 V_3S
MD63 MD61 MD62 MD58 V_3S MD60 MD56 MD57 MD59 CAS7#/DQM7 CAS2#/DQM2 MA01 CKEB V_3S MA04 MA05 MD22 MD23 MD20 MD21 MD19 MD17 V_3S MD18 MD16 SCASA# SCASB# MECC3 MECC7 MECC6 MECC2 V_3S MECC1 MECC5 MECC4 MECC0 MD43 MD41 MD45 V_3S
MID0 Reserved V_DC V_DC V_DC V_DC V_DC Reserved MID2 AD00 AD01 AD02 AD03 V_3S AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 V_3S AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 V_3S AD20 AD21 AD22 RAS2#/CS2# RAS3#/CS3# RAS4#/CS4# RAS5#/CS5#
MID1 Reserved V_DC V_DC V_DC V_DC V_DC Reserved MID3 FRAME# LOCK# DEVSEL# IRDY# V_3S TRDY# STOP# PHOLD# PHLDA# PCI_RST# SERR# REQ0# REQ1# REQ2# REQ3# GNT0# GNT1# GNT2# GNT3# L2_ZZ Reserved V_3S Reserved PPP_PP# CLKRUN# SM_CLK SM_DATA ATF_INT# SUSCLK
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
MD12 MA06 MA07 MA08 MA09 CAS1#/DQM1 CAS4#/DQM4 MA10 V_3S MA11 MD39 MD37 MD38 MD36 MD33 MD35 MD32 MD34 V_3S OEM_PD FQS0 HCLK1
MD42 MD40 MD44 MD46 MD47 CAS5#/DQM5 CAS0#/DQM0 MA12 V_3S MA13 MD07 MD02 MD00 MD04 MD01 MD03 MD06 MD05 V_3S PCLK FQS1 HCLK0
AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 V_3S AD31 C/BE0# C/BE1# C/BE2# C/BE3# IGNNE# FERR# A20M# V_CPUIO ITP0 ITP1 CPU3.3_2.5#
SUS_STAT# OEM_PU VR_ON VR_PWRGD Reserved Reserved INIT# V_CPUIO INTR CPURST STPCLK# SMI# V_CPUIO TRST# TCLK
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Assignments connector assignments manufacturer' system electronics.
MMC-1 surface mount connector 0.6-milimeter pitch pins. Refer Section 5.1.4 Height Restrictions"for size information. Figure shows
Figure 280-Pin Connector Footprint Numbers, Module Secondary Side
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Table summarizes specifications MMC-1 connector. Table Connector Specifications
Parameter
Material Contact Housing Electrical Current Voltage
Condition
Copper Alloy
Specification
Thermo Plastic Molded Compound: minimum maximum maximum contact cycles contact 0.35 contact
Insulation Resistance Termination Resistance Capacitance Mechanical Mating Cycles Connector Mating Force Contact Unmating Force
FUNCTIONAL DESCRIPTION E_SMRAM feature that supports write-back cacheable SMRAM space megabyte. minimize power consumption while system idle, internal 82443DX Host Bridge clock turned (gated off). This accomplished setting G_CLK enable power management register 82443DX through system BIOS. 4.3.1 Memory Organization
Pentium Processor With On-die Cache Mobile Module MMC-1
Pentium processor with on-die cache mobile module MMC-1 offered speeds megahertz, megahertz, megahertz, megahertz, megahertz. processor speeds have speed megahertz. Cache
on-die cache kilobytes, four-way associative, runs speed processor core. 82443DX Host Bridge System Controller Intel' 82443DX Host Bridge system controller combines mobile Pentium processor with on-die cache controller, DRAM controller, controller into component. 82443DX Host Bridge multiple power management features designed specifically notebook systems such CLKRUN#, feature that enables controlling clock off. 82443DX Host Bridge suspend modes, which include Suspend-to-RAM (STR), Suspend-to-Disk (STD), Powered-on-Suspend (POS). System Management (SMRAM) power management modes, which include Compatible SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets.
MMC-1 connector signaling interface supports 82443DX Host Bridge standard mode, memory configurations, modes operation. This allows memory interface support following: memory control signals, sufficient support three SO-DIMM sockets banks SDRAM megahertz. signal each bank. Memory features supported 82443DX Host Bridge system controller standard MMC-1 mode are: Support eight banks memory. Second memory address lines (MAA[13:0]). Accelerated Graphics Port (AGP). 82443DX Host Bridge system controller supports DRAM technologies SDRAM. These memory types should mixed system, that DRAM rows (RAS[5:0]#) must same technology. 82443DX Host Bridge system controller targets 60-nanosecond DRAMs, 66-megahertz SDRAMs. Pentium processor with on-die cache mobile module' clocking architecture supports SDRAM. Tight timing requirements 66-megahertz SDRAM clocks
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
allow host SDRAM clocks generated from same clocking architecture system electronics. complete details about using SDRAM memory trace length guidelines, refer Mobile Pentium® processor 82443BX PCIset Advanced Platform Recommended Design Debug Practices. Refer Intel® 440BX PCIset Datasheet details memory device support, organization, size, addressing.
4.3.2
Reset Strap Options
Several strap options memory address define behavior module after reset. Other straps allowed override default settings. Table shows various straps their implementation.
Table Configuration Straps 82443DX Host Bridge System Controller
Signal
MAB[12]# MAB[11]# MAB[10] MAB[9]# MAB[7]# MAB[6]#
Function
Host Frequency Select order queue depth Quick Start select disable Config Host Buffer Mode select
Module Default Setting
strap- 66-MHz default. strap- maximum queue depth set, i.e. Strapped high module Quick Start mode. Strapped disable AGP. Strapped MMC-1 compatible mode. Strapped high module mobile buffers.
4.3.3
Interface
interface 82443DX Host Bridge available connector. 82443DX Host Bridge supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. Refer Mobile Design Guide complete details Clockrun protocol. 82443DX Host Bridge responsible arbitrating bus. With MMC-1 connector 82443DX Host Bridge support five masters. There five Request/Grant pairs, REQ[4:0]# GNT[4:0]#, available manufacturer' system electronics. interface connector volts only. devices that drive outputs 5.0Vt nominal level supported. 82443DX Host Bridge system controller compliant with specification, which improves worst case access latency from earlier specifications. detailed specification, 82443DX Host Bridge supports only Mechanism accessing configuration space. This implies that signals AD[31:11] available IDSEL signals. However, since 82443DX Host Bridge always device AD11 will never asserted during configuration cycles IDSEL. 82443DX reserves AD12 AGPbus, which supported MMC-1 connector. Thus, AD13 first available address line usable IDSEL. AD18 should used PIIX4E/M.
4.3.4
Feature
Intel MMC-1 connector family does support graphics port interface. information, refer Intel® Pentium® Processor Mobile Module: Mobile Module Connector (MMC-2).
Power Management
4.4.1
Clock Control Architecture
Pentium processor with on-die cache mobile module' clock control architecture optimal notebook designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep. Auto Halt state provides power clock state that controlled through software execution instruction. Quick Start state provides power, exit latency clock state that used hardware controlled idle" computer states. Deep Sleep state provides extremely power state that used Power-onSuspend states, which alternative shutting processor' power. exit latency Deep Sleep state been reduced microseconds. Stop Grant Sleep states available Pentium processor with on-die cache mobile module these states intended desktop server systems.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Stop Grant Quick Start clock states mutually exclusive. example strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal ground Reset enables Quick Start state. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state useful platforms
supported Pentium processor with on-die cache mobile module MMC-1. Quick Start state available module provides significantly lower power level. Figure provides illustration clocking architecture. Performing state transitions shown Figure neither recommended supported.
Normal State
HS=false
STPCLK#
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs
Stop Grant
Snoop serviced
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# Intel mobile modules support shaded clock control states
Figure Clock Control States
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.4.2
Normal State processor. These latched events will serviced until processor returns Normal state. Only each event will recognized upon return Normal state. 4.4.5 Quick Start State
This normal operating mode. processor' core clock running processor actively executing instructions. 4.4.3 Auto Halt State
This power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#). Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant Quick Start state, which issues Stop Grant Acknowledge cycle. Deasserting STPCLK# will cause processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. Returning from handler either Normal state Auto Halt state. Intel Architecture Software Developer' Manual, Volume III: System Programmer' Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state. 4.4.4 Stop Grant State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. While processor Quick Start state, will respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted. 4.4.6 HALT/Grant Snoop State
Intel mobile modules support Stop Grant state. processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still responds snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) will latched
processor will respond snoop transactions while Auto Halt state, Stop Grant state, Quick Start state. When snoop transaction presented processor will enter HALT/Grant Snoop state. processor will remain this state until snoop been serviced quiet. After snoop been serviced, processor will return previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state, except those signal transitions that required perform snoop. 4.4.7 Sleep State
Intel mobile modules support Sleep state. Sleep state very power state which processor maintains context phase-locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state SLP# signal asserted, causing
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor' input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
4.4.8
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Stopping BCLK input processor enters Sleep state. proper operation, BCLK input should stopped state. processor will return Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30millisecond delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
Table Clock State Characteristics Clock State Normal Auto Halt Stop Grant Quick Start
Exit Latency Approximately clocks clocks Through snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks
Processor Power Varies 1.2W 1.2W 0.5W
Snooping
System Uses Normal program execution controlled entry idle mode controlled entry/exit mobile throttling controlled entry/exit mobile throttling
HALT/Grant Snoop Sleep Deep Sleep
NOTES:
clocks after snoop activity. Stop Grant state clocks msec
specified 0.5W
Supports snooping power states controlled entry/exit desktop idle mode support controlled entry/exit mobile powered-on suspend support
Intel mobile modules support shaded clock control states. 100% tested. Specified design characterization.
Typical Power
Table shows typical power values. Table Power State
NOTE: These average values measurement guidelines only.
Typical MMC-1 Power 0.475W 0.018W
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.6.1 Electrical Requirements
Requirements
Table provides power supply design criteria.
following section provides information electrical requirements Pentium processor with on-die cache mobile module MMC-1. Table Power Supply Design Specifications Parameter Input Voltage Input Current Maximum Surge Current
Symbol DC-Surge DC-Leakage 5-Surge 5-Leakage 3-Surge 3-Leakage 3S-Surge 3S-Leakage VCPUPU CPUPU VCLK
Unit
Notes
12.0
21.0 17.3
Typical Leakage Current Power Managed Voltage Supply Power Managed Current Maximum Surge Current Typical Leakage Current Power Managed 3.3V Voltage Supply Power Managed 3.3V Current Maximum Surge Current Typical Leakage Current Power Managed 3.3V Voltage Supply Power Managed 3.3V Current Maximum Surge Current Typical Leakage Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current 3.135 2.375 2.375 24.0 3.135 4.75
5.25 3.465 0.35 35.0 3.465 2.625 2.625 80.0
0.125 0.125
NOTES: Unless otherwise noted, specifications this table apply Intel mobile module frequencies. V_DC order determine typical V_DC current. V_DC order determine maximum V_DC current. Leakage current that expected when VR_ON deactivated V_DC still applied. These values system dependent.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.6.2
Requirements
Table provides clock (BCLK) requirements Pentium processor with on-die cache mobile module MMC-1. Table BCLK Specifications Processor Core Pins Parameter Unit Figure
1,2,3
Notes processor core frequencies
Frequency
NOTES:
66.67
6,7,8
±250 0.875 0.875
BCLK Period
15.0
BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time
0.175 0.175
>1.8V <0.7V (0.9V-1.6V) (1.6V-0.9V)
Unless otherwise noted, specifications this table apply Intel mobile modules. timings GTL+ signals referenced BCLK rising edge 1.25V processor core pin. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00V processor core pins. timings CMOS signals referenced BCLK rising edge 1.25V processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25V processor core pins. internal core clock frequency derived from clock. clock core clock ratio determined during initialization described predetermined Pentium processor with on-die cache mobile module. BCLK period allows +0.5 tolerance clock driver variation. CK97 Clock Synthesizer/Driver Specification further information. Measured rising edge adjacent BCLKs 1.25V. jitter present must accounted component BCLK skew between devices. clock driver' closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into 10-pF 20-pF load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer/Driver Specification further details. 100% tested. Specified design characterization clock driver requirement.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.6.2.1
BCLK Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor core BCLK signal. Figure describes signal quality waveform BCLK processor core pins. Table BCLK Signal Quality Specifications Processor Core Parameter Unit BCLK BCLK
-0.8
V/ns
Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback
BCLK rising/falling slew-rate
NOTES:
Unless otherwise noted, specifications this table apply Intel mobile modules. BCLK must rise fall monotonically between VIL,BCLK VIH, BCLK. mobile Pentium processor with on-die cache clock overshoot undershoot specification 66MHz operation. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. proper signal termination, refer Clocking Guidelines Mobile Pentium® Processor 440BX PCIset Advanced Platform Recommend Design Debug Practices.
000806
Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Voltage Regulator 4.7.1 voltage regulator (DC/DC converter) provides appropriate core voltage, ring voltage, sideband signal pullup voltage Pentium processor with on-die cache mobile module. voltage range volts volts. Voltage Regulator Efficiency
Table lists voltage regulator efficiencies.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Table Typical Voltage Regulator Efficiency
Icore,
NOTES:
V_DC,
12.0 12.0 12.0 12.0 12.0 12.0 12.0 21.0 21.0 21.0 21.0 21.0 21.0 21.0
I_DC,
0.370 0.702 1.044 1.404 1.762 2.144 2.528 0.159 0.295 0.438 0.584 0.736 0.890 1.043 0.091 0.170 0.253 0.340 0.429 0.519 0.617
Efficiency1
82.8% 88.8% 89.8% 89.7% 88.1% 86.4% 85.0% 79.7% 87.0% 87.8% 87.3% 86.1% 84.9% 83.8% 79.3% 86.0% 87.3% 85.3% 84.1% 82.9% 80.7%
These efficiencies will change with future voltage regulators that accommodate wider ranges input voltages. With V_DC applied voltage regulator off, typical leakage with maximum Icore indicates core current being drawn during test measurement.
4.7.2
Control Voltage Regulator VR_PWRGD signal indicates that voltage regulator power operating stable voltage level. VR_PWRGD system electronics control power inputs gate PWROK PIIX4E/M. Table lists voltage signal definitions sequences, Figure shows signal sequencing voltage planes sequencing required normal operation Pentium processor with on-die cache mobile module MMC-1.
VR_ON turns voltage regulator off. VR_ON should controlled function SUSB#, which controls system' power planes. VR_ON should switch high only when following conditions met: V_5(s) volts V_DC 4.75 volts. Caution- Turning VR_ON prior meeting these conditions will severely damage Pentium processor with on-die cache mobile module.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.7.2.1
Voltage Signal Definition Sequencing Table Voltage Signal Definitions Sequences Signal Source System Electronics Definitions Sequences voltage driven from power supply required between V_DC powers module' DC-to-DC converter processor core voltages. cannot inserted removed while V_DC powered supplied system electronics 82443DX. supplied system electronics 82443DX' 5.0-V reference voltage voltage regulator. V_3S supplied system electronics. This 3.3-V power supply that turned during suspend during system states STR, STD, Soff. Enables voltage regulator circuit. When driven active high (3.3V) voltage regulator circuit module activated. signal driving VR_ON should digital signal with rise fall time less than equal (VIL (max)=0.4V, (min)=3.0V.) result VR_ON being asserted, V_CORE output DC-DC regulator module driven core voltage processor. also used host GTL+ termination voltage, known VTT. V_BSB_IO 1.8V. system electronics uses this voltage power cache-to-processor interface circuitry. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD will assert logic high (3.3V). This signal must pulled system electronics. VR_PWRGD should ANDed" with V_3s generate PIIX4E/M input signal, PWROK. system electronics should monitor VR_PWRGD verify asserted high prior active high assertion PIIX4E/M PWROK. V_CPUIO 2.5V. system electronics uses this voltage power PIIX4E/M-to-processor interface circuitry, well HCLK(0:1) drivers processor clock.
V_DC
V_3S VR_ON
System Electronics System Electronics System Electronics System Electronics
V_CORE (also host GTL+ termination voltage VTT) V_BSB_IO VR_PWRGD
Module
Module Module
V_CPUIO
Module
following list provides additional specifications clarifications power sequence timing Figure provides illustration power sequence timing. VR_ON signal only asserted logical high digital signalafter V_DC volts, volts, volts. Rise Time Fall Time VR_ON must less than equal microsecond when goes through Vih. VR_ON Vil(max) +0.4 volts Vih(min) +3.0 volts. VR_PWRGD will asserted logic high (3.3 volts) after V_CORE stabilized V_DC reaches volts. This signal should pulled system electronics. power-on process, Intel recommends raise higher voltage power plane first (V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. power-off process should reverse process, i.e. VR_ON gets deasserted, followed lower power planes, finally higher power plane. VR_ON must monotonically rise through fall through points. sign slope change between rising falling. VR_ON must provide instantaneous in-rush current module with following values listed Table
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Table VR_ON In-rush Current Instantaneous Operating 41.0
NOTE: These values based 3.3V VR_ON signal.
VR_ON Valid-Low Time: This specifies long VR_ON needs valid before VR_ON turned back again. going from valid then back following conditions must prevent damage system Intel mobile module: VR_ON must millisecond. original voltage level requirements turn-on must before assertion VR_ON (i.e. V_DC volts, volts, volts).
V_DC V_3S VR_ON VR_PWRGD V_CPUPU/ V_CLK
POWER SEQUENCE TIMING
PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E/M. V_DC 4.7V, V_5>=4.5V, V_3S>=3.0V. V_CPUPU V_CLK generated Intel Mobile Module. This power supplied processor module connector. This should first plane power VR_PWRGD specified associated high/active module regulator within less than equal max. after assertion VR_ON.
Figure Power-on Sequence Timing
4.7.3
Power Planes: Bulk Capacitance Requirements
order provide adequate filtering in-rush current protection system design, bulk capacitance required. small amount bulk capacitance supplied
module. However, order achieve proper filtering additional capacitance should placed system electronics. Table details bulk capacitance requirements system electronics.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Table Capacitance Requirements Power Plane Power Plane V_DC V_3S V_CPUIO
NOTES: Placement above capacitance requirements should located near connector. V_CPUIO filtering should located next system clock synthesizer. Ripple current specification depends V_DC input. 5.0-V V_DC, 3.5-A device required. V_DC higher, sufficient.
Capacitance Requirements 0.01
Ripple Current 1-3.5A
Rating tolerance tolerance tolerance tolerance tolerance
0.01 0.01 0.01 8200
4.7.4
Surge Current Guidelines
module would approximately amperes. This information also used develop bulk capacitance requirements. Table more information. Note: Depending system electronics design, different impedances yield different result. thorough analysis should performed understand implications surge current their system. Figure shows electrical model used when analyzing instantaneous power-on conditions, Figure7 illustrates results with SPICE simulation.
This section provides results worst case, surge current analysis. analysis determines maximum amount surge current that Pentium processor with on-die cache mobile module MMC-1 manage. analysis, module microfarads with 0.15 ohms total. MMC-1 connector approximately milliohms series resistance, total series resistance ohms. user powers system with adapter volts), amount surge current
Figure Instantaneous In-rush Current Model
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Figure Instantaneous In-rush Current stringent component height requirements Pentium processor with on-die cache mobile module, Polymerized Organic Semiconductor capacitors must used input bulk capacitance voltage regulator circuit. Because capacitor' susceptibility high rush current, special care must taken. soften in-rush current provide overvoltage overcurrent protection ramp V_DC slowly using circuit similar shown Figure
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
NOTE:
Values shown reference only. Figure Overcurrent Protection Circuit 4.7.4.1 Slew-rate Control: Circuit Description Figure voltage generated applying Adaptor Battery. (on) P-Channel MOSFET such Siliconix* SI4435DY. When voltageOn applied increased over 4.75 volts, UNDER_VOLTAGE_LOCKOUT circuit allows pull gate start turn-on sequence. pulls drain toward ground, forcing current flow through will start source current until after t_delay with t_delay defined
t_delay
Vpwr Vgs_max
Vgs_max
manufacturer' Vgs_max specification volts must never exceeded. However, Vgs_max must high enough keep (On) device
Vpwr
possible. After initial t_delay, will begin source current V_DC will start ramp ramp time, t_ramp, defined
t_ramp
Maximum current during voltage ramping
Vsat Vgs_max
t_delay
Vpwr Ctotal t_ramp
shown circuit Figure t_delay 5.53 t_tran 14.0 I_max
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Figure shows SPICE ulation circuit Figure increase reliability Tantalum capacitors, slew-rate control circuit described Figure8 voltage derate capacitor about percent. example, maximum input voltage volts, 35-volt, capacitor with high ripple current capability. Place five, 22microfarad/35-volt capacitors baseboard directly V_DC pins connector.
slew-rate control circuit should also applied every input power source system V_DC provide most protection. power logically together node, there still potential problem. example, Li-Ion battery pack powering system volts PWR), Adaptor volts) plugged into system, will immediately source current node V_DC rapidly. This because slew-rate control already Therefore, slew-rate control must applied every input power source provide most protection.
Figure Spice Simulation Using In-rush Protection- Example Only Undervoltage Lockout: Circuit Description (V_uv_lockout) circuit shown Figure provides undervoltage protection locks applied voltage module prevent accidental turn-on voltage. output 4.7.4.2
this circuit, LM339 comparator, opencollector output. when applied voltage less than 4.75 volts. This voltage calculated with following equation with voltage across volts 2.5-volt reference generator).
V_uv_lockout
Vref.
R18.
V_uv_lockout 4.757 volts
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
4.7.4.3
Overvoltage Lockout: Circuit Description (V_ov_lockout) Pentium processor with on-die cache mobile module MMC-1is specified operate with maximum input voltage volts. This circuit locks input voltage
exceeds maximum volts. output this circuit, LM339 comparator, open collector output. when applied voltage more than volts. This voltage calculated with following equation:
V_ov_lockout
Vref.
V_ov_lockout 20.998 volt
4.7.4.4 Overcurrent Protection: Circuit Description Figure shows that circuit detects overcurrent condition cuts input voltage applied Pentium processor with on-die cache mobile module. This circuit different current limit trip points. This takes into account different maximum current drain Celeron processor mobile module different input voltages. With Adaptor (I_wAdaptor): Assuming Adaptor voltage volts battery Li-Ion configuration with minimum volts, maximum current above circuit calculated using following expression:
I_wAdaptor
Vref Vbe_Q1.
I_wAdaptor 0.989 Without Adaptor (I_woAdaptor):
I_woAdaptor
Vref Vbe_Q1 R14.
I_woAdaptor 2.375
Active Thermal Feedback
Table identifies addresses allocated SMBus thermal sensor. Table Thermal Sensor SMBus Address Table
Function
Thermal Sensor
NOTE:
SMBus Address
1001
thermal sensor used compliant with SMBus addressing. Please refer Pentium® processor Thermal Sensor Interface Specification.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Thermal Sensor Configuration Register Standby mode. thermal sensor will still perform temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Convert mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active, only Auto Convert mode should used. Refer Mobile Pentium Processor Pentium Processor Mobile Module Thermal Sensor Interface Specifications.
configuration register thermal sensor controls operating mode (Auto Convert Standby) device. Since processor temperature varies dynamically during normal operation, Auto Convert mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters Auto Convert mode. RUN/STOP high, then thermal sensor immediately stops converting enters
Name MASK RUN/STOP
Table Thermal Sensor Configuration Register Reset State Function Masks SMBALERT# when high. Standby mode control bit. low, device enters Auto Convert mode. high, device immediately stops converting, enters standby mode where oneshot command performed. Reserved future use.
NOTE:
bits should written read don' care"for programming purposes.
MECHANICAL SPECIFICATION
Module Dimensions
This section provides physical dimensions Pentium processor with on-die cache mobile module MMC-1.
Figure shows board dimensions orientation Pentium processor with on-die cache mobile module MMC-1.
Figure Board Dimensions
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
5.1.1
MMC-1 Connector Location
Figure shows location connector referenced adjacent mounting hole.
Figure Board Dimensions- Orientation 5.1.2 Printed Circuit Board Thickness Note: Ensure that mechanical restraining method system-level contacts able support this range thickness compatibility with future Intel mobile modules.
Figure shows Pentium processor with on-die cache mobile module MMC-1 profile associated minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies with current future Intel mobile modules.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
min: 0.90 max: 1.10
Printed Circuit Board
Figure Printed Circuit Board Thickness 5.1.3 Height Restrictions cache mobile module MMC-1 thesystem electronics selecting three possible mating connectors. mating connector sizes millimeters, millimeters, millimeters. These three options provide system manufacturer with flexibility choosing components between boards. Information these connectors obtained from your local Intel representative.
Figure shows mechanical stack-up associated component clearance requirements. This referred module keep-out zone should entered altered. system manufacturer establishes board-to-board clearance between Pentium processor with on-die
NOTE: topside component clearance independent thickness.
Figure Keep-out Zone
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Thermal Transfer Plate
82433BX provides heat dissipation thermal attach point where system manufacturer attach heat pipe, heat spreader plate, thermal solution transfer heat through notebook system. Figure Figure attachment dimensions from thermal interface block TTP. When attaching mating block TTP, thermal elastimer thermal grease should used. This material reduces thermal resistance. thermal interface block should secured with 2.0-millimeter screws using
maximum torque Kg*cm Kg*cm (equivalent 0.147 to.197 N*m). thread length 2.00millimeter screws should 2.25-millimeter gageable thread (2.25-millimeters minimum 2.80-millimeters maximum). system manufacturer should exact dimensions maximum contact area ensure that warpage occurs. warpage occurs, thermal resistance module could adversely affected. thermal resistance between processor core system interface (top TTP) less than Celsius watt.
Figure Thermal Transfer Plate
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Figure Thermal Transfer Plate Physical Support surrounding ring, which used with metal standoff shielding purposes. Standoffs should used provide support installed Pentium processor with on-die cache mobile module. distance from bottom module system electronics board with connectors mated millimeters +0.16 millimeters -0.13 millimeters. However warpage baseboard vary should calculated into final dimensions standoffs used. calculations made with Intel® MMC-1 Standoff/Receptacle Height Spreadsheet. Information this spreadsheet obtained from your local Intel representative. Figure shows standoff support hole patterns, board edge clearance, dimensions containment ring, keep-out area.
5.3.1
Mounting Requirements
Three mounting holes available securing module system base system electronics. Figure mounting hole locations. These hole locations board edge clearances will remain fixed Intel mobile modules. Intel recommended that three mounting holes used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762 millimeters (0.030 inches) wide containment ring around perimeter module. This ring each layer module grounded. surface module, metal exposed shielding purposes. hole patterns placed module also have plated
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
Hole detail, places
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
Figure Standoff Holes, Board Edge Clearance, Containment Ring (Topside) operating environments, processor junction temperature, must within range Celsius Celsius. power handling capability system thermal solution reduced less than recommended typical thermal design power with implementation firmware/software control throttling" that reduces power consumption dissipation.
5.3.2
Module Weight
Pentium processor with on-die cache mobile module MMC-1 weighs approximately grams. THERMAL SPECIFICATION
Thermal Sensor Setpoint
Thermal Design Power
typical thermal design power (TDP) typical total power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while executing worst case power instruction mix. This includes power dissipated relevant components. During
thermal sensor implements SMBALERT# signal described SMBus specification. SMBALERT# always asserted when temperature processor core thermal diode thermal sensor internal temperature exceeds either upper lower temperature thresholds. SMBALERT# also asserted measured temperature equals either upper lower threshold.
Table Thermal Design Power Specifications Symbol module
NOTE: During operating environments, processor temperature, must within specified range Celsius Celsius. module thermal solution design reference point thermal solution readiness total module power.
Parameter Thermal Design Power
Typical 11.5
Notes Module core, 82443DX, voltage regulator.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
LABELING INFORMATION secondary side module shown Figure consists characters contains following information:
Pentium processor with on-die cache mobile module MMC-1 tracked ways. first Product Tracking Code (PTC). Intel uses label determine assembly level module. label
Example: PMF3661001AA Definition: Processor Module Pentium processor with on-die cache mobile module MMC-1= Speed Identity 266, 300, 333, 366, Cache Size (256K) Notifiable Design Revision (Start 001) Notifiable Processor Revision (Start
Note: other Intel mobile modules, second field defined Pentium processor with on-die cache mobile module (MMC-2)
Figure Product Tracking Code
second tracking method generated software utility. Four strapping resistors located Pentium processor with on-die cache mobile module MMC-1 determine production level. connected terminated properly, module revision levels determined. generated software utility then
read these bits with stepping provide complete module manufacturing revision level. current module information, please refer latest Product Change Notification letter, which obtained from your local Intel sales representative.
Intel® Pentium® Processor With On-die Cache Mobile Module MMC-1
ENVIRONMENTAL STANDARDS
Table defines environmental standards Pentium processor with on-die cache mobile module MMC-1. Table Environmental Standards
Parameter
Temperature Cycle Humidity Voltage
Condition
Non-operating Operating Unbiased
Specification
-40° relative humidity 3.3V Half Sine, msec Trapezoidal, 50G, msec Inclined Impact ft/s Half Sine, msec Simulated Free Fall gRMS random gRMS 11,800 impacts (low frequency) Non-powered test module only noncatastrophic failure. module tested then inserted system functional test.
Shock
Non-operating Unpackaged Packaged Packaged
Vibration
Unpackaged Packaged Packaged
Damage
Human Body Model
UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. 58119, Santa Clara, 95052-8119 Tel: 765-8080 JAPAN, Intel Japan K.K. Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. Quai Grenelle, 75015 Paris Tel: 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England Tel: 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 85622 Feldkirchen/ Muenchen Tel: 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Pacific Place, Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor Canada, Ltd. Attwell Drive, Suite Rexdale, Ontario Tel: +416 675-2438 BRAZIL, Intel Semicondutores Brasil Centro Empresarial Unidas Torre Oeste Unidas, 12.901 18o. andar Brooklin Novo 04578.000 Paulo S.P. Brasil Tel: +55-11-5505-2296
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