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PENTIUM PROCESSORS WITH VOLTAGE REDUCTION TECHNOLOGY

Max. Operating Frequency iCOMP ® Index 2.0 Rating 75 MHz 67 100 MHz 90 120 MHz 100 133 MHz 111 150 MHz 114

PENTIUM PROCESSORS WITH VOLTAGE REDUCTION TECHNOLOGY
Max. Operating Frequency iCOMP ® Index 2.0 Rating 75 MHz 67 100 MHz 90 120 MHz 100 133 MHz 111 150 MHz 114
Note: Contact Intel Corporation for more information about iCOMP® Index 2.0 ratings.
Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture - Two Pipelined Integer Units Are Capable of 2 Instructions / Clock - Pipelined Floating Point Unit Separate Code and Data Caches - 8K Code, 8K Writeback Data - MESI Cache Protocol Advanced Design Features - Branch Prediction - Virtual Mode Extensions Low Voltage BiCMOS Silicon Technology 4M Pages for Increased TLB Hit Rate
IEEE 1149.1 Boundary Scan Internal Error Detection Features n SL Enhanced Power Management Features - System Management Mode - Clock Control n Voltage Reduction Technology - 2.9V V CC for core supply (75 / 90 / 100 / 120 / 133 MHz) - 3.1V V CC for core supply (150 MHz) - 3.3V V CC for I / O buffer supply n Fractional Bus Operation - 75-MHz Core / 50-MHz Bus - 100-MHz Core / 66-MHz Bus - 120-MHz Core / 60-MHz Bus - 133-MHz Core / 66-MHz Bus - 150-MHz Core / 60-MHz Bus
August 1996
Order Number: 242557-005
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
CONTENTS
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
INTRODUCTION
MICROPROCESSOR ARCHITECTURE OVERVIEW
Intel is manufacturing a reduced power version of the latest Pentium® processor, the Pentium processor with voltage reduction technology, targeting the mobile market. Voltage reduction technology allows the processor to "talk" to industry standard 3.3-volt components while its inner core, operating at 2.9 volts (current 150-MHz processors inner core is 3.1 volts, with plans to have a 2.9 volt version in the future), consumes less power to promote a longer battery life. The Pentium processor with voltage reduction technology is offered in the Tape Carrier Package (TCP) and the Staggered Pin Grid Array (SPGA) package. It has all the advanced features of the 3.3V Pentium except for the differences listed in sections 3.1 and 7.1.1. The Pentium processor with voltage reduction technology has several features which allow highperformance notebooks to be designed with the Pentium processor, including the following: · TCP dimensions are ideal for small form-factor designs. · TCP has superior characteristics. thermal resistance
The Pentium processor with voltage reduction technology extends the Intel Pentium family of microprocessors. It is compatible with a host of other Intel products. The Pentium processor family consists of the Pentium processor with voltage reduction technology described in this document, the original mobile Pentium processor and the various desktop Pentium processors. "Pentium processor" will be used in this document to refer to the entire Pentium processor family in general. The mobile Pentium processor family architecture contains all of the features of the Intel486 CPU family, and provides significant enhancements and additions including the following: · · · · · · · · · · · · · · · · · Superscalar Architecture Dynamic Branch Prediction Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 8K Code and 8K Data Caches Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Bus Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions Voltage Reduction Technology SL Power Management Features
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Mobile Pentium ® Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The on-chip memory management unit (MMU) is completely compatible with the Intel386 family and Intel486 family of CPUs. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the Branch Target Buffer (BTB) so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 CPU. Faster algorithms provide up to 10X speed-up for common operations including add, multiply and load. Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache is 8 Kbytes in size, with a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be writeback or
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Figure 1. Pentium ® Processor Block Diagram
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
TCP PINOUT Pentium ® Processor with Voltage Reduction Technology Differences from the SPGA 3.3V Pentium Processor
To better streamline the part for mobile applications, the following features have been eliminated from the TCP and SPGA Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC and Master / Checker functional redundancy. Table 1 lists the corresponding pins which exist on the SPGA 3.3V Pentium processor but have been removed on the TCP and SPGA Pentium processor with voltage reduction technology.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 1. Signals Removed in Pentium Signal ADSC#
Processor with Voltage Reduction Technology Function
BRDYC#
CPUTYP D / P# FRCMC# PBGNT# PBREQ# PHIT# PHITM# PICCLK PICD0 DPEN# PICD1 APICEN
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
TCP Pinout and Pin Descriptions
TCP PENTIUM ® PROCESSOR PINOUT
VCC2 VCC3 VSS HOLD WB / WT# VCC2 VSS NA# BOFF# BRDY# VCC2 VSS KEN# AHOLD INV EWBE# VCC2 VSS VCC3 VSS CACHE# M / IO# VCC3 VSS BP3 VSS VCC2 BP2 PM1 / BP1 PM0 / BP0 FERR# VSS VCC2 IERR# VCC3 VSS DP7 D63 D62 D61 VCC2 VSS VCC3 VSS D60 D59 D58 D57 VCC2 VSS VCC3 VSS D56 DP6 D55 D54 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VCC3 VSS
VSS SMIACT# PRDY VCC2 PCHK# APCHK# VSS VCC3 BREQ HLDA VSS VCC2 AP VSS VCC3 VSS VCC2 LOCK# VSS VCC3 PCD PWT D / C# EADS# ADS# VCC3 VSS HITM# HIT# VCC3 VSS W / R# BUSCHK# FLUSH# A20M# BE0# BE1# BE2# BE3# VCC3 VSS BE4# BE5# BE6# BE7# VCC3 VSS SCYC CLK NC RESET VSS VCC2 VSS VCC2 A20 VCC3 VSS A19 VSS VCC2 A18 VCC3 VCC2 VSS A17 A16 VCC3 VSS A15 VSS VCC2 A14 VCC3 VSS A13 VSS VCC2 A12 VCC3
VCC2 VSS A11 A10 VCC3 VSS A9 VSS VCC2 A8 VCC3 VSS A7 A6 VCC3 VCC2 VSS A5 A4 VCC3 VSS A3 VSS VCC2 VCC3 VSS A31 A30 A29 A28 VCC3 VSS A27 A26 A25 A24 VCC3 VSS A23 A22 A21 NMI R / S# INTR SMI# VCC2 VSS IGNNE# INIT PEN# VCC2 VSS VCC2 VSS BF0 BF1 NC VCC2 VSS STPCLK# VCC2 VSS VCC3 VCC2 VSS NC VCC2 VSS VCC2 VSS VCC2 VSS VCC2 TRST# VSS VCC2 TMS TDI TDO TCK
D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 VCC3 VSS D28 D27 D26 D25 VCC3 VSS VCC2 VSS D24 DP2 D23 D22 VCC3 VSS D21 D20 D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS D7 D6 D5 D4 VCC3 VSS D3 D2 D1 D0 VCC2 VSS NC NC VCC2 NC VSS VCC3
Figure 2. TCP Pentium ® Processor Pinout
Pentium® Processor with Voltage Reduction Technology TCP Pinout
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
3.2.2. TCP PENTIUM ® PROCESSOR PIN CROSS REFERENCE Table 2. TCP Pin Cross Reference by Pin Name Address A3 A4 A5 A6 A7 A8 219 222 223 227 228 231 A9 A10 A11 A12 A13 A14 234 237 238 242 245 248 A15 A16 A17 A18 A19 A20 251 254 255 259 262 265 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 152 151 150 149 146 145 144 143 139 138 137 134 133 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 132 131 128 126 125 122 121 120 119 116 115 113 108 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 107 106 105 102 101 100 96 95 94 93 90 89 88 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 87 83 82 81 78 77 76 75 72 70 69 64 63 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 62 61 56 55 53 48 47 46 45 40 39 38 A21 A22 A23 A24 A25 A26 200 201 202 205 206 207 A27 A28 A29 A30 A31 208 211 212 213 214
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# 286 296 14 308 315 285 284 283 282 279 278 277 276 9 28 25 10 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# 312 288 21 298 140 127 114 99 84 71 54 37 297 16 31 287 292 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# PEN# PM0 / BP0 293 311 4 34 193 192 197 15 13 303 22 8 199 300 316 191 30 Clock Control BF0 BF1 186 185 CLK STPCLK# 272 181 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# 29 318 299 198 270 273 196 319 161 163 162 164 167 289 5
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VCC 2 1 6 11 17 27 33 41 49 57 65 111 153 157 165 168 170 172 174 177 180 VCC 3 2 19 23 35 43 51 59 67 73 79 85 91 97 103 109 117 123 129 135 141 147 160 178 204 210 216 221 226 230 236 241 247 253 258 264 275 281 291 295 301 306 313 183 188 190 195 217 225 232 240 243 249 257 260 266 268 304 309 317
NOTE: ® These VCC2 pins are 2.9V (3.1V for 150 MHz) inputs for the TCP Pentium processor with voltage reduction technology, but may change to a different voltage on future offerings of this microprocessor family. All VCC3 pins will remain at 3.3V power inputs for the TCP Pentium processor.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VSS 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 173 176 179 182 187 189 194 203 NC 155 156 158 175 184 271 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 3. TCP Pin Cross Reference by Pin Number (Pins 1-160) Pin #
Signal
VCC2 VCC3 VSS HOLD WB / WT# VCC2 VSS NA# BOFF# BRDY# VCC2 VSS KEN# AHOLD INV EWBE# VCC2 VSS VCC3 VSS CACHE# M / IO# VCC3 VSS BP3 VSS VCC2 BP2 PM1 / BP1 PM0 / BP0 FERR# VSS VCC2 IERR# VCC3 VSS DP7 D63 D62 D61
Signal
VCC2 VSS VCC3 VSS D60 D59 D58 D57 VCC2 VSS VCC3 VSS D56 DP6 D55 D54 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VCC3 VSS
Signal
D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 VCC3 VSS D28 D27 D26 D25 VCC3 VSS VCC2 VSS D24 DP2 D23 D22 VCC3 VSS D21 D20
Signal
D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS D7 D6 D5 D4 VCC3 VSS D3 D2 D1 D0 VCC2 VSS NC NC VCC2 NC VSS VCC3
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 3. TCP Pin Cross Reference by Pin Number (Pins 161-320) (Contd.) Pin #
161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NOTES: 1. VCC2 pins are 2.9V (3.1V for 150 MHz) power inputs to the core. 2. VCC3 pins are 3.3V power inputs to the core.
Signal
TCK TDO TDI TMS VCC2 VSS TRST# VCC2 VSS VCC2 VSS VCC2 VSS VCC2 NC VSS VCC2 VCC3 VSS VCC2 STPCLK# VSS VCC2 NC BF1 BF0 VSS VCC2 VSS VCC2 PEN# INIT IGNNE# VSS VCC2 SMI# INTR R / S# NMI A21
Signal
A22 A23 VSS VCC3 A24 A25 A26 A27 VSS VCC3 A28 A29 A30 A31 VSS VCC3 VCC2 VSS A3 VSS VCC3 A4 A5 VSS VCC2 VCC3 A6 A7 VSS VCC3 A8 VCC2 VSS A9 VSS VCC3 A10 A11 VSS VCC2
Signal
VCC3 A12 VCC2 VSS A13 VSS VCC3 A14 VCC2 VSS A15 VSS VCC3 A16 A17 VSS VCC2 VCC3 A18 VCC2 VSS A19 VSS VCC3 A20 VCC2 VSS VCC2 VSS RESET NC CLK SCYC VSS VCC3 BE7# BE6# BE5# BE4# VSS
Signal
VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W / R# VSS VCC3 HIT# HITM# VSS VCC3 ADS# EADS# D / C# PWT PCD VCC3 VSS LOCK# VCC2 VSS VCC3 VSS AP VCC2 VSS HLDA BREQ VCC3 VSS APCHK# PCHK# VCC2 PRDY SMIACT# VSS
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active HIGH inputs should be connected to GND (VSS). No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Quick Pin Reference
This section gives a brief functional description of each of the pins. For a detailed description, see the
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
A31-A3
ADS# AHOLD
APCHK#
BE7#-BE5# BE4#-BE0# BF1:0
BP3:2 PM / BP1:0
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
BUSCHK#
CACHE#
D63-D0
DP7-DP0
EADS#
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
FERR#
FLUSH#
HITM#
IERR#
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
LOCK#
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
NMI PCD
PCHK#
PM / BP1:0
RESET
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 4. Quick Pin Reference (Contd.) Symbol SMI# Type I Name and Function The system management interrupt causes a system management interrupt request to be latched internally. When the latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode. An active system management interrupt active is operating in System Management Mode. output indicates that the processor
SMIACT# STPCLK#
TMS TRST# VCC2 VCC3 VSS W / R#
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 5. Bus Frequency Selections Pentium ® Processor Core Frequency (max) 150 MHz 133 MHz 120 MHz 100 MHz 90 MHz 75 MHz
NOTE: · Default setting
External Bus Frequency (max) 60 MHz 66 MHz 60 MHz 66 MHz 60 MHz 50 MHz
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Pin Reference Tables
Table 6. Output Pins Name Active Level Low Low Low High Low Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF#
ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO
NOTE: · All output and input / output pins are floated during tristate test mode (except TDO).
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 7. Input Pins Name A20M# AHOLD BF1:0 BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level Low High High Low Low Low n / a Low Low Low High Low High High High Low Low High Low n / a High Low Low n / a n / a n / a Low n / a Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous Synchronous Synchronous Pullup Pullup Bus State T2, T12, T2P BRDY# Pullup Internal resistor Qualified
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 8. Input / Output Pins Name A31-A3 AP BE4#-BE0# D63-D0 DP7-DP0 Active Level n / a n / a Low n / a n / a When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pulldown Internal Resistor
NOTES: · All output and input / output pins are floated during tristate test mode (except TDO). · BE3#-BE0# have pulldowns during RESET only.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Pin Grouping According to Function
Table 9 organizes the pins with respect to their function. Table 9. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating Point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Probe Mode CLK RESET, INIT, BF1:0 A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-2 STPCLK# R / S#, PRDY Pins
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
TCP PENTIUM ® PROCESSOR ELECTRICAL SPECIFICATIONS Maximum Ratings
WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor with voltage reduction technology contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. Case temperature under bias ...... -65°C to 110°C Storage temperature ............. -65°C to 150°C 3V Supply voltage with respect to VSS ............... -0.5V to +4.6V 2.9V Supply voltage with respect to VSS ............... -0.5V to +4.1V 3V Only Buffer DC Input Voltage .........................-0.5V to VCC3 (2) .......................... +0.5 not to exceed 4.6V 5V Safe Buffer DC Input Voltage..............-0.5V to 6.5V (1, 3)
NOTES: 1. Applies to CLK. 2. Applies to all Pentium processors with voltage reduction technology inputs except CLK. 3. See Table 11.
DC Specifications
Tables 10, 11 and 12 list the DC specifications which apply to the TCP Pentium processor with voltage reduction technology. The Pentium processor with voltage reduction technology core operates at 2.9V (3.1V for 150 MHz) internally while the I / O interface operates at 3.3V. The CLK input may be 3.3V or 5V. Since the 3.3V (5V safe) input levels defined in Table 11 are the same as the 5V TTL levels, the CLK input is compatible with existing 5V clock drivers. The power dissipation specification in Table 13 is provided for design of thermal solutions during operation in a sustained maximum level. This is the worst-case power the device would dissipate in a system for a sustained period of time. This number is used for design of a thermal solution for the device. 4.2.1. POWER SEQUENCING
There is no specific sequence required for powering up or powering down the VCC2 and VCC3 power supplies. However, for compatibility with future mobile processors, it is recommended that the VCC2 and VCC3 power supplies be either both on or both off within one second of each other.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Power Supply Current from 3.3V I / O buffer supply
NOTES: 1. Parameter measured at 4 mA. 2. Parameter measured at 3 mA. 3. 3.3V TTL levels apply to all signals except CLK. 4. This value should be used for power supply design. It was determined using a worst-case instruction mix and VCC+165mV. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from stop clock to full active modes. For more information, refer to section 4.3.2. 5. Refer to document 242973 for previous process specification.
Table 11. 3.3V (5V Safe) DC Specifications Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level (1) TTL Level (1)
NOTE: 1. Applies to CLK only.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
NOTES: 1. This parameter is for input without pull up or pull down. 2. This parameter is for input with pull up. 3. This parameter is for input with pull down. 4. Guaranteed by design.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Table 13. Power Dissipation Requirements for Thermal Design Parameter Thermal Design Power (7) Typical (1) Max (2) 4.4 5.9 7.1 7.9 10.0 1.7-2.3 2.0-3.0 2.5-3.5 3.0-4.0 3.8-5.0 N / A Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Notes @75 MHz (6) @100 MHz (6) @120 MHz (5) @133 MHz @150 MHz @75 MHz (6) @100 MHz (6) @120 MHz (5) @133 MHz @150 MHz @75 MHz (3) @100 MHz (3) @120 MHz (3) @133 MHz (3) @150 MHz (3) (4)
Active Power (8)
Stop Grant / Auto Halt Power
Stop Clock Power
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
AC Specifications
instruction, causing the processor to enter the Auto HALT Powerdown state, or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the processor. Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 µf range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the processor (on the 3.3V plane and the 2.9V (3.1V for 150 MHz) plane (or island)) to ensure that these supply voltages stay within specified limits during changes in the supply current during operation. For more detailed information, please contact Intel or refer to the Pentium® Processor with Voltage Reduction Technology: Power Supply Design Considerations for Mobile Systems application note (Order Number 242558). 4.3.3. CONNECTION SPECIFICATIONS
For clean on-chip power distribution, the TCP Pentium processor with voltage reduction technology has 37 VCC2 (2.9V power), 42 VCC3 (3.3V power) and 72 VSS (ground) inputs. Power and ground connections must be made to all external VCC2, VCC3 and VSS pins of the Pentium processor with voltage reduction technology. On the circuit board all VCC2 pins must be connected to a 2.9V VCC2 plane (or island) and all VCC3 pins must be connected to a 3.3V VCC3 plane. All VSS pins must be connected to a VSS plane. Please refer to Table 2 for the list of VCC2, VCC3 and VSS pins. 4.3.2. DECOUPLING RECOMMENDATIONS
Transient power surges can occur as the processor is executing instruction sequences or driving large loads. To mitigate these high frequency transients, liberal high frequency decoupling capacitors should be placed near the processor. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the processor and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the 3.3V plane and the 2.9V (3.1V for 150 MHz) plane (or island). Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. Power transients also occur as the processor rapidly transitions from a low level of power consumption to a much higher level (or high to low power). A typical example would be entering or exiting the Stop Grant state. Another example would be executing a HALT
All NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to ground. 4.3.4. AC TIMINGS FOR A 50-MHz BUS
The AC specifications given in Table 14 consist of output delays, input setup requirements and input hold requirements for a 50-MHz external bus. All AC specifications (with the exception of those for the TAP signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
t6b t6c t7
t8 t9a t10a t10b t11a t11b t12 t13
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
4.3.5. AC TIMINGS FOR A 60-MHz BUS signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation.
The AC specifications given in Table 15 consists of output delays, input setup requirements and input hold requirements for the 120-MHz Pentium processor. The AC specifications given in Table 16 consists of output delays, input setup requirements and input hold requirements for the 150-MHz Pentium processor. All AC specifications (with the exception of those for the TAP signals and APIC
Table 15. Mobile Pentium ® Processor 120 MHz AC Specifications for 60-MHz Bus Operation
Symbol Frequency t1a t1b t2 t3 t4 t5 t6a CLK Period
Parameter
Min 30.0 16.67
Unit MHz nS pS nS nS
Figure
Notes
3 (1), (19) 3 3 3 3 4 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (5) (0.8V-2.0V), (1), (5) (22)
CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time ADS#, PWT, PCD, BE0-7#, M / IO#, D / C#, CACHE#, SCYC, W / R# Valid Delay AP Valid Delay LOCK# Valid Delay A3-A31, Valid Delay ADS#, AP, A3-A31, PWT, PCD, BE0-7#, M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ, HLDA Valid Delay SMIACT# Valid Delay HIT# Valid Delay 1.0 1.0 1.0 1.0 1.0 4.0 4.0 0.15 0.15 1.0
t6b t6c t6e t7
t8a t8b t9a t9b t10a
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Table 15. Mobile Pentium ® Processor 120 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24 t25a t25b t26
Parameter HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time EADS#, INV, AP Hold Time KEN# Setup Time NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time
Min 1.1 1.0 1.0 1.3
Max 6.0 10.0 8.0 7.5 10.0
Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Notes
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Table 15. Mobile Pentium ® Processor 120 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42a t42b
Parameter A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, VCC & CLK Stable RESET Active After VCC & CLK Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async.
Min 1.0 5.0 1.0 2.0 5.0 1.0 2.0 3.0 1.5 5.0 1.0 15 1.0 5.0 1.0 2.0 2.0
Unit nS nS nS CLKs nS nS CLKs nS nS nS nS CLKs mS nS nS CLKs CLKs
Figure 6 6 6 (12)
Notes
6 6 7 7 7 7 7 7 7 7 (11), (15) (12) (16) Power up (11), (15), (16) (12) To RESET falling edge (15) To RESET falling edge (21) To RESET falling edge (21)
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Table 15. M obile Pentium ® Processor 120 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t42d
Parameter Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously BF1:0 Setup Time BF1:0 Hold Time BE4# Setup Time BE4# Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
Min 1.0
Unit nS
Figure
Notes To RESET falling edge (1), (21)
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS
(18) to RESET falling edge (18) to RESET falling edge To RESET falling edge To RESET falling edge
3 3 3 3 3 9 8 8 8 8 8 8 8 8 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8) (1), (8) (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
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Table 16. Mobile Pentium ® Processor 150 MHz AC Specifications for 60-MHz Bus Operation
Symbol Frequency t1a t1b t2 t3 t4 t5 t6a CLK Period
Parameter
Min 30.0 16.67
Unit MHz nS pS nS nS
Figure
Notes
3 (1), (19) 3 3 3 3 4 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (5) (0.8V-2.0V), (1), (5) (22)
CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time PWT, PCD, BE0-7#, D / C#, CACHE#, SCYC, W / R# Valid Delay AP Valid Delay LOCK# Valid Delay A3-A16 Valid Delay M / IO# Valid Delay ADS# Valid Delay A17-A31 Valid Delay ADS#, AP, A3-A31, PWT, PCD, BE0-7#, M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ, HLDA Valid Delay SMIACT# Valid Delay HIT# Valid Delay 0.85 1.0 1.0 1.0 1.0 4.0 4.0 0.15 0.15 0.8
t6b t6c t6e t6f t6g t6h t7
t8a t8b t9a t9b t10a
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Table 16. Mobile Pentium ® Processor 150 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24 t25a t25b t26
Parameter HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time EADS#, INV, AP Hold Time KEN# Setup Time NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time
Min 0.9 0.85 1.0 1.3
Max 6.0 10.0 8.0 7.5 10.0
Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Notes
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Table 16. Mobile Pentium ® Processor 150 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42a t42b
Parameter A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, VCC & CLK Stable RESET Active After VCC & CLK Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async.
Min 1.0 5.0 1.0 2.0 5.0 1.0 2.0 3.0 1.5 5.0 1.0 15 1.0 5.0 1.0 2.0 2.0
Unit nS nS nS CLKs nS nS CLKs nS nS nS nS CLKs mS nS nS CLKs CLKs
Figure 6 6 6 (12)
Notes
6 6 7 7 7 7 7 7 7 7 (11), (15) (12) (16) Power up (11), (15), (16) (12) To RESET falling edge (15) To RESET falling edge (21) To RESET falling edge (21)
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Table 16. M obile Pentium ® Processor 150 MHz AC Specifications for 60-MHz Bus Operation (Contd.)
Symbol t42d
Parameter Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously BF1:0 Setup Time BF1:0 Hold Time BE4# Setup Time BE4# Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
Min 1.0
Unit nS
Figure
Notes To RESET falling edge (1), (21)
t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
mS CLKs CLKs CLKs MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS
(18) to RESET falling edge (18) to RESET falling edge To RESET falling edge To RESET falling edge
3 3 3 3 3 9 8 8 8 8 8 8 8 8 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8) (1), (8) (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
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AC TIMINGS FOR A 66-MHz BUS
signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation.
The AC specifications given in Table 17 consist of output delays, input setup requirements and input hold requirements for the 66-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC Table 17. Mobile Pentium
Processor AC Specifications for 66-MHz Bus Operation
Symbol Frequency t1a t1b t2 t3 t4 t5 t6a t6b t6c t6d t6e t6f t7 CLK Period
Parameter
Min 33.33 15.0
Unit MHz nS pS nS nS
Figure
Notes
3 (1), (19) 3 3 3 3 4 4 4 4 4 4 5 (1) @2V, (1) @0.8V, (1) (2.0V-0.8V), (1) (0.8V-2.0V), (1)
CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time PWT, PCD, BE0-7#, D / C#, W / R#, CACHE#, SCYC Valid Delay AP Valid Delay LOCK# Valid Delay ADS# Valid Delay A3-A31 Valid Delay M / IO# Valid Delay ADS#, AP, A3-A31, PWT, PCD, BE0-7#, M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay 1.0 1.0 1.0 1.0 4.0 4.0 0.15 0.15 1.0 1.0 1.1 1.0 1.1 1.0
t8a t8b t9a t9b
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Table 17. Mobile Pentium
Processor AC Specifications for 66-MHz Bus Operation (Contd.)
Symbol t9c t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24a t24b t25a t25b t26 t27
Parameter HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, AP Setup Time EADS# Setup Time EADS#, INV, AP Hold Time KEN# Setup Time NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time
Min 1.0 1.0 1.1 1.0 1.0 1.3
Max 6.8 6.8 6.0 10.0 8.0 7.5 10.0
Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
Notes
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Table 17. Mobile Pentium
Processor AC Specifications for 66-MHz Bus Operation (Contd.)
Symbol t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42a t42b
Parameter INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, VCC & CLK Stable RESET Active After VCC & CLK Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Reset Configuration Signal BRDY# Hold Time, RESET driven synchronously
Min 5.0 1.0 2.0 5.0 1.0 2.0 2.8 1.5 5.0 1.0 15.0 1.0 5.0 1.0 2.0 2.0
Unit nS nS CLKs nS nS CLKs nS nS nS nS CLKs mS nS nS CLKs CLKs
Figure 6 6
Notes (11), (15), (16) (12) (14), (16)
6 6 7 7 7 7 7 7 7 7 (11), (15) (12) (16) Power up (11), (15), (16) (12) To RESET falling edge (15) To RESET falling edge (21) To RESET falling edge (21) To RESET falling edge (1), (21)
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Table 17. Mobile Pentium
Processor AC Specifications for 66-MHz Bus Operation (Contd.)
Symbol t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
Parameter BF1:0 Setup Time BF1:0 Hold Time BE4# Setup Time BE4# Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
Min 1.0 2.0 2.0 2.0 - 62.5 25.0 25.0
Unit mS CLKs CLKs CLKs
Notes (18) to RESET falling edge (18) to RESET falling edge To RESET falling edge To RESET falling edge
MHz nS nS nS 3 3 3 3 3 9 8 8 8 8 8 8 8 8 @2V, (1) @0.8V, (1) (2.0V-0.8V), (1), (8), (9) (0.8V-2.0V), (1), (8), (9) (1), Asynchronous (7) (7) (8) (1), (8) (3), (8), (10) (1), (3), (8), (10) (3), (7), (10) (3), (7), (10)
NOTES: ® Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium processor family. 1. Not 100 percent tested. Guaranteed by design. 2. TTL input test waveforms are assumed to be 0 to 3V transitions with 1V / nS rise and fall times. 3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to boundary scan operations. 4. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 5. 0.8V / ns CLK input rise / fall time 8V / ns. 6. 0.3V / ns input rise / fall time 5V / ns. 7. Referenced to TCK rising edge.
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8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. Referenced to TCK falling edge. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz. During probe mode operation, do not use the boundary scan timings (t55-58). Setup time is required to guarantee recognition on a specific clock. Hold time is required to guarantee recognition on a specific clock. All TTL timings are referenced from 1.5V. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. This input may be driven asynchronously. When driven asynchronously, RESET, NMI, FLUSH#, R / S#, INIT, and SMI# must be de-asserted (inactive) for a minimum of two clocks before being returned active. The D / C#, M / IO#, W / R#, CACHE#, and A5-A31 signals are sampled only on the CLK that ADS# is active. BF should be strapped to VCC3 or left floating. These signals are measured on the rising edge of adjacent CLKs at 1.5V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1 / 3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. Timing (t14) is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active). BUSCHK# is used as a reset configuration signal to select buffer size. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays.
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PP0051
Figure 3. Clock Waveform
PP0052
Figure 4. Valid Delay Timings
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PP0053
Figure 5. Float Delay Timings
PP0054
Figure 6. Setup and Hold Timings
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PP0055
Figure 7. Reset and Configuration Timings
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PP0056
Figure 8. Test Timings
PP0059
Figure 9. Test Reset Timings
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I / O Buffer Models
This section describes the I / O buffer models of the Pentium processor with voltage reduction technology. The first order I / O buffer model is a simplified representation of the complex input and output buffers used in the Pentium processor with voltage reduction technology. Figures 10 and 11 show the structure of the input buffer model and Figure 12 shows the output buffer model. Tables 18 and 19 show the parameters used to specify these models. Although simplified, these buffer models will accurately model flight time and signal quality. For these parameters, there is very little added accuracy in a complete transistor model. The following two models represent the input buffer models. The first model, Figure 10, represents all of
the input buffers except for a special group of input buffers. The second model, Figure 11, represents these special buffers. These buffers are the inputs: AHOLD, EADS#, KEN#, WB / WT#, INV, NA#, EWBE#, BOFF# and CLK. In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them. Note, however, some signal quality specifications require that the diodes be removed from the input model. The series resistors (Rs) are a part of the diode model. Remove these when removing the diodes from the input model.
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Note: VCC in Figure 10 refers to the I / O buffer VCC3.
PP0059
Figure 10. Input Buffer Model, Except Special Group
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PP0060
Figure 11. Input Buffer Model for Special Group
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Table 18. Parameters Used in the Specification of the First Order Input Buffer Model Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance Diode Series Resistance Ideal Diodes
Figure 12 shows the structure of the output buffer model. This model is used for all of the output buffers of the Pentium processor with voltage reduction technology.
PP0061
Figure 12. First Order Output Buffer Model
Table 19. Parameters Used in the Specification of the First Order Output Buffer Model Parameter dV / dt Ro Co Lp Cp Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model Minimum and maximum value of the output impedance of the output buffer model Minimum and Maximum value of the capacitance of the output buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance
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4.4.1. BUFFER MODEL PARAMETERS might not be met, or too much overshoot and ringback may occur. There are no other selection choices all of the configurable buffers get set to the same size at the same time. The input, output and bidirectional buffer values of the TCP Pentium processor with voltage reduction technology are listed in Table 22. This table contains listings for all three types, do not get them confused during simulation. When a bidirectional pin is operating as an input, use the Cin, Cp and Lp values if it is operating as a driver, use all of the data parameters. Please refer to Table 21 for the groupings of the buffers. Table 20. Buffer Selection Chart Environment Typical Stand Alone Component Loaded Component BRDY# 1 0 Buffer Selection EB2 EB2A
This section gives the parameters for each TCP Pentium processor with voltage reduction technology input, output and bidirectional signal, as well as the settings for the configurable buffers. Some pins on the TCP Pentium processor with voltage reduction technology have selectable buffer sizes. These pins use the configurable output buffer EB2. Table 20 shows the drive level for BRDY# required at the falling edge of RESET to select the buffer strength. The buffer sizes selected should be the appropriate size required otherwise AC timings
NOTES: For correct buffer selection, the BUSCHK# signal must be held inactive (high) at the falling edge of RESET.
Table 21. TCP Signal to Buffer Type Signals CLK A20M#, AHOLD, BF1:0, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, R / S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB / WT# APCHK#, BE7:5#, BP3:2, BREQ, FERR#, HLDA, IERR#, PCD, PCHK#, PM0 / BP0, PM1 / BP1, PRDY, PWT, SMIACT#, TDO, U / O# A31:21, AP, BE4:0#, CACHE#, D / C#, D63:0, DP8:0, LOCK#, M / IO#, SCYC A20:3, ADS#, HITM#, W / R# HIT# Type I I Driver Buffer Type Receiver Buffer Type ER0 ER1
EB1 EB2 / EB2A EB3
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Table 22. TCP Pentium Buffer Type Transition min ER0 (input) ER1 (input) ED1 (output) EB1 (bidir) EB2 (bidir) EB2A (bidir) EB3 (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 2.4 3 / 2.4 3 / 3.0 3 / 2.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.9 3.7 / 0.9 3.7 / 0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 9.0 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7
Processor Input, Output and Bidirectional Buffer Model Parameters Ro (Ohms) min max min 0.3 0.3 0.2 0.2 0.3 0.3 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Cp (pF) max 0.4 0.4 0.5 0.5 0.6 0.6 0.5 0.5 0.5 0.5 0.5 0.5 0.4 0.4 min 3.9 3.9 3.1 3.1 3.7 3.7 2.9 2.9 3.1 3.1 3.1 3.1 3.2 3.2 Lp (nH) max 5.0 5.0 6.0 6.0 6.6 6.6 6.1 6.1 6.4 6.4 6.4 6.4 4.1 4.1 min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 9.1 9.1 3.3 3.3 Co / Cin (pF) max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 9.7 9.7 3.9 3.9
dV / dt (V / nsec) max
Table 23. Input Buffer Model Parameters: D (Diodes) Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient D1 1.4e-14A 1.19 6.5 ohms 3 ns 0.983V 0.281 pF 0.385 D2 2.78e-16A 1.00 6.5 ohms 6 ns 0.967V 0.365 pF 0.376
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Signals driven by the system into the Pentium processor with voltage reduction technology must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: Ringback and Settling Time. 4.4.2.1. Ringback
Excessive ringback can contribute to long-term reliability degradation of the Pentium processor with voltage reduction technology, and can cause false signal detection. Ringback is simulated at the input pin of a component using the input buffer model. Ringback can be simulated with or without the diodes that are in the input buffer model. Ringback is the absolute value of the voltage at the receiving pin below VCC3 VSS) relative to VCC3 (or VSS) level after has reached its maximum voltage level. diodes are assumed present. maximum (or above the signal The input
PP0110
Figure 13. Overshoot / Undershoot and Ringback Guidelines
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
4.4.2.2. Settling Time Use the following procedure to verify board simulation and tuning with concerns for settling time. · · Simulate settling time at the slow corner for a particular signal. If settling time violations occur, simulate signal trace with D.C. diodes in place at the receiver pin. The D.C. diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. If settling time violations still occur, simulate flight times for five consecutive cycles for that particular signal. If flight time values are consistent over the five simulations, settling time should not be a concern. If however, flight times are not consistent over the five simulations, tuning of the layout is required. Note that, for signals that are allocated two cycles for flight time, the recommended settling time is doubled.
The settling time is defined as the time a signal requires at the receiver to settle within 10 percent of VCC3 or VSS. Settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, second-order effects and other effects serve to dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time may be simulated with the diodes included or excluded from the input buffer model. If diodes are included, settling time recommendation will be easier to meet. Although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts.
A typical design method would include a settling time that ensures a signal is within 10 percent of VCC3 or VSS for at least 2.5 ns prior to the end of the CLK period.
PP0111
Figure 14. Settling Time
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
TCP PENTIUM ® PROCESSOR MECHANICAL SPECIFICATIONS
body size of 24 mm and polyimide up for pick-andplace handling. TCP components are shipped with the leads flat in slide carriers, and are designed to be excised and lead formed at the customer manufacturing site. Recommendations for the manufacture of this package are included in Chapter 12 of the 1996 Packaging Data Book. Figure 15 shows a cross-sectional view of the TCP as mounted on the Printed Circuit Board. Figures 16 and 17 show the TCP as shipped in its slide carrier, and key dimensions of the carrier and package. Figure 18 shows a cross-section detail of the package. Figure 19 shows an enlarged view of the outer lead bond area of the package. Tables 24 and 25 provide the Pentium processor with voltage reduction technology TCP dimensions.
TCP Mechanical Diagrams
Encapsulant Gold Bump
Polyimide Support Ring
TAB Lead (OFC Copper)
Polyimide Keeper Bar
PCB PCB 1 / 2 X-Section Thermally & Electrically Conductive Adhesive (Silver Filled Thermoplastic) Note: Thermal vias Ground plane Sketches Not to Scale
PCB Full X-Section
Figure 15. Cross-Sectional View of the Mounted TCP
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Figure 16. One TCP Site in Carrier (Bottom Vie w of Die)
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Figure 17. One TCP Site in Carrier (Top View of Die)
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Figure 18. One TCP Site (Cross-Sectional Detail)
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
Figure 19. Outer Lead Bond (OLB) Window Detail
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NOTES: · Dimensions are in millimeters unless otherwise noted. · Dimensions in parentheses are for reference only.
Table 25. Mounted TCP Dimensions Description Package Height Terminal Dimension Package Weight 0.75 maximum 29.5 nominal 0.5 g maximum Dimension
NOTES: · Dimensions are in millimeters unless otherwise noted. · Package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY
TCP PENTIUM ® PROCESSOR THERMAL SPECIFICATIONS
The TCP Pentium processor with voltage reduction technology is specified for proper operation when the case temperature, TCASE, (TC) is within the specified range of 0 °C to 95 °C.
Measuring Thermal Values
P (maximum power consumption) is specified in section 4.2.
TCP Thermal Characteristics
Thermal Equations
The primary heat transfer path from the die of the TCP is through the back side of the die and into the PC board. There are two thermal paths traveling from the PC board to the ambient air. One is the spread of heat within the board and the dissipation of heat by the board to the ambient air. The other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. Solder-side heat sinking, compared to TCP component-side heat sinking, is the preferred method due to reduced risk of die damage, easier mechanical implementation and larger surface area for attachment. However, component-side heat sinking is possible. The design requirements in a component-side thermal solution are: no direct loading of inner lead bonds on the TCP, a maximum force of 4.5 kgf on the center of a clean TCP, no direct loading of the TAB tape or outer lead bonds and controlled board deflection.
where,
PC Board Enhancements
Copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the PC board to the ambient air. Tables 26 and 27 present thermal resistance data for copper plane thickness and via effects. It should be noted that although thicker copper planes will reduce the CA of a system without any thermal enhancements, they have less effect on the CA of a system with thermal enhancements. However, placing vias under the die will reduce the CA of a system with and without thermal enhancements.
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Figure 20. Technique for Measuring Case Temperature (T
Table 26. Thermal Resistance vs. Copper Plane Thickness with and without Enhancements Copper Plane Thickness 1 oz. Cu 3 oz. Cu
CA (°C / W) No Enhancements 18 14
CA (°C / W) With Heat Pipe 8 8
Table 27. Thermal Resistance vs. Thermal Vias underneath the Die Thermal Via Configuration No thermal vias 20 mil drill on 40 mil pitch CA (°C / W) No Enhancements 15 13
Table 28. Pentium ® Processor TCP Thermal Resistance without Enhancements JC (°C / W) Thermal Resistance without Enhancements 0.8 CA (°C / W) 13.9
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Heat sink with Fan @ 1.7 CFM Heat sink with Airflow @ 400 LFM Heat sink with Airflow @ 600 LFM
STANDARD TEST BOARD CONFIGURATION
All TCP thermal measurements provided in the tables were taken with the component soldered to a 2" x 2" test board outline. This six-layer board contains 13.5 mil drill on 40 mil pitch vias (underneath the die) in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. For the TCP Pentium processor with voltage reduction technology, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). The die is attached to the die attach pad using a thermally and electrically conductive adhesive. This test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board. NOTE Thermal resistance values should be used as guidelines only, and are highly system dependent. Final system verification should always refer to the case temperature specification.
SPGA PENTIUM ® PROCESSOR WITH VOLTAGE REDUCTION TECHNOLOGY SPECIFICATIONS SPGA Pentium ® Processor with Voltage Reduction Technology Differences from 3.3V Pentium Processor
All SPGA Pentium processor with voltage reduction technology specifications, except the differences described in this section, are identical to those of the 3.3V Pentium processor. 7.1.1. FEATURES REMOVED
The following features have been removed for the Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC and Master / Checker functional redundancy. Table 1 lists the corresponding pins which exist on the 3.3V Pentium processor but have been removed on the Pentium processor with voltage reduction technology.
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7.1.2. MAXIMUM RATING WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 7.1.3. DC SPECIFICATIONS
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the SPGA Pentium processor with voltage reduction technology contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields. Case temperature under bias ...... -65°C to 110°C Storage temperature ............. -65°C to 150°C 3V Supply voltage with respect to VSS ............... -0.5V to +4.6V 2.9V Supply voltage with respect to VSS ............... -0.5V to +4.1V 3V Only Buffer DC Input Voltage... ..-0.5V to VCC3 (2) .......................... +0.5 not to exceed 4.6V 5V Safe Buffer DC Input Voltage..............-0.5V to 6.5V (1, 3)
NOTES: 1. Applies to CLK. 2. Applies to all SPGA Pentium processor with voltage reduction technology inputs except CLK. 3. See Table 32.
Tables 31, 32 and 33 list the DC specifications which apply to the SPGA Pentium processor with voltage reduction technology. The SPGA Pentium processor with voltage reduction technology core operates at 2.9V (3.1V for 150 MHz) internally while the I / O interface operates at 3.3V. The CLK input may be at 3.3V or 5V. Since the 3.3V (5V safe) input levels defined in Table 32 are the same as the 5V TTL levels, the CLK input is compatible with existing 5V clock drivers. The power dissipation specification in Table 34 is provided for design of thermal solutions during operation in a sustained maximum level. This is the worst-case power the device would dissipate in a system for a sustained period of time. This number is used for design of a thermal solution for the device.
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Table 32. 3.3V (5V Safe) DC Specifications Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level (1) TTL Level (1)
NOTES : 1. Applies to CLK only.
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Table 33. In