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MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY ON 0.25 MICRON

Order Number: 243468-002

MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY ON 0.25 MICRON
Operating Frequency n n n n 166 MHz 200 MHz n 233 MHz 266 MHz Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions 0.25 Micron Process Technology 1.8 V core supply (166 / 200 / 233 MHz) 2.0 V core supply (266 MHz) 2.5 V I / O Interface (166 / 200 / 233 / 266 MHz ) Internal Error Detection Features On-Chip Local APIC Controller Power Management Features System Management Mode Clock Control Fractional Bus Operation 166-MHz Core / 66-MHz Bus 200-MHz Core / 66-MHz Bus 233-MHz Core / 66-MHz Bus 266-MHz Core / 66-MHz Bus
Support for MMX Technology Compatible with Large Software Base MS-DOS, Windows, OS / 2, UNIX 32-Bit CPU with 64-Bit Data Bus Superscalar Architecture Enhanced pipelines Two Pipelined Integer Units Capable of 2 Instructions / Clock Pipelined MMX Technology Pipelined Floating-Point Unit Separate Code and Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol 4-Mbyte Pages for Increased TLB Hit Rate 320-pin TCP or Mobile Module IEEE 1149.1 Boundary Scan
January 1998
Order Number: 243468-002
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
CONTENTS
PAGE 1.0. INTRODUCTION ...................... 4 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW .......................... 4 2.1. Mobile Pentium ® Processor Family Architecture ........................ 5 2.2. Mobile Pentium ® Processor with MMX Technology ......................... 7 2.2.1. Full support for Intel MMX technology ...................... 7 2.2.2. Doubled code and data caches to 16K each........................... 7 2.2.3. Improved branch prediction ......... 7 2.2.4. Enhanced pipeline ................ 8 2.3 0.25 Micron Technology.. .. .. .. .. .. .. .8 3.0. MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT .......... 8 3.1. Mobile Differences from Desktop ........ 8 3.2. TCP Pinout and Pin Descriptions ........ 9 3.2.1. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT ........... 9 3.2.2. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PIN CROSS REFERENCE ................... 10 3.3. Design Notes ...................... 17 3.4. Quick Pin Reference ................. 17 3.5. Bus Frequency ..................... 26 3.6. Pin Reference Tables ................ 27 PAGE 3.7. Pin Grouping According to Function ..... 30 4.0. ELECTRICAL SPECIFICATIONS ........ 31 4.1. Maximum Ratings ................... 31 4.2. DC Specifications ................... 31 4.2.1. POWER SEQUENCING ........... 31 4.3. AC Specifications ................... 34 4.3.1. POWER AND GROUND .......... 34 4.3.2. DECOUPLING RECOMMENDATION 34 4.3.3. CONNECTION SPECIFICATIONS ... 35 4.3.4. AC TIMINGS FOR A 66-MHZ BUS .. 35 4.4. I / O Buffer Models ................... 46 4.4.1. BUFFER MODEL PARAMETERS ... 49 4.4.2. SIGNAL QUALITY SPECIFICATION . 51 4.4.3. CLOCK SIGNAL MEASUREMENT METHODOLOGY ................ 55 5.0. MECHANICAL SPECIFICATIONS ........ 57 5.1. TCP Mechanical Diagrams ............ 58 6.0. THERMAL SPECIFICATIONS ........... 64 6.1. Measuring Thermal Values for TCP ..... 64 6.1.1. TCP Thermal Equations ........... 64 6.1.2. TCP Thermal Characteristics ....... 64 6.1.3. TCP PC Board Enhancements ...... 64 6.1.3.1. TCP STANDARD TEST BOARD CONFIGURATION ............... 65
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
2.0. 1.0. INTRODUCTION
MICROPROCESSOR ARCHITECTURE OVERVIEW
The mobile Pentium® processors with MMX technology on 0.25 micron are fully compatible with the existing mobile Pentium processors with MMX technology (120, 133, 150, & 166 MHz) with the following differences: voltage supplies, power consumption, and performance. These processors, when used in a TCP package, are socket compatible with the mobile Pentium processor (75, 90, 100, 120, 133, 150 MHz) making it possible to design a flexible motherboard that supports both the mobile Pentium processor (75 MHz - 150 MHz) and the mobile Pentium processor with MMX technology (120 MHz - 266 MHz). It has all the advanced features of the desktop version of the Pentium processor with MMX technology except for the differences listed in Section 3.1. The mobile Pentium processor with MMX technology on 0.25 micron has several features which allow high-performance notebooks to be designed, including the following: · · · TCP dimensions are ideal for small form-factor designs. TCP has superior thermal resistance characteristics. 1.8V (166 / 200 / 233 MHz) / 2.0V (266 MHz) core and 2.5V I / O buffer VCC inputs reduce power consumption significantly. The SL Enhanced feature set.
The mobile Pentium processor with MMX technology on 0.25 micron extends the mobile Pentium processor with MMX technology family. It is binary compatible with the 8086 / 88 , 80286 , Intel386 DX, Intel386 SX, Intel486 DX, Intel486 SX, Intel486 DX2, and mobile Pentium processors with voltage reduction technology (75150). The mobile Pentium processor family consists of the mobile Pentium processor with MMX technology (120, 133, 150, & 166), The mobile Pentium processor with MMX technology on 0.25 micron (166, 200, 233, & 266) and the mobile Pentium processor with voltage reduction technology (75 MHz -150 MHz). The mobile Pentium processor with MMX technology on 0.25 micron contains all of the features of previous Intel Architecture and provides significant enhancements and additions including the following: · · · · · · · · · · · · · · · · · · · Support for MMX Technology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 16K Code and 16K Data Caches Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Enhanced Bus Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions 0.25 Micron Process Technology SL Power Management Features Pool of four write buffers used by both pipes
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Mobile Pentium ® Processor Family Architecture
The application instruction set of the mobile Pentium processor family includes the complete Intel486 CPU family instruction set with extensions to accommodate some of the additional functionality of the Pentium processors. All application software written for the Intel386 and Intel486 family microprocessors will run on the Pentium processors without modification. The onchip memory management unit (MMU) is completely compatible with the Intel386 and Intel486 families of processors. The Pentium processors implement several enhancements to increase performance. The two instruction pipelines and floating-point unit on Pentium processors are capable of independent operation. Each pipeline issues frequently used instructions in a single clock. Together, the dual pipes can issue two integer instructions in one clock, or one floating-point instruction (under certain circumstances, two floating-point instructions) in one clock. Branch prediction is implemented in the Pentium processors. To support this, Pentium processors implement two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the Branch Target Buffer (BTB) so the needed code is almost always prefetched before it is needed for execution. The floating-point unit has been completely redesigned over the Intel486 processor. Faster algorithms provide up to 10X speed-up for common operations including add, multiply and load. Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache has a 32-byte line size and is 4-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be writeback or writethrough on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are also triple ported to support snooping and split line accesses. Individual pages can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
The separate code and data caches are shown, . The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache.
TLB Branch Prefetch Target Buffer Address
Code Cache 16 KBytes
Instruction
Pointer
Prefetch Buffers Instruction Decode
Control ROM
64-Bit Data Bus
Branch Verif. & Target Addr
Control Unit
V-Pipeline Connection
32-Bit Address Bus
Bus Unit
Page Unit
U-Pipeline Connection
FloatingPoint Unit Control Register File
Generate
(U Pipeline)
Address
Address Generate
(V Pipeline)
Control Integer Register File ALU ALU
(U Pipeline)
MMX Unit
Divide
(V Pipeline)
Multiply
Barrel Shifter
64-Bit Data Bus Data
32-Bit Addr. Bus
Control APIC
Data Cache 16 KBytes TLB
PP0115
Figure 1. Mobile Pentium ® Processor with MMX Technology Block Diagram
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
technology
MMX technology is based on SIMD technique (Single Instruction, Multiple Data) which enables increased performance on a wide variety of multimedia and communications applications. Fiftyseven new instructions and four new 64-bit data types are supported in the mobile Pentium processor with MMX technology. All existing operating system and application software are fullycompatible. 2.2.2. Doubled code / data caches to 16K each On-chip level-1 data and code cache sizes have been doubled to 16KB each and are 4-way set associative on the mobile Pentium processor with MMX technology. Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recentlyused instructions and data. The instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. The data cache supports a writeback (or alternatively, write-through, on a line by line basis) policy for memory updates. 2.2.3. Improved branch prediction Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved on the mobile Pentium processor with MMX technology to increase its accuracy. Further, this processor has four prefetch 7
Mobile Pentium ® Processor with MMX Technology
The mobile Pentium processor with MMX technology is a significant addition to the mobile Pentium processor family. Available at 120, 133, 150, 166, 200, 233, and 266 MHz, it is the first microprocessor to support Intel MMX technology.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY PINOUT Mobile Differences from Desktop
To better streamline the part for mobile applications, the following features have been eliminated: Upgrade, Dual Processing (DP), and Master / Checker functional redundancy. Table 1 lists the corresponding pins which exist on the desktop Pentium processor with MMX technology but have been removed on the mobile Pentium processor with MMX technology on 0.25 micron.
0.25 micron technology
The 0.25 micron technology is the latest state-ofthe-art CMOS manufacturing process Intel unveiled on April 12, 1997, which enables the use of lower core supply to sub-2V. As a result, the mobile Pentium processor with MMX technology on 0.25 Table 1. Signals Removed in Mobile Pentium Signal ADSC#
Processor with MMX Technology 200 / 233 MHz Function
Additional Address Status. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. Additional Burst Ready. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. CPU Type. This signal is used for dual processing systems. Dual / Primary processor identification. This signal is only used for an upgrade processor. Functional Redundancy Checking. This signal is only used for error detection via processor redundancy and requires two Pentium ® processors (master / checker). Private Bus Grant. This signal is only used for dual processing systems. Private Bus Request. This signal is used only for dual processing systems. Private Hit. This signal is only used for dual processing systems. Private Modified Hit. This signal is only used for dual processing systems.
BRDYC#
CPUTYP D / P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
TCP Pinout and Pin Descriptions
this section is not the actual text which will be marked on the packages). 3.2.1. MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY ON 0.25 MICRON TCP PINOUT
The text orientation on the top side view drawings in this section represent the orientation of the ink mark on the actual packages (Note that the text shown in
M / IO# VCC3 VSS BP3 VSS VCC2 BP2 PM1 / BP1 PM0 / BP0 FERR# VSS VCC2 IERR#
CACHE#
VCC2 VCC3 VSS HOLD WB / WT# VCC2 VSS NA# BOFF# BRDY# VCC2 VSS KEN# AHOLD INV EWBE# VCC2 VSS VCC3 VSS
VSS SMIACT# PRDY VCC2 PCHK# APCHK# VSS VCC3 BREQ HLDA VSS VCC2 AP VSS VCC3 VSS VCC2 LOCK# VSS VCC3 PCD PWT D / C# EADS# ADS# VCC3 VSS HITM# HIT# VCC3 VSS W / R# BUSCHK# FLUSH# A20M# BE0# BE1# BE2# BE3# VCC3 VSS BE4# BE5# BE6# BE7# VCC3 VSS SCYC CLK NC RESET VSS VCC2 VSS VCC2 A20 VCC3 VSS A19 VSS VCC2 A18 VCC3 VCC2 VSS A17 A16 VCC3 VSS A15 VSS VCC2 A14 VCC3 VSS A13 VSS VCC2 A12 VCC3
VSS DP7 D63 D62 D61 VCC2 VSS VCC3 VSS D60 D59 D58 D57
VSS VCC3 VSS D56 DP6 D55 D54 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VCC3 VSS
VCC2 VSS A11 A10 VCC3 VSS A9 VSS VCC2 A8 VCC3 VSS A7 A6 VCC3 VCC2 VSS A5 A4 VCC3 VSS
VSS VSS
VCC2 VCC3
A30 A29 A28 VCC3 VSS
D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 VCC3 VSS D28 D27 D26 D25 VCC3 VSS VCC2 VSS D24 DP2 D23 D22 VCC3 VSS D21 D20 D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS D7 D6 D5 D4 VCC3 VSS D3 D2 D1 D0 VCC2 VSS PICCLK PICD0 VCC2 PICD1 VSS VCC3
TCP Pinout
A25 A24
VCC3 VSS A23 A22 A21 NMI R / S# INTR SMI# VCC2 VSS IGNNE# INIT PEN#
VSS VCC2 VSS BF0 BF1 BF2 VCC2 VSS STPCLK# VCC2 VSS VCC3 VCC2 VSS NC VCC2 VSS VCC2 VSS VCC2 VSS VCC2
TRST#
VSS VCC2 TMS TDI TDO TCK
PP0116
Figure 2. TCP Mobile Pentium ® Processor with MMX Technology on 0.25 Micron Pinout
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
3.2.2. TCP MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY ON 0.25 MICRON PIN CROSS REFERENCE Table 2. TCP Pin Cross Reference by Pin Name Address A3 A4 A5 A6 A7 A8 219 222 223 227 228 231 A9 A10 A11 A12 A13 A14 234 237 238 242 245 248 A15 A16 A17 A18 A19 A20 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 152 151 150 149 146 145 144 143 139 138 137 134 133 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 132 131 128 126 125 122 121 120 119 116 115 113 108 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 APIC PICCLK PICD0 PICD1 155 156 158 107 106 105 102 101 100 96 95 94 93 90 89 88 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 87 83 82 81 78 77 76 75 72 70 69 64 63 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 62 61 56 55 53 48 47 46 45 40 39 38 251 254 255 259 262 265 A21 A22 A23 A24 A25 A26 200 201 202 205 206 207 A27 A28 A29 A30 A31 208 211 212 213 214
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# 286 296 14 308 315 285 284 283 282 279 278 277 276 9 28 25 10 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# HIT# 312 288 21 298 140 127 114 99 84 71 54 37 297 16 31 287 292 Clock Control BF0 BF1 BF2 CLK PICCLK STPCLK# 186 185 184 272 155 181 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# PEN# 293 311 4 34 193 192 197 15 13 303 22 8 199 300 316 191 PM0 / BP0 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# 30 29 318 299 198 270 273 196 319 161 163 162 164 167 289 5
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VCC21 1 6 11 17 27 33 41 49 57 65 111 153 157 165 168 170 172 174 177 180 VCC32 2 19 23 35 43 51 59 67 73 79 85 91 97 103 109 117 123 129 135 141 147 160 178 204 210 216 221 226 230 236 241 247 253 258 264 275 281 291 295 301 306 313 183 188 190 195 217 225 232 240 243 249 257 260 266 268 304 309 317
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 2. TCP Pin Cross Reference by Pin Name (Contd.) VSS 3 7 12 18 20 24 26 32 36 42 44 50 52 58 60 66 68 74 80 86 92 98 104 110 112 118 124 130 136 142 148 154 159 166 169 171 NC 175 184 271 173 176 179 182 187 189 194 203 209 215 218 220 224 229 233 235 239 244 246 250 252 256 261 263 267 269 274 280 290 294 302 305 307 310 314 320
NOTE: 1. These VCC2 pins are 1.8V (166 / 200 / 233 MHz) or 2.0V (266 MHz) inputs to the core, but may change to a different voltage on future offerings of this microprocessor family. 2. All V CC3 pins are 2.5V I / O power inputs.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-320) Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 14 Signal VCC2 VCC3 VSS HOLD WB / WT# VCC2 VSS NA# BOFF# BRDY# VCC2 VSS KEN# AHOLD INV EWBE# VCC2 VSS VCC3 VSS CACHE# M / IO# V CC3 VSS BP3 VSS VCC2 BP2 PM1 / BP1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Pin # Signal V CC2 VSS VCC3 VSS D60 D59 D58 D57 VCC2 VSS VCC3 VSS D56 DP6 D55 D54 VCC2 VSS VCC3 VSS D53 D52 D51 D50 VCC2 VSS VCC3 VSS D49 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Pin # Signal D42 D41 D40 DP4 VCC3 VSS D39 D38 D37 D36 VCC3 VSS D35 D34 D33 D32 VCC3 VSS DP3 D31 D30 D29 V CC3 VSS D28 D27 D26 D25 V CC3 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 Signal D19 D18 VCC3 VSS D17 D16 DP1 D15 VCC3 VSS D14 D13 D12 D11 VCC3 VSS D10 D9 D8 DP0 VCC3 VSS D7 D6 D5 D4 V CC3 VSS D3
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-320) Pin # 30 31 32 33 34 35 36 37 38 39 40 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 Signal PM0 / BP0 FERR# VSS VCC2 IERR# VCC3 VSS DP7 D63 D62 D61 TCK TDO TDI TMS VCC2 VSS TRST# VCC2 VSS V CC2 VSS V CC2 VSS V CC2 NC VSS V CC2 VCC3 VSS 70 71 72 73 74 75 76 77 78 79 80 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Pin # Signal D48 DP5 D47 VCC3 VSS D46 D45 D44 D43 VCC3 VSS A22 A23 VSS V CC3 A24 A25 A26 A27 VSS VCC3 A28 A29 A30 A31 VSS V CC3 V CC2 VSS A3 Pin # 110 111 112 113 114 115 116 117 118 119 120 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 Signal VSS VCC2 VSS D24 DP2 D23 D22 VCC3 VSS D21 D20 V CC3 A12 VCC2 VSS A13 VSS VCC3 A14 VCC2 VSS A15 VSS V CC3 A16 A17 VSS V CC2 V CC3 A18 Pin # 150 151 152 153 154 155 156 157 158 159 160 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 Signal D2 D1 D0 VCC2 VSS PICCLK PICD0 VCC2 PICD1 VSS VCC3 VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W / R# VSS V CC3 HIT# HITM# VSS V CC3 ADS# EADS# D / C# PWT 15
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 3. TCP Pin Cross References by Pin Number (Pins 1-320) Pin # 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Signal V CC2 STPCLK# VSS VCC2 BF2 BF1 BF0 VSS V CC2 VSS V CC2 PEN# INIT IGNNE# VSS V CC2 SMI# Pin # 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 Signal VSS VCC3 A4 A5 VSS V CC2 V CC3 A6 A7 VSS V CC3 A8 V CC2 VSS A9 VSS V CC3 A10 A11 VSS V CC2 Pin # 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Signal V CC2 VSS A19 VSS V CC3 A20 V CC2 VSS V CC2 VSS RESET NC CLK SCYC VSS V CC3 BE7# BE6# BE5# BE4# VSS Pin # 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Signal PCD V CC3 VSS LOCK# V CC2 VSS V CC3 VSS AP V CC2 VSS HLDA BREQ V CC3 VSS APCHK# PCHK# V CC2 PRDY SMIACT# VSS
INTR / LINT0 237 R / S# NMI / LINT1 A21 238 239 240
NOTE: 1. VCC2 pins are 1.8V (166 / 200 / 233 MHz) or 2.0V (266 MHz) inputs to the core. 2. VCC3 pins are 2.5V inputs to the I / O.
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active HIGH inputs should be connected to GND (VSS). No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Quick Pin Reference
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
A31-A3
ADS# AHOLD
APCHK#
BE7#-BE5# BE4#-BE0# BF2:0
APICEN PICD1
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
BRDY#
BUSCHK#
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
DP7-DP0
EADS# EWBE#
FERR#
FLUSH#
HITM#
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
IERR#
IGNNE#
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Table 4. Quick Pin Reference (Contd.) Symbol LOCK# Type O Name and Function The bus lock pin indicates that the current bus cycle is locked. The processor will not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is guaranteed to be de-asserted for at least one clock between back-to-back locked cycles. The memory / input-output is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. M / IO# distinguishes between memory and I / O cycles. An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. The processor will issue ADS# for a pending cycle two clocks after NA# is asserted. The processor supports up to two outstanding bus cycles. The non-maskable interrupt request signal indicates that an external nonmaskable interrupt has been generated. The page cache disable pin reflects the state of the PCD bit in CR3 Page Directory Entry or Page Table Entry. The purpose of PCD is to provide an external cacheability indication on a page-by-page basis.
NMI PCD
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
PCHK#
The parity check output indicates the result of a parity check on a data read. It is driven with parity status two clocks after BRDY# is returned. PCHK# remains low one clock for each clock in which a parity error was detected. Parity is checked only for the bytes on which valid data is returned. The parity enable input (along with CR4.MCE) determines whether a machine check exception will be taken as a result of a data parity error on a read cycle. If this pin is sampled active in the clock, a data parity error is detected. The processor will latch the address and control signals of the cycle with the parity error in the machine check registers. If, in addition, the machine check enable bit in CR4 is set to "1", the processor will vector to the machine check exception before the beginning of the next instruction. The APIC interrupt controller serial data bus clock is driven into the programmable interrupt controller clock input of the Pentium ® processor with MMX technology. Programmable interrupt controller data lines 0-1 of the Pentium® processor with MMX technology comprise the data portion of the APIC 3-wire bus. They are open-drain outputs that require external pull-up resistor. These signals are multiplexed with APICEN. These pins function as part of the performance monitoring feature. The breakpoint 1-0 pins are multiplexed with the performance monitoring 1 -0 pins. The PB1 and PB0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins. The pins come out of RESET configured for performance monitoring.
PICCLK
PICD0-1 APICEN
PM / BP1:0
PRDY PWT
The probe ready output pin indicates that the processor has stopped normal execution in response to the R / S# pin going active or Probe Mode being entered. The page writethrough pin reflects the state of the PWT bit in CR3, the page directory entry, or the page table entry. The PWT pin is used to provide an external writeback indication on a page-by-page basis.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
RESET
SMIACT# STPCLK#
TMS TRST# VCC2
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Table 4. Quick Pin Reference (Contd.) Symbol VCC3 VSS W / R# Type I I O Name and Function These pins are the 2.5V power inputs to the I / O. These pins are the ground inputs. Write / read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W / R# distinguishes between write and read cycles. The writeback / writethrough input allows a data cache line to be defined as writeback or writethrough on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
MOBILE PENTIUM ® PROCESSOR WITH MMX TECHNOLOGY
Bus Frequency
Core and bus frequencies can be set according to Table 5 below. Each mobile Pentium processor with MMX technology is specified to operate within
a single bus-to-core ratio. Operation in other busto-core ratios or outside the specified operating frequency range is not supported.
Table 5. Bus Frequency Selections (1) BF2 0 0 0 1 BF1 0 0 1 0 BF0 0 1 1 0 Bus / Core Ratio 2 / 5 1 / 3 2 / 7 1 / 4 Max Bus / Core Frequency (MHz) 66 / 166 66 / 200 66 / 233 66 / 266
NOTES: 1. Each processor must be externally configured with the BF0-2 pins to operate in the specified bus fraction mode. Operation out of the specification is not supported.
MOBILE PENTIUM® PROCESSOR WITH MMX TECHNOLOGY
Pin Reference Tables
Table 6. Output Pins 1 Name Active Level Low Low Low High Low Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF#
ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM# 2 HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO
NOTE: 1. All output and input / output pins are floated during tristate test mode (except TDO). 2. HITM# pin has an internal pull-up resistor.
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Table 7. Input Pins Name A20M# AHOLD BF0 BF1 BF2 BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# PICCLK R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# 28 Active Level LOW HIGH HIGH HIGH HIGH LOW LOW LOW n / a LOW LOW LOW HIGH LOW HIGH HIGH HIGH LOW LOW HIGH LOW HIGH n / a HIGH LOW LOW n / a n / a n / a LOW Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup TCK TCK Pullup Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous / RESET Synchronous / RESET Synchronous Synchronous Synchronous Pullup Pullup Bus State T2, T12, T2P BRDY# Pulldown Pullup Pulldown Internal resistor Qualified
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Synchronous
First BRDY# / NA#
Table 8. Input / Output Pins 1 Name A31-A3 AP BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1APICEN Active Level n / a n / a Low n / a n / a n / a n / a When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown 2 Internal Resistor
NOTES: 1. All output and input / output pins are floated during tristate test mode (except TDO). 2. BE3#-BE0# have pulldowns during RESET only.
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Pin Grouping According to Function
Table 9 organizes the pins with respect to their function. Table 9. Pin Functional Grouping Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating-point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Debugging CLK RESET, INIT, BF2:0 A31-A3, BE7# - BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-2 STPCLK# R / S#, PRDY Pins
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
WARNING Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the mobile Pentium processor with MMX technology contains protective circuitry to resist damage from Electrostatic Discharge (ESD), always take precautions to avoid high static voltages or electric fields. Case temperature under bias ..... -65° to 110° C C Storage temperature............ -65° to 150° C C VCC3 Supply voltage with respect to V SS ............. -0.5V to +3.2V VCC2 Supply voltage with respect to V SS ............. -0.5V to +2.8V 2.5V Only Buffer DC Input Voltage .................. -0.5V to V CC3+0.5V not to exceed V
DC Specifications
Tables 10, 11, 12 and 13 list the DC specifications which apply to the mobile Pentium processor with MMX technology on 0.25 Micron. The processor core operates at 1.8V (166 / 200 / 233 MHz) or 2.0V (266 MHz) internally while the I / O interface operates at 2.5V. 4.2.1. POWER SEQUENCING
There is no specific sequence required for powering up or powering down the VCC2 and VCC3 power supplies. However, for compatibility with future mobile processors, it is recommended that the VCC2 and VCC3 power supplies be either both ON or both OFF within one second of each other.
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Table 11. DC Specifications 1 Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage V CC3 - 0.4 V CC3 - 0.2
Min -0.3 VCC3 - 0.7
Max 0.5 VCC3 + 0.3 0.4
Notes
TTL Level TTL Level 1 TTL Level 2 TTL Level 3
Table 12. ICC Specifications Symbol ICC2 Parameter Power Supply Current Min Max 2.35 2.70 3.10 4.00 0.33 0.33 0.38 0.38 Unit A A A A A A A A Notes 166 MHz 1 200 MHz 1 233 MHz 1 266 MHz 1 166 MHz 1 200 MHz 1 233 MHz 1 266 MHz 1
Power Supply Current
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Table 13. Power Dissipation Requirements for Thermal Design Parameter Thermal Design Power Typical 1 Max2 4.1 5.0 5.5 7.6 2.3 2.7 3.0 4.5 0.42 0.46 0.53 0.70 0.02 0.02 0.02 0.05 0.05 0.05 0.06 Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Frequency 166 MHz 200 MHz 233 MHz 266 MHz 166 MHz 200 MHz 233 MHz 266 MHz 166 MHz 200 MHz 233 MHz 266 MHz 166 MHz 200 MHz 233 MHz 266 MHz Notes
Active Power 5
Stop Grant / Auto Halt Powerdown Power Dissipation 3
Stop Clock Power 4
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NOTES: 1. This parameter is for inputs / outputs without an internal pull up or pull down. 2. This parameter is for inputs with an internal pull up. 3. This parameter is for inputs with an internal pull down. 4. Guaranteed by design. 5. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
AC Specifications
DECOUPLING RECOMMENDATIONS
The AC specifications of the mobile Pentium processor with MMX technology on 0.25 Micron consist of setup times, hold times, and valid delays at 0 pF. 4.3.1. POWER AND GROUND
For clean on-chip power distribution, the TCP has 37 VCC2 (core power), 42 VCC3 (I / O power) and 72 VSS (ground) inputs. Power and ground connections must be made to all external VCC2, VCC3 and VSS pins. On the circuit board all VCC2 pins must be connected to a 1.8V (166 / 200 / 233 MHz) or 2.0V (266 MHz) VCC2 plane (or island) and all VCC3 pins must be connected to a 2.5V VCC3 plane. All VSS pins must be connected to a VSS plane. Please refer to Table 2 for the list of VCC2, VCC3 and VSS pins.
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Powerdown state, or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the processor. 4.3.3. CONNECTION SPECIFICATIONS
All NC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to ground. 4.3.4. AC TIMINGS FOR A 66-MHZ BUS
Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 µ range are f required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the processor on both VCC2 plane and VCC3 plane to ensure that the supply voltages stay within specified limits during changes in the supply current during operation. For more detailed information, please contact Intel or refer to the Mobile Pentium® Processor with MMX Technology: Power Supply Design Considerations application note (Order Number 243306).
The AC specifications given in Table 15 consist of output delays, input setup requirements and input hold requirements for the mobile standard 66 MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to VCC3 / 2 for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, asynchronous inputs must be stable for correct operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. Do not select a bus fraction and clock speed which will cause the processor to exceed its internal maximum frequency.
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CLK Frequency
Min 33.33 15.0
Unit MHz nS pS nS nS
Notes
t1a t1b t2 t3 t4 t5 t6a t6b t6c t6d t6e t6f t6g t7
CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time PWT, PCD, CACHE# Valid Delay AP Valid Delay LOCK# Valid Delay ADS# Valid Delay A3-A31 Valid Delay M / IO# Valid Delay BE0-7#, D / C#, W / R#, SCYC Valid Delay ADS#, AP, A3-A31, PWT, PCD, BE0-7#, M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay
@ VCC3 - 0.7V, (1) @ 0.5V, (1) (VCC3 - 0.7V to 0.5V), (1, 5) (0.5V to V CC3 - 0.7V), (1, 5)
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t50 t51 t52 t53 t54 t55 t56 t57 t58
TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time
CLKs nS nS nS nS nS nS nS nS
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Table 16. Mobile Pentium® Processor with MMX Technology on 0.25 Micron APIC AC Specifications Symbol t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j t61 t62 t63 Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (L to H) PICD0-1 High Time (H to L) PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK / PICCLK) Min 2.0 60 15 15 0.15 0.15 3 2.5 4 4 5.0 2.0 4 38 22 2.5 2.5 Max 16.66 500 Unit MHz nS nS nS nS nS nS nS nS nS nS nS 3 3 3 3 3 6 6 4 4 6 6 To PICCLK To PICCLK From PICCLK, 21 From PICCLK, 21 To CLK To CLK 22 Figure Notes
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PP0051
Figure 3. Clock Waveform
Tx max.
S ignal Vcc3 / 2 VALID
PP0052
Figure 4. Valid Delay Timings
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Tx Ty Signal
Figure 5. Float Delay Timings
Vcc3 / 2 CLK Tx Ty
Signal
VALID
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CLK Tz RESET
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TDI TMS
TDO Ty Output Signals
Input Signals
Figure 8. Test Timings
TRST#
Figure 9. Test Reset Timings
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I / O Buffer Models
This section describes the I / O buffer models of the mobile Pentium processor with MMX technology on 0.25 Micron. The first order I / O buffer model is a simplified representation of the complex input and output buffers used. Figure 10 shows the structure of the input buffer model and Figure 11 shows the output buffer model. Tables 17 and 18 show the parameters used to specify these models. Although simplified, these buffer models will accurately model flight time and signal quality. For these parameters, there is very little added accuracy in a complete transistor model. In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them. Note, however, some signal quality specifications require that the diodes be removed from the input model. The series resistors (RS) are a part of the diode model. Remove these when removing the diodes from the input model.
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Figure 10. First Order Input Buffer Model
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Table 17. Parameters Used in the Specification of the First Order Input Buffer Model Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance Diode Series Resistance Ideal Diodes
PP0061
Figure 11. First Order Output Buffer Model
Table 18. Parameters Used in the Specification of the First Order Output Buffer Model Parameter dV / dt RO CO LP CP Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model Minimum and maximum value of the output impedance of the output buffer model Minimum and Maximum value of the capacitance of the output buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance
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BUFFER MODEL PARAMETERS
This section gives the parameters for each input, output and bidirectional buffers. The input, output and bidirectional buffer values of the processor are listed in Table 20. These tables contain listings for all three types, do not get them confused during simulation. When a bidirectional pin is operating as an input, use the CIN, CP and LP
Table 19. TCP Signal to Buffer Type Signals A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R / S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB / WT# APCHK#, BE7:5#, BP3:2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0 / BP0, PM1 / BP1, PRDY, PWT, SMIACT#, TDO A31: 3, AP, BE4:0#, CACHE#, D / C#, D63:0, DP8:0, HLDA, LOCK#, M / IO#, SCYC, ADS#, HITM#, HIT#, W / R#, PICD0, PICD1 Type I Driver Buffer Type Receiver Buffer Type ER1
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Table 20. Input, Output and Bi-directional Buffer Model Parameters for TCP Buffer Type Transition dV / dt (V / nsec) Min ER1 (input) ED1 Rising Falling Rising 2.2 / 2.2 2.2 / 2.9 2.2 / 2.2 2.2 / 2.9 2.7 / 0.15 29 2.7 / 0.22 25 2.7 / 0.15 29 2.7 / 0.22 25 65 75 65 75 Max RO (Ohms) Min Max CP (pF) Min 0.2 0.2 0.2 0.2 0.2 0.2 Max 0.4 0.4 0.5 0.5 0.4 0.4 Min 6.4 6.4 5.4 5.4 5.2 5.2 LP (nH) Max 11.3 11.3 11.7 11.7 10.3 10.3 CO / CIN (pF) Min 0.8 0.8 2.0 2.0 2.0 2.0 Max 1.2 1.2 2.6 2.6 2.6 2.6
(output) Falling EB1 (bidir) Rising Falling
Table 21. Input Buffer Model Parameters: D (Diodes) Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient D1 1.4e-14A 1.19 6.5 ohms 3 ns 0.983V 0.281 pF 0.385 D2 2.78e-16A 1.00 6.5 ohms 6 ns 0.967V 0.365 pF 0.376
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Signals driven by the system into the mobile Pentium processor with MMX technology on 0.25 Micron must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: Ringback and Settling Time. See Section 4.4.2.3 for CLK signal quality specification. 4.4.2.1. Ringback
Excessive ringback can contribute to long-term reliability degradation of the processor, and can cause false signal detection. Ringback is simulated at the input pin of a component using the input buffer model. Ringback can be simulated with or without the diodes that are in the input buffer model. Ringback is the absolute value of the maximum voltage at the receiving pin below VCC3 (or above
Figure 12. Overshoot / Undershoot and Ringback Guidelines
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Settling Time
The settling time is defined as the time a signal requires at the receiver to settle within 10 percent of VCC3 or VSS. Settling time is the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, second-order effects and other effects serve to dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time may be simulated with the diodes included or excluded from the input buffer model. If diodes are included, settling time recommendation will be easier to meet. Although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts.
Figure 13. Settling Time 52
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UNDERSHOOT THRESHOLD DURATION SPECIFICATION: The undershoot threshold duration is defined as the sum of all time during which the CLK signal is below -0.3V within a single clock period. The undershoot threshold duration must not exceed 20 percent of the period. MAXIMUM RINGBACK SPECIFICATION: The maximum ringback of CLK associated with their high states (overshoot) must not drop below VCC3 0.7V as shown in Figure 15. Similarly, the maximum ringback of CLK associated with their low states (undershoot) must not exceed 0.5V as shown in Figure 17. Refer to Table 22 and Table 23 for a summary of the clock overshoot and undershoot specifications for the 200- and 233 MHz Pentium processor with MMX technology.
Signal Quality Specification
The maximum overshoot, maximum undershoot, overshoot threshold duration, undershoot threshold duration, and maximum ringback specifications for CLK are described below: MAXIMUM OVERSHOOT AND MAXIMUM UNDERSHOOT SPECIFICATION: The maximum overshoot of the CLK signals should not exceed VCC3, nominal + 0.6V. The maximum undershoot of the CLK signals must not drop below -0.6V. OVERSHOOT THRESHOLD DURATION SPECIFICATION: The overshoot threshold duration is defined as the sum of all time during which the CLK signal is above VCC3, nominal + 0.3V within a single clock period. The overshoot threshold duration must not exceed 20 percent of the period.
NOTES: 1. VCC3, nominal refers to the voltage measured at the bottom side of the V CC3 pins. See Section 4.3.1. for details. 2. See Figures 14 and 15.
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Maximum Ringback
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4.4.3. CLOCK SIGNAL MEASUREMENT METHODOLOGY: The waveform of the clock signals should be measured at the bottom side of the processor pins using an oscilloscope with a 3 dB bandwidth of at least 20 MHz (100 MS / s digital sampling rate). There should be a short isolation ground lead attached to a processor pin on the bottom side of the board. An 1 MOhm probe with loading of less than 1 pF (e.g., Tektronics 6243 or Tektronics 6245) is recommended. The measurement should be taken at the CLK (AK18) pin and its nearest V SS pin (AM18). MAXIMUM OVERSHOOT, MAXIMUM UNDERSHOOT AND MAXIMUM RINGBACK SPECIFICATIONS: The display should show continuous sampling (e.g., infinite persistence) of the waveform at 500 mV / div and 5 nS / div for a recommended duration of approximately five seconds. Adjust the vertical position to measure the maximum overshoot and associated ringback with the largest possible granularity. Similarly, readjust the vertical position to measure the maximum undershoot and associated ringback. There is no allowance for crossing the maximum overshoot, maximum undershoot or maximum ringback specifications. OVERSHOOT THRESHOLD DURATION SPECIFICATION: A snapshot of the clock signal should be taken at 500 mV / div and 500 pS / div. Adjust the vertical position and horizontal offset position to view the threshold duration. The overshoot threshold duration is defined as the sum of all time during which the clock signal is above VCC3, nominal + 0.3V within a single clock period. The overshoot threshold duration must not exceed 20 percent of the period. UNDERSHOOT THRESHOLD DURATION SPECIFICATION: A snapshot of the clock signal should be taken at 500 mV / div and 500 pS / div. Adjust the vertical position and horizontal offset position to view the threshold duration. The undershoot threshold duration is defined as the sum of all time during which the clock signal is below 0.3V within a single clock period. The undershoot threshold duration must not exceed 20 percent of the period. These overshoot and undershoot specifications are illustrated graphically in Figures 14 through 17.
Maximum Overshoot Level Overshoot Threshold Level VCC3, nominal
Overshoot Threshold Duration
Figure 14. Maximum Overshoot Level, Overshoot Threshold Level, and Overshoot Threshold Duration 55
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VCC3, nominal Maximum Ringback
Figure 15. Maximum Ringback Associated with the Signal High State
Undershoot Threshold Duration
VSS, nominal Undershoot Threshold Level Maximum Undershoot Level
Figure 16. Maximum Undershoot Level, Undershoot Threshold Level, and Undershoot Threshold Duration
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Maximum Ringback VSS, nominal
Figure 17. Maximum Ringback Associated with the Signal Low State
MECHANICAL SPECIFICATIONS
be excised and lead formed at the customer manufacturing site. Recommendations for the manufacture of this package are included in the 1996 Packaging Databook (Order Number 240800) or at www.intel.lv / design / packtech / chap12.pdf. Figure 18 shows a cross-section view of the TCP as mounted on the Printed Circuit Board. Figures 19 and 20 show the TCP as shipped in its slide carrier, and key dimensions of the carrier and package. Figure 21 shows a cross-section detail of the package. Figure 22 shows an enlarged view of the outer lead bond area of the package.
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TCP Mechanical Diagrams
Encapsulant Gold Bump
Polyimide Support Ring
Polyimide TAB Lead Keeper (OFC Copper) Bar
PCB PCB 1 / 2 Cross-Section Thermally Conductive Adhesive Note: Thermal vias Ground plane Sketches Not to Scale
PCB Full Cross-Section
Figure 18. Cross-Sectional View of the Mounted TCP
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Figure 19. One TCP Site in Carrier (Bottom View of Die)
Figure 20. One TCP Site in Carrier (Top View of Die)
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Figure 21. One TCP Site (Cross-Sectional Detail)
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Figure 22. Outer Lead Bond (OLB) Window Detail
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NOTES: · Dimensions are in millimeters unless otherwise noted. · Dimensions in parentheses are for reference only.
Table 25. Mounted TCP Dimensions Symbol A D, E WT Description Package Height Terminal Dimension Package Weight Dimension 0.75 maximum 29.5 nominal 0.5 g maximum
NOTE: · Dimensions are in millimeters unless otherwise noted. · Package terminal dimension (lead tip-to-lead tip) assumes the use of a keeper bar.
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where,
THERMAL SPECIFICATIONS
The mobile Pentium processor with MMX technology on 0.25 Micron is specified for proper operation when the case temperature, TCASE (TC), for TCP is within the specified range of 0 ° to 95 C ° C.
Measuring Thermal Values for TCP
P (maximum power consumption) is specified in Section 3.1. 6.1.2. TCP Thermal Characteristics
The primary heat transfer path from the die of the TCP is through the back side of the die and into the PC board. There are two thermal paths traveling from the PC board to the ambient air. One is the spread of heat within the board and the dissipation of heat by the board to the ambient air. The other is the transfer of heat through the board and to the opposite side where thermal enhancements (e.g., heat sinks, pipes) are attached. Solder-side heat sinking, compared to TCP component-side heat sinking, is the preferred method due to reduced risk of die damage, easier mechanical implementation and larger surface area for attachment. However, component-side heat sinking is possible. The design requirements in a component-side thermal solution are: no direct loading of inner lead bonds on the TCP, a maximum force of 4.5 kgf on the center of a clean TCP, no direct loading of the TAB tape or outer lead bonds and controlled board deflection. 6.1.3. TCP PC Board Enhancements
For the TCP mobile Pentium processor with MMX technology, an ambient temperature (TA) is not specified directly. The only requirement is that the case temperature (TC) is met. The ambient temperature can be calculated from the following equations:
Copper planes, thermal pads, and vias are design options that can be used to improve heat transfer from the PC board to the ambient air. Tables 26 and 27 present thermal resistance data for copper plane thickness and via effects. It should be noted that although thicker copper planes will reduce the ca of a system without any thermal enhancements, they have less effect on the ca of a system with thermal enhancements. However, placing vias under the die will reduce the ca of a system with and without thermal enhancements.
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Figure 23. Technique for Measuring Case Temperature (T C) on TCP Table 26. TCP Thermal Resistance vs. Copper Plane Thickness With and Without Enhancements Copper Plane Thickness 1 oz. Cu 3 oz. Cu
NOTE: 225 vias underneath the die
CA (° C / Watt) No Enhancements 18 14
CA (° C / Watt) With Heat Pipe and Al Plates 7.8 7.8
Table 27. TCP Thermal Resistance vs. Thermal Vias Underneath the Die Number of Vias Under the Die 0 144
NOTE: 3 oz. copper planes in tet boards
CA (° C / Watt) No Enhancements 15 13
TCP STANDARD TEST BOARD CONFIGURATION
All Tape Carrier Package (TCP) thermal measurements familiarity provided in the following tables were taken with the component soldered to a 2" x 2" test board outline. This six-layer board contains 225 vias in the die attach pad which are connected to two 3 oz. copper planes located at layers two and five. For the TCP, the vias in the die attach pad should be connected without thermal reliefs to the ground plane(s). The die is attached to the die
attach pad using a thermally conductive adhesive. This test board was designed to optimize the heat spreading into the board and the heat transfer through to the opposite side of the board. NOTE Thermal resistance values should be used as guidelines only, and are highly system dependent. Final system verification should always refer to the case temperature specification.
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Table 28. TCP Thermal Resistance without Enhancements JC (° C / Watt) Thermal Resistance without Enhancements 0.8 CA (° C / Watt) 14
Table 30. TCP Thermal Resistance with Enhancements (With Airflow) Thermal Enhancements Heat sink with Fan @ 1.7 CFM Heat sink with Airflow @ 400 LFM Heat sink with Airflow @ 600 LFM
CA (° C / W) 5.0 5.1 4.3
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