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MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY 0.25 MICRON
Operating Frequency Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions 0.25 Micron Process Technology core supply (166/200/233 MHz) core supply (266 MHz) Interface (166/200/233/266 Internal Error Detection Features On-Chip Local APIC Controller Power Management Features System Management Mode Clock Control Fractional Operation 166-MHz Core/66-MHz 200-MHz Core/66-MHz 233-MHz Core/66-MHz 266-MHz Core/66-MHz
Support MMXTechnology Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit with 64-Bit Data Superscalar Architecture Enhanced pipelines Pipelined Integer Units Capable Instructions/Clock Pipelined Technology Pipelined Floating-Point Unit Separate Code Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol 4-Mbyte Pages Increased Rate 320-pin Mobile Module IEEE 1149.1 Boundary
mobile Pentium® processor with MMXtechnology 0.25 micron extends mobile Pentium processor family, providing additional performance notebook applications. mobile Pentium processor with technology 0.25 micron compatible with entire installed base applications MSDOS*, Windows*, OS/2*, UNIX* major microprocessors support Intel technology. Furthermore, mobile Pentium processor with technology 0.25 micron superscalar architecture which execute instructions clock cycle, enhanced branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. mobile Pentium processor with technology 0.25 micron million transistors, built Intel's 0.25 micron manufacturing process technology full Enhanced power management features including System Management Mode (SMM) clock control. additional Enhanced features, 1.8/2.0V core operation along with 2.5V buffer operation, 320-pin Tape Carrier Package (TCP), Intel mobile module, make mobile Pentium processor with technology 0.25 micron ideal enabling mobile technology designs. mobile Pentium processor with technology 0.25 micron contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available upon request.
January 1998
Order Number: 243468-002
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
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Copyright Intel Corporation1997. Third-party brands names property their respective owners.
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
CONTENTS
PAGE 1.0. INTRODUCTION 2.0. MICROPROCESSOR ARCHITECTURE OVERVIEW 2.1. Mobile Pentium Processor Family Architecture 2.2. Mobile Pentium Processor with Technology 2.2.1. Full support Intel technology 2.2.2. Doubled code data caches each. 2.2.3. Improved branch prediction 2.2.4. Enhanced pipeline 0.25 Micron Technology. 3.0. MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY PINOUT 3.1. Mobile Differences from Desktop 3.2. Pinout Descriptions 3.2.1. MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY PINOUT 3.2.2. MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY CROSS REFERENCE 3.3. Design Notes 3.4. Quick Reference 3.5. Frequency 3.6. Reference Tables PAGE 3.7. Grouping According Function 4.0. ELECTRICAL SPECIFICATIONS 4.1. Maximum Ratings 4.2. Specifications 4.2.1. POWER SEQUENCING 4.3. Specifications 4.3.1. POWER GROUND 4.3.2. DECOUPLING RECOMMENDATION 4.3.3. CONNECTION SPECIFICATIONS 4.3.4. TIMINGS 66-MHZ 4.4. Buffer Models 4.4.1. BUFFER MODEL PARAMETERS 4.4.2. SIGNAL QUALITY SPECIFICATION 4.4.3. CLOCK SIGNAL MEASUREMENT METHODOLOGY 5.0. MECHANICAL SPECIFICATIONS 5.1. Mechanical Diagrams 6.0. THERMAL SPECIFICATIONS 6.1. Measuring Thermal Values 6.1.1. Thermal Equations 6.1.2. Thermal Characteristics 6.1.3. Board Enhancements 6.1.3.1. STANDARD TEST BOARD CONFIGURATION
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
2.0. 1.0. INTRODUCTION
MICROPROCESSOR ARCHITECTURE OVERVIEW
mobile Pentium® processors with MMXtechnology 0.25 micron fully compatible with existing mobile Pentium processors with technology (120, 133, 150, MHz) with following differences: voltage supplies, power consumption, performance. These processors, when used package, socket compatible with mobile Pentium processor (75, 100, 120, 133, MHz) making possible design flexible motherboard that supports both mobile Pentium processor MHz) mobile Pentium processor with technology (120 MHz). advanced features desktop version Pentium processor with technology except differences listed Section 3.1. mobile Pentium processor with technology 0.25 micron several features which allow high-performance notebooks designed, including following: dimensions ideal small form-factor designs. superior thermal resistance characteristics. 1.8V (166/200/233 MHz)/2.0V (266 MHz) core 2.5V buffer inputs reduce power consumption significantly. Enhanced feature set.
mobile Pentium processor with technology 0.25 micron extends mobile Pentium processor with technology family. binary compatible with 8086/88, 80286, Intel386DX, Intel386 Intel486DX, Intel486 Intel486 DX2, mobile Pentium processors with voltage reduction technology (75150). mobile Pentium processor family consists mobile Pentium processor with technology (120, 133, 150, 166), mobile Pentium processor with technology 0.25 micron (166, 200, 233, 266) mobile Pentium processor with voltage reduction technology -150 MHz). mobile Pentium processor with technology 0.25 micron contains features previous Intel Architecture provides significant enhancements additions including following: Support MMXTechnology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate Code Data Caches Writeback MESI Protocol Data Cache 64-Bit Data Enhanced Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions 0.25 Micron Process Technology Power Management Features Pool four write buffers used both pipes
architecture internal features mobile Pentium processor with technology 0.25 micron identical desktop version specifications provided Pentium® Processor Family Developer' Manual (Order Number 241428), except several features used mobile applications which have been eliminated streamline mobile applications. This document should used conjunction with Pentium® Processor Family Developer' Manual (Order Number: 241428)
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
2.1.
Mobile Pentium Processor Family Architecture
application instruction mobile Pentium processor family includes complete Intel486 family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. onchip memory management unit (MMU) completely compatible with Intel386 Intel486 families processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, prefetch code linear fashion, that prefetches code according Branch Target Buffer (BTB) needed code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 processor. Faster algorithms provide speed-up common operations including add, multiply load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache 32-byte line size 4-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple ported support snooping split line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware.
Pentium processors have increased data bits improve data transfer rate. Burst read burst writeback cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' contains optional extensions architecture which allow 4-Kbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. more more functions integrated chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap tual 8086 monitor. Figure shows block diagram mobile Pentium processor with technology. block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
separate code data caches shown,. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache.
Branch Prefetch Target Buffer Address
Code Cache KBytes
InstructioPointer
Prefetch Buffers Instruction Decode
Control
64-Bit Data
Branch Verif. Target Addr
Control Unit
V-Pipeline Connectio
32-Bit Address
Unit
Page Unit
U-Pipeline Connectio
FloatingPoint Unit Control Register File
Generate
Pipeline)
Address
Address Generate
Pipeline)
Control Integer Register File
Pipeline)
Unit
Divide
Pipeline)
Multiply
Barrel Shifter
64-Bit Data Data
32-Bit Addr.
Control APIC
Data Cache KBytes
PP0115
Figure Mobile Pentium Processor with MMXTechnology Block Diagram
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
mobile Pentium processor with technology both software compatible with previous members mobile Pentium processor family. contains million transistors manufactured lntel's enhanced 0.35 micron (120/133/150/166 MHz) 0.25 micron (166/200/233/266 MHz) CMOS process which allows voltage reduction technology power high density. This enables mobile Pentium processor with technology remain within thermal envelope while providing significant performance increase. addition architecture described previous section mobile Pentium processor family, mobile Pentium processor with technology several additional microarchitectural enhancements, which described below. 2.2.1. Full support Intel
code cache, branch target buffer prefetch buffers responsible getting instructions into execution units mobile Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions mobile Pentium processor execute instruction. control contains microcode which controls sequence operations that must performed implement mobile Pentium processor architecture. control unit direct control over both pipelines. mobile Pentium processor contains pipelined floating-point unit that provides significant floating-point performance advantage over previous generations processors. addition features described above, mobile Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. combination these improvements makes mobile Pentium processor good choice energy-efficient notebook designs. mobile Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. mobile Pentium® processor with MMXtechnology 0.25 micron contains on-chip advanced programmable interrupt controller (APIC). This function reserved future multi-processing function. architectural features introduced this section more fully described Pentium® Processor Family Developer's Manual (Order Number: 241428).
technology
technology based SIMD technique (Single Instruction, Multiple Data) which enables increased performance wide variety multimedia communications applications. Fiftyseven instructions four 64-bit data types supported mobile Pentium processor with technology. existing operating system application software fullycompatible. 2.2.2. Doubled code data caches each On-chip level-1 data code cache sizes have been doubled 16KB each 4-way associative mobile Pentium processor with technology. Larger separate internal caches improve performance reducing average memory access time providing fast access recentlyused instructions data. instruction data caches accessed simultaneously while data cache supports data references simultaneously. data cache supports writeback alternatively, write-through, line line basis) policy memory updates. 2.2.3. Improved branch prediction Dynamic branch prediction uses Branch Target Buffer (BTB) boost performance predicting most likely instructions executed. been improved mobile Pentium processor with technology increase accuracy. Further, this processor four prefetch
2.2.
Mobile Pentium Processor with Technology
mobile Pentium processor with technology significant addition mobile Pentium processor family. Available 120, 133, 150, 166, 200, 233, MHz, first microprocessor support Intel technology.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
buffers that hold four successive code streams. 2.2.4. Enhanced pipeline additional pipeline stage been added pipeline been enhanced improve performance. integration technology pipeline with integer pipeline very similar that floating-point pipeline. Under some circumstances, instructions integer instruction paired issued clock cycle increase throughput. enhanced pipeline described more detail Pentium® Processor Family Developer' Manual (Order Number 241428). Deeper write buffers. pool four write buffers shared between dual pipelines improve memory write performance. micron consumes significantly less power even higher speeds. mobile Pentium processor with technology 0.25 micron first Intel microprocessor utilizing 0.25 micron technology.
3.0.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY PINOUT Mobile Differences from Desktop
3.1.
better streamline part mobile applications, following features have been eliminated: Upgrade, Dual Processing (DP), Master/Checker functional redundancy. Table lists corresponding pins which exist desktop Pentium processor with technology have been removed mobile Pentium processor with technology 0.25 micron.
2.3.
0.25 micron technology
0.25 micron technology latest state-ofthe-art CMOS manufacturing process Intel unveiled April 1997, which enables lower core supply sub-2V. result, mobile Pentium processor with technology 0.25 Table Signals Removed Mobile Pentium Signal ADSC#
Processor with MMXTechnology 200/233 Functio
Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems.
BRDYC#
CPUTYP D/P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
3.2.
Pinout Descriptions
this section actual text which will marked packages). 3.2.1. MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY 0.25 MICRON PINOUT
text orientation side view drawings this section represent orientation mark actual packages (Note that text shown
M/IO# VCC3 VCC2 PM1/BP1 PM0/BP0 FERR# VCC2 IERR#
CACHE#
VCC2 VCC3 HOLD WB/WT# VCC2 BOFF# BRDY# VCC2 KEN# AHOLD EWBE# VCC2 VCC3
SMIACT# PRDY VCC2 PCHK# APCHK# VCC3 BREQ HLDA VCC2 VCC3 VCC2 LOCK# VCC3 D/C# EADS# ADS# VCC3 HITM# HIT# VCC3 W/R# BUSCHK# FLUSH# A20M# BE0# BE1# BE2# BE3# VCC3 BE4# BE5# BE6# BE7# VCC3 SCYC RESET VCC2 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3
VCC3
VCC2 VCC3
VCC3 VCC2 VCC3 VCC2 VCC3 VCC3 VCC3
VCC2
VCC2 VCC3 VCC2 VCC3 VCC3 VCC2 VCC3
VCC2 VCC3
VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 PICCLK PICD0 VCC2 PICD1 VCC3
Pinout
VCC3 R/S# INTR SMI# VCC2 IGNNE# INIT PEN#
VCC2
VCC2 VCC2 STPCLK# VCC2 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2
TRST#
VCC2
PP0116
Figure Mobile Pentium Processor with MMXTechnology 0.25 Micron Pinout
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
3.2.2. MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY 0.25 MICRON CROSS REFERENCE Table Cross Reference Name Address Data APIC PICCLK PICD0 PICD1
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Cross Reference Name (Contd.) Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# FLUSH# HIT# Clock Control PICCLK STPCLK# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT#
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Cross Reference Name (Contd.) VCC21 VCC32
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Cross Reference Name (Contd.)
NOTE: These VCC2 pins 1.8V (166/200/233 MHz) 2.0V (266 MHz) inputs core, change different voltage future offerings this microprocessor family. pins 2.5V power inputs.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Cross References Number (Pins 1-320) Signal VCC2 VCC3 HOLD WB/WT# VCC2 BOFF# BRDY# VCC2 KEN# AHOLD EWBE# VCC2 VCC3 CACHE# M/IO# VCC2 PM1/BP1 Signal VCC3 VCC2 VCC3 VCC2 VCC3 VCC2 VCC3 Signal VCC3 VCC3 VCC3 Signal VCC3 VCC3 VCC3 VCC3
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Cross References Number (Pins 1-320) Signal PM0/BP0 FERR# VCC2 IERR# VCC3 VCC2 TRST# VCC2 VCC3 Signal VCC3 VCC3 VCC3 Signal VCC2 VCC3 VCC2 VCC3 VCC2 Signal VCC2 PICCLK PICD0 VCC2 PICD1 VCC3 VCC3 BE3# BE2# BE1# BE0# A20M# FLUSH# BUSCHK# W/R# HIT# HITM# ADS# EADS# D/C#
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Cross References Number (Pins 1-320) Signal STPCLK# VCC2 PEN# INIT IGNNE# SMI# Signal VCC3 Signal RESET SCYC BE7# BE6# BE5# BE4# Signal LOCK# HLDA BREQ APCHK# PCHK# PRDY SMIACT#
INTR/LINT0 R/S# NMI/LINT1
NOTE: VCC2 pins 1.8V (166/200/233 MHz) 2.0V (266 MHz) inputs core. VCC3 pins 2.5V inputs I/O.
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
3.3.
Design Notes
Note input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. pins classified Input Output based their function Master Mode. Error Detection chapter Pentium® Processor Family Developer' Manual, further information.
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active HIGH inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
3.4.
Quick Reference
This section gives brief functional description each pins. detailed description, Hardware Interface chapter Pentium® Processor Family Developer's Manual.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference Symbol A20M# Type Name Function When address mask asserted, mobile Pentium processor with MMXtechnology emulates address wraparound Mbyte which occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3), next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31 -3). Frequency pins determine bus-to-core frequency ratio. [2:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[2:0] must change values while RESET active. Table Frequency Selection. order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Drving these pins with active logic recommended unless stability during RESET guaranteed. During power RESET should asserted prior ramped simultaneously with core voltage supply processor. BOFF# backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. Advanced Programmable Interrupt Controller Enable enables disables onchip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal.
A31-A3
ADS# AHOLD
APCHK#
BE7#-BE5# BE4#-BE0# BF[2:0]
[APICEN] PICD1
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Contd.) Symbol BP[3:2] PM/BP[1:0] Type Name Function breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. NOTE: assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. CACHE# processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. This 3.3V-tolerant-only Pentium® processor with MMXtechnology. NOTE: recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device. D/C# data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles.
BRDY#
BREQ
BUSCHK#
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Contd.) Symbol D63-D0 Type Name Function These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using MS-DOS type floating-point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicating completion writeback invalidation. NOTE: FLUSH# sampled when RESET transitions from high low, tristate test mode entered. HIT# indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive processor will resume driving bus. processor cycle pending, will driven same clock that HLDA de-asserted.
DP7-DP0
EADS# EWBE#
FERR#
FLUSH#
HITM#
HLDA
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Contd.) Symbol HOLD Type Name Function response hold request processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. INTR active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle.
IERR#
IGNNE#
INIT
KEN#
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Contd.) Symbol LOCK# Type Name Function lock indicates that current cycle locked. processor will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3; Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis.
M/IO#
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
PCHK#
parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor with MMXtechnology. Programmable interrupt controller data lines Pentium® processor with MMXtechnology comprise data portion APIC 3-wire bus. They open-drain outputs that require external pull-up resistor. These signals multiplexed with APICEN. These pins function part performance monitoring feature. breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring.
PEN#
PICCLK
PICD0-1 [APICEN]
PM/BP[1:0]
PRDY
probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Quick Reference (Contd.) Symbol R/S# Type Name Function run/stop input provided with Intel debug port. Please refer Pentium Processor Family Developer' Manual (Order Number 241428) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine tristate test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with voltage reduction technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. These pins 1.8V (166/200/233 MHz) 2.0V (266 MHz) power inputs core.
RESET
SCYC
SMI#
SMIACT# STPCLK#
TRST# VCC2
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Table Quick Reference (Contd.) Symbol VCC3 W/R# Type Name Function These pins 2.5V power inputs I/O. These pins ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
WB/WT#
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3.5.
Frequency
Core frequencies according Table below. Each mobile Pentium processor with technology specified operate withi
single bus-to-core ratio. Operation other busto-core ratios outside specified operating frequency range supported.
Table Frequency Selections Bus/Core Ratio Bus/Core Frequency (MHz) 66/166 66/200 66/233 66/266
NOTES: Each processor must externally configured with BF0-2 pins operate specified fraction mode. Operation specification supported.
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3.6.
Reference Tables
Table Output Pins Name Active Level High High High High High High states except Shift-DR Shift-IR Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated Hold, BOFF#
ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT#
NOTE: output input/output pins floated during tristate test mode (except TDO). HITM# internal pull-up resistor.
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Table Input Pins Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# Active Level HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T2,T12,T2P BRDY# Pulldown Pullup Pulldown Internal resistor Qualified
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WB/WT#
Synchronous
First BRDY#/NA#
Table Input/Output Pins Name A31-A3 BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1[APICEN] Active Level When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown Internal Resistor
NOTES: output input/output pins floated during tristate test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
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3.7.
Grouping According Functio
Table organizes pins with respect their function. Table Functional Grouping Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Debugging RESET, INIT, BF[2:0] A31-A3, BE7# BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-2 STPCLK# R/S#, PRDY Pins
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4.0. 4.1.
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
WARNING Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although mobile Pentium processor with technology contains protective circuitry resist damage from Electrostatic Discharge (ESD), always take precautions avoid high static voltages electric fields. Case temperature under bias -65° 110° Storage temperature. -65° 150° VCC3 Supply voltage with respect -0.5V +3.2V VCC2 Supply voltage with respect -0.5V +2.8V 2.5V Only Buffer Input Voltage -0.5V CC3+0.5V* *not exceed
4.2.
Specifications
Tables list specifications which apply mobile Pentium processor with technology 0.25 Micron. processor core operates 1.8V (166/200/233 MHz) 2.0V (266 MHz) internally while interface operates 2.5V. 4.2.1. POWER SEQUENCING
There specific sequence required powering powering down VCC2 VCC3 power supplies. However, compatibility with future mobile processors, recommended that VCC2 VCC3 power supplies either both both within second each other.
Table CASE Specifications Package TCASE Supply VCC2 Voltage 1.665V 1.850V VCC3 2.375V Voltage 1.935V 2.150V 2.625V Voltage Tolerance 1.8V 0.135V 2.0V 0.150V 2.5V 0.125V Frequency 166/200/233 166/200/233/266
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Table Specifications Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage
NOTES: Parameter measured Parameter measured Parameter measured 1mA; 100% tested, guaranteed design.
-0.3 VCC3
VCC3
Unit
Notes
Level Level Level Level
Table Specifications Symbol ICC2 Parameter Power Supply Current 2.35 2.70 3.10 4.00 0.33 0.33 0.38 0.38 Unit Notes
ICC3
Power Supply Current
NOTE: This value should used power supply design. determined using worst case instruction maximum Tcase Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
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Table Power Dissipation Requirements Thermal Design Parameter Thermal Design Power Typical Max2 0.42 0.46 0.53 0.70 0.02 0.02 0.02 0.05 0.05 0.05 0.06 Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts Frequency Notes
Active Power
Stop Grant Auto Halt Powerdown Power Dissipation
Stop Clock Power
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device 1.8V (166/200/233 MHz) 2.0V (266 MHz) running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit processor' maximum power. maximum thermal design power determined using worst-case instruction with 1.8V (166/200/233 MHz) 2.0V (266 MHz) also takes into account thermal time constant package. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. When this mode, processor feature which allows power down additional circuitry enable lower power dissipation. This power without snooping Vcc2 1.8V/2.0V with TR12 set. order enable this feature, TR12 must (the default disabled). Stop grant/Auto Halt Powerdown power dissipation without TR12 bit21 higher. rating changed future spec update. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. This specified Tcase Active power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature.
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Table Input Output Characteristics Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input High Leakage Current Input Leakage Current -400 Unit 0<VIN <VIL, <VCC3(1) 0<VIN <VIL, <VCC3(1) 0.4V 0.4V (2,5) Notes
NOTES: This parameter inputs/outputs without internal pull pull down. This parameter inputs with internal pull This parameter inputs with internal pull down. Guaranteed design. This specification applies HITM# when driven input (e.g., JTAG mode).
4.3.
Specifications
4.3.2.
DECOUPLING RECOMMENDATIONS
specifications mobile Pentium processor with technology 0.25 Micron consist setup times, hold times, valid delays 4.3.1. POWER GROUND
Liberal decoupling capacitance should placed near processor. processor' large address data buses cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced shortening circuit board traces between processor decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from level power consumption high level high power transition). typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing processor enter Auto HALT
clean on-chip power distribution, VCC2 (core power), VCC3 (I/O power) (ground) inputs. Power ground connections must made external VCC2, VCC3 pins. circuit board VCC2 pins must connected 1.8V (166/200/233 MHz) 2.0V (266 MHz) VCC2 plane island) VCC3 pins must connected 2.5V VCC3 plane. pins must connected plane. Please refer Table list VCC2, VCC3 pins.
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Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. 4.3.3. CONNECTION SPECIFICATIONS
pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground. 4.3.4. TIMINGS 66-MHZ
Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor both VCC2 plane VCC3 plane ensure that supply voltages stay within specified limits during changes supply current during operation. more detailed information, please contact Intel refer Mobile Pentium® Processor with MMXTechnology: Power Supply Design Considerations application note (Order Number 243306).
specifications given Table consist output delays, input setup requirements input hold requirements mobile standard external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced VCC3/2 both logic levels unless otherwise specified. Within sampling window, asynchronous inputs must stable correct operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays. select fraction clock speed which will cause processor exceed internal maximum frequency.
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Table Mobile Pentium® Processor with MMXTechnology 0.25 Micron Specifications 66-MHz Operation Table CASE Specifications, Symbol Parameter
Frequency
33.33 15.0
66.66 30.0
Unit
Figure
Notes
Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay LOCK# Valid Delay ADS# Valid Delay A3-A31 Valid Delay M/IO# Valid Delay BE0-7#, D/C#, W/R#, SCYC Valid Delay ADS#, A3-A31, PWT, PCD, BE0-7#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay
0.15 0.15 10.0
VCC3 0.7V, 0.5V, (VCC3 0.7V 0.5V), (0.5V 0.7V),
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Table Mobile Pentium® Processor with MMXTechnology 0.25 Micron Specifications 66-MHz Operation (Contd.) Table CASE Specifications, Symbol t10a t10b t11a t11b t16a t16b t18a t18b t24a t24b t25a t25b Parameter PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM0-1, BP0-3 Valid Delay PRDY Valid Delay D0-D63, DP0-7 Write Data Valid Delay D0-D63, DP0-3 Write Data Float Delay A5-A31 Setup Time A5-A31 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time 4.75 10.0 10.0 Unit Figure Notes
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Table Mobile Pentium® Processor with MMXTechnology 0.25 Micron Specifications 66-MHz Operation (Contd.) Table CASE Specifications, Symbol t42a Parameter A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#) Hold Time, Async. 15.0 Unit CLKs CLKs CLKs CLKs Power RESET falling edge (15) RESET falling edge Figure Notes
t42b
CLKs
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Table Mobile Pentium® Processor with MMXTechnology 0.25 Micron Specifications 66-MHz Operation (Contd.) Table CASE Specifications, Symbol t43b t43c t43d Parameter BF0-BF2 Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time 62.5 25.0 25.0 16.0 Unit CLKs CLKs CLKs Vcc3 0.7V 0.5V (Vcc3-0.7V 0.5V (0.5V Vcc3 0.7V) Asynchronous(1) Figure Notes RESET falling edge(18) RESET falling edge RESET falling edge
TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time
40.0 13.0 20.0 25.0 20.0 25.0 13.0
CLKs
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Table Mobile Pentium® Processor with MMXTechnology 0.25 Micron APIC Specifications Symbol t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay PICD0-1 High Time PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK/PICCLK) 0.15 0.15 16.66 Unit PICCLK PICCLK From PICCLK, From PICCLK, Figure Notes
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NOTES TABLES Notes general apply standard signals used with Pentium processor family. 100% tested. Guaranteed design/characterization. input test waveforms assumed 2.5V transitions with 1V/nS rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions (i.e., glitches). 0.87V/ns input rise/fall time 8.7V/ns. 0.3V/ns input rise/fall time 5V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. During probe mode operation, boundary scan timings 55-58). Setup time required guarantee recognition specific clock. Hold time required guarantee recognition specific clock. timings referenced from CC3/2. guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must de-asserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A5-A31 signals sampled only that ADS# active. BF[2:0] must change values while RESET active. order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. These signals measured rising edge adjacent CLKs CC3/2. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within ±250ps. Therefore, input cannot changed dynamically. Timing (t14) required external snooping (e.g., address setup which EADS# sampled active). This assumes external pullup resistor lumped capacitive load. pullup resistor must between ohms ohms, capacitance must between 20pF 120pF, product must between 36nS. PICCLK ratio integer ratio (CLK/PICCLK) cannot smaller than input frequency must either 33.33 MHz) 66.66 MHz). Operations range between 33.33 66.6 supported. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
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Vcc3-0.7V 0.5V t49, t60e t48, t60f t46, t60c t45, t60b t47, t60d
PP0051
Figure Clock Waveform
Vcc3/2
max.
ignal Vcc3/2 VALID
t10, t11, t12, t60i
PP0052
Figure Valid Delay Timings
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Vcc3/2
Signal
t6min, t12mi
Figure Float Delay Timings
Vcc3/2
Signal
VALID
t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g PICCLK), t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h PICCLK), Figure Setup Hold Timings
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RESET
Vcc3/2
Vcc3/2
Config =t42, t43c, t43e, t43b, t43d, t43f, t38, Figure Reset Configuration Timings VALID
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Vcc3/2
Output Signals
Input Signals
Figure Test Timings
TRST#
Vcc3/2
Figure Test Reset Timings
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4.4.
Buffer Models
This section describes buffer models mobile Pentium processor with technology 0.25 Micron. first order buffer model simplified representation complex input output buffers used. Figure shows structure input buffer model Figure shows output buffer model. Tables show parameters used specify these models. Although simplified, these buffer models will accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model. addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them. Note, however, some signal quality specifications require that diodes removed from input model. series resistors (RS) part diode model. Remove these when removing diodes from input model.
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Figure First Order Input Buffer Model
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Table Parameters Used Specification First Order Input Buffer Model Parameter Description Minimum Maximum value capacitance input buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance Diode Series Resistance Ideal Diodes
PP0061
Figure First Order Output Buffer Model
Table Parameters Used Specification First Order Output Buffer Model Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model Minimum maximum value output impedance output buffer model Minimum Maximum value capacitance output buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance
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4.4.1.
BUFFER MODEL PARAMETERS
values; operating driver, data parameters. Please refer Table groupings buffers. input, output bi-directional buffer' values listed below. These tables contain listings three types. When bi-directional operating input, just CIN, values, operating driver data parameters.
This section gives parameters each input, output bidirectional buffers. input, output bidirectional buffer values processor listed Table These tables contain listings three types, them confused during simulation. When bidirectional operating input, CIN,
Table Signal Buffer Type Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE[7:5]#, BP[3:2], BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, A[31: BE[4:0]#, CACHE#, D/C#, D[63:0], DP[8:0], HLDA, LOCK#, M/IO#, SCYC, ADS#, HITM#, HIT#, W/R#, PICD0, PICD1 Type Driver Buffer Type Receiver Buffer Type
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Table Input, Output Bi-directional Buffer Model Parameters Buffer Type Transition dV/dt (V/nsec) (input) Rising Falling Rising 2.2/2.2 2.2/2.9 2.2/2.2 2.2/2.9 2.7/0.15 2.7/0.22 2.7/0.15 2.7/0.22 (Ohms) (pF) (nH) 11.3 11.3 11.7 11.7 10.3 10.3 CO/CIN (pF)
(output) Falling (bidir) Rising Falling
Table Input Buffer Model Parameters: (Diodes) Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14A 1.19 ohms 0.983V 0.281 0.385 2.78e-16A 1.00 ohms 0.967V 0.365 0.376
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4.4.2. SIGNAL QUALITY SPECIFICATIONS VSS) relative VCC3 VSS) level after signal reached maximum voltage level. input diodes assumed present. Maximum Ringback Inputs 0.5V falling edge) Maximum Ringback Inputs 0.7V (rising edge (with diodes) simulated without input diodes, follow Maximum Overshoot/Undershoot specification. meeting overshoot/undershoot specification, signal guaranteed ringback excessively. simulated with diodes present input model, follow maximum ringback specification. Overshoot (Undershoot) absolute value maximum voltage above VCC3 (below VSS). guideline assumes absence diodes input.
Signals driven system into mobile Pentium processor with technology 0.25 Micron must meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect reliability component. There signal quality parameters: Ringback Settling Time. Section 4.4.2.3 signal quality specification. 4.4.2.1. Ringback
Excessive ringback contribute long-term reliability degradation processor, cause false signal detection. Ringback simulated input component using input buffer model. Ringback simulated with without diodes that input buffer model. Ringback absolute value maximum voltage receiving below VCC3 above
Figure Overshoot/Undershoot Ringback Guidelines
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4.4.2.2.
Settling Time
settling time defined time signal requires receiver settle within percent VCC3 VSS. Settling time maximum time allowed signal reach within percent final value. Most available simulation tools unable simulate settling time that accurately reflects silicon measurements. physical board, second-order effects other effects serve dampen signal receiver. Because these concerns, settling time recommendation tool layout tuning specification. Settling time simulated slow corner, make sure that there impact flight times signals waveform settled. Settling time simulated with diodes included excluded from input buffer model. diodes included, settling time recommendation will easier meet. Although simulated settling time shown good correlation with physical, measured settling time, settling time simulations still used tool tune layouts.
following procedure verify board simulation tuning with concerns settling time. Simulate settling time slow corner particular signal. settling time violations occur (signal requires more than 12.5 settle percent final value), simulate signal trace with D.C. diodes place receiver pin. D.C. diode behaves almost identically actual (non-linear) diode part long excessive overshoot does occur. settling time violations still occur, simulate flight times five consecutive cycles that particular signal. flight time values consistent over five simulations, settling time should concern. however, flight times consistent over five simulations, tuning layout required. Note that, signals that allocated cycles flight time, recommended settling time doubled. Maximum Settling Time within 12.5
volts
Figure Settling Time
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UNDERSHOOT THRESHOLD DURATION SPECIFICATION: undershoot threshold duration defined time during which signal below -0.3V within single clock period. undershoot threshold duration must exceed percent period. MAXIMUM RINGBACK SPECIFICATION: maximum ringback associated with their high states (overshoot) must drop below VCC3 0.7V shown Figure Similarly, maximum ringback associated with their states (undershoot) must exceed 0.5V shown Figure Refer Table Table summary clock overshoot undershoot specifications 200- Pentium processor with technology.
4.4.2.3.
Signal Quality Specificatio
maximum overshoot, maximum undershoot, overshoot threshold duration, undershoot threshold duration, maximum ringback specifications described below: MAXIMUM OVERSHOOT MAXIMUM UNDERSHOOT SPECIFICATION: maximum overshoot signals should exceed VCC3,nominal 0.6V. maximum undershoot signals must drop below -0.6V. OVERSHOOT THRESHOLD DURATION SPECIFICATION: overshoot threshold duration defined time during which signal above VCC3,nominal 0.3V within single clock period. overshoot threshold duration must exceed percent period.
Table Overshoot Specification Summary Specification Name Threshold Level Value VCC3,nominal (CLK PICCLK) VCC3,nominal (All other inputs) Maximum Overshoot Level VCC3,nominal (CLK PICCLK) VCC3,nominal (All other inputs) Maximum Threshold Duration Maximum Ringback clock period above threshold voltage VCC3,nominal Units Notes
NOTES: VCC3, nominal refers voltage measured bottom side pins. Section 4.3.1. details. Figures
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Table Undershoot Specification Summary Specification Name Threshold Level Value (CLK PICCLK) (All other inputs) Minimum Undershoot Level (CLK PICCLK) (All other inputs) Maximum Threshold Duration clock period below threshold voltage Units Notes Figures Figures Figures Figures
Maximum Ringback
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4.4.3. CLOCK SIGNAL MEASUREMENT METHODOLOGY: waveform clock signals should measured bottom side processor pins using oscilloscope with bandwidth least (100 MS/s digital sampling rate). There should short isolation ground lead attached processor bottom side board. MOhm probe with loading less than (e.g., Tektronics 6243 Tektronics 6245) recommended. measurement should taken (AK18) nearest (AM18). MAXIMUM OVERSHOOT, MAXIMUM UNDERSHOOT MAXIMUM RINGBACK SPECIFICATIONS: display should show continuous sampling (e.g., infinite persistence) waveform mV/div nS/div recommended duration approximately five seconds. Adjust vertical position measure maximum overshoot associated ringback with largest possible granularity. Similarly, readjust vertical position measure maximum undershoot associated ringback. There allowance crossing maximum overshoot, maximum undershoot maximum ringback specifications. OVERSHOOT THRESHOLD DURATION SPECIFICATION: snapshot clock signal should taken mV/div pS/div. Adjust vertical position horizontal offset position view threshold duration. overshoot threshold duration defined time during which clock signal above VCC3,nominal 0.3V within single clock period. overshoot threshold duration must exceed percent period. UNDERSHOOT THRESHOLD DURATION SPECIFICATION: snapshot clock signal should taken mV/div pS/div. Adjust vertical position horizontal offset position view threshold duration. undershoot threshold duration defined time during which clock signal below 0.3V within single clock period. undershoot threshold duration must exceed percent period. These overshoot undershoot specifications illustrated graphically Figures through
Maximum Overshoot Level Overshoot Threshold Level VCC3, nominal
Overshoot Threshold DuratioFigure Maximum Overshoot Level, Overshoot Threshold Level, Overshoot Threshold Duration
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
VCC3, nominal Maximum Ringback
Figure Maximum Ringback Associated with Signal High State
Undershoot Threshold Duratio
VSS,nominal Undershoot Threshold Level Maximum Undershoot Level
Figure Maximum Undershoot Level, Undershoot Threshold Level, Undershoot Threshold Duratio
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Maximum Ringback VSS, nominal
Figure Maximum Ringback Associated with Signal State
5.0.
MECHANICAL SPECIFICATIONS
Today's portable computers face challenge meeting desktop performance environment that constrained thermal, mechanical electrical design considerations. These considerations have driven development implementation Intel' Tape Carrier Package (TCP). Intel been designed offer high count, profile, reduced footprint package with uncompromised thermal electrical performance. Intel continues provide packaging solutions that meet rigorous criteria quality performance. features include: surface mount technology design, lead pitch 0.25 polyimide body size polyimide pick-andplace handling. components shipped with leads flat slide carriers, designed
excised lead formed customer manufacturing site. Recommendations manufacture this package included 1996 Packaging Databook (Order Number 240800) Figure shows cross-section view mounted Printed Circuit Board. Figures show shipped slide carrier, dimensions carrier package. Figure shows cross-section detail package. Figure shows enlarged view outer lead bond area package.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
5.1.
Mechanical Diagrams
Encapsulant Gold Bump
Polyimide Support Ring
Polyimide Lead Keeper (OFC Copper)
Cross-Section Thermally Conductive Adhesive Note: Thermal vias Ground plane Sketches Scale
Full Cross-Sectio255703
Figure Cross-Sectional View Mounted
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
255705
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Figure Site Carrier (Bottom View Die)
255706
Figure Site Carrier (Top View Die)
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
255707
Figure Site (Cross-Sectional Detail)
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
255708
Figure Outer Lead Bond (OLB) Window Detail
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
Table Dimensions Symbol D1,E1 Description Leadcount Tape Width Site Length Test Pitch Outer Lead Pitch Outer Lead Width Package Body Size Package Height Length Width Lead Thickness Encap Length Encap Width Dimension leads 48.18 ±0.12 (43.94) reference only 0.40 nominal 0.25 nominal 0.10 ±0.01 24.0 ±0.1 0.597 ±0.030 10.450 0.015 9.088 0.015 0.025 11.053 0.015 9.691 0.015
NOTES: Dimensions millimeters unless otherwise noted. Dimensions parentheses reference only.
Table Mounted Dimensions Symbol Description Package Height Terminal Dimension Package Weight Dimension 0.75 maximum 29.5 nominal maximum
NOTE: Dimensions millimeters unless otherwise noted. Package terminal dimension (lead tip-to-lead tip) assumes keeper bar.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
where,
6.0.
THERMAL SPECIFICATIONS
ambient case temperatures Case-to-Ambient thermal resistance C/W) Junction-to-Ambient thermal resistance C/W) Junction-to-Case thermal resistance C/W) maximum power consumption (Watts)
mobile Pentium processor with technology 0.25 Micron specified proper operation when case temperature, TCASE (TC), within specified range
6.1.
Measuring Thermal Values
(maximum power consumption) specified Section 3.1. 6.1.2. Thermal Characteristics
verify that proper (case temperature) maintained, should measured center package surface (encapsulant). minimize measurement errors, following techniques recommended: gauge finer diameter type thermocouples. Intel's laboratory testing done using thermocouple made Omega (part number: 5TC-TTK-36-36). Attach thermocouple bead junction center package surface using highly thermally conductive cements. Intel's laboratory testing done using Omega Bond* (part number: OB-100). thermocouple should attached 90°angle shown Figure 6.1.1. Thermal Equations
primary heat transfer path from through back side into board. There thermal paths traveling from board ambient air. spread heat within board dissipation heat board ambient air. other transfer heat through board opposite side where thermal enhancements (e.g., heat sinks, pipes) attached. Solder-side heat sinking, compared component-side heat sinking, preferred method reduced risk damage, easier mechanical implementation larger surface area attachment. However, component-side heat sinking possible. design requirements component-side thermal solution are: direct loading inner lead bonds TCP, maximum force center clean TCP, direct loading tape outer lead bonds controlled board deflection. 6.1.3. Board Enhancements
mobile Pentium processor with technology, ambient temperature (TA) specified directly. only requirement that case temperature (TC) met. ambient temperature calculated from following equations:
Copper planes, thermal pads, vias design options that used improve heat transfer from board ambient air. Tables present thermal resistance data copper plane thickness effects. should noted that although thicker copper planes will reduce system without thermal enhancements, they have less effect system with thermal enhancements. However, placing vias under will reduce system with without thermal enhancements.
MOBILE PENTIUM® PROCESSOR WITH MMXTECHNOLOGY
255704
Figure Technique Measuring Case Temperature Table Thermal Resistance Copper Plane Thickness With Without Enhancements Copper Plane Thickness*
NOTE: *225 vias underneath
C/Watt) Enhancements
C/Watt) With Heat Pipe Plates
Table Thermal Resistance Thermal Vias Underneath Number Vias Under Die*
NOTE: copper planes boards
C/Watt) Enhancements
6.1.3.1.
STANDARD TEST BOARD CONFIGURATION
Tape Carrier Package (TCP) thermal measurements familiarity provided following tables were taken with component soldered test board outline. This six-layer board contains vias attach which connected copper planes located layers five. TCP, vias attach should connected without thermal reliefs ground plane(s). attached
attach using thermally conductive adhesive. This test board designed optimize heat spreading into board heat transfer through opposite side board. NOTE Thermal resistance values should used guidelines only, highly system dependent. Final system verification should always refer case temperature specification.
MOBILE PENTIUM PROCESSOR WITH MMXTECHNOLOGY
Table Thermal Resistance without Enhancements C/Watt) Thermal Resistance without Enhancements C/Watt)
Table Thermal Resistance with Enhancements (Without Airflow) Thermal Enhancements Heat sink Plate Plate with Heat Pipe C/W) 11.7 Notes 0.3" Heat pipe x0.3"Al plate
Table Thermal Resistance with Enhancements (With Airflow) Thermal Enhancements Heat sink with Heat sink with Airflow Heat sink with Airflow
NOTES: heat sink Linear Feet/Minute Cubic Feet/Minute
C/W)
Notes 1.2" x1.2" x.35"HS
UNITED STATES, Intel Corporation 2200 Mission College Blvd., P.O. 58119, Santa Clara, 95052-8119 Tel: 765-8080 JAPAN, Intel Japan K.K. Tokodai, Tsukuba-shi, Ibaraki-ken 300-26 Tel: 81-29847-8522 FRANCE, Intel Corporation S.A.R.L. Quai Grenelle, 75015 Paris Tel: 1-45717171 UNITED KINGDOM, Intel Corporation (U.K.) Ltd. Pipers Way, Swindon, Wiltshire, England Tel: 1-793-641440 GERMANY, Intel GmbH Dornacher Strasse 85622 Feldkirchen/ Muenchen Tel: 89/99143-0 HONG KONG, Intel Semiconductor Ltd. 32/F Pacific Place, Queensway, Central Tel: +852 2844-4555 CANADA, Intel Semiconductor Canada, Ltd. Attwell Drive, Suite Rexdale, Ontario Tel: +416 675-2438
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