SBOS197 DECEMBER 2001 1.6GHz, Low-Noise, FET-Input OPERATIONAL AM
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OPA657
SBOS197 DECEMBER 2001
1.6GHz, Low-Noise, FET-Input OPERATIONAL AMPLIFIER
FEATURES
HIGH GAIN BANDWIDTH PRODUCT: 1.6GHz HIGH BANDWIDTH 275MHz +10) INPUT OFFSET VOLTAGE: ±0.25mV INPUT BIAS CURRENT: INPUT VOLTAGE NOISE: 4.8nV/ HIGH OUTPUT CURRENT: 70mA FAST OVERDRIVE RECOVERY
DESCRIPTION
OPA657 combines high gain bandwidth, distor-tion, voltage-feedback with voltage noise JFET-input stage offer very high dynamic range amplifier high precision (Analog-to-Digital Converter) driving wideband transimpedance applications. Photodiode applications will improved noise bandwidth using this decompensated, high gain bandwidth amplifier. Very level signals significantly amplified single OPA657 gain stage with exceptional bandwidth accuracy. Having high 1.6GHz gain bandwidth product will give 10MHz signal bandwidths gains 160V/V (44dB). very input bias current capacitance will support this performance even relatively high source impedances. Broadband photodetector applications will benefit from voltage noise JFET inputs OPA657. JFET input contributes virtually current noise while broadband applications, voltage noise also required. 4.8nV/ input voltage noise will provide exceptional input sensitivity higher bandwidth applications. example shown below will give total equivalent input noise current 1.8pA/ over 10MHz bandwidth.
APPLICATIONS
WIDEBAND PHOTODIODE AMPLIFIER WAFER SCANNING EQUIPMENT INPUT AMPLIFIER TEST MEASUREMENT FRONT HIGH GAIN PRECISION AMPLIFIER
200k TRANSIMPEDANCE BANDWIDTH 10MHz Bandwidth
RELATED OPERATIONAL AMPLIFIER PRODUCTS
SLEW VOLTAGE RATE NOISE (MHz) (V/µS) (nV/HZ) AMPLIFIER DESCRIPTION 5.80 Unity-Gain Unity-Gain Unity-Gain Unity-Gain Unity-Gain Stable Stable Stable Stable Stable CMOS FET-Input FET-Input FET-Input FET-Input
Transimpedance Gain (dB)
DEVICE
OPA355 OPA655 OPA656 OPA627 THS4601
0.1pF 200k
100kHz
1MHz Frequency
10MHz
50MHz
(12pF)
OPA657
Wideband Photodiode Transimpedance Amplifier
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATAinformation current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2001, Texas Instruments Incorporated
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PACKAGE/ORDERING INFORMATION
PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE -40°C +85°C PACKAGE MARKING OPA657U ORDERING NUMBER(2) OPA657U OPA657U/2K5 OPA657UB OPA657UB/2K5 OPA657N/250 OPA657N/3K OPA657NB/250 OPA657NB/3K TRANSPORT MEDIA, QUANTITY Rails, Tape Reel, 2500 Rails, Tape Reel, 2500 Tape Reel, Tape Reel, 3000 Tape Reel, Tape Reel, 3000
PRODUCT OPA657U
PACKAGE-LEAD SO-8 Surface Mount
OPA657UB
SO-8 Surface Mount
-40°C +85°C
OPA657UB
OPA657N
SOT23-5
-40°C +85°C
OPA657NB
SOT23-5
-40°C +85°C
NOTES: most current specifications package information, refer site www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage ±6.5V Internal Power Dissipation Thermal Characteristics Differential Input Voltage Input Voltage Range Storage Temperature Range -40°C +125°C Lead Temperature +260°C Junction Temperature +175°C Rating (Human Body Model) 2000V (Machine Model) 200V NOTE: Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified implied.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
CONFIGURATIONS
View SO-8 View SOT23-5
Output
Noninverting Input
Inverting Input
Inverting Input Noninverting Input
Output
Orientation/Package Marking
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ELECTRICAL CHARACTERISTICS:
453, 100, +10, unless otherwise noted. Figure performance. OPA657U, (Standard-Grade) +25°C 1600 -106 ±0.25 +2.5 -4.0 1012 1012 Load ±3.9 ±3.5 0.02 Junction-to-Ambient °C/W °C/W ±3.7 ±2.2 ±1800 ±900 +1.9 -3.4 ±2.6 ±5000 ±2500 +1.8 -3.3 MIN/MAX OVER TEMPERATURE +25°C(1) 70°C(2) -40°C +85°C(2) MIN/ TEST LEVEL(3)
PARAMETER PERFORMANCE (Figure Small-Signal Bandwidth
CONDITIONS
UNITS
Gain-Bandwidth Product Bandwidth 0.1dB flatness Peaking Gain Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Settling Time 0.02% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Input Current Noise PERFORMANCE(4) Open-Loop Voltage Gain (AOL) Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current INPUT Most Positive Input Voltage(5) Most Negative Input Voltage(5) Common-Mode Rejection Ratio (CMRR) Input Impedance Differential Common-Mode OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Maximum Quiescent Current Minimum Quiescent Current Power-Supply Rejection Ratio (+PSRR) (-PSRR) TEMPERATURE RANGE Specified Operating Range: Package Thermal Resistance, SO-8 SOT23-5
200mVp-p +10, 200mVp-p +20, 200mVp-p +10, 2Vp-p +10, 2Vp-p +10, Step 0.2V Step +10, Step +10, 5MHz, 2Vp-p 100kHz 100kHz
V/µs nV/Hz fA/Hz µV/°C
±1.8
+2.0 -3.5
±0.5V
±3.3
±3.2
±3.1
+10, 0.1MHz
15.8 11.7
4.50V 5.50V 4.50V -5.50V
11.4
16.1 11.1
NOTES: Junction temperature ambient 25°C guaranteed specifications.(2) Junction temperature ambient temperature limit: junction temperature ambient +20°C high temperature limit over temperature guaranteed specifications. Test Levels: 100% tested 25°C. Over temperature limits characterization simulation. Limits characterization simulation. Typical value only information. Current considered positive out-of-node. input common-mode voltage. Tested below minimum specified CMRR ±CMIR limits.
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ELECTRICAL CHARACTERISTICS: ±5V: High Grade Specifications(1)
453, 100, +10, unless otherwise noted. OPA657UB, (High-Grade) +25°C ±0.1 ±0.5 MIN/MAX OVER TEMPERATURE +25°C(2) 70°C(3) ±0.85 ±450 ±450 -40°C +85°C(3) ±0.9 ±1250 ±1250 MIN/ TEST LEVEL(4)
PARAMETER Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common-Mode Rejection Ratio (CMRR) Power-Supply Rejection Ratio (+PSRR) (-PSRR)
CONDITIONS ±0.5V 4.5V 5.5V -4.5V -5.5V
UNITS µV/°C
±0.6
NOTES: other specifications same standard-grade. Junction temperature ambient 25°C guaranteed specifications.(3) Junction temperature ambient temperature limit: junction temperature ambient +20°C high temperature limit over temperature guaranteed specifications. Test Levels: 100% tested 25°C. Over temperature limits characterization simulation.
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TYPICAL CHARACTERISTICS:
+25°C, +10, 453, 100, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 0.2Vp-p
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 0.2Vp-p
Normalized Gain (dB)
Frequency (MHz) Figure
Normalized Gain (dB)
Frequency (MHz) Figure
NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE 0.2Vp-p 1Vp-p
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 0.2Vp-p 1Vp-p 1Vp-p
Gain (dB)
Figure
Gain (dB)
2Vp-p 5Vp-p
Figure
5Vp-p
Frequency (MHz)
Frequency (MHz)
NONINVERTING PULSE RESPONSE
Large-Signal Output Voltage (400mV/div) Small-Signal Output Voltage (200mV/div) Small-Signal Output Voltage (200mV/div)
INVERTING PULSE RESPONSE Small-Signal Left Scale -0.2 -0.4 -0.6 Figure -0.8 Time (10ns/div) -1.6 -0.4 -0.8 -1.2 Large-Signal Right Scale
Large-Signal Output Voltage (400mV/div)
Small-Signal Left Scale -0.2 -0.4 -0.6 Figure -0.8 Time (10ns/div) Large-Signal Right Scale
-0.4 -0.8 -1.2 -1.6
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TYPICAL CHARACTERISTICS: (Cont.)
+25°C, +10, 453, 100, unless otherwise noted.
HARMONIC DISTORTION LOAD RESISTANCE Harmonic 2Vp-p 5MHz
HARMONIC DISTORTION OUTPUT VOLTAGE (5MHz) 5MHz
Harmonic Distortion (dBc)
-100 -105 -110 Resistance Figure Harmonic
Harmonic Distortion (dBc)
Harmonic
Figure -100 -105
Harmonic
Output Voltage Swing (Vp-p)
HARMONIC DISTORTION FREQUENCY Harmonic -100 -110 Frequency (MHz) Harmonic Figure 2Vp-p
HARMONIC DISTORTION OUTPUT VOLTAGE (1MHz) 1MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
Harmonic
Harmonic -100 Figure -105 -110 Output Voltage Swing (Vp-p)
HARMONIC DISTORTION NONINVERTING GAIN 2Vp-p 5MHz Harmonic
HARMONIC DISTORTION INVERTING GAIN 2Vp-p 5MHz
Harmonic Distortion (dBc)
-100
Harmonic Distortion (dBc)
Harmonic
Harmonic
Harmonic -100
Figure Adjusted -110 Gain (V/V) -110
Figure Adjusted Gain (V/V)
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TYPICAL CHARACTERISTICS: (Cont.)
+25°C, +10, 453, 100, unless otherwise noted.
INPUT CURRENT VOLTAGE NOISE DENSITY 3rd-Order Spurious Level (dBc)
2-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
OPA657
20MHz 15MHz
(nV/Hz)
(fA/Hz)
Input Voltage Noise 4.8nV/Hz
10MHz 5MHz -100 Single-Tone Load Power (dBm)
Input Current Noise 1.3fA/Hz (Hz) 100k
COMMON-MODE REJECTION RATIO POWER-SUPPLY REJECTION RATIO FREQUENCY CMRR Open-Loop Gain (dB)
OPEN-LOOP GAIN PHASE log(AOL) -100 -122 -144 -166 -188 -210 100k 100M Frequency (Hz)
CMRR (dB)
PSRR (dB)
+PSRR -PSRR
100k
100M
Frequency (Hz)
RECOMMENDED CAPACITIVE LOAD
FREQUENCY RESPONSE CAPACITIVE LOAD
Normalized Gain Capacitive Load (dB)
10pF Frequency (MHz)
OPA657
22pF 100pF
Maximally Flat Frequency Response Capacitive Load (pF)
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Open-Loop Phase (30°/div)
TYPICAL CHARACTERISTICS: (Cont.)
+25°C, +10, 453, 100, unless otherwise noted.
TYPICAL INPUT OFFSET VOLTAGE DRIFT OVER TEMPERATURE
Input Offset Voltage (mV)
TYPICAL INPUT BIAS CURRENT COMMON-MODE INPUT VOLTAGE
Input Bias Current (pA)
-0.5 -1.0 -1.5
-0.5
-1.0 Ambient Temperature (°C)
-2.0 Common-Mode Input Voltage
TYPICAL INPUT BIAS CURRENT DRIFT OVER TEMPERATURE 1000
Input Bias Current (pA)
SUPPLY OUTPUT CURRENT TEMPERATURE Supply Current Right Scale Left Scale Sourcing Current Left Scale Sinking Current Ambient Temperature (°C)
Ambient Temperature (°C)
NONINVERTING INPUT OVERDRIVE RECOVERY
Output Voltage
INVERTING INPUT OVERDRIVE RECOVERY
Output Voltage
Input Voltage
0.25 Input Voltage Right Scale 0.20 0.15
Input Voltage
Input Voltage Right Scale Output Voltage Left Scale
Time (20ns/div) Figure Output Voltage Left Scale
0.10 0.05 -0.05 -0.10 -0.15 -0.20 -0.25
-0.1 -0.2 -0.3
Figure
-0.4 -0.5 Time (20ns/div)
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Supply Current (3mA/div)
Output Current (25mA/div)
TYPICAL CHARACTERISTICS: (Cont.)
+25°C, +10, 453, 100, unless otherwise noted.
OUTPUT VOLTAGE CURRENT LIMITATIONS
CLOSED-LOOP OUTPUT IMPEDANCE FREQUENCY
Internal Power
OPA657
Output Impedance
-100
Internal Power (mA)
0.01 Frequency (MHz)
COMMON-MODE REJECTION RATIO COMMON-MODE INPUT VOLTAGE
CMRR (dB)
Common-Mode Input Voltage
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APPLICATIONS INFORMATION
WIDEBAND, NON-INVERTING OPERATION
OPA657 provides unique combination input voltage noise, very high gain bandwidth, precision trimmed JFET-input stage give exceptional high input impedance, high gain stage amplifier. very high Gain Bandwidth Product (GBP) used either deliver high signal bandwidths high gains, extend achievable bandwidth gain photodiode-transimpedance applications. achieve full performance OPA657, careful attention board layout component selection required discussed following sections this data sheet. Figure shows noninverting gain circuit used basis most Typical Characteristics. Most curves were characterized using signal sources with driving impedance, with measurement equipment presenting load impedance. Figure shunt resistor terminal matches source impedance test generator, while series resistor terminal provides matching resistor measurement equipment load. Generally, data sheet voltage swing specifications output Figure while output power specifications matched load. total load output combined with total feedback network load, presents OPA657 with effective output load circuit Figure
0.1µF 6.8µF
bandwidth OPA657. lower non-inverting gains than minimum recommended gain OPA657, consider unity gain stable JFET input OPA656.
WIDEBAND, INVERTING GAIN OPERATION
There significant benefits operating OPA657 inverting amplifier. This particularly true when matched input impedance required. Figure shows inverting gain circuit used starting point typical characteristics showing inverting-mode performance.
0.1µF
6.8µF
Load
OPA657
Source
0.1µF
6.8µF
FIGURE Inverting Specifications Test Circuit. Driving this circuit from source, constraining gain resistor (RG) equal will give both signal bandwidth noise advantage. this case acting both input termination resistor gain setting resistor circuit. Although signal gain circuit Figure double that Figure their noise gains equal when source resistor included. This interesting effect doubling equivalent amplifier. This seen comparing small signal frequency response curves. Both show about 250MHz bandwidth, inverting configuration Figure giving higher signal gain. signal source actually impedance output another amplifier, should increased minimum value allowed output that amplifier adjusted desired gain. critical stable operation OPA657 that this driving amplifier show very output impedance through frequencies exceeding expected closed-loop bandwidth OPA657. Figure also shows noninverting input tied directly ground. Often, bias current canceling resistor ground included here null errors caused input bias currents. This only useful when input bias currents matched. JFET part like OPA657, input bias currents match begin with 5pA) that errors input bias currents negligible. Hence, resistor recommended noninverting input inverting signal gain condition.
Source Load
OPA657
6.8µF
0.1µF
FIGURE Noninverting Specifications Test Circuit. Voltage-feedback amps, unlike current-feedback amplifiers, wide range resistor values their gain. retain controlled frequency response noninverting voltage amplifier Figure parallel combination should always 150. noninverting configuration, parallel combination will form pole with parasitic input capacitance inverting node OPA657 (including layout parasitics). best performance, this pole should frequency greater than closed-loop
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WIDEBAND, HIGH SENSITIVITY, TRANSIMPEDANCE DESIGN
high input voltage current noise OPA657 make ideal wideband-transimpedance amplifier moderate high transimpedance gains. Unity-gain stability required application transimpedance amplifier. transimpedance design example shown front page data sheet. Designs that require high bandwidth from large area detector with relatively high transimpedance gain will benefit from input voltage noise OPA657. This input voltage noise peaked over frequency diode source capacitance, can, many cases, become limiting factor input sensitivity. elements design expected diode capacitance (CD) with reverse bias voltage (-VB) applied, desired transimpedance gain, OPA657 (1600MHz). Figure shows design from 50pF source capacitance diode through 200k transimpedance gain. With these variables (and including parasitic input capacitance OPA657 added CD), feedback capacitor value (CF) control frequency response.
This will give approximate -3dB bandwidth
f-3dB 2RFCD
example Figure will give approximately 5MHz flat bandwidth using 0.2pF feedback compensation. total output noise bandlimited frequency less than feedback pole frequency, very simple expression equivalent input noise current derived
2CDF)
Where: Equivalent input noise current output noise bandlimited 1/(2RFCF). Input current noise inverting input. Input voltage noise amp. Diode capacitance. Bandlimiting frequency (usually postfilter prior further signal processing). 1.6E 290°K
Supply Decoupling Shown
OPA657
200k 50pF 0.2pF
Evaluating this expression feedback pole frequency 3.9MHz circuit Figure gives equivalent input noise current 3.4pA/ This much higher than 1.2fA/ just itself. This result being dominated last term equivalent input noise expression. essential this case voltage noise like OPA657. lower transimpedance gain, wider bandwidth solutions needed, consider bipolar input OPA686 OPA687. These parts offer comparable gain bandwidth products much lower input noise voltage expense higher input current noise.
FIGURE Wideband, Noise, Transimpedance Amplifier. achieve maximally flat 2nd-order Butterworth frequency response, feedback pole should
1/(2RFCF (GPB /(4RFCD
GAIN COMPENSATION
Where gain desired, inverting operation acceptable, external compensation technique used retain full slew rate noise benefits OPA657 while maintaining increased loop gain associated improvement distortion offered decompensated architecture. This technique shapes loop gain good stability while giving easily controlled 2nd-order low-pass frequency response. Considering only noise gain circuit Figure low-frequency noise gain, (NG1) will resistor ratios while high frequency noise gain (NG2) will capacitor ratios. capacitor values both transition frequencies high-frequency noise gain. this noise gain, determined CS/CF, value greater than recommended minimum stable gain noise gain pole, 1/RFCF, placed correctly, very well controlled 2nd-order low-pass frequency response will result.
Adding common-mode differential mode input capacitance (0.7 4.5)pF 50pF diode source capacitance Figure targeting 200k transimpedance gain using 1600MHz OPA657 will require feedback pole 3.5MHz. This will require total feedback capacitance 0.2pF. Typical surface-mount resistors have parasitic capacitance 0.2pF, therefore, while Figure shows 0.2pF feedback-compensation capacitor, this will actually parasitic capacitance 200k resistor.
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OPA657
27pF 2.9pF
values shown Figure f-3dB will approximately 130MHz. This less than that predicted simply dividing product NG1. compensation network controls bandwidth lower value while providing full slew rate output exceptional distortion performance increased loop gain frequencies below capacitor values shown Figure calculated 10.5 with adjustment parasitics.
Gain (3dB/div)
FIGURE Broadband Gain Inverting External Compensation. choose values both parameters only three equations need solved. first parameter target high-frequency noise gain NG2, which should greater than minimum stable gain OPA657. Here, target 10.5 will used. second parameter desired low-frequency signal gain, which also sets lowfrequency noise gain NG1. simplify this discussion, will target maximally flat 2nd-order low-pass Butterworth frequency response 0.707). signal gain shown Figure will frequency noise gain RF/RG this example). Then, using only these gains OPA657 (1600MHz), frequency compensation determined
Frequency (MHz) 170MHz
FIGURE Frequency Response with External Compensation. Figure shows measured frequency response circuit Figure This showing expected gain with exceptional flatness through 70MHz -3dB bandwidth 170MHz. real benefit this compensation allow high slew rate, exceptional precision provide overshoot, fast settling pulse response. output step, 700V/µs slew rate OPA657 will allow rise time limited edge rate (2ns 170Mhz bandwidth). While unitygain stable amps offer comparable bandwidths, their lower slew rates will extend settling time larger steps. instance, OPA656 also provide 150MHz gain bandwidth implying 2.3ns transition time. However, lower slew rate this unity gain stable amplifier (290V/us) will limit step transition 3.5ns delay settling time slewing transition recovered. combination higher slew rate exceptional precision OPA657 yield fastest, most precise, pulse amplifiers using circuit Figure added benefit compensation Figure increase loop gain above that achievable comparable gains internally compensated amplifiers. circuit Figure will have lower harmonic distortion through 10Mhz than OPA656 operated gain
Physically, this (10.6MHz values shown above) 1/(2 RF(CF CS)) frequency which rising portion noise gain would intersect unity gain projected back gain. actual zero noise gain occurs pole noise gain occurs Since expressed multiply this solving:
RFZONG2
2.86pF)
Finally, since high-frequency noise gain, determine [Using 10.5]: (NG2 1)CF 27.2pF)
resulting closed-loop bandwidth will approximately equal
f-3dB
130MHz)
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OPERATING SUGGESTIONS
SETTING RESISTOR VALUES MINIMIZE NOISE
OPA657 provides very input noise voltage while requiring 14mA quiescent current. take full advantage this input noise, careful attention other possible noise contributors required. Figure shows noise analysis model with noise terms included. this model, noise terms taken noise voltage current density terms either
FREQUENCY RESPONSE CONTROL
Voltage-feedback amps exhibit decreasing closed-loop bandwidth signal gain increased. theory, this relationship described Gain Bandwidth Product (GBP) shown specifications. Ideally, dividing non-inverting signal gain (also called Noise Gain, will predict closed-loop bandwidth. practice, this only holds true when phase margin approaches 90°, does high-gain configurations. gains (increased feedback factors), most high-speed amplifiers will exhibit more complex response with lower phase margin. OPA657 compensated give maximally flat 2nd-order Butterworth closed-loop response noninverting gain (Figure This results typical gain bandwidth 275MHz, exceeding that predicted dividing 1600MHz Increasing gain will cause phase margin approach bandwidth more closely approach predicted value (GBP/NG). gain OPA657 will show 32MHz bandwidth predicted using simple formula typical 1600MHz. Inverting operation offers some interesting opportunities increase available gain-bandwidth product. When source impedance matched gain resistor (Figure signal gain -(RF/RG) while noise gain bandwidth purposes RF/RG). This cuts noise gain half, increasing minimum stable gain inverting operation under these condition equivalent gain bandwidth product 3.2GHz.
OPA657
4kTRS
4kTRF 1.6E -20J 290°K
FIGURE Noise Analysis Model. total output spot noise voltage computed square root squared contributing terms output noise voltage. This computation adding contributing noise powers output superposition, then taking square root back spot noise voltage. Equation shows general form this output noise voltage using terms shown Figure
ENI2 (IBNRS 4kTRS (IBIRF 4kTRFNG
DRIVING CAPACITIVE LOADS
most demanding very common load conditions capacitive loading. Often, capacitive load input converter including additional external capacitance which recommended improve linearity. high speed, high open-loop gain amplifier like OPA657 very susceptible decreased stability closed-loop response peaking when capacitive load placed directly output pin. When amplifier's open loop output resistance considered, this capacitive load introduces additional pole signal path that decrease phase margin. Several external solutions this problem have been suggested. When primary considerations frequency response flatness, pulse response fidelity and/or distortion, simplest most effective solution isolate capacitive load from feedback loop inserting series isolation resistor between amplifier output capacitive load. This does eliminate pole from loop response, rather shifts adds zero higher frequency. additional zero acts cancel phase from capacitive load pole, thus increasing phase margin improving stability.
Dividing this expression noise gain RF/RG) will give equivalent input referred spot noise voltage non-inverting input shown Equation
4kTRF ENI2 (IBNRS 4kTRS
Putting high resistor values into Equation quickly dominate total equivalent input referred noise. source impedance noninverting input 1.6k will Johnson voltage noise term equal just that amplifier itself (5nV/ Hz). While JFET input OPA657 ideal high source impedance applications, both overall bandwidth noise limited these higher source impedances non-inverting configuration Figure
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Typical Characteristics illustrate Recommended Capacitive Load resulting frequency response load. this case, design target maximally flat frequency response used. Lower values used some peaking tolerated. Also, operating higher gains (than used Typical Characteristics) will require lower values minimally peaked frequency response. Parasitic capacitive loads greater than begin degrade performance OPA657. Long board traces, unmatched cables, connections multiple devices easily cause this value exceeded. Always consider this effect carefully, recommended series resistor close possible OPA657 output (see Board Layout section).
D.C. ACCURACY OFFSET CONTROL
OPA657 provide excellent accuracy high open-loop gain, high common-mode rejection, high power-supply rejection, trimmed input offset voltage (and drift) along with negligible errors introduced input bias current. best precision, high-grade version (OPA657UB OPA657NB) screens parameters even tighter limit. Both standard- high-grade versions take advantage final test technique 100% test input offset voltage drift over temperature. This discussion will high-grade typical min/max electrical characteristics illustration, however, identical analysis applies standard-grade version. total output offset voltage configuration temperature will combination number possible error terms. JFET part like OPA657, input bias current terms typically quite unmatched. Using bias current cancellation techniques, more typical bipolar input amplifiers, does improve output offset errors. Errors input bias current will only become dominant elevated temperatures. OPA657 shows typical increase every 10°C common JFET-input stage amplifiers. Using maximum tested value 25°C, 20°C internal self heating (see thermal analysis), maximum input bias current 85°C ambient will 2(105 25)/10 1280pA. noninverting configurations, this term only begins significant term versus input offset voltage source impedances 750k. This would also feedback resistor value transimpedance applications (Figure where output error inverting input bias current order that contributed input offset voltage. general, except these extremely high-impedance values, output errors input bias current neglected. After input offset voltage itself, most significant term contributing output offset voltage PSRR negative supply. This term modeled input offset voltage shift changes negative power supply voltage (and similarly +PSRR). high-grade test limit -PSRR 68dB. This translates into 0.40mV/V input offset voltage shift 10(-68/20). This sensitivity negative supply voltage would require 1.5V change negative supply match ±0.6mV input offset voltage error. +PSRR tested minimum value 78dB. This translates into 10(-78/20) 0.125mV/V sensitivity input offset voltage positive power-supply changes. example, compute worst-case output error transimpedance circuit Figure 25°C then shift over 70°C range given following assumptions. Negative Power Supply ±0.2V with ±5mV/°C worst-case shift Positive Power Supply ±0.2V with ±5mV/°C worst-case shift Initial 25°C Output Error Band ±0.6mV (OPA657 high-grade input offset voltage limit) ±0.08mV (due -PSRR 0.4mV/V ±0.2V) ±0.04mV (due +PSRR 0.2mV/V ±0.2V) Total ±0.72mV
DISTORTION PERFORMANCE
OPA657 capable delivering distortion signal high frequencies over wide range gains. distortion plots Typical Characteristics show typical distortion under wide variety conditions. Generally, until fundamental signal reaches very high frequencies powers, 2nd-harmonic will dominate distortion with negligible 3rd-harmonic component. Focusing then 2nd-harmonic, increasing load impedance improves distortion directly. Remember that total load includes feedback network-in non-inverting configuration this while inverting configuration this just (Figure Increasing output voltage swing increases harmonic distortion directly. increase output swing will generally increase 2nd-harmonic 12dB 3rd-harmonic 18dB. Increasing signal gain will also increase 2nd-harmonic distortion. Again increase gain will increase 2nd- 3rd-harmonic about even with constant output power frequency. finally, distortion increases fundamental frequency increases rolloff loop gain with frequency. Conversely, distortion will improve going lower frequencies down dominant open loop pole approximately 100kHz. Starting from -70dBc 2nd-harmonic 5MHz, 2Vp-p fundamental into load (from Typical Characteristics), 2nd-harmonic distortion frequencies lower than 100kHz will approximately -90dBc. OPA657 extremely 3rd-order harmonic distortion. This also shows 2-tone 3rd-order intermodulation spurious (IM3) response curves. 3rd-order spurious levels extremely -80dBc) output power levels. output stage continues hold them even fundamental power reaches higher levels. Typical Characteristics show, spurious intermodulation powers increase predicted traditional intercept model. fundamental power level increases, dynamic range does decrease significantly. tones centered 10MHz, with 4dBm/tone into matched load (i.e., 1Vp-p each tone load, which requires 4Vp-p overall 2-tone envelope output pin), Typical Characteristics show 82dBc difference between test tone 3rd-order intermodulation spurious levels. This exceptional performance improves further when operating lower frequencies and/or higher load impedances.
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This would worst-case error band volume production 25°C acceptance testing given conditions stated. Over temperature range (0°C 70°C), expect following worst-case shifting from initial value. 20°C internal junction self-heating assumed here. ±0.36mV (OPA656 high-grade input offset drift) ±6µV/°C (70°C 20°C 25°C) ±0.11mV (-PSRR 66dB with (70°C 25°C) supply shift) ±0.04mV (+PSRR 76dB with (70°C 25°C) supply shift) Total ±0.51mV This would worst-case shift from initial offset over 70°C ambient conditions stated. Typical initial output error bands shifts over temperature will much lower than these worst-case estimates. transimpedance configuration, CMRR errors neglected since input common-mode voltage held ground. noninverting gain configurations (Figure CMRR term will need considered will typically lower than input offset voltage term. With tested minimum 91dB (28uV/V), added apparent error will more than ±0.06mV input swing circuit Figure
worst-case example, compute maximum using OPA657N (SOT23-5 package) circuit Figure operating maximum specified ambient temperature +85°C driving grounded load. 16.1mA (100 500)) 236mW Maximum +85°C (0.24W 150°C/W) 121°C. actual applications will operating lower internal power junction temperature.
BOARD LAYOUT
Achieving optimum performance with high-frequency amplifier like OPA657 requires careful attention board layout parasitics external component types. Recommendations that will optimize performance include: Minimize parasitic capacitance ground signal pins. Parasitic capacitance output inverting input pins cause instability-on noninverting input, react with source impedance cause unintentional bandlimiting. reduce unwanted capacitance, window around signal pins should opened ground power planes around those pins. Otherwise, ground power planes should unbroken elsewhere board. Minimize distance 0.25") from power-supply pins high-frequency 0.1uF decoupling capacitors. device pins, ground power plane layout should close proximity signal pins. Avoid narrow power ground traces minimize inductance between pins decoupling capacitors. power-supply connections should always decoupled with these capacitors. Larger (2.2µF 6.8µF) decoupling capacitors, effective lower frequency, should also used supply pins. These placed somewhat farther from device shared among several devices same area board. Careful selection placement external components will preserve high frequency performance OPA657. Resistors should very reactance type. Surface-mount resistors work best allow tighter overall layout. Metal film carbon composition axially leaded resistors also provide good high-frequency performance. Again, keep their leads board trace length short possible. Never wirewound-type resistors high-frequency application. Since output inverting input most sensitive parasitic capacitance, always position feedback series output resistor, any, close possible output pin. Other network components, such noninverting input termination resistors, should also placed close package. Where double-side component mounting allowed, place feedback resistor directly under package other side board between output inverting input pins. Even with parasitic capacitance shunting external resistors, excessively high resistor values create significant time constants that degrade performance. Good axial metal film surface-mount resistors have approximately 0.2pF shunt with resistor. resistor values 1.5k, this parasitic
POWER-SUPPLY CONSIDERATIONS
OPA657 intended operation supplies. Single-supply operation allowed with minimal change from stated specifications performance from single supply +12V maximum. limit lower supply voltage operation useable input voltage range JFET-input stage. Operating from single supply +12V have numerous advantages. With negative supply ground, errors -PSRR term minimized. Typically, performance improves slightly +12V operation with minimal increase supply current.
THERMAL ANALYSIS
OPA657 will require heatsinking airflow most applications. Maximum desired junction temperature will maximum allowed internal power dissipation described below. case should maximum junction temperature allowed exceed 175°C. Operating junction temperature (TJ) given total internal power dissipation (PD) quiescent power (PDQ) additional power dissipated output stage (PDL) deliver load power. Quiescent power simply specified no-load supply current times total supply voltage across part. will depend required output signal load would-for grounded resistive load-be maximum when output fixed voltage equal either supply voltage (for equal bipolar supplies). Under this condition VS2/(4 where includes feedback network loading. Note that power output stage into load that determines internal power dissipation.
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capacitance pole and/or zero below 500MHz that effect circuit operation. Keep resistor values possible consistent with load driving considerations. been suggested here that good starting point design would keep voltage amplifier applications. Doing this will automatically keep resistor noise terms low, minimize effect their parasitic capacitance. Transimpedance applications (Figure whatever feedback resistor required application long feedback-compensation capacitor considering parasitic capacitance terms inverting node. Connections other wideband devices board made with short direct traces through onboard transmission lines. short connections, consider trace input next device lumped capacitive load. Relatively wide traces (50mils 100mils) should used, preferably with ground power planes opened around them. Estimate total capacitive load from plot Recommended Capacitive Load. parasitic capacitive loads 5pF) need since OPA657 nominally compensated operate with parasitic load. Higher parasitic capacitive loads without allowed signal gain increases (increasing unloaded phase margin) long trace required, signal loss intrinsic doubly-terminated transmission line acceptable, implement matched-impedance transmission line using microstrip stripline techniques (consult design handbook microstrip stripline layout techniques). environment normally necessary onboard, fact higher impedance environment will improve distortion shown distortion versus load plots. With characteristic board trace impedance defined based board material trace dimensions, matching series resistor into trace from output OPA657 used well terminating shunt resistor input destination device. Remember also that terminating impedance will parallel combination shunt resistor input impedance destination device- this total effective impedance should match trace impedance. attenuation doubly-terminated transmission line unacceptable, long trace series-terminated source only. Treat trace capacitive load this case series resistor value shown plot Capacitive Load. This will preserve signal integrity well doubly-terminated line. input impedance destination device low, there will some signal attenuation voltage divider formed series output into terminating impedance.
Socketing high-speed part like OPA657 recommended. additional lead length pin-to-pin capacitance introduced socket create extremely troublesome parasitic network which make almost impossible achieve smooth, stable frequency response. Best results obtained soldering OPA657 onto board.
INPUT PROTECTION
OPA657 built using very high-speed complementary bipolar process. internal junction breakdown voltages relatively these very small geometry devices. These breakdowns reflected Absolute Maximum Ratings table. device pins protected with internal protection diodes power supplies shown Figure
External
Internal Circuitry
FIGURE Internal Protection. These diodes provide moderate protection input overdrive voltages above supplies well. protection diodes typically support 30mA continuous current. Where higher currents possible (e.g., systems with ±12V supply parts driving into OPA657), current limiting series resistors should added into inputs. Keep these resistor values possible since high values degrade both noise performance frequency response.
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PACKAGE DRAWINGS
MSOI002B JANUARY 1995 REVISED SEPTEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 0.010 (0,25)
PLASTIC SMALL-OUTLINE PACKAGE
0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81)
0.008 (0,20)
Gage Plane 0.044 (1,12) 0.016 (0,40)
0.010 (0,25)
Seating Plane 0.069 (1,75) 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS
0.197 (5,00) 0.189 (4,80)
0.344 (8,75) 0.337 (8,55)
0.394 (10,00) 0.386 (9,80)
4040047/E 09/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0.006 (0,15). Falls within JEDEC MS-012
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PACKAGE DRAWINGS (Cont.) (R-PDSO-G5)
MPDS018D FEBRUARY 1996 REVISED JANUARY 2001
PLASTIC SMALL-OUTLINE
0,95
0,50 0,30
0,20
1,70 1,50
3,00 2,60
0,15
3,00 2,80
Gage Plane
0,25 0°-8° 0,55 0,35
Seating Plane 1,45 0,95 0,05 0,10 4073253-4/F 10/00
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion. Falls within JEDEC MO-178
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PACKAGE OPTION ADDENDUM
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3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE OPA657N/250 OPA657N/3K OPA657NB/250 OPA657NB/3K OPA657U OPA657U/2K5 OPA657UB OPA657UB/2K5 STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE SOIC SOIC SOIC SOIC PACKAGE DRAWING PINS PACKAGE 3000 3000 2500 2500
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
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