Quad 3-State Flip-Flop with Common Clock Reset MC74HC173A identic
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Quad 3-State Flip-Flop with Common Clock Reset
MC74HC173A identical pinout LS173. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. Data, when enabled, clocked into four flip-flops with rising edge common Clock. When either both Output Enable Controls high, outputs high-impedance state. This feature allows HC173A used bus-oriented systems. Reset feature asynchronous active high. Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity FETs Equivalent Gates LOGIC DIAGRAM
MC74HC173A
SUFFIX 16-LEAD PLASTIC PACKAGE CASE 648-08
SUFFIX 16-LEAD PLASTIC SOIC PACKAGE CASE 751B-05
ORDERING INFORMATION MC74HCXXXAN MC74HCXXXAD Plastic SOIC
ASSIGNMENT
3-STATE NONINVERTING OUTPUTS RESET
DATA INPUTS
CLOCK RESET OUTPUT ENABLES
DATA- ENABLES
CLOCK
FUNCTION TABLE
Inputs Output Enables Reset Clock Data Enables Data Output
Change Change Change Change Change High Impedance High Impedance High Impedance
6/97
Motorola, Inc. 1997
MC74HC173A
MAXIMUM RATINGS*
Symbol Vout Iout Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Storage Temperature Plastic SOIC Package Tstg
Lead Temperature, from Case Seconds (Plastic SOIC Package)
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Recommended Operating Conditions. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Unit Supply Voltage (Referenced GND)
Vin, Vout
Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure
1000
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
25_C 3.15 1.35
85_C 125_C
3.15 1.35 3.15 1.35
Unit
Minimum High-Level Input Voltage
Vout |Iout|
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage
|Iout|
Maximum Low-Level Output Voltage
|Iout| |Iout| |Iout| |Iout|
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
|Iout| |Iout| |Iout|
0.26 0.26 0.26
0.33 0.33 0.33
0.40 0.40 0.40
High-Speed CMOS Logic Data DL129
MC74HC173A
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Guaranteed Limit Symbol Parameter Test Conditions 25_C
85_C 125_C
Unit
Maximum Input Leakage Current Maximum Three-State Leakage Current
Output High-Impedance State Vout Iout
Maximum Quiescent Supply Current (per Package)
NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS Input
Guaranteed Limit Symbol fmax Parameter 25_C
85_C 125_C
Unit
Maximum Clock Frequency (50% Duty Cycle) (Figures
tPLH, tPHL
Maximum Propagation Delay, Clock (Figures
tPHL
Maximum Propagation Delay, Reset (Figures
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable (Figures
tPZL, tPZH
Maximum Propagation Delay, Output Enable (Figures
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
Cout
Maximum Three-State Output Capacitance (Output High-Impedance State)
NOTES: propagation delays with loads other than Chapter Motorola High-Speed CMOS Data Book (DL129/D). Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Flip-Flop)*
Used determine no-load dynamic power consumption: load considerations, Chapter Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129
MC74HC173A
TIMING REQUIREMENTS (Input
Guaranteed Limit Symbol Parameter 25_C
85_C 125_C
Unit
Minimum Setup Time, Input Clock (Figure
Minimum Hold Time, Clock Input (Figure
trec
Minimum Recovery Time, Reset Inactive Clock (Figure
Minimum Pulse Width, Clock (Figure
Minimum Pulse Width, Reset (Figure
Maximum Input Rise Fall Times (Figure
1000
1000
1000
NOTE: Information typical parametric values found Chapter Motorola High-Speed CMOS Data Book (DL129/D).
DESCRIPTIONS
INPUTS (Pins 4-bit data inputs. Data these pins, when enabled Data-Enable Controls, entered into flip-flops rising edge clock. CLOCK (Pin Clock input. OUTPUTS (Pins 3-state register outputs. During normal operation device, outputs flip-flops appear these pins. During 3-state operation, these outputs assume high- impedance state.
CONTROL INPUT Reset (Pin Asynchronous reset input. high level this resets flip-flops forces outputs low, they already high-impedance state. DE1, (Pins Active-low Data Enable Control inputs. When both Data Enable Controls low, data inputs loaded into flip-flops with rising edge Clock input. When either both these controls high, there change state flip-flops, regardless changes Clock inputs. OE1, (Pins Output Enable Control inputs. When either both Output Enable Controls high, outputs device high-impedance state. When both controls low, device outputs display data flip-flops.
High-Speed CMOS Logic Data DL129
MC74HC173A
SWITCHING WAVEFORMS
CLOCK 1/fmax tPLH tTLH tTHL tPHL tPHL trec CLOCK RESET
Figure
Figure
tPZL tPZH tPHZ HIGH IMPEDANCE CLOCK tPLZ HIGH IMPEDANCE VALID INPUT
Figure
Figure
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST TEST POINT OUTPUT CONNECT WHEN TESTING tPLZ tPZL. CONNECT WHEN TESTING tPHZ tPZH.
DEVICE UNDER TEST
Includes probe capacitance
Includes probe capacitance
Figure
Figure
High-Speed CMOS Logic Data DL129
MC74HC173A
LOGIC DETAIL
DATA INPUTS
DATA- ENABLES
RESET
CLOCK OUTPUT ENABLES
High-Speed CMOS Logic Data DL129
MC74HC173A
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 2.54 0.050 1.27 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0.020 0.040 0.51 1.01
0.25 (0.010)
SEATING PLANE
SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE
0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 0.25 0.19 0.25 0.10 6.20 5.80 0.50 0.25 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
SEATING
PLANE
0.25 (0.010)
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High-Speed CMOS Logic Data DL129
MC74HC173A/D
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