12-Bit Serial Input Multiplying CMOS Converter DAC8043 CONNECTION

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12-Bit Serial Input Multiplying CMOS Converter DAC8043 CONNECTION

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FEATURES 12-Bit Accuracy 8-Pin Mini-DIP Fast Serial Data Input Double Data Buffers Gain Error: ppm/ Tempco Resistant Cost Available Form APPLICATIONS Autocalibration Systems Process Control Industrial Automation Programmable Amplifiers Attenuators Digitally-Controlled Filters
12-Bit Serial Input Multiplying CMOS Converter DAC8043
CONNECTIONS GENERAL DESCRIPTION 8-Pin Epoxy (P-Suffix) 8-Pin Cerdip (Z-Suffix)
DAC8043 high accuracy 12-bit CMOS multiplying space-saving 8-pin mini-DIP package. Featuring serial data input, double buffering, excellent analog performance, DAC8043 ideal applications where board space premium. Also, improved linearity gain error performance permit reduced parts count through elimination trimming components. Separate input clock load control lines allow full user control data loading analog output. circuit consists 12-bit serial-in, parallel-out shift register, 12-bit register, 12-bit CMOS DAC, control logic. Serial data clocked into input register rising edge CLOCK pulse. When data word been clocked loaded into register with input pin. Data register converted output current converter. DAC8043's fast interface timing reduce timing design considerations while minimizing microprocessor wait states. applications requiring asynchronous CLEAR function more versatile microprocessor interface logic, refer PM-7543. Operating from single power supply, DAC8043 ideal power, small size, high performance solution many application problems. available plastic cerdip packages that compatible with auto-insertion equipment.
16-Lead Wide-Body (S-Suffix)
N.C. N.C. VREF N.C. N.C.
DAC8043
VIEW IOUT (Not Scale) N.C. N.C. N.C.
CONNECT
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
DAC8043-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
STATIC ACCURACY Resolution Nonlinearity (Note Differential Nonlinearity (Note Gain Error (Note
IOUT Full Temperature Range specified under Absolute Maximum Ratings unless otherwise noted).
Symbol
GFSE
Conditions
DAC8043
Units
Bits ppm/°C
DAC8043A/E/G DAC8043F DAC8043A/E DAC8043F/G +25°C DAC8043A/E DAC8043F/G Full Temperature Range Grades
Gain Tempco Gain/ Temp) (Note Power Supply Rejection Ratio Gain/ VDD) Output Leakage Current (Note
TCGFS +25°C Full Temperature Range DAC8043A DAC8043E/F/G +25°C Full Temperature Range DAC8043A DAC8043E/F/G 0.0006
PSRR ILKG
0.002 0.03 0.61 0.15
Zero Scale Error (Notes
IZSE
Input Resistance (Note PERFORMANCE Output Current Settling Time (Notes Digital Analog Glitch Energy (Note Feedthrough Error (VREF IOUT) (Note Total Harmonic Distortion (Note Output Noise Voltage Density (Note DIGITAL INPUTS Digital Input HIGH Digital Input Input Leakage Current (Note Input Capacitance (Note ANALOG OUTPUTS Output Capacitance (Note
+25°C VREF IOUT Load CEXT Register Loaded Alternately with VREF Digital Input 0000 0000 0000 +25°C VREF Register Loaded with between IOUT
0.25
nV/Hz
COUT
Digital Inputs Digital Inputs
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DAC8043
DAC8043
Parameter Symbol Conditions Units TIMING CHARACTERISTICS (NOTES Data Setup Time Data Hold Time Clock Pulse Width High Clock Pulse Width Load Pulse Width Clock Into Input Register Load Register Time tASB POWER SUPPLY Supply Voltage Supply Current
Full Temperature Range Full Temperature Range Full Temperature Range Full Temperature Range Full Temperature Range Full Temperature Range
4.75 5.25
Digital Inputs Digital Inputs
NOTES 0.012% full scale. grades monotonic 12-bits over temperature. Using internal feedback resistor. Applies OUT; digital inputs Guaranteed design tested. IOUT Load CEXT digital input Extrapolated LSB; propagation delay where measured time constant final decay. VREF digital inputs Absolute temperature coefficient less than +300 ppm/°C. Digital inputs CMOS gates; typically +25°C. VREF digital inputs digit inputs Calculated from worst case REF: IZSE LSBs) (RREF ILKG 4096)/VREF. Calculations from where: Boltzmann constant, J/°K, resistance, resistor temperature, bandwidth, Tested VDD. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
CAUTION
.+17 VREF VRFB Digital Input Voltage Range -0.3 Output Voltage (Pin -0.3 Operating Temperature Range Versions -55°C +125°C EZ/FZ/FP Versions -40°C +85°C Version +70°C Junction Temperature +150°C Storage Temperature -65°C +150°C Lead Temperature (Soldering, sec) +300°C Package Type 8-Pin Hermetic 8-Pin Plastic
apply voltages higher than less than potential terminal except VREF (Pin (Pin digital control inputs Zener-protected; however, permanent damage occur unprotected units from high energy electrostatic fields. Keep units conductive foam times until ready use. proper antistatic handling procedures. Absolute Maximum Ratings apply both packaged devices DICE. Stresses above those listed under Absolute Maximum Ratings cause permanent damage device.
ORDERING GUIDE1
Model DAC8043AZ2 DAC8043AZ/8832 DAC8043EZ DAC8043FS DAC8043FZ DAC8043FP DAC8043GP DAC8043HP Relative Accuracy Temperature Range -55°C +125°C -55°C +125°C -40°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C +70°C +70°C Package Option 8-Pin Cerdip 8-Pin Cerdip 8-Pin Cerdip 16-Lead (Wide) 8-Pin Cerdip 8-Pin Epoxy 8-Pin Epoxy 8-Pin Epoxy
Units °C/W °C/W
specified worst case mounting conditions, socket cerdip P-DIP packages.
specified device
NOTES commercial industrial temperature range parts available with burn-in. devices processed total compliance MIL-STD-883, add/883 after part number. Consult factory data sheet.
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DAC8043 WAFER TEST LIMITS
Parameter STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Power Supply Rejection Ratio Output Leakage Current (IOUT) REFERENCE INPUT Input Resistance DIGITAL INPUTS Digital Input HIGH Digital Input Input Leakage Current POWER SUPPLY Supply Current
VREF IOUT
Symbol GFSE PSRR ILKG Conditions DAC8043GBC Limit 0.002 7/15 Units Bits min/max
Using Internal Feedback Resistor Digital Inputs
Digital Inputs Digital Inputs
NOTE Electrical tests performed wafer probe limits shown. variations assembly methods normal yield loss, yield after packaging guaranteed standard product dice. Consult factory negotiate specifications based dice qualifications through sample assembly testing.
DICE CHARACTERISTICS
VREF IOUT Substate (die backside) internally connected VDD.
SIZE 0.116 0.109 inch, 12,644 mils (2.95 2.77 8.17
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although DAC8043 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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DAC8043 TYPICAL PERFORMANCE CHARACTERISTICS
Gain Frequency (Output Amplifier: OP42)
Total Harmonic Distortion Frequency (Multiplying Mode)
Supply Current Logic Input Voltage
Linearity Error Digital Code
Linearity Error Reference Voltage
Logic Threshold Voltage Supply Voltage
Error Reference Voltage
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DAC8043
PARAMETER DEFINITIONS
INTEGRAL NONLINEARITY (INL)
This single most important specification. measures maximum deviation analog output (from ideal) from straight line drawn between points. expressed percent full-scale range terms LSBs. Refer 1988 Data Book section additional digitalto-analog converter definitions.
INTERFACE LOGIC INFORMATION
DAC8043 been designed ease operation. timing diagram illustrates input register loading sequence. Note that most significant (MSB) loaded first. Once input register full, data transferred register taking momentarily low.
DIGITAL SECTION
Figure Digital Input Protection
digital circuitry forms interface which serial data loaded under microprocessor control into 12-bit shift register then transferred, parallel, 12-bit register. simplified circuit DAC8043 shown Figure inverted R-2R ladder network consisting silicon-chrome, highly-stable (+50 ppm/°C) thin-film resistors, twelve pairs NMOS current-steering switches. These switches steer binarily weighted currents into either IOUT GND; this yields constant current each ladder leg, regardless digital input code. This constant current results constant input resistance VREF equal VREF input driven reference voltage current, that within limits stated Absolute Maximum Ratings. twelve output current-steering NMOS switches series with each R-2R resistor, they introduce errors same resistance value. They were designed such that switch "ON" resistance binarily scaled that voltage drop across each switch remains constant. example, switch Figure designed with "ON" resistance switch etc., constant drop will then maintained across each switch.
DAC8043's digital inputs, SRI, CLK, compatible. input voltage levels affect amount current drawn from supply; peak supply current occurs digital input (VIN) passes through transition region. Supply Current Logic Input Voltage graph located under typical performance characteristics curves. Maintaining digital input voltage levels close possible supplies, GND, minimizes supply current consumption. DAC8043's digital inputs have been designed with resistance incorporated through careful layout inclusion input protection circuitry. Figure shows input protection diodes series resistor; this input structure duplicated each digital input. High voltage static charges applied inputs shunted supply ground rails through forward biased diodes. These protection diodes were designed clamp inputs well below dangerous levels during static discharge conditions.
GENERAL CIRCUIT INFORMATION
DAC8043 12-bit multiplying converter with very temperature coefficient. contains R-2R resistor ladder network, data input control logic, data registers.
Write Cycle Timing Diagram
REV.
DAC8043
further insure accuracy across full temperature range, permanently "ON" switches were included series with feedback resistor R-2R ladder's terminating resistor. "Simplified Circuit," Figure shows location series switches. These series switches equivalently scaled times switch (MSB) switch (LSB) respectively maintain constant relative voltage drops with varying temperature. During testing resistor ladder RFEEDBACK (such incoming inspection), must present turn "ON" these series switches.
DYNAMIC PERFORMANCE
OUTPUT IMPEDANCE
DAC8043's output resistance, case output capacitance, varies with digital input code. This resistance, looking back into IOUT terminal, between (the feedback resistor alone when digital inputs LOW) (the feedback resistor parallel with approximate R-2R ladder network resistance when single logic HIGH). Static accuracy dynamic performance will affected these variations. This variation best illustrated using circuit Figure equation: VERROR where function digital code, and: more than four bits logic single logic Therefore, offset gain varies follows: code 0011 1111 1111, VERROR1 code 0100 0000 0000,
Figure Simplified Circuit
EQUIVALENT CIRCUIT ANALYSIS
VERROR2 error difference VOS.
Figure shows equivalent analog circuit DAC8043. VREF)/R current source code dependent current generated DAC. current source ILKG consists surface junction leakages doubles approximately every 10°C. COUT output capacitance; result N-channel switches varies from depending digital input code. equivalent output resistance that also varies with digital input code. nominal R-2R resistor ladder resistance.
Since weight (for VREF DAC8043, clearly important that minimized, either using amplifier's nulling pins, external nulling network, selection amplifier with inherently VOS. Amplifiers with sufficiently include ADI's OP77, OP07, OP27, OP42.
Figure Equivalent Analog Circuit Figure Simplified Circuit
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DAC8043
gain phase stability output amplifier, board layout, power supply decoupling will affect dynamic performance. small compensation capacitor required when high-speed operational amplifiers used. connected across amplifier's feedback resistor provide necessary phase compensation critically damp output. DAC8043's output capacitance resistor form pole that must outside amplifier's unity gain crossover frequency. considerations when using high-speed amplifiers are: Phase compensation (see Figures Power supply decoupling device socket proper grounding techniques.
Figure Unipolar Operation with Fast Gain Error Trimming (2-Quadrant)
APPLICATIONS INFORMATION
APPLICATION TIPS
most applications, linearity depends upon potential IOUT (pins being exactly equal each other. most applications, connected external with noninverting input tied ground (see Figures amplifier selected should have input bias current drift over temperature. amplifier's input offset voltage should nulled less than +200 (less than LSB). operational amplifier's noninverting input should have minimum resistance connection ground; usual bias current compensation resistor should used. This resistor cause variable offset voltage appearing varying output error. grounded pins should single common ground point, avoiding ground loops. power supply should have noise level with transients greater than
UNIPOLAR OPERATION (2-QUADRANT)
analog output shown Table limiting parameters VREF range maximum input voltage range whichever lowest. Gain error trimmed adjusting shown Figure register must first loaded with then adjusted until VOUT -VREF (4095/4096). case adjustable VREF, omitted, with VREF adjusted yield desired full-scale output. most applications DAC8043's negligible zero scale error very gain error permit elimination trimming components external without adverse effects circuit performance.
Table Unipolar Code Table
Digital Input 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Nominal Analog Output (VOUT shown Figures
4095 -VREF 4096
circuit shown Figures used with reference voltage. circuit's output will range between approximately -VREF (4095/4096) depending upon digital input code. relationship between digital input
-VREF 4096
2048 VREF -VREF 4096 2047 -VREF 4096
2049
-VREF 4096 -VREF
4096
NOTES Nominal full scale circuits Figures given -VREF
Figure Unipolar Operation with High Accuracy (2-Quadrant)
4095 4096
VREF (2-n). 4096
Nominal magnitude circuits Figures given VREF
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DAC8043
Table Bipolar (Offset Binary) Code Table
Digital Input 1111 1111 1111
Nominal Analog Output (VOUT Shown Figure
2047 +VREF 2048 +VREF 2048
Resistors must selected match within 0.01% must same (preferably metal foil) type assure temperature coefficient matching. Mismatching between causes offset full scale errors while mismatch will result full-scale error. Calibration performed loading register with 1000 0000 0000 adjusting until VOUT omitted, adjusting ratio yield VOUT Full scale adjusted loading register with 1111 1111 1111 either adjusting amplitude VREF value until desired VOUT achieved.
ANALOG/DIGITAL DIVISION
1000 0000 0001 1000 0000 0000 0111 1111 1111
-VREF 2048 -VREF 2048
2048 -VREF 2048
2047
transfer function DAC8043 connected multiplying mode shown Figures
-VIN
0000 0000 0001
0000 0000 0000
where assumes value "ON" "OFF" bit. transfer function modified when connected feedback operational amplifier shown Figure becomes:
NOTES Nominal full scale circuit Figure given VREF
2047 2048 2048
Nominal magnitude circuit Figure given VREF
BIPOLAR OPERATION (4-QUADRANT)
Figure details suggested circuit bipolar, offset binary operation. Table shows digital input analog output relationship. circuit uses offset binary coding. Two's complement code converted offset binary software inversion addition external inverter input.
above transfer function division analog voltage (VREF) digital word. amplifier goes rails with bits "OFF" since division zero infinity. With bits "ON," gain LSB). gain becomes 4096 with LSB, "ON."
Figure Bipolar Operation (4-Quadrant, Offset Binary)
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DAC8043
DAC8043 INTERFACE 8085
DAC8043's interface 8085 microprocessor shown Figure Note that microprocessor's line used present data serially DAC. Data clocked into DAC8043 executing memory write instructions. clock input generated decoding address 8000 Data loaded into register with memory write instruction address A000. Serial data supplied DAC8043 must present right justified format registers microprocessor.
Figure Analog/Digital Divider
INTERFACING MC6800
shown Figure DAC8043 interfaced 6800 successively executing memory WRITE instructions while manipulating data between WRITEs, that each WRITE presents next bit. this example most significant bits found memory location 0000 0001. four MSBs found lower half 0000, eight LSBs 0001. data taken from line. serial data loading triggered pulse which asserted decoded memory WRITE memory location 2000, R/W, WRITE address 4000 transfers data from input register register.
Figure DAC8043-8085 Interface
DAC8043 68000 INTERFACING
DAC8043 interfacing 68000 microprocessor shown Figure Again, serial data taken from microprocessor's data lines.
Figure DAC8043-MC6800 Interface
Figure DAC8043-68000 Interface
-10-
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-11-
-12-
000000000
PRINTED U.S.A.

12-Bit Serial Input Multiplying CMOS Converter DAC8043 CONNECTION

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