AC'97 SoundMAX® Codec AD1881A ENHANCED FEATURES Mobile Power Mixe

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AC'97 SoundMAX® Codec AD1881A ENHANCED FEATURES Mobile Power Mixe

Datasheet Thumbnail

Top Searches for this datasheet

AC'97 FEATURES Variable Sample Rate True Line-Level Output Supports Secondary Codec Modes
AC'97 SoundMAX® Codec AD1881A
ENHANCED FEATURES Mobile Power Mixer Mode Digital Audio Mixer Mode Full Duplex Variable Sampling Rate with Resolution PHATStereo Stereo Enhancement Split Power Supplies (3.3 Digital/5 Analog) Extended 6-Bit Master Volume Control Audio Power-Down Signal
AC'97 FEATURES Designed AC'97 Analog Component 48-Lead LQFP Package Multibit Converter Architecture Improved Ratio Greater than 16-Bit Stereo Full-Duplex Codec Four Analog Line-Level Stereo Inputs Connection from LINE, VIDEO, Analog Line-Level Mono Inputs Speakerphone BEEP Mono Input Switchable from External Sources High Quality Input with Ground Sense Stereo Line-Level Output Mono Output Speakerphone Internal Speaker Power Management Support FUNCTIONAL BLOCK DIAGRAM
EAPD
MODE
AD1881A
MODE/SYNCHRONIZER
MIC1 MIC2 LINE_IN
0dB/ 20dB
VIDEO PHONE_IN
SELECTOR
16-BIT CONVERTER
16-BIT CONVERTER
RESET
SYNC MONO_OUT
LINK
SAMPLE RATE GENERATORS
BIT_CLK
LNLVL_OUT_L
SDATA_OUT
LINE_OUT_L
PHAT STEREO
16-BIT CONVERTER
SDATA_IN
LINE_OUT_R
PHAT STEREO
16-BIT CONVERTER
LNLVL_OUT_R PC_BEEP
GAIN ATTENUATE MUTE MASTER VOLUME CONNECT
OSCILLATORS
XTL_OUT
XTL_IN
SoundMAX registered trademark PHAT trademark Analog Device, Inc.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2000
AD1881A-SPECIFICATIONS
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply (VDD) Analog Supply (VCC) Sample Rate (FS) Input Signal 1008 Test Conditions Calibrated Attenuation Relative Full-Scale Input Output Load Test Conditions Calibrated Gain Input -3.0 Relative Full-Scale
ANALOG INPUT
Parameter Input Voltage (RMS Values Assume Sine Wave Input) LINE_IN, AUX, VIDEO, PHONE_IN, PC_BEEP with Gain (M20 with Gain (M20 Input Impedance* Input Capacitance*
MASTER VOLUME
2.83 0.283 2.83
Unit
Parameter Step Size -94.5 dB); LINE_OUT_L, LINE_OUT_R Output Attenuation Range Span* Step Size -46.5 dB); MONO_OUT Output Attenuation Range Span* Mute Attenuation Fundamental*
PROGRAMMABLE GAIN AMPLIFIER-ADC
-94.5 -46.5
Unit
Parameter Step Size 22.5 Gain Range Span
ANALOG MIXER-INPUT GAIN/AMPLIFIERS/ATTENUATORS
22.5
Unit
Parameter Signal-to-Noise Ratio (SNR) LINE_OUT Other LINE_OUT Step Size (+12 -34.5 dB): (All Steps Tested) MIC, LINE_IN, AUX, VIDEO, PHONE_IN, Input Gain/Attenuation Range: MIC, LINE, AUX, VIDEO, PHONE_IN, Step Size dB): (All Steps Tested) PC_BEEP Input Gain/Attenuation Range: PC_BEEP
*Guaranteed, tested. Specifications subject change without notice.
-46.5
Unit
REV.
AD1881A
DIGITAL DECIMATION INTERPOLATION FILTERS*
Parameter Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband
ANALOG-TO-DIGITAL CONVERTERS
0.09
Unit
12/FS
Parameter Resolution Total Harmonic Distortion (THD) Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Crosstalk* Line Inputs (Input Ground Read Input Ground Read LINE_IN Other Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Offset Error
DIGITAL-TO-ANALOG CONVERTERS
0.02
Unit Bits
-100 10.5
Parameter Resolution Total Harmonic Distortion (THD) LINE_OUT, LNLVL_OUT Dynamic Range (-60 Input THD+N Referenced Full Scale, A-Weighted) Signal-to-Intermodulation Distortion* (CCIF Method) Gain Error (Full-Scale Span Relative Nominal Input Voltage) Interchannel Gain Mismatch (Difference Gain Errors) Crosstalk* (Input Zero Measure R_OUT; Input Zero Measure L_OUT) Total Audible Out-of-Band Energy (Measured from kHz)*
ANALOG OUTPUT
0.02
Unit Bits
Parameter Full-Scale Output Voltage (LINE_OUT, LNLVL_OUT) Output Impedance* External Load Impedance* Output Capacitance* External Load Capacitance VREF VREF_OUT Mute Click (Muted Output Minus Unmuted Midscale Output)
*Guaranteed, tested. Specifications subject change without notice.
2.83
Unit
REV.
AD1881A-SPECIFICATIONS
STATIC DIGITAL SPECIFICATIONS
Parameter High Level Input Voltage (VIH Digital Inputs Level Input Voltage (VIL High Level Output Voltage (VOH -0.5 Level Output Voltage (VOL +0.5 Input Leakage Current Output Leakage Current
POWER SUPPLY
0.65 DVDD DVDD
0.35 DVDD DVDD
Unit
Parameter Power Supply Range Analog Power Supply Range Digital (3.3 Power Dissipation V/3.3 Analog Supply Current Digital Supply Current Power Supply Rejection (100 Signal kHz)* Both Analog Digital Supply Pins, Both ADCs DACs)
CLOCK SPECIFICATIONS*
4.75
5.25
Unit
Parameter Input Clock Frequency Recommended Clock Duty Cycle
POWER-DOWN MODE
Unit
24.576
Parameter Mixer (Analog Mixer Mixer Mixer Mixer Analog Only (AC-Link Analog Only (AC-Link Off) Standby
*Guaranteed, tested. Specifications subject change without notice.
Bits PR1, LPMIX, PR1, PR2, PR2, PR2, PR1, LPMIX, PR5, PR1, LPMIX, PR1, PR0, PR4, PR5, PR4, PR3, PR2, PR1,
DVDD (3.3
AVDD
Unit
REV.
AD1881A
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter RESET Active Pulsewidth RESET Inactive BIT_CLK Startup Delay SYNC Active High Pulsewidth SYNC Pulsewidth SYNC Inactive BIT_CLK Startup Delay BIT_CLK Frequency BIT_CLK Period BIT_CLK Output Jitter2 BIT_CLK High Pulsewidth BIT_CLK Pulsewidth SYNC Frequency SYNC Period Setup Falling Edge BIT_CLK Hold from Falling Edge BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time Slot BIT_CLK, SDATA_IN Setup Trailing Edge RESET (Applies SYNC, SDATA_OUT) Rising Edge RESET HI-Z Delay (ATE Test Mode) Propagation Delay RESET Rise Time
NOTES Guaranteed, tested. Output jitter directly dependent crystal input jitter. Specifications subject change without notice.
Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW tSYNC_PERIOD tSETUP tHOLD tRISECLK tFALLCLK tRISESYNC tFALLSYNC tRISEDIN tFALLDIN tRISEDOUT tFALLDOUT tS2_PDOWN tSETUP2RST tOFF
Unit
19.5 162.8 12.288 81.4 36.62 36.62 40.69 40.69 48.0 20.8 44.76 44.76
REV.
AD1881A
tRST_LOW
RESET
tRST2CLK
BIT_CLK
tRISECLK
SYNC
tFALLCLK
BIT_CLK
Figure Cold Reset
tRISESYNC
SDATA_IN
tFALLSYNC
tSYNC_HIGH
SYNC BIT_CLK
tRST2CLK
SDATA_OUT
tRISEDIN
tFALLDIN
tRISEDOUT
tFALLDOUT
Figure Warm Reset
Figure Signal Rise Fall Time
tCLK_LOW
BIT_CLK
tCLK_HIGH tCLK_PERIOD
SYNC
SLOT
SLOT
BIT_CLK
tSYNC_LOW
SYNC
SDATA_OUT
WRITE 0x26
DATA
DON'T CARE
tSYNC_HIGH tSYNC_PERIOD
SDATA_IN
tS2_PDOWN
NOTE: BIT_CLK SCALE
Figure Clock Timing
Figure Link Power Mode Timing
tSETUP
RESET
BIT_CLK
SDATA_OUT
SYNC SDATA_OUT
tSETUP2RST
SDATA_IN, BIT_CLK HI-Z
tHOLD
tOFF
Figure Data Setup Hold
Figure Test Mode
REV.
AD1881A
ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE
Parameter Power Supplies Digital (VDD) Analog (VCC) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Ambient Temperature (Operating) Storage Temperature
-0.3 -0.3 -0.3 -0.3
+3.6 +6.0 +150
Unit Model
Temperature Range
Package Description 48-Lead LQFP
Package Option ST-48
AD1881AJST 70°C
ENVIRONMENTAL CONDITIONS
*Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Ambient Temperature Rating TAMB TCASE TCASE Case Temperature Power Dissipation Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Package LQFP
76.2°C/W
17°C/W
59.2°C/W
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD1881A features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
CONFIGURATION 48-Lead LQFP
EAPD/CHAIN_IN
LNLVL_OUT_R
LNLVL_OUT_L
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET PC_BEEP
IDENTIFIER
AVDD2
MODE
MONO_OUT
LINE_OUT_R LINE_OUT_L CX3D RX3D FILT_L FILT_R AFILT2 AFILT1 VREFOUT VREF AVSS1
AD1881A
VIEW (Not Scale)
PHONE_IN AUX_L
AVSS2
MIC1
MIC2
CD_GND_REF
CONNECT
REV.
LINE_IN_R
VIDEO_R CD_L
AUX_R
CD_R
LINE_IN_L
VIDEO_L
AD1881A
FUNCTION DESCRIPTIONS
Digital
Name XTL_IN XTL_OUT SDATA_OUT BIT_CLK SDATA_IN SYNC RESET
LQFP
Description Crystal Clock) Input, 24.576 MHz. Crystal Output. AC-Link Serial Data Output, AD1881A Input Stream. AC-Link Clock. 12.288 Serial Data Clock. Daisy Chain Output Clock. AC-Link Serial Data Input. AD1881A Output Stream. AC-Link Frame Sample Sync Fixed Rate. AC-Link Reset. AD1881A Master Reset.
Miscellaneous Connections
Name EAPD MODE
Analog
LQFP
Description Chip Select Chip Select External Power-Down Control Signal, Default Active MODE Select.
These signals connect AD1881A component analog sources sinks, including microphones speakers. Name PC_BEEP PHONE_IN AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND_REF MIC1 MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT LNLVL_OUT_L LNLVL_OUT_R
Filter/Reference
LQFP
Description Beep. Speaker Beep Passthrough. Phone. From Telephony Subsystem Speakerphone Handset. Auxiliary Input Left Channel. Auxiliary Input Right Channel. Video Audio Left Channel. Video Audio Right Channel. Audio Left Channel. Audio Analog Ground Reference Pseudo-Differential Input. Audio Right Channel. Microphone Desktop Microphone Input. Microphone Second Microphone Input. Line Left Channel. Line Right Channel. Line Left Channel. Line Right Channel. Monaural Output Telephony Subsystem Speakerphone. Line-Level Output Left Channel. Line-Level Output Right Channel.
These signals connected resistors, capacitors, specific voltages. Name VREF VREFOUT AFILT1 AFILT2 FILT_R FILT_L RX3D CX3D LQFP Description Voltage Reference Filter. Voltage Reference Output Drive (Intended Bias). Antialiasing Filter Capacitor-ADC Right Channel. Antialiasing Filter Capacitor-ADC Left Channel. AC-Coupling Filter Capacitor-ADC Right Channel. AC-Coupling Filter Capacitor-ADC Left Channel. PHAT Stereo Enhancement-Capacitor. PHAT Stereo Enhancement-Capacitor.
REV.
AD1881A
Power Ground Signals
Name DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2
Connects
LQFP
Type
Description Digital Digital Digital Digital Analog Analog Analog Analog
Name
LQFP
Type
Description Connect Connect Connect
MIC1 MIC2
0x20
0dB/20dB 0x0E
LS/RS 0x1C
AD1881A
LINE_IN
VIDEO PHONE_IN
STEREO MONO STEREO
MONO_OUT
0x1C LS/RS LS/RS
0X1C
16-BIT
0X74
0X1C
16-BIT
RESET
0x20
0x0C 0x0C 0x0E 0x10 0x16 0x12 0x14 0x0E 0x10 0x16 0x12 0x14
0x1A
SYNC
RATE 0x2C 0x7A RATE 0x32 0x78
LPBK 0x20
LINK
BIT_CLK
SDATA_OUT
LNLVL_OUT_L
SDATA_IN 0x02 0x22 0x20 0x18
LINE_OUT_L
PHAT 0x20
16-BIT
LINE_OUT_R
0x02
0x22 0x20
PHAT 0x20
0x20
0x18
16-BIT
LNLVL_OUT_R
0x0A 0x0A GAIN ATTENUATE MUTE MASTER VOLUME
PC_BEEP
OSCILLATORS
XTL_OUT
XTL_IN
Figure Block Diagram Register
REV.
AD1881A
PRODUCT OVERVIEW Analog-to-Digital Signal Path
AD1881A meets Audio Codec Extensions. addition, AD1881A SoundMAX Codec designed meet requirements Audio Codec '97, Component Specification, Revision 1.03, 1996, Intel Corporation, found www.Intel.com. AD1881A also includes some other Codec enhanced features such built-in PHAT Stereo enhancement. AD1881A analog front high performance audio applications. AC'97 architecture defines 2-chip audio solution comprising digital audio controller, plus high quality analog component that includes Digital-to-Analog Converters (DACs), Analog-to-Digital Converters (ADCs), mixer I/O. main architectural features AD1881A high quality analog mixer section, channels conversion, channels conversion with Data Direct Scrambling (D2S) rate generators. AD1881A's left channel compatible modem applications supporting irrational sample rates modem filtering requirements.
FUNCTIONAL DESCRIPTION
selector sends left right channel information programmable gain amplifier (PGA). following selector allows independent gain control each channel entering from +22.5 steps. Each channel independent, process left right channel data different sample rates.
Sample Rates
AD1881A default mode sets Codec operate sample rates. converter pairs process left right channel data different sample rates. AD1881A sample rate generator allows Codec instantaneously change process sample rates from with resolution in-band integrated noise distortion artifacts introduced rate conversions below AD1881A uses 4-bit structure Data Directed Scrambling (D2S) enhance noise immunity motherboards enclosures, suppress idle tones below device's quantization noise floor. process pushes noise distortion artifacts caused errors multibit frequencies beyond auditory response human then filters them.
Digital-to-Analog Signal Path
This section overviews functionality AD1881A intended general introduction capabilities device. Detailed reference information found descriptions Indexed Control Registers.
Analog Inputs
Codec contains stereo pair ADCs. Inputs selected from following analog signals: telephony (PHONE_IN), mono microphone (MIC1 MIC2), stereo line (LINE_IN), auxiliary line input (AUX), stereo (CD), stereo audio from video source (VIDEO) post-mixed stereo mono line output (LINE_OUT).
Analog Mixing
analog output gained attenuated from -34.5 steps, summed with analog input signals. summed analog signal enters Master Volume stage where each channel mixer output attenuated from -94.5 steps muted.
Line-Level Outputs
AD1881A offers true line-level output notebook docking station home theater applications. line-level output does change with master volume settings.
Host-Based Echo Cancellation Support
PHONE_IN, MIC1 MIC2, LINE_IN, AUX, VIDEO mixed analog domain with stereo output from DACs. Each channel stereo analog inputs independently gained attenuated from -34.5 steps. summing path mono inputs (PHONE_IN, MIC1, MIC2 LINE_OUT) duplicates mono channel data both left right LINE_OUT. Additionally, attention signal (PC_BEEP) mixed with line output. switch allows output DACs bypass PHAT Stereo enhancement.
Digital Audio Mode
AD1881A supports time correlated data format presenting data left channel mono summation left right output right channel. splittable; left right data sampled different rates.
Power Management Modes
AD1881A designed meet ACPI power consumption requirements through flexible power management control internal resources.
AD1881A designed with Digital Audio Mode (DAM) that allows mixing analog inputs independent output signal path. Mixed analog input signals sent ADCs processing controller host, used during simultaneous capture playback different sample rates.
-10-
REV.
AD1881A
Indexed Control Registers
Name Reset Master Volume Reserved Master Volume Mono Default 0410h
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h 8000h
2Ch/ (7Ah)* (78h)*
Reserved Beep Volume Phone Volume Volume Line Volume Volume Video Volume Volume Record Select Record Gain Reserved General Purpose Control Power-Down Cntrl/Stat Extended Audio Extended Audio Stat/Ctrl Rate (SR1)
EAPD SR15
SR14
SR13
8000h 8008h
PCV3 PCV2 PCV1 PCV0 PHV4 PHV3 PHV2 PHV1 PHV0
MCV4 MCV3 MCV2 MCV1 MCV0 8008h RLV4 RLV3 RLV2 RLV1 RLV0 RCV4 RCV3 RCV2 RCV1 RCV0 RVV4 RVV3 RVV2 RVV1 RVV0 RAV4 RAV3 RAV2 RAV1 RAV0 ROV4 ROV3 ROV2 ROV1 ROV0 8808h 8808h 8808h 8808h 8808h 0000h 8000h 0000h 0000h 000Xh 0001h 0000h BB80h
LLV4 LLV3 LLV2 LLV1 LLV0 LCV4 LCV3 LCV2 LCV1 LCV0 LVV4 LVV3 LVV2 LVV1 LVV0 LAV4 LAV3 LAV2 LAV1 LAV0 LOV4 LOV3 LOV2 LOV1 LOV0 SR12
LIM3 LIM2 LIM1 LIM0 SR11 SR10
RIM3 RIM2 RIM1 RIM0
LPBK
Rate (SR0)
SR15
SR14
SR13
SR12
SR11
SR10
BB80h
Reserved Vendor Reserved**
Reserved Serial Configuration
SLOT
7X0Xh
Misc. Control Bits
LPMI
DLSR
ALSR 10D7
DRSR
ARSR
0404h
Vendor Vendor
4144h 5348h
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0
NOTES registers shown bits containing assumed reserved. register addresses aliased next lower even address. Reserved registers should written. Zeros should written reserved bits. *Indicates Aliased register AD1819, AD1819A backward compatibility. **Vendor Reserved registers should written.
REV.
-11-
AD1881A
Reset (Index 00h)
Name Reset Default 0410h
Note: Writing value this register performs register reset, which causes registers revert their default values (except 74h, which forces serial configuration). Reading this register returns code part code type Stereo Enhancement. ID[9:0] Identify Capability. decodes capabilities AD1881A based following: Function Dedicated Channel Modem Line Codec Support Bass Treble Control Simulated Stereo (Mono Stereo) Headphone Out/True Line-Level Loudness (Bass Boost) Support 18-Bit Resolution 20-Bit Resolution 18-Bit Resolution 20-Bit Resolution AD1881A
SE[4:0] Stereo Enhancement. stereo enhancement identifies Analog Devices stereo enhancement.
Master Volume Registers (Index 02h)
Name Master Volume Default
LMV5 LMV4 LMV3 LMV2 LMV1 LMV0
RMV5 RMV4 RMV3 RMV2 RMV1 RMV0 8000h
RMV[5:0] LMV[5:0]
Right Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Left Master Volume Control. least significant represents This register controls output from maximum attenuation -94.5 Master Volume Mute. When this "1," channel muted. xMV5 xMV0 0000 1111 1111 xxxx Function Attenuation -46.5 Attenuation -94.5 Attenuation Attenuation
Master Volume Mono (Index 06h)
Name Default
Master Volume Mono
MMV4 MMV3 MMV2 MMV1 MMV0 8000h
MMV[4:0]
Mono Master Volume Control. least significant represents This register controls output from maximum attenuation -46.5 Mono Master Volume Mute. When this "1," channel muted.
-12-
REV.
AD1881A
Beep Register (Index 0Ah)
Name PC_BEEP Volume Default 8000h
PCV3 PCV2 PCV1 PCV0
PCV[3:0]
Beep Volume Control. least significant represents attenuation. This register controls output from maximum attenuation Beep routed Left Right Line outputs even when RESET asserted. This that Power Self-Test (POST) codes heard user case hardware problem with Beep Mute. When this "1," channel muted. PCV3 PCV0 0000 1111 xxxx Function Attenuation Attenuation Attenuation
Phone Volume (Index 0Ch)
Name Phone Volume Default
PHV4 PHV3 PHV2 PHV1 PHV0 8008h
PHV[4:0]
Phone Volume. Allows setting Phone Volume Attenuator steps. represents range -34.5 default value mute enabled. Phone Mute. When this "1," channel muted.
Volume (Index 0Eh)
Name MCV4 MCV3 MCV2 MCV1 MCV0 Default 8008h
Volume
MCV[4:0]
Volume Gain. Allows setting Volume attenuator steps. represents range -34.5 default value mute enabled. Microphone Gain Block Disabled; Gain Enabled; Gain Mute. When this "1," channel muted.
Line Volume (Index 10h)
Name RLV4 RLV3 RLV2 RLV1 RLV0 Default 8808h
Line InVolume
LLV4 LLV3 LLV2 LLV1 LLV0
RLV[4:0] LLV[4:0]
Right Line Volume. Allows setting Line right channel attenuator steps. represents range -34.5 default value mute enabled. Line Volume Left. Allows setting Line left channel attenuator steps. represents range -34.5 default value mute enabled. Line Mute. When this "1," channel muted.
REV.
-13-
AD1881A
Volume (Index 12h)
Name Default
Volume
LCV4 LCV3 LCV2 LCV1 LCV0
RCV4 RCV3 RCV2 RCV1 RCV0 8808h
RCV[4:0] LCV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
Video Volume (Index 14h)
Name Default
Video Volume
LVV4 LVV3 LVV2 LVV1 LVV0
RVV4 RVV3 RVV2 RVV1 RVV0 8808h
RVV[4:0] LVV[4:0]
Right Video Volume. Allows setting Video right channel attenuator steps. represents range -34.5 default value mute enabled. Left Video Volume. Allows setting Video left channel attenuator steps. represents range -34.5 default value mute enabled. Video Mute. When this "1," channel muted.
Volume (Index 16h)
Name Volume Default
LAV4 LAV3 LAV2 LAV1 LAV0
RAV4 RAV3 RAV2 RAV1 RAV0 8808h
RAV[4:0] LAV[4:0]
Right Aux. Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Aux. Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Aux. Mute. When this "1," channel muted.
Volume (Index 18h)
Name Volume Default
LOV4 LOV3 LOV2 LOV1 LOV0
ROV4 ROV3 ROV2 ROV1 ROV0 8808h
ROV[4:0] LOV[4:0]
Right Volume. Allows setting right channel attenuator steps. represents range -34.5 default value mute enabled. Left Volume. Allows setting left channel attenuator steps. represents range -34.5 default value mute enabled. Volume Mute. When this "1," channel muted.
Volume Table (Index 18h)
00000 01000 11111 xxxxx
Function Gain Gain -34.5 Gain Gain
-14-
REV.
AD1881A
Record Select Control Register (Index 1Ah)
Name Default 0000h
Record Select
RS[2:0] LS[2:0]
Right Record Select Left Record Select.
Used select record source independently right left. table legend. default value 0000h, which corresponds
Record Gain (Index 1Ch)
Name Record Gain LIM3 LIM2 LIM1 LIM0 RIM3 RIM2 RIM1 RIM0 Default 8000h
Right Record Source CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mono PHONE_IN Left Record Source CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mono PHONE_IN
RIM[3:0] LIM[3:0]
Right Input Mixer Gain Control. Each represents 0000 range +22.5 Left Input Mixer Gain Control. Each represents 0000 range +22.5 Input Mute. Unmuted, Muted gain. xIM3 xIM0 1111 0000 xxxxx Function +22.5 Gain Gain Gain
REV.
-15-
AD1881A
General Purpose Register (Index 20h)
Name General Purpose LPBK Default 0000h
Note: This register should read before writing generate mask only bit(s) that need changed. function default value 0000h which off. LPBK Loopback Control. ADC/DAC Digital Loopback Mode Select MIC1. MIC2. Mono Output Select Mix. MIC. PHAT Stereo Enhancement PHAT Stereo off. PHAT Stereo Output Path Mute. controls optional bypass path (the pre- post-3D paths mutually exclusive). pre-3D. post-3D.
Control Register (Index 22h)
Name Control Default 0000h
DP[2:0]
Depth Control. Sets "Depth" PHAT Stereo enhancement according table below. 0000 0001 1110 1111 Depth 6.67% 93.33% 100%
-16-
REV.
AD1881A
Subsection Ready Register (Index 26h)
Name Power-Down Cntrl/Stat Default
EAPD
Note: ready bits read only, writing REF, ANL, DAC, will have effect. These bits indicate status AD1881A subsections. one, then that subsection "ready." Ready defined subsection able perform nominal state. PR[5:0] section ready transmit data. section ready accept data. Analog gain, attenuators mute blocks, mixers ready. Voltage References, VREF VREFOUT nominal level. AD1881A Power-Down Modes. first three bits used individually rather than combination with each other. last used combination with itself. mixer reference cannot powered down unless ADCs DACs also powered down. Nothing else powered until reference effect unless ADCs, DACs, AC-Link powered down. reference mixer either down, power-up sequences must allowed completion before both set. multiple-codec systems, master codec's bits control slave codec. also effective slave codec master's clear, effect except enable disable PR5. EAPD External Audio Power Down. Available when programmed AC'97 codec. state (default). state. Power-Down State Power-Down Power-Down Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Mixer Power-Down Standby
Extended Audio Register (Index 28h)
Name Extended Audio Default 0000h
Note: Extended Audio read only register. ID[1:0] Variable Rate Audio. enables Variable Rate Audio. ID1, 2-bit field that indicates codec configuration: Primary Secondary
REV.
-17-
AD1881A
Extended Audio Status Control Register (Index 2Ah)
Name Extended Audio St/Ctrl Default 0000h
Note: Extended Audio Status Control Register read/write register that provides status control extended audio features. Variable Rate Audio. enables Variable Rate Audio mode (sample rate control registers SLOTREQ signaling.
Rate Register (Index 2Ch)
Name SR15 SR14 SR13 SR12 SR11 SR10 Default
2Ch/(7Ah) Rate
BB80h
Note: alias 7Ah. register must alias work; zero written VRA, both sample rates reset 48k. SR[15:0] Writing this register allows programming sampling frequency from (1B80h) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (bb80h) causes codec saturate rate greater than programmed 7.040 rate less than 7.040 programmed. rates, value written register supported, that value will echoed back when read, otherwise closest rate supported returned.
Rate Register (Index 32h)
32h/(78h) Name Rate SR15 SR14 SR13 SR12 SR11 SR10 Default
BB80h
Note: alias 78h. register must alias work; zero written VRA, both sample rates reset 48k. SR[15:0] Writing this register allows programming sampling frequency from (1B80) (BB80h) increments. Programming value outside range 7040 (1b80h) 48000 (bb80h) causes codec saturate rate greater than programmed, 7.040 rate less than 7.040 programmed. rates, value written register supported, that value will echoed back when read, otherwise closest rate supported returned.
Serial Configuration (Index 74h)
Name Serial Configuration SLOT Default
7x0xh
Note: This register reset when reset register (register 00h) written. SLOT16 Enable 16-bit slots. DRQEN DxRQx retained only compatibility with AD1819. controller designs should register request bits status address slot instead. your system uses only single AD1881A, ignore register mask slave 1/slave request bits. write this register, write ones register mask bits. SLOT16 makes Link slots bits length, formatted into slots.
-18-
REV.
AD1881A
Miscellaneous Control Bits (Index 76h)
Name Misc Control Bits LPMI ALSR DRSR ARSR Default 0404h
DLSR
SRX10 SRX8
ARSR
right sample generator select Selected (32h) Selected (2Ch). right sample generator select Selected (32h) Selected (2Ch). Multiply rate 8/7. Multiply rate 10/7. SRX10D7 SRX8D7 mutually exclusive; SRX10D7 priority both set. Modem filter enable (left channel only). Change only when DACs powered down. left sample generator select Selected (32h) Selected (2Ch). left sample generator select Selected (32h) Selected (2Ch). Digital Mono Select. Mixer Left Right DAC. Digital Audio Mode. Outputs bypass analog mixer sent directly codec output. Power Mixer. Keeps LINE_OUT alive notebook applications. Zero fill (vs. repeat) starved data.
DRSR
SRX8D7 SRX10D7 MODEN ALSR
DLSR
LPMIX DACZ
Sample Rate (Index 78h)
Name Default
Sample Rate SR015 SR014 SR013 SR012 SR011 SR010 SR09 SR08 SR07 SR06 SR05 SR04 SR03 SR02 SR01 SR00 BB80H
Note: alias 78h. register must alias work; zero written then both sample rates reset 48k. SR0[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
REV.
-19-
AD1881A
Sample Rate (Index 7Ah)
Name Default
Sample Rate SR115 SR114 SR113 SR112 SR111 SR110 SR19 SR18 SR17 SR16 SR15 SR14 SR13 SR12 SR11 SR10 BB80h
Note: alias 7Ah. register must alias work; zero written VRA, both sample rates reset 48k. SR1[15:0] Writing this register allows user program sampling frequency from (1B58h) (BB80h) Hertz increments. Programming value greater than less than cause unpredictable results.
Vendor Registers (Index 7Ch-7Eh)
Name Vendor Default 4144h
S[7:0] F[7:0]
Name
This register ASCII encoded "A." This register ASCII encoded "D."
REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Default 5348h
Vendor
T[7:0] REV[7:0]
This register ASCII encoded "S." Revision Register field.
These bits read-only should verified before accessing vendor defined features.
AD1881A/AD1881 USER VISIBLE DIFFERENCES
MODE pin, longer CHAIN_CLK. AD1881 chaining mode supported. register instead 40h.
-20-
REV.
AD1881A
APPLICATIONS CIRCUITS
AD1881A been designed require minimum amount external circuitry. recommended applications circuits shown Figure Reference designs AD1881A available obtained contacting your local Analog Devices' sales representative authorized distributor.
+5AVDD +3.3DVDD
100nF 100nF 100nF 100nF
100nF
100nF
AVSS1 AVSS2 AVDD1 AVDD2 PC_BEEP
DVDD1 DVDD2 DVSS1 DVSS2
0.33 0.33 0.33 MIC1 0.33 MIC2 0.33 CD_R 0.33 CD_L 0.33 CD_GND 0.33 VIDEO_L 0.33 VIDEO_R 0.33 AUX_L 0.33 AUX_R 0.33 PHONE_IN 0.33
MONO_OUT
LINE_IN_R LINE_IN_L RESET SDATA_OUT SDATA_IN SYNC BIT_CLK 47pF DIGITAL CONTROLLER
AD1881A
EAPD MODE LNLVL_OUT_L LNLVL_OUT_R FILT_L FILT_R CX3D
EAPD
LINE_OUT_R
LINE_OUT_L AFILT1 AFILT2 RX3D VREFOUT
VREF
XTL_IN
XTL_OUT
100nF 270pF 270pF 47nF 2.25VDC 100nF TANT 600Z ANALOG GROUND NOTE: OPTIMAL PERFORMANCE REGULATED ANALOG POWER SUPPLY. 22pF
24.576MHz 22pF
DIGITAL GROUND
Figure Recommended Codec Application Circuit
REV.
-21-
AD1881A
CD-ROM CONNECTIONS
CD-ROM audio output level should investigated; typical drives generate output require voltage divider compatibility with Codec input range). recommended circuit basically group divide-by-two voltage dividers shown Figure CD_GND_REF used cancel differential ground noise from CD-ROM. optimum noise cancellation, this section divider should have approximately half impedance right left channel section dividers.
VOLTAGE DIVIDER 4.7k 2.7k 2.7k 0.33 4.7k 0.33
CODEC CD_L INPUT
HEADER AUDIO (LGGR)
CODEC CD_GND_REF INPUT
4.7k 4.7k
0.33
CODEC CD_R INPUT
Figure Typical CD-ROM Audio Connections
LINE_IN, VIDEO INPUT CONNECTIONS
Most these audio sources also generate audio level require input voltage divider compatible with Codec inputs. Figure shows recommended application circuit. applications requiring compliance, components should configured selected provide adequate immunity emissions control.
LINE/AUX/VIDEO INPUT 600Z 470pF 4.7k 4.7k 0.33 CODEC LEFT CHANNEL INPUT COMPONENTS 600Z 470pF VOLTAGE DIVIDER 4.7k 4.7k AC-COUPLING 0.33 CODEC RIGHT CHANNEL INPUT
Figure LINE_IN, AUX, Video Input Connections
MICROPHONE CONNECTIONS
AD1881A contains internal microphone preamp with gain, most cases direct microphone connection shown Figure adequate. microphone level low, external preamp added shown Figure either case microphone bias derived from Codec's internal reference (VREFOUT) using resistor. preamp circuit, VREFOUT signal also provide mid-point bias amplifier. meet PC99 1.0A requirements, signal should placed microphone jack bias ring. This configuration supports electret microphones with three conductor plugs, well dynamic microphones with conductor plugs (ring sleeve shorted together). Additional filtering required limit microphone response audio band interest.
-22-
REV.
AD1881A
COMPONENTS INPUT 600Z AC-COUPLING 600Z 470pF 470pF 0.22 CODEC MIC1 MIC2 INPUT
2.2k
FROM CODEC VREFOUT
Figure Recommended Microphone Input Connections
PREAMP COMPONENTS INPUT 600Z AC-COUPLING 600Z 470pF 470pF 0.22 AD8531 BIAS 2.2k FROM CODEC VREFOUT 0.22 100k +5AVDD AC-COUPLING CODEC MIC1 MIC2 INPUT
Figure Microphone with Additional External Preamp Gain)
LINE OUTPUT CONNECTIONS
AD1881A Codec provides stereo LINE_OUT signals standard level. These signals must ac-coupled before they connected external load. After ac-coupling, minimal resistive load recommended keep capacitors properly biased reduce click when plugging stereo equipment into output jack. capacitor values should selected provide desired frequency response, taking into account nominal impedance external load. meet PC99 specification PCs, testing must performed with load, therefore value recommended achieve less than roll-off
COMPONENTS STEREO LINE_OUT JACK 600Z 470pF 600Z 470pF AC-COUPLING FROM CODEC LINE_OUT_R
FROM CODEC LINE_OUT_L
NOTE: OUTPUT USED, AC-COUPLING VALUES WILL DEPEND DESIGN.
Figure Recommended LINE_OUT Connections
USING EXTERNAL HEADPHONE/POWER
SSM2250 Power Amplifier ideal companion AD1881A. amplifier provide output stereo mode into mono speaker connected bridge-tied load (BTL) configuration. SM2250 mode control that used switch between stereo output mode mono speaker. Figure shows typical configuration where SSM2250 drives stereo headphones external speakers, well internal mono speaker. normalizing pins stereo jack senses stereo plug insertion automatically switches from driving internal mono speaker driving external stereo load. conserve power, SSM2250 shut down EAPD AD1881A, using proper power management software. This particularly important portable applications. shutdown mode, SSM2250 consumes only
REV.
-23-
AD1881A
5AVDD 100k
49.9k
600Z 470pF
STEREO HP/SPEAKER OUTPUT
AD1881A
EAPD/CHAIN_IN 49.9k LINE_OUT_L 0.33 LIN_OUT_R 49.9k 0.33 SSM2250RU
600Z 470pF INTERNAL MONO SPEAKER STEREO 3.5mm JACK
LEFT
LEFT OUT/BLT BTL+ BYPASS RIGHT
SHUTDOWN SE/BTL RIGHT
MONO_OUT
CONNECT
49.9k
Figure Using SSM2250 Amplifier Stereo Mono Output
GROUNDING LAYOUT
reduce noise emissions, Analog Devices recommends split ground plane shown Figure purpose splitting ground plane create noise analog area that somewhat isolated from digital ground current noise generated system's logic. analog circuitry should placed analog ground plane area. reference purposes, return power supply currents, analog digital ground planes must connected some point, ideally small bridge under near Codec should provided. resistor ferrite bead should also considered since these allow some flexibility optimizing layout meet requirements.
DIGITAL GROUND PLANE
CONNECT SPLIT GROUND PLANES NEAR CODEC.
ISOLATION TRENCH
AD1881A
ANALOG GROUND PLANE
Figure Recommended Split Ground Plane
ANALOG POWER SUPPLY
minimize audio noise, Codec analog power supply (AVDD) should well decoupled regulated. systems recommended that analog supply derived from power supply using localized linear voltage regulator. Preferably, analog power supply should connected Codec's analog section using ferrite bead.
-24-
REV.
AD1881A
LM78M05CP 600Z 5AVDD
Figure Recommended Regulator Circuit Analog Power Supply
power plane layer being used system design, recommended that analog power plane Codec also split (mirroring analog ground plane). this case, analog power supply ferrite bead should bridge isolation trench, close Codec location.
REV.
-25-
AD1881A
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
0.063 (1.60) 0.030 (0.75) 0.018 (0.45) SEATING PLANE 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.354 (9.00) 0.276 (7.0)
VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05)
0.007 (0.18) 0.004 (0.09)
0.020 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
-26-
REV.
PRINTED U.S.A.
C3747-8-4/00 (rev. 00752
48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48)

AC'97 SoundMAX® Codec AD1881A ENHANCED FEATURES Mobile Power Mixe

Top Searches for this datasheet

Other recent searches