PowerNPNP4GS3 Network Processor January 2003 Copyright Discl
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PowerNPNP4GS3 Network Processor
January 2003
Copyright Disclaimer
Copyright International Business Machines Corporation 1999, 2003 Rights Reserved
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Printed United States America January 2003
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np3_DS_title.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Contents
About This Book
Should Read This Manual Related Publications Conventions Used This Manual
General Information
Features Ordering Information Overview NP4GS3-Based Systems Structure 1.5.1 Structure 1.5.1.1 Coprocessors 1.5.1.2 Enhanced Threads 1.5.1.3 Hardware Accelerators 1.5.2 NP4GS3 Memory Data Flow 1.6.1 Basic Data Flow 1.6.2 Data Flow
Physical Description
Information 2.1.1 Packet Routing Switch Interface Pins 2.1.2 Flow Control Interface Pins 2.1.3 Interface Pins 2.1.4 DRAM Interface Pins 2.1.4.1 Interface Pins 2.1.4.2 D4_0 D4_1 Interface Pins 2.1.4.3 D6_x Interface Pins 2.1.4.4 Interface Pins 2.1.5 Interface Pins 2.1.5.1 Pins 2.1.5.2 GMII Pins 2.1.5.3 SMII Pins 2.1.5.4 Pins 2.1.6 Pins 2.1.7 Management Interface Pins 2.1.8 Miscellaneous Pins 2.1.9 Filter Circuit 2.1.10 Thermal Usage 2.1.10.1 Temperature Calculation 2.1.10.2 Measurement Calibration Clocking Domains Mechanical Specifications IEEE 1149 (JTAG) Compliance 2.4.1 Statement JTAG Compliance
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2.4.2 JTAG Compliance Mode 2.4.3 JTAG Implementation Specifics 2.4.4 Brief Overview JTAG Instructions Signal Lists
Physical Multiplexer
Ethernet Overview 3.1.1 Ethernet Interface Timing Diagrams 3.1.2 Ethernet Counters 3.1.3 Ethernet Support Overview 3.2.1 Timing Diagrams 3.2.2 Counters 3.2.3 Support
Ingress Enqueuer Dequeuer Scheduler
Overview Operation 4.2.1 Operational Details Ingress Flow Control 4.3.1 Flow Control Hardware Facilities 4.3.2 Hardware Function 4.3.2.1 Exponentially Weighted Moving Average (EWMA) 4.3.2.2 Flow Control Hardware Actions
Switch Interface
Ingress Switch Data Mover 5.1.1 Cell Header 5.1.2 Frame Header Ingress Switch Cell Interface 5.2.1 Idle Cell Format 5.2.1.1 Bytes: Word 5.2.1.2 I-SCI Transmit Header Idle Cell 5.2.2 Switch Data Cell Format Ingress Egress Data-Aligned Synchronous Link Interface Egress Switch Cell Interface 5.4.1 Master Multicast Grant Reporting 5.4.2 Output Queue Grant Reporting 5.4.2.1 Reporting External Wrap Mode 5.4.3 Switch Fabric Network Processor Egress Idle Cell 5.4.4 Receive Header Formats Sync Cells Egress Switch Data Mover Packet Routing Switch PRS28.4G Configuration Notes
Egress Enqueuer Dequeuer Scheduler
Functional Blocks Operation Egress Flow Control
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PowerNP NP4GS3 Preliminary Network Processor
6.3.1 Flow Control Hardware Facilities 6.3.2 Remote Egress Status 6.3.2.1 Sequence Timing 6.3.2.2 Configuration 6.3.3 Hardware Function 6.3.3.1 Exponentially Weighted Moving Average 6.3.3.2 Flow Control Hardware Actions Egress Scheduler 6.4.1 Egress Scheduler Components 6.4.1.1 Scheduling Calendars 6.4.1.2 Flow Queues 6.4.1.3 Target Port Queues 6.4.2 Configuring Flow Queues 6.4.2.1 Additional Configuration Notes 6.4.3 Scheduler Accuracy Capacities
Embedded Processor Complex
Overview 7.1.1 Thread Types Dyadic Protocol Processor Unit (DPPU) 7.2.1 Core Language Processor (CLP) 7.2.1.1 Core Language Processor Address 7.2.2 Opcode Formats 7.2.3 DPPU Coprocessors 7.2.4 Shared Memory Pool Opcode Formats 7.3.1 Control Opcodes 7.3.1.1 Opcode 7.3.1.2 Exit Opcode 7.3.1.3 Test Branch Opcode 7.3.1.4 Branch Link Opcode 7.3.1.5 Return Opcode 7.3.1.6 Branch Register Opcode 7.3.1.7 Branch Relative Opcode 7.3.1.8 Branch Reg+Off Opcode 7.3.2 Data Movement Opcodes 7.3.2.1 Memory Indirect Opcode 7.3.2.2 Memory Address Indirect Opcode 7.3.2.3 Memory Direct Opcode 7.3.2.4 Scalar Access Opcode 7.3.2.5 Scalar Immediate Opcode 7.3.2.6 Transfer Quadword Opcode 7.3.2.7 Zero Array Opcode 7.3.3 Coprocessor Execution Opcodes 7.3.3.1 Execute Direct Opcode 7.3.3.2 Execute Indirect Opcode 7.3.3.3 Execute Direct Conditional Opcode 7.3.3.4 Execute Indirect Conditional Opcode 7.3.3.5 Wait Opcode 7.3.3.6 Wait Branch Opcode
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7.3.4 Opcodes 7.3.4.1 Arithmetic Immediate Opcode 7.3.4.2 Logical Immediate Opcode 7.3.4.3 Compare Immediate Opcode 7.3.4.4 Load Immediate Opcode 7.3.4.5 Arithmetic Register Opcode 7.3.4.6 Count Leading Zeros Opcode DPPU Coprocessors 7.4.1 Tree Search Engine Coprocessor 7.4.2 Data Store Coprocessor 7.4.2.1 Data Store Coprocessor Address 7.4.2.2 Data Store Coprocessor Commands 7.4.3 Control Access (CAB) Coprocessor 7.4.3.1 Coprocessor Address 7.4.3.2 Access NP4GS3 Structures 7.4.3.3 Coprocessor Commands 7.4.4 Enqueue Coprocessor 7.4.4.1 Enqueue Coprocessor Address 7.4.4.2 Enqueue Coprocessor Commands 7.4.5 Checksum Coprocessor 7.4.5.1 Checksum Coprocessor Address 7.4.5.2 Checksum Coprocessor Commands 7.4.6 String Copy Coprocessor 7.4.6.1 String Copy Coprocessor Address 7.4.6.2 String Copy Coprocessor Commands 7.4.7 Policy Coprocessor 7.4.7.1 Policy Coprocessor Address 7.4.7.2 Policy Coprocessor Commands 7.4.8 Counter Coprocessor 7.4.8.1 Counter Coprocessor Address 7.4.8.2 Counter Coprocessor Commands 7.4.9 Coprocessor Response 7.4.9.1 Coprocessor Response Address 7.4.9.2 Coprocessor Response Commands 7.4.9.3 14-bit Coprocessor Response 7.4.10 Semaphore Coprocessor 7.4.10.1 Semaphore Coprocessor Commands 7.4.10.2 Error Conditions 7.4.10.3 Software Models Interrupts Timers 7.5.1 Interrupts 7.5.1.1 Interrupt Vector Registers 7.5.1.2 Interrupt Mask Registers 7.5.1.3 Interrupt Target Registers 7.5.1.4 Software Interrupt Registers 7.5.2 Timers 7.5.2.1 Timer Interrupt Counters Dispatch Unit 7.6.1 Port Configuration Memory 7.6.1.1 Port Configuration Memory Index Definition
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7.6.2 Port Configuration Memory Contents Definition 7.6.3 Completion Unit Hardware Classifier 7.7.1 Ingress Classification 7.7.1.1 Ingress Classification Input 7.7.1.2 Ingress Classification Output 7.7.2 Egress Classification 7.7.2.1 Egress Classification Input 7.7.2.2 Egress Classification Output 7.7.3 Completion Unit Label Generation Policy Manager Counter Manager 7.9.1 Counter Manager Usage 7.10 Semaphore Manager
Tree Search Engine
Overview 8.1.1 Addressing Control Store (CS) 8.1.2 Control Store. 8.1.3 Logical Memory Views 8.1.4 Control Store Restrictions 8.1.5 Object Shapes 8.1.6 Illegal Memory Access 8.1.7 Memory Range Checking (Address Bounds Check) Trees Tree Searches 8.2.1 Input Color Register Trees 8.2.2 Input Color Register Trees 8.2.3 Direct Table 8.2.3.1 Pattern Search Control Blocks (PSCB) 8.2.3.2 Leaves Compare-at-End Operation 8.2.3.3 Cascade/Cache 8.2.3.4 Cache Flag NrPSCBs Registers 8.2.3.5 Cache Management 8.2.3.6 Search Output 8.2.4 Tree Search Algorithms 8.2.4.1 Trees 8.2.4.2 Trees 8.2.4.3 PSCB Structure Memory 8.2.4.4 Compact PSCB Support 8.2.4.5 Trees with Multibit Compare 8.2.4.6 Trees 8.2.4.7 Compare-at-End Operation 8.2.4.8 Ropes 8.2.4.9 Aging 8.2.5 Tree Configuration Initialization 8.2.5.1 LUDefTable 8.2.5.2 Free Lists (TSE_FL) 8.2.6 Registers Register 8.2.7 Instructions 8.2.7.1 Tree Search (TS_FM)
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8.2.7.2 Tree Search (TS_LPM) 8.2.7.3 Tree Search (TS_SMT) 8.2.7.4 Memory Read (MRD) 8.2.7.5 Memory Write (MWR) 8.2.7.6 Hash (HK) 8.2.7.7 Read LUDefTable (RDLUDEF) 8.2.7.8 Compare-at-End (COMPEND) 8.2.7.9 DistinguishPosition Fast Table Update (DISTPOS_GDH) 8.2.7.10 Read PSCB Fast Table Update (RDPSCB_GDH) 8.2.7.11 Write PSCB Fast Table Update (WRPSCB_GDH) 8.2.7.12 SetPatBit_GDH 8.2.8 Hardware Assist Instructions 8.2.8.1 Hash (HK_GTH) 8.2.8.2 Read LUDefTable (RDLUDEF GTH) 8.2.8.3 Tree Search Enqueue Free List (TSENQFL) 8.2.8.4 Tree Search Dequeue Free List (TSDQFL) 8.2.8.5 Read Current Leaf from Rope (RCLR) 8.2.8.6 Advance Rope with Optional Delete Leaf (ARDL) 8.2.8.7 Tree Leaf Insert Rope (TLIR) 8.2.8.8 Clear PSCB (CLRPSCB) 8.2.8.9 Read PSCB (RDPSCB) 8.2.8.10 Write PSCB (WRPSCB) 8.2.8.11 Push PSCB (PUSHPSCB) 8.2.8.12 Distinguish (DISTPOS) 8.2.8.13 TSR0 Pattern (TSR0PAT) 8.2.8.14 Pattern 2DTA (PAT2DTA) 8.2.9 Hash Functions
Serial Parallel Manager Interface
Interface Components Interface Data Flow Interface Protocol Address Space 9.4.1 Byte Access Space 9.4.2 Word Access Space 9.4.3 EEPROM Access Space 9.4.3.1 EEPROM Single-Byte Access 9.4.3.2 EEPROM 2-Byte Access 9.4.3.3 EEPROM 3-Byte Access 9.4.3.4 EEPROM 4-Byte Access
Embedded PowerPCSubsystem
10.1 Description 10.2 Processor Local Device Control Register Buses 10.2.1 Processor Local (PLB) 10.2.2 Device Control Register (DCR) 10.3 Address 10.4 Address 10.5 Universal Interrupt Controller (UIC) Macro
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10.6 PCI/PLB Bridge Macro 10.7 Interface Macro 10.7.1 PowerPC Address (PwrPC_CAB_Addr) Register 10.7.2 PowerPC Data (PwrPC_CAB_Data) Register 10.7.3 PowerPC Control (PwrPC_CAB_Cntl) Register 10.7.4 PowerPC Status (PwrPC_CAB_Status) Register 10.7.5 PowerPC Mask (PwrPC_CAB_Mask) Register 10.7.6 PowerPC Write Under Mask Data (PwrPC_CAB_WUM_Data) 10.7.7 Host Address (Host_CAB_Addr) Register 10.7.8 Host Data (Host_CAB_Data) Register 10.7.9 Host Control (Host_CAB_Cntl) Register 10.7.10 Host Status (Host_CAB_Status) Register 10.7.11 Host Mask (Host_CAB_Mask) Register 10.7.12 Host Write Under Mask Data (Host_CAB_WUM_Data) Register 10.8 Mailbox Communications DRAM Interface Macro 10.8.1 Mailbox Communications Between Host PowerPC Subsystem 10.8.2 Interrupt Status (PCI_Interr_Status) Register 10.8.3 Interrupt Enable (PCI_Interr_Ena) Register 10.8.4 PowerPC Subsystem Host Message Resource (P2H_Msg_Resource) Register 10.8.5 PowerPC Subsystem Host Message Address (P2H_Msg_Addr) Register 10.8.6 PowerPC Subsystem Host Doorbell (P2H_Doorbell) Register 10.8.7 Host PowerPC Subsystem Message Address (H2P_Msg_Addr) Register 10.8.8 Host PowerPC Subsystem Doorbell (H2P_Doorbell) Register 10.8.9 Mailbox Communications Between PowerPC Subsystem 10.8.10 PowerPC Subsystem Resource (E2P_Msg_Resource) Register 10.8.11 PowerPC Subsystem Message Address (E2P_Msg_Addr) Register 10.8.12 PowerPC Subsystem Doorbell (E2P_Doorbell) Register 10.8.13 Interrupt Vector Register 10.8.14 Interrupt Mask Register 10.8.15 PowerPC Subsystem Message Address (P2E_Msg_Addr) Register 10.8.16 PowerPC Subsystem Doorbell (P2E_Doorbell) Register 10.8.17 Mailbox Communications Between Host 10.8.18 Host Resource (E2H_Msg_Resource) Register 10.8.19 Host Message Address (E2H_Msg_Addr) Register 10.8.20 Host Doorbell (E2H_Doorbell) Register 10.8.21 Host Message Address (H2E_Msg_Addr) Register 10.8.22 Host Doorbell (H2E_Doorbell) Register 10.8.23 Message Status (Msg_Status) Register 10.8.24 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst) 10.8.25 PowerPC Machine Check (PwrPC_Mach_Chk) Register 10.8.26 Parity Error Status Reporting 10.8.27 Slave Error Address Register (SEAR) 10.8.28 Slave Error Status Register (SESR) 10.8.29 Parity Error Counter (Perr_Count) Register 10.9 System Start-Up Initialization 10.9.1 NP4GS3 Resets 10.9.2 Systems Initialized External Host Processors 10.9.3 Systems with Host Processors Initialized PowerPC Subsystem 10.9.4 Systems Without Host Processors Initialized PowerPC Subsystem 10.9.5 Systems Without Host Delayed Configuration Initialized
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Reset Initialization
11.1 Overview 11.2 Step I/Os 11.3 Step Reset NP4GS3 11.4 Step Boot 11.4.1 Boot Embedded Processor Complex (EPC) 11.4.2 Boot PowerPC Processor 11.4.3 Boot Summary 11.5 Step Setup 11.6 Step Diagnostics 11.7 Step Setup 11.8 Step Hardware Initialization 11.9 Step Diagnostics 11.10 Step Operational 11.11 Step Configure 11.12 Step Initialization Complete
Debug Facilities
12.1 Debugging Picoprocessors 12.1.1 Single Step 12.1.2 Break Points 12.1.3 Accessible Registers 12.2 RISCWatch
Configuration
13.1 Memory Configuration 13.1.1 Memory Configuration Register (Memory_Config) 13.1.2 DRAM Parameter Register (DRAM_Parm) 13.1.3 Delay Calibration Registers (NP4GS3C (R3.x)) 13.2 Master Grant Mode Register (MG_Mode) 13.3 Mode Register (TB_Mode) 13.3.1 Toggle Mode 13.3.1.1 information 13.3.1.2 ENQE Command Qclass 13.4 Egress Reassembly Sequence Check Register (E_Reassembly_Seq_Ck) 13.5 Aborted Frame Reassembly Action Control Register (AFRAC) 13.6 Packing Registers 13.6.1 Packing Control Register (Pack_Ctrl) 13.6.2 Packing Delay Register (Pack_Dly) (NP4GS3B (R2.0)) 13.7 Initialization Control Registers 13.7.1 Initialization Register (Init) 13.7.2 Initialization Done Register (Init_Done) 13.8 NP4GS3 Ready Register (NPR_Ready) 13.9 Phase-Locked Loop Registers 13.9.1 Phase-Locked Loop Fail Register (PLL_Lock_Fail) 13.10 Software Controlled Reset Register (Soft_Reset) 13.11 Ingress Free Queue Threshold Configuration
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13.11.1 BCB_FQ Threshold Registers 13.11.2 BCB_FQ Threshold Guided Traffic (BCB_FQ_Th_GT) 13.11.3 BCB_FQ_Threshold_0 Register (BCB_FQ_TH_0) 13.11.4 BCB_FQ_Threshold_1 Register (BCB_FQ_TH_1) 13.11.5 BCB_FQ_Threshold_2 Register (BCB_FQ_Th_2) 13.12 I-GDQ Threshold Register (I-GDQ_Th) (NP4GS3C (R3.x)) 13.13 Ingress Target Data Storage Register (I_TDMU_DSU) 13.14 Embedded Processor Complex Configuration 13.14.1 PowerPC Core Reset Register (PowerPC_Reset) 13.14.2 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst) 13.14.3 Watch Reset Enable Register (WD_Reset_Ena) 13.14.4 Boot Override Register (Boot_Override) 13.14.5 Thread Enable Register (Thread_Enable) 13.14.6 Data Disable Register (GFH_Data_Dis) 13.14.7 Ingress Maximum Entries (I_Max_DCB) 13.14.8 Egress Maximum Entries (E_Max_DCB) 13.14.9 Target Blade Address Register (My_TB) 13.14.10 Local Target Blade Vector Register (Local_TB_Vector) 13.14.11 Local MCTarget Blade Vector Register (Local_MC_TB_Max) 13.14.12 Ordered Semaphore Enable Register (Ordered_Sem_Ena) 13.14.13 Enhanced Classification Enable Register (Enh_HWC_Ena) (NP4GS3C (R3.x)) 13.15 Flow Control Structures 13.15.1 Ingress Flow Control Hardware Structures 13.15.1.1 Ingress Transmit Probability Memory Register (I_Tx_Prob_Mem) 13.15.1.2 Ingress pseudorandom Number Register (I_Rand_Num) 13.15.1.3 Free Queue Thresholds Register (FQ_Th) 13.15.2 Egress Flow Control Structures 13.15.2.1 Egress Transmit Probability Memory (E_Tx_Prob_Mem) Register 13.15.2.2 Egress pseudorandom Number (E_Rand_Num) 13.15.2.3 Twin Count Threshold (P0_Twin_Th) 13.15.2.4 Twin Count Threshold (P1_Twin_Th) 13.15.2.5 Egress Twin Count EWMA Threshold Register (E_P0_Twin_EWMA_Th) 13.15.2.6 Egress Twin Count EWMA Threshold Register (E_P1_Twin_EWMA_Th) 13.15.3 Exponentially Weighted Moving Average Constant Register (EWMA_K) 13.15.4 Exponentially Weighted Moving Average Sample Period Register (EWMA_T) 13.15.5 Flow Control Force Discard Register (FC_Force_Discard) (NP4GS3B (R2.0)) 13.15.6 Remote Egress Status Configuration Enables (RES_Data_Cnf) 13.16 Target Port Data Storage (TP_DS_MAP) Register 13.17 Egress Stack Threshold Register (E_SDM_Stack_Th) 13.18 Free Queue Extended Stack Maximum Size (FQ_ES_Max) Register 13.19 Egress Free Queue Thresholds 13.19.1 FQ_ES_Threshold_0 Register (FQ_ES_Th_0) 13.19.2 FQ_ES_Threshold_1 Register (FQ_ES_Th_1) 13.19.3 FQ_ES_Threshold_2 Register (FQ_ES_Th_2) 13.20 Egress Frame Data Queue Thresholds (E_GRx_GBx_th) (NP4GS3C (R3.x)) 13.21 Discard Flow Register (Discard_QCB) 13.22 Bandwidth Allocation Register (BW_Alloc_Reg) (NP4GS3B (R2.0)) 13.23 Miscellaneous Controls Register (MISC_CNTRL) (NP4GS3C (R3.x)) 13.24 Frame Control Block Size Register (FCB_FQ_Max)
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13.25 Data Mover Unit (DMU) Configuration Registers 13.26 Frame Configuration Register (DMU_Pad) (NP4GS3C (R3.x)) 13.27 Ethernet Jumbo Frame Size Register (EN_Jumbo_FS) (NP4GS3C (R3.x)) 13.28 Accuracy Register (QD_Acc) 13.29 Packet Over SONET Control Register (POS_Ctrl) 13.29.1 Initial Value Determination 13.30 Packet Over SONET Maximum Frame Size (POS_Max_FS) 13.31 Ethernet Encapsulation Type Register Control (E_Type_C) 13.32 Ethernet Encapsulation Type Register Data (E_Type_D) 13.33 Source Address Array (SA_Array) 13.34 Destination Address Array (DA_Array) (NP4GS3C (R3.x)) 13.35 DASL Initialization Configuration 13.35.1 DASL Configuration Register (DASL_Config) 13.35.1.1 Dynamic Switch Interface Selection 13.35.2 DASL Bypass Wrap Register (DASL_Bypass_Wrap) 13.35.3 DASL Start Register (DASL_Start) 13.36 Programmable Register (PIO_Reg)
Electrical Thermal Specifications
14.1 Driver Specifications 14.2 Receiver Specifications 14.3 Other Driver Receiver Specifications 14.3.1 DASL Specifications
Glossary Terms Abbreviations Revision
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List Tables
Table 2-1. Signal Functions Table 2-2. 28.4 Gbps Packet Routing Switch Interface Pins Table 2-3. Flow Control Pins Table 2-4. SRAM Interface Pins Table 2-5. SRAM Interface Pins Table 2-6. SRAM Timing Diagram Legend (for Figure 2-2) Table 2-7. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-8. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-9. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Table 2-10. Interface Pins Table 2-11. Memory Pins Table 2-12. D4_0 D4_1 Interface Pins Table 2-13. D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins Table 2-14. Interface Pins Table 2-15. Interface Pins Table 2-16. Interface Multiplexing Table 2-17. Interface Pins: Debug (DMU_D Only) Table 2-18. Parallel Data 8B/10B Position Mapping (TBI Interface) Table 2-19. Interface Pins: Mode Table 2-20. Timing Diagram Legend (for Figure 2-8) Table 2-21. Interface Pins: GMII Mode Table 2-22. GMII Timing Diagram Legend (for Figure 2-9) Table 2-23. Interface Pins: SMII Mode Table 2-24. SMII Timing Diagram Legend (for Figure 2-10) Table 2-25. Interface Pins POS32 Mode Table 2-26. Signals Table 2-27. Timing Diagram Legend (for Figure 2-11 Figure 2-12) Table 2-28. Pins Table 2-29. Timing Diagram Legend (for Figure 2-13) Table 2-30. Management Pins Table 2-31. Timing Diagram Legend (for Figure 2-14) Table 2-32. Miscellaneous Pins Table 2-33. Signals Requiring Pull-Up Pull-Down Table 2-34. Mechanical Specifications Table 2-35. JTAG Compliance-Enable Inputs Table 2-36. Implemented JTAG Public Instructions Table 2-37. Complete Signal Listing Signal Name Table 2-38. Complete Signal Listing Grid Position
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Table 3-1. Ingress Ethernet Counters .118 Table 3-2. Egress Ethernet Counters .119 Table 3-3. Ethernet Support .122 Table 3-4. Framer Configurations .123 Table 3-5. Receive Counter Addresses Ingress .129 Table 3-6. Transmit Counter Addresses Egress .131 Table 3-7. Support .133 Table 4-1. Flow Control Hardware Facilities .141 Table 5-1. Cell Header Fields .147 Table 5-2. Frame Header Fields .150 Table 5-3. Idle Cell Format Transmitted Switch Interface .152 Table 5-4. Switch Data Cell Format .154 Table 5-5. Receive Cell Header Byte Idle Cell .160 Table 5-6. Idle Cell Format Received from Switch Interface 16-blade Mode .160 Table 5-7. Idle Cell Format Received from Switch Interface 32-blade Mode .161 Table 5-8. Idle Cell Format Received from Switch Interface 64-blade Mode .161 Table 6-1. Flow Control Hardware Facilities .170 Table 6-2. Flow Queue Parameters .177 Table 6-3. Valid Combinations Scheduler Parameters .177 Table 6-4. Configure Flow .183 Table 7-1. Core Language Processor Address .193 Table 7-2. Shared Memory Pool .196 Table 7-3. Condition Codes (Cond Field) .197 Table 7-4. AluOp Field Definition .217 Table 7-5. Field Definition .219 Table 7-6. Arithmetic Opcode Functions .223 Table 7-7. Coprocessor Instruction Format .227 Table 7-8. Data Store Coprocessor Address .228 Table 7-9. Ingress DataPool Byte Address Definitions .230 Table 7-10. Egress Frames DataPool Quadword Addresses .232 Table 7-11. DataPool Byte Addressing with Cell Header Skip .233 Table 7-12. Number Frame-bytes DataPool .234 Table 7-13. WREDS Input .236 Table 7-14. WREDS Output .236 Table 7-15. RDEDS Input .237 Table 7-16. RDEDS Output .238 Table 7-17. WRIDS Input .238 Table 7-18. WRIDS Output .238 Table 7-19. RDIDS Input .239
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Table 7-20. RDIDS Output Table 7-21. RDMOREE Input Table 7-22. RDMOREE Output Table 7-23. RDMOREI Input Table 7-24. RDMOREI Output Table 7-25. LEASETWIN Output Table 7-26. EDIRTY Inputs Table 7-27. EDIRTY Output Table 7-28. IDIRTY Inputs Table 7-29. IDIRTY Output Table 7-30. Coprocessor Address Table 7-31. Address Field Definitions Table 7-32. Address, Functional Island Encoding Table 7-33. CABARB Input Table 7-34. CABACCESS Input Table 7-35. CABACCESS Output Table 7-36. Enqueue Coprocessor Address Table 7-37. Ingress FCBPage Description Table 7-38. Egress FCBPage Description Table 7-39. ENQE Target Queues Table 7-40. Egress Target Queue Selection Coding Table 7-41. Egress Target Queue Parameters Table 7-42. Type Field Discard Queue Table 7-43. ENQE Command Input Table 7-44. Egress Queue Class Definitions Table 7-45. ENQI Target Queues Table 7-46. Ingress Target Queue Selection Coding Table 7-47. Ingress Target Queue FCBPage Parameters Table 7-48. ENQI Command Input Table 7-49. Ingress-Queue Class Definition Table 7-50. ENQCLR Command Input Table 7-51. ENQCLR Output Table 7-52. RELEASE_LABEL Output Table 7-53. Checksum Coprocessor Address Table 7-54. GENGEN/GENGENX Command Inputs Table 7-55. GENGEN/GENGENX/GENIP/GENIPX Command Outputs Table 7-56. GENIP/GENIPX Command Inputs Table 7-57. CHKGEN/CHKGENX Command Inputs Table 7-58. CHKGEN/CHKGENX/CHKIP/CHKIPX Command Outputs
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Table 7-59. CHKIP/CHKIPX Command Inputs .270 Table 7-60. String Copy Coprocessor Address .271 Table 7-61. StrCopy Command Input .271 Table 7-62. StrCopy Command Output .272 Table 7-63. Policy Coprocessor Address .272 Table 7-64. PolAccess Input .273 Table 7-65. PolAccess Output .273 Table 7-66. Counter Coprocessor Address .273 Table 7-67. Ctrinc Input .274 Table 7-68. CtrRInc Input (NP4GS3C (R3.x)) .275 Table 7-69. CtrAdd Input .275 Table 7-70. CtrRAdd Input (NP4GS3C (R3.x)) .275 Table 7-71. CtrRd/CtrRdClr Input .276 Table 7-72. CtrRd/CtrRdClr Output .276 Table 7-73. CtrWr15_0/CtrWr31_16 Input .276 Table 7-74. Coprocessor Response Coprocessor Address .277 Table 7-75. Coprocessor Response Coprocessor Command Summary .277 Table 7-76. CrbSetBusy Output .277 Table 7-77. 14-bit Response Cycle Definition .278 Table 7-78. Semaphore Lock Input .279 Table 7-79. Semaphore Unlock Input .279 Table 7-80. Reservation Release Input .279 Table 7-81. Priority Assignments Dispatch Unit Queue Arbiter .285 Table 7-82. Port Configuration Memory Index .286 Table 7-83. Relationship Between Field, Queue, Port Configuration Memory Index .287 Table 7-84. Port Configuration Memory Content .287 Table 7-85. Protocol Identifiers .290 Table 7-86. HCCIA Table .291 Table 7-87. Protocol Identifiers Frame Encapsulation Types .292 Table 7-88. General Purpose Register Definitions Ingress Classification Flags .293 Table 7-89. Flow Control Information Values .294 Table 7-90. HCCIA Index Definition .295 Table 7-91. General Purpose Register Definitions Egress Classification Flags .295 Table 7-92. Completion Unit Label .296 Table 7-93. PolCB Field Definitions .298 Table 7-94. Counter Manager Components .302 Table 7-95. Counter Types .302 Table 7-96. Counter Actions .302 Table 7-97. Counter Definition Entry Format .303
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Table 7-98. Counter Manager Passed Parameters Table 7-99. Counter Manager Address Bits Table 8-1. Control Store Address Mapping References Table 8-2. Address Table 8-3. Control Store Addressing Table 8-4. DTEntry, PSCB, Leaf Shaping Table 8-5. Height, Width, Offset Restrictions Objects Table 8-6. Tree Fixed Leaf Formats Table 8-7. Tree Fixed Leaf Formats Table 8-8. Search Input Parameters Table 8-9. Cache Status Registers Table 8-10. Search Output Parameters Table 8-11. DTEntry PSCBLine Formats Table 8-12. DTEntry PSCBLine Formats Table 8-13. NLASMT Field Format Table 8-14. CompDefTable Entry Format Table 8-15. LUDefTable Rope Parameters Table 8-16. NLARope Field Format Table 8-17. LUDefTable Entry Definitions Table 8-18. Free List Entry Definition Table 8-19. Scalar Registers Only Table 8-20. Array Registers Table 8-21. Registers (Tree Management) Table 8-22. Scalar Registers Table 8-23. PSCB Register Format Table 8-24. Indirect Registers Table 8-25. Address PSCB0-2 Registers Table 8-26. General Instructions Table 8-27. Tree Search Input Operands Table 8-28. Tree Search Results (TSR) Output Table 8-29. Tree Search Input Operands Table 8-30. Tree Search Results Output Table 8-31. Tree Search Input Operands Table 8-32. Tree Search Results Output Table 8-33. Memory Read Input Operands Table 8-34. Memory Read Output Results Table 8-35. Memory Write Input Operands Table 8-36. Hash Input Operands Table 8-37. Hash Output Results
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Table 8-38. RDLUDEF Input Operands .351 Table 8-39. RDLUDEF Output Results .351 Table 8-40. COMPEND Input Operands .352 Table 8-41. COMPEND Output Results .352 Table 8-42. DISTPOS_GDH Input Operands .353 Table 8-43. DISTPOS_GDH Output Results .354 Table 8-44. RDPSCB_GDH Input Operands .355 Table 8-45. RDPSCB_GDH Output Results .356 Table 8-46. WRPSCB_GDH Input Operands .356 Table 8-47. WRPSCB_GDH Output Results .357 Table 8-48. SetPatBit_GDH Input Operands .358 Table 8-49. SetPatBit_GDH Output Results .358 Table 8-50. General Instructions .359 Table 8-51. Hash Input Operands .360 Table 8-52. Hash Output Results .360 Table 8-53. RDLUDEF_GTH Input Operands .361 Table 8-54. RDLUDEF_GTH Output Results .361 Table 8-55. TSENQFL Input Operands .361 Table 8-56. TSENQFL Output Results .361 Table 8-57. TSDQFL Input Operands .362 Table 8-58. TSDQFL Output Results .362 Table 8-59. RCLR Input Operands .363 Table 8-60. RCLR Output Results .363 Table 8-61. ARDL Input Operands .363 Table 8-62. ARDL Output Results .364 Table 8-63. TLIR Input Operands .364 Table 8-64. TLIR Output Results .364 Table 8-65. CLRPSCB Input Operands .364 Table 8-66. CLRPSCB Output Results .365 Table 8-67. RDPSCB Input Operands .365 Table 8-68. RDPSCB Output Results .365 Table 8-69. WRPSCB Input Operands .366 Table 8-70. PUSHPSCB Input Operands .367 Table 8-71. PUSHPSCB Output Results .367 Table 8-72. DISTPOS Input Operands .367 Table 8-73. DISTPOS Output Results .367 Table 8-74. TSR0PAT Input Operands .368 Table 8-75. TSR0PAT Output Results .368 Table 8-76. PAT2DTA Input Operands .368
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Table 8-77. PAT2DTA Output Results Table 8-78. General Hash Functions Table 9-1. Field Definitions Addresses Table 10-1. Master Connections Table 10-2. Device Control Registers Table 10-3. Address Interface Macro Table 10-4. Address Mailbox DRAM Interface Macro Table 10-5. Address Mailbox DRAM Interface Macro Table 10-6. Interrupt Assignments Table 10-7. NP4GS3 Device Configuration Header Values Table 10-8. Address PCI/PLB Macro Table 10-9. PCI/PLB Bridge Macro Configuration Registers Table 10-10. Reset Domains Table 11-1. Reset Initialization Sequence Table 11-2. I/Os Checklist Table 11-3. Setup Checklist Table 11-4. Diagnostics Checklist Table 11-5. Setup Checklist Table 11-6. Hardware Initialization Checklist Table 11-7. Diagnostic Checklist Table 11-8. Configure Checklist Table 14-1. Absolute Maximum Ratings Table 14-2. Input Capacitance (pF) Table 14-3. Operating Supply Voltages Table 14-4. Operating Supply Currents Table 14-5. Thermal Characteristics Table 14-6. Definition Terms Table 14-7. CMOS Driver Voltage Specifications Table 14-8. CMOS Driver Minimum Currents Rated Voltage Table 14-9. CMOS Driver Voltage Specifications Table 14-10. CMOS Driver Minimum Currents Rated Voltage Table 14-11. V-Tolerant CMOS Driver Voltage Specifications Table 14-12. LVTTL Driver Voltage Specifications Table 14-13. LVTTL/5.0 V-Tolerant Driver Voltage Specifications Table 14-14. LVTTL Driver Minimum Currents Rated Voltage Table 14-15. CMOS Receiver Voltage Specifications Table 14-16. CMOS Receiver Voltage Specifications Table 14-17. LVTTL Receiver Voltage Specifications Table 14-18. LVTTL Tolerant Receiver Voltage Specifications
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Table 14-19. Receiver Maximum Input Leakage Current Input Specifications .579 Table 14-20. LVDS Receiver Specifications .581 Table 14-21. SSTL2 Specifications .581 Table 14-22. DASL Receiver Specifications IDASL_A .583 Table 14-23. DASL Driver Specifications ODASL_A .583
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List Figures
Figure 1-1. Function Placement NP4GS3-Based System Figure 1-2. NP4GS3 Major Functional Blocks Figure 1-3. Data Flow Overview Figure 1-4. Basic Data Flow Figure 2-1. Device Interfaces Figure 2-2. SRAM Timing Diagram Figure 2-3. Control Timing Diagram Figure 2-4. Read Timing Diagram Figure 2-5. Write Output Timing Diagram Figure 2-6. NP4GS3 Clock Connections Figure 2-7. NP4GS3 Clock Connections (POS Overview) Figure 2-8. Timing Diagram Figure 2-9. GMII Timing Diagram Figure 2-10. SMII Timing Diagram Figure 2-11. Transmit Timing Diagram Figure 2-12. Receive Timing Diagram Figure 2-13. Timing Diagram Figure 2-14. Timing Diagram Figure 2-15. Filter Circuit Diagram Figure 2-16. Thermal Monitor Figure 2-17. Clock Generation Distribution Figure 2-18. Pins Diagram Figure 2-19. Mechanical Diagram Figure 3-1. Overview Figure 3-2. Ethernet Mode Figure 3-3. SMII Timing Diagram Figure 3-4. GMII Timing Diagram Figure 3-5. Timing Diagram Figure 3-6. GMII Mode Timing Diagram Figure 3-7. OC-3c OC-12 OC-12c Configuration Figure 3-8. OC-48 Configuration Figure 3-9. OC-48c Configuration Figure 3-10. Receive POS8 Interface Timing 8-bit Data (OC-3c) Figure 3-11. Transmit POS8 Interface Timing 8-bit Data (OC-3c) Figure 3-12. Receive POS8 Interface Timing 8-bit Data (OC-12c) Figure 3-13. Transmit POS8 Interface Timing 8-bit Data (OC-12c) Figure 3-14. Receive POS32 Interface Timing 32-bit Data (OC-48c) Figure 3-15. Transmit POS32 Interface Timing 32-bit Data (OC-48c)
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Figure 4-1. Logical Organization Ingress Data Flow Management .136 Figure 4-2. Ring Structure .138 Figure 4-3. Ingress Logical Structure .139 Figure 5-1. Switch Interface Functional Blocks .144 Figure 5-2. Cell Header Format .146 Figure 5-3. Cell Header Format 32-Blade Mode .146 Figure 5-4. Frame Header Format .149 Figure 5-5. Frame Header Blade32 Format Bytes .150 Figure 5-6. Calculation Example .153 Figure 5-7. External Wrap Mode (Two NP4GS3 interconnected) .158 Figure 5-8. External Wrap Mode (single NP4GS3 configuration) .159 Figure 6-1. Egress Functional Blocks .164 Figure 6-2. Cell Formats Storage Egress .167 Figure 6-3. TPQ, FCB, Egress Frame Example .168 Figure 6-4. Timing .172 Figure 6-5. Hub-based configuration support more than NP4GS3s .174 Figure 6-6. Configuration Using External Transceivers .175 Figure 6-7. Egress Scheduler .178 Figure 7-1. Embedded Processor Complex Block Diagram .188 Figure 7-2. Dyadic Protocol Processor Unit Functional Blocks .191 Figure 7-3. Core Language Processor .193 Figure 7-4. Field Definition: Loading Halfword/Word GPRs from Halfword/Word Array .202 Figure 7-5. Field Definition: Loading Byte From Array Byte .203 Figure 7-6. Field Definition: Loading Halfword/Word from Array Byte .204 Figure 7-7. FIeld Definition: Store Byte/Halfword/Word Array Byte/Halfword/Word .205 Figure 7-8. ot3i Field Definition .218 Figure 7-9. ot2i Field Definition: Compare Halfword/Word Immediate .220 Figure 7-10. ot4i Field Definition Load Immediate Halfword/Word .221 Figure 7-11. ot4i Field Definition: Load Immediate Byte .222 Figure 7-12. ot3r Field Definition .224 Figure 7-13. Frame Ingress Data Store .231 Figure 7-14. Frame Egress Data Store .232 Figure 7-15. Ingress FCBPage Format .249 Figure 7-16. Egress FCBPage Format (NP4GS3B (R2.0)) .251 Figure 7-17. Egress FCBPage Format (NP4GS3C (R3.x)) .252 Figure 7-18. Dispatch Unit .284 Figure 7-19. Split between Picocode Hardware Policy Manager .297 Figure 7-20. Counter Manager Block Diagram .301 Figure 7-21. Counter Definition Entry .304
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Figure 7-22. Counter Blocks Sets Figure 8-1. Example Shaping Dimensions Figure 8-2. Effects Using Direct Table Figure 8-3. Example PSCB Detail Layout Memory Figure 8-4. Example PSCB Compact PSCB Layout Memory Figure 8-5. Multibit PSCB Detail Layout Figure 8-6. Example Multibit Tree Layout Figure 8-7. Example Input Leaf Pattern Fields Figure 8-8. Rope Structure Figure 8-9. General Layout Fields Shared Memory Pool Figure 8-10. General Layout RDLUDEF Shared Memory Pool Figure 8-11. Shared Memory Pool with DISTPOS_GDH Command Subfields Figure 8-12. Shared Memory Pool with PSCB Subfields Figure 8-13. No-Hash Function Figure 8-14. 192-Bit Hash Function Figure 8-15. Hash Function Figure 8-16. Network Dispatcher Hash Function Figure 8-17. 48-Bit Hash Function Figure 8-18. 60-Bit Hash Function Figure 8-19. 8-bit Hash Function Figure 8-20. 12-bit Hash Function Figure 8-21. Hash Function Figure 9-1. Interface Block Diagram Figure 9-2. Boot Image External EEPROM Figure 9-3. Timing Figure 9-4. Interface Write Protocol Figure 9-5. Interface Read Protocol Figure 10-1. PowerPC Subsystem Block Diagram Figure 10-2. Polled Access Flow Diagram Figure 11-1. System Environments Figure 13-1. NP4GS3 Memory Subsystems Figure 14-1. LVTTL Tolerant BP33 IP33 Receiver Input Current/Voltage Curve
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About This Book
This datasheet describes PowerNP NP4GS3 explains basics building system using Note: this document, NP4GS3C (R3.x) refers both PowerNP NP4GS3C (R3.0) PowerNP NP4GS3C (R3.1). terms abbreviations list provided Section Glossary Terms Abbreviations page 585.
Should Read This Manual
This datasheet provides information network hardware engineers programmers using NP4GS3 develop interconnect solutions Internet enterprise network providers. includes overview data flow through device descriptions each functional block. addition, provides electrical, physical, thermal, configuration information about device.
Related Publications
PowerPC 405GP Embedded Processor User's Manual Specification, version (http://www.pcisig.com)
Conventions Used This Manual
following conventions used this manual. notation following sections non-IBM, meaning that zero least significant most significant 4-byte word. Section Section Section Section Section Section Section Physical Description Physical Multiplexer Ingress Enqueuer Dequeuer Scheduler Switch Interface Egress Enqueuer Dequeuer Scheduler Embedded Processor Complex Serial Parallel Manager Interface
notation Section Tree Search Engine Section Embedded PowerPCSubsystem IBM-standard, meaning that least significant zero most significant 4-byte word. Nibble numbering same byte numbering. left-most nibble most significant starts zero. counters wrap back zero when they exceed their maximum values. Exceptions this rule noted counter definitions. Overbars (TxEnb, example) designate signals that asserted "low."
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Numeric notation follows: Hexadecimal values preceded example: x`0B00'. Binary values text either spelled (zero one) appear quotation marks. example: `10101'. Binary values Default Description columns register sections often isolated from text this example: action read access Auto-reset interrupt request register upon read access Field length conventions follows: byte bits word bytes double word (DW) words bytes quadword (QW) words bytes
signal field definitions, when field designated "Reserved": must sent zero input into NP4GS3, either signal value reserved field control block used input picocode process. must checked modified output from NP4GS3, either signal value reserved field control block used input external code process. code point results unpredictable behavior.
About This Book
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General Information
Features
million packets second (Mpps) Layer Layer switching. Eight dyadic protocol processor units (DPPUs) picocode processors DPPU shared coprocessors DPPU Four threads DPPU Zero context switching overhead between threads Embedded processor external 33/66 32-bit enhanced design flexibility. supports RISCWatch through JTAG interface Integrated Ethernet packet over SONET (POS) medium access controls (MACs) four Gigabit Ethernet Fast Ethernet ports, accessed through Serial MediaIndependent (SMII), Gigabit Media-Independent (GMII), Ten-Bit (TBI) interfaces, that support industry standard physical layer devices Ethernet statistics counters million software-defined, hardware-assisted counters, enabling support many standard Management Information Bases (MIBs) wire speed OC-3c, OC-12, OC-12c, OC-48, OC-48c integrated interfaces that support industry standard framers Hardware VLAN support (detection, insertion deletion). data-aligned synchronous link (DASL) ports Attach device Packet Routing Switch, another NP4GS3, itself. Rated 3.25 Gigabits second (Gbps) Compliant with EIA/JEDEC JESD8-6 standard differential HSTL Addressing capability target network processors, enabling design network systems with 1024 ports. PowerPC Advanced flow control mechanisms that tolerate high rates temporary oversubscription without collapse. Fast lookups powerful search engines based geometric hash functions that yield lower collision rates than conventional bitscrambling methods. Hardware support port mirroring1. Mirrored traffic share bandwidth with user traffic separate switch data path, eliminating normal penalty port mirroring. Support jumbo frames. NP4GS3C (R3.x): maximum length determined value Ethernet Jumbo Frame Size register (see Section 13.27 page 536). NP4GS3B (R2.0): maximum length fixed 9018 bytes. Both values increased four octets VLAN tagged frames. Hardware-managed, software-configured bandwidth allocation control 2047 concurrent communication flows. Serial management interface support physical layer devices, board, functions SA-27E, 0.18 technology. Voltage ratings: supply voltage compatibility with drivers receivers 1.25 reference voltage SSTL drivers compatibility DASL interfaces 1088-pin Bottom Surface Metallurgy Ceramic Column Grid Array (BSM-CCGA) package with Signal I/O. IEEE® 1149.1a JTAG compliant.
OC-48c ports supported port mirroring functions.
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Ordering Information
Part Number IBM32NPR161EPXCAE133 IBM32NPR161EPXCAF133 IBM32NPR162EPXCAG133 Description PowerNP NP4GS3B (R2.0) PowerNP NP4GS3C (R3.0) PowerNP NP4GS3C (R3.1)
Note: this document, NP4GS3C (R3.x) refers both PowerNP NP4GS3C (R3.0) PowerNP NP4GS3C (R3.1).
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Overview
PowerNPNP4GS3 network processor enables network hardware designers create fast, powerful, scalable systems. NP4GS3 contains Embedded Processor Complex (EPC) which processors coprocessors work with hardware accelerators increase processing speed power. Additional features, such integrated search engines, variable packet length schedulers, support functions, support needs customers require high function, high capacity, media-rate switching. NP4GS3 also highly scalable, capable supporting systems with 1024 ports. heart NP4GS3, evaluating, defining, processing data. maximizes speed processing power device provides with functionality above that independent switching device. Within EPC, eight dyadic protocol processor units (DPPUs) combine picocode processors, coprocessors, hardware accelerators support functions such high-speed pattern search, data manipulation, internal chip management, frame parsing, data prefetching. NP4GS3 provides fast switching integrating switching engine, search engine, security functions device. supports Layer Ethernet frame switching, includes three switch priority levels port mirroring, high priority user frames, priority frames. supports Ethernet, packet over SONET (POS), Point-to-Point Protocol (PPP) protocols. Because device's ability enforce hundreds rules with complex range action specifications, NP4GS3-based systems uniquely suited server clusters. NP4GS3-based systems range from desktop system with single device multi-rack systems with network processors. Scaling this nature accomplished through IBM's high performance, non-blocking, packet switching technology IBM's data-aligned synchronous link (DASL) interface, which adapted other switch technologies. Using NP4GS3 with Packet Routing Switch enables addressing ports. Third-party switches address 1024 ports. Systems developed with NP4GS3 distributed software model. support this model, device hardware Code Development Suite include on-chip debugger facilities, picocode assembler, picocode system simulator, which decrease time market applications. order take advantage these features, designer must know device works fits into system. following sections discuss basic placement device within system, major functional blocks, movement data through chapters following this overview explore these issues detail.
NP4GS3-Based Systems
NP4GS3 scalable, enabling multiple system configurations: Low-end systems with single device that uses Switch Interface (SWI) wrap traffic from ingress egress side Medium-end systems with devices that directly connected through their SWIs High-end systems with NP4GS3s that connected through single redundant switch; single Packet Routing Switch address NP4GS3s. High-end systems address Gigabit Ethernet 1024 Fast Ethernet (OC-3) ports.
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Systems developed with NP4GS3 distributed software model, which relies control point execute software instructions. high-end system, control point external microprocessor connected through Ethernet link interface. NP4GS3's Embedded PowerPC processor perform control point functions smaller system. this model, functions divided between control point network processor, illustrated Figure 1-1. control point supports Layer Layer routing protocols, Layer Layer network applications, maintenance, Management Information Base (MIB) collection (that control point functions SNMP agent), other systems management functions. Other functions, such forwarding, filtering, classification tables generated routing protocols, performed dyadic protocol processor units (DPPUs) each network processor system. Core Language Processors (CLPs) each DPPU execute EPC's core software instruction set, which includes conditional execution, conditional branching, signed unsigned operations, counts leading zeros, more. Figure 1-1. Function Placement NP4GS3-Based System
Packet Routing Switch 3.25 Gbps
Control Store
Control Store
Control Store
Data Store PowerNP PowerNP
Data Store PowerNP
Data Store
Control Point Support (Spanning Tree.) Support (OSPF.) Network Applications Networking Management Agent (RMON.) Services Forwarding Filtering Learning Forwarding Filtering Flow Classification Priority Shaping
PowerNP Frame Repository Queueing Flow Control Frame Alteration Multicast Handling
Network Management Counters
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Structure
PowerNP NP4GS3 network processor eight major functional blocks, illustrated Figure page Embedded PowerPC Ingress Enqueuer Dequeuer Scheduler (Ingress EDS) Egress Enqueuer Dequeuer Scheduler (Egress EDS) Ingress Switch Interface (Ingress SWI) Egress Switch Interface (Egress SWI) Provides processing functions device. control point device; Control Store interface provides program space PowerPC. Provides logic frames traveling from physical layer devices switch fabric. Provides logic frames traveling from switch fabric physical layer devices. Transfers frames from Ingress switch fabric another NP4GS3. Transfers frames from switch fabric another NP4GS3 Egress EDS.
Ingress Physical Receives frames from physical layer devices. Multiplexer (Ingress PMM) Egress Physical Multiplexer (Egress PMM) Transmits frames physical layer devices.
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Figure 1-2. NP4GS3 Major Functional Blocks
SDRAM SRAM
Ingress Enqueuer Dequeuer Scheduler
Ingress Switch Interface Internal SRAMs Embedded Power
Egress Switch Interface
Egress Enqueuer Dequeuer Scheduler
Interface
Data Store Ingress Multiplexed MACs
Embedded Processor Complex
SDRAM Data Store
Egress Multiplexed MACs
Physical Layer Devices
1.5.1 Structure contains eight dyadic protocol processor units (DPPUs). Each DPPU contains Core Language Processors (CLPs) that share coprocessors, coprocessor command bus, memory pool. eight DPPUs share threads, four which enhanced, three hardware accelerators. Together, eight DPPUs capable operating frames parallel. They share words internal picocode instruction store, providing 2128 million instructions second (MIPS) processing power. addition, contains Hardware Classifier parse frames fly, preparing them processing picocode.
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1.5.1.1 Coprocessors Each DPPU contains picocode processors, CLPs, that execute EPC's core instruction control thread swapping instruction fetching. CLPs share eight dedicated coprocessors that parallel with CLPs: Checksum Interface Calculates verifies frame header checksums. Controls thread access Control Access (CAB) through Arbiter; Control, Arbiter, Interface enable debug access NP4GS3 data structures. coprocessor response (CRB) interface internal coprocessor that enables attachment external coprocessor with results returned internal register. Picocode determines processing status (busy/ busy) busy managed coprocessor. Updates counters picocode engines. Interfaces frame buffer memory (ingress egress directions), providing 320-byte working area. Provides access Ingress Egress Data Stores. Manages control blocks containing frame parameters; works with Completion Unit hardware accelerator enqueue frames switch target port output queues. Determines incoming data stream complies with configured profiles. Accelerates data movement between coprocessors within shared memory pool. Performs pattern analysis through tree searches (based algorithms provided picocode) read write accesses, protected memory range checking; accesses Control Store memory independently. Assists controlling access shared resources, such tables control structures, through semaphores; grants semaphores either dispatch order (ordered semaphores) request order (unordered semaphores).
Coprocessor Response
Counter Data Store
Enqueue
Policy String Copy Tree Search Engine
Semaphore Manager
1.5.1.2 Enhanced Threads Each threads, making four threads DPPU, total. Twenty-eight threads General Data Handlers (GDHs), used forwarding frames, four threads enhanced: Guided Frame Handler (GFH) General Table Handler (GTH) Handles Guided Frames, in-band control mechanism between devices system, including control point. Builds table data Control Memory
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General PowerPC Handler Request (GPH-Req) General PowerPC Handler Response (GPH-Resp)
Processes frames bound Embedded PowerPC.
Processes responses from Embedded PowerPC.
1.5.1.3 Hardware Accelerators DPPUs share three hardware accelerators: Completion Unit Dispatch Unit Control Store Arbiter Assures frame order data exits threads. Fetches data parses work among DPPUs. Enables processors share access Control Store.
1.5.2 NP4GS3 Memory Storage NP4GS3 provided both internal external memories (see Figure page 32). Control Store contains tables, counters, other data needed picocode. Data Stores contain frame data forwarded used picocode (via Data Store coprocessor) create guided traffic. NP4GS3 following stores: common instruction memory that holds instruction words normal processing control functions internal SRAM input frame buffering internal SRAM Control Store High capacity external SDRAM egress frame buffering large forwarding tables; amount memory vary depending configuration. External SRAM fast table access interface interface (for Scheduler)
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Data Flow
Figure 1-3. Data Flow Overview
Switch Fabric
Ingress
Egress
Ingress
Embedded Processor Complex
Egress
Ingress Egress
Physical Layer Devices
1.6.1 Basic Data Flow many data flow routes possibilities exist fully document this overview. However, data generally moves through NP4GS3 following manner (see Figure 1-3): Ingress receives frame from physical layer device forwards Ingress EDS. Ingress identifies frame enqueues EPC. processes frame data (see Section 1.6.2). discard frame modify frame data directly then return updated data Ingress EDS's Data Store. frame enqueued Ingress EDS, Ingress Scheduler selects frame transmission moves data SWI. forwards frame switch fabric, another NP4GS3, Egress this device. Egress receives frame from switch fabric, another NP4GS3, from Ingress SWI. forwards frame Egress EDS, which reassembles frame enqueues once fully reassembled.
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processes (see Section 1.6.2). discard frame modify using frame alteration hardware assists. extensive modification required, append rewrite frame Data Store. frame enqueued Egress EDS, Egress Scheduler, enabled, selects frame transmission moves data Egress PMM. Scheduler enabled, forward frame target port queue, wrap port, GPH. Egress sends frame physical layer device. 1.6.2 Data Flow Figure 1-4. Basic Data Flow
Ingress Egress
Ingress Queue Interface
Completion Unit
Egress Queue Interface
Control Store Arbiter
Ingress
Available DPPU
Egress
Enqueue coprocessor
Tree Search Engine
Ingress Data Store Instruction Memory
Data Store coprocessor
Egress Data Store (External) Hardware Classifier
Dispatch Unit
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functional center device, plays pivotal role data flow. This section presents basic overview data flow EPC. Ingress Side Ingress enqueues data frame EPC. Dispatch Unit fetches portion frame sends next available thread. Simultaneously, Hardware Classifier (HC) determines starting Common Instruction Address (CIA), parses different frame formats (for example: bridged, IPX), forwards results thread. picocode examines information from examine data further; assembles search keys launches Tree Search Engine (TSE). performs table searches, using search algorithms based format downloaded tables. Control Store Arbiter allocates Control Store memory bandwidth among protocol processors. Frame data moves into Data Store coprocessor's memory buffer. Forwarding frame alteration information identified results search. Ingress insert overlay VLAN tags frame (hardware-assisted frame alteration) picocode allocate remove buffers allow alteration frame (flexible frame alteration). Enqueue coprocessor builds necessary information enqueue frame provides Completion Unit (CU), which guarantees frame order data moves from threads DPPU Ingress queues. frame enqueued Ingress EDS. Ingress forwards frame Ingress Scheduler. Scheduler selects frame transmission Ingress SWI. Note: entire frame sent once. Scheduler sends cell time. With help Ingress EDS, Ingress Switch Data Mover (I-SDM) (see Section beginning page 135) segments frames from switch interface queues into 64-byte cells inserts Cell Header Frame Header bytes they transmitted SWI. Egress Side Egress enqueues data frame EPC. Dispatch Unit fetches portion frame sends next available thread. Simultaneously, determines starting CIA, parses different frame formats (for example: bridged, IPX), forwards results thread. picocode examines information from examine data further; assembles search keys launches TSE. performs table searches, using search algorithms based format downloaded tables. Control Store Arbiter allocates Control Store memory bandwidth among protocol processors. Frame information, including alteration instructions, moves into queues Egress EDS; flexible frame alteration used, Data Store coprocessor moves additional frame data Data Store. Forwarding frame alteration information identified results search.
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PowerNP NP4GS3 Network Processor
NP4GS3 provides frame alteration techniques: hardware-assisted frame alteration flexible frame alteration: hardware-assisted frame alteration, commands passed Egress hardware during enqueueing. These commands can, example, update field header, generate frame CRC, overlay existing Layer wrapper with one. flexible frame alteration, picocode allocates additional buffers Data Store coprocessor places data into these buffers. additional buffers allow prepending data received frame bypassing part received data when transmitting. This useful frame fragmentation when when header header must prepended received data order form frame fragment correct size. Enqueue coprocessor builds necessary information enqueue frame Egress provides which guarantees frame order data moves from threads DPPU Egress queues. frame enqueued Egress EDS. frame enqueued Egress EDS, which forwards Egress Scheduler enabled). Scheduler selects frame transmission target port queue. Scheduler enabled, will forward frame directly target queue. Egress selects frames transmission from target port queue moves their data Egress PMM.
General Information
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PowerNP NP4GS3 Preliminary Network Processor
Physical Description
Figure 2-1. Device Interfaces
Packet Routing Switch Packet Routing Switch
Data Stores: SRAM Control Store SDRAM Control Store D0/1/2/3 Interface SDRAM Control Store Interface SDRAM Control Store Interface Clk, TEST, RESET, etc. SDRAM
PowerNP NP4GS3
SDRAM
Interface
EEPROM Interface
Note: Memory Array consists following SDRAMs: DRAMs devices each DRAMs device each DRAM devices
SMll GMll
SMll GMll
SMll GMll
SMll GMll
EEPROM
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Physical Description
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PowerNP NP4GS3 Network Processor
Information
This section describes many interfaces associated pins NP4GS3 Network Processor. summary device's interfaces many pins each contains, Table 2-1: Signal Functions page information signal locations, Table 2-37: Complete Signal Listing Signal Name page Table 2-38: Complete Signal Listing Grid Position page 101. following table groups interfaces pins function, briefly describes them, points location specific information chapter. Table 2-1. Signal Functions (Page
Type 28.4 Gbps Packet Routing Switch Interface Flow Control SRAM Interface Interface with SRAM lookups Function Resources
Interface with Packet Table 2-2: 28.4 Gbps Packet Routing Switch Interface Pins page Routing Switch Table 2-3: Flow Control Pins page Table 2-4: SRAM Interface Pins page Table 2-5: SRAM Interface Pins page Figure 2-2: SRAM Timing Diagram page Table 2-10: Interface Pins page Table 2-11: Memory Pins page Figure 2-3: Control Timing Diagram page Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page
Interface with SDRAM used implement Memory memories
D4_0 D4_1 Memory
Table 2-12: D4_0 D4_1 Interface Pins page Interface with Figure 2-3: Control Timing Diagram page DRAM used implement Figure 2-4: Read Timing Diagram page memories Figure 2-5: Write Output Timing Diagram page Table 2-13: D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins page Figure 2-3: Control Timing Diagram page Figure 2-4: Read Timing Diagram page Figure 2-5: Write Output Timing Diagram page
D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory
Interface with SDRAM used implement PowerPC Store
Memory
Table 2-14: Interface Pins page Interface with Figure 2-3: Control Timing Diagram page DRAM used implement Figure 2-4: Read Timing Diagram page memories Figure 2-5: Write Output Timing Diagram page
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Table 2-1. Signal Functions (Page
Type Function Resources
Table 2-15: Interface Pins page Interface with physical Table 2-16: Interface Multiplexing page layer devices through folFigure 2-6: NP4GS3 Clock Connections page lowing buses: Table 2-18: Parallel Data 8B/10B Position Mapping (TBI Interface) page Table 2-19: Interface Pins: Mode page Figure 2-8: Timing Diagram page Table 2-21: Interface Pins: GMII Mode page Figure 2-9: GMII Timing Diagram page Table 2-23: Interface Pins: SMII Mode page Figure 2-10: SMII Timing Diagram page Figure 2-7: NP4GS3 Clock Connections (POS Overview) page Table 2-25: Interface Pins POS32 Mode page Table 2-26: Signals page Figure 2-11: Transmit Timing Diagram page Figure 2-12: Receive Timing Diagram page Table 2-28: Pins page Figure 2-13: Timing Diagram page
Interface
GMII SMII
Interface
Interface
Management
Translated into various "host" Table 2-30: Management Pins page buses external FPGA Figure 2-14: Timing Diagram page (SPM) Various interfaces Table 2-32: Miscellaneous Pins page Table 2-33: Signals Requiring Pull-Up Pull-Down page
Miscellaneous
2.1.1 Packet Routing Switch Interface Pins Table 2-2. 28.4 Gbps Packet Routing Switch Interface Pins (Page
Signal (Clock Domain) DASL_Out_A(7:0) (Switch DASL_Out_A(7:0) (Switch DASL_In_A(7:0) (Switch DASL_In_A(7:0) (Switch DASL_Out_B(7:0) (Switch Description positive half output eight custom power differential drivers. Runs frequency Switch_Clock_A negative half 8-bit differential described above. Runs frequency Switch_Clock_A positive half input eight custom power differential receivers. Runs frequency Switch_Clock_A negative half 8-bit differential described above. Runs frequency Switch_Clock_A positive half output eight custom power differential drivers. Runs frequency Switch_Clock_B Type Output DASL Output DASL Input DASL Input DASL Output DASL
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-2. 28.4 Gbps Packet Routing Switch Interface Pins (Page
Signal (Clock Domain) DASL_Out_B(7:0) (Switch DASL_In_B(7:0) (Switch DASL_In_B(7:0) (Switch Master_Grant_A(1:0) (Switch Master_Grant_B(1:0) (Switch Description negative half 8-bit differential described above. Runs frequency Switch_Clock_B positive half input eight custom power differential receivers. Runs frequency Switch_Clock_B negative half 8-bit differential described above. Runs frequency Switch_Clock_B Type Output DASL Input DASL Input DASL
Master Grant indicates whether connection switch fabric able receive cells Input from NP4GS3. definitions these I/Os configured Master Grant mode con- V-tolerant figuration registers. Section 13.2 page 472. LVTTL Master Grant indicates whether connection switch fabric able receive cells Input from NP4GS3. definitions these I/Os configured Master Grant mode con- V-tolerant figuration registers. Section 13.2 page 472. LVTTL
Multicast Grant indicates whether connection switch fabric able receive multicast cells. Bits (1:0) Definition grants Priority granted Multicast_Grant_A(1:0) Priority granted Priority granted this serves master grant high priority channel, priority channel. This signal runs frequency Switch Clock Multicast Grant indicates whether connection switch fabric able receive multicast cells from NP4GS3. Bits (1:0) Definition grants Priority granted Multicast_Grant_B(1:0) Priority granted Priority granted this serves master grant high priority channel, priority channel. This signal runs frequency Switch Clock
Input V-tolerant LVTTL
Input V-tolerant LVTTL
Send_Grant_A (Switch
Send Grant indicates whether connection NP4GS3 able receive cells from switch fabric. Output Unable (the Packet Routing Switch should send only idle cells) V-tolerant LVTTL Able NP4GS3 changes state this signal. Send Grant indicates whether connection NP4GS3 able receive cells from switch fabric. Output Unable (the Packet Routing Switch should send only idle cells) V-tolerant LVTTL Able NP4GS3 changes state this signal.
Send_Grant_B (Switch
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
2.1.2 Flow Control Interface Pins Table 2-3. Flow Control Pins
Signal I_FreeQ_Th Ingress Free Queue Threshold Threshold exceeded Threshold exceeded Remote Egress Status synchronization (sync) driven network processor that configured provide this signal. received other network processors. Shared data sync pulse. Indicates start time division multiplex cycle. Remote Egress Status data driven single network processor during designated time slot. exceeded Network processor's exponentially weighted moving average (EWMA) egress offered rate exceeds configured threshold. Description Type Output V-tolerant LVTTL Input/Output V-tolerant LVTTL
RES_Sync
RES_Data
Input/Output V-tolerant LVTTL Output CMOS 2.5V Output CMOS 2.5V
RES_Data_Drv_Enable Driver enable signal which used external drivers RES_Data.
RES_Sync_Drv_Enable Driver enable signal which used external driver RES_Sync.
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Physical Description
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PowerNP NP4GS3 Network Processor
2.1.3 Interface Pins These pins interface with SRAM lookups described Table Table 2-5. Table 2-4. SRAM Interface Pins
Signal LU_Clk LU_Addr(18:0)NP4GS3B (R2.0) LU_Addr(19:0) NP4GS3C (R3.x) LU_Data(35:0) Description Look-Up clock. period (133 MHz). Type Output CMOS Output CMOS Input/Output CMOS Output CMOS Input/Output CMOS
Look-Up Address signals sampled rising edge LU_Clk.
Look-Up Data. When used SRAM inputs, rising edge LU_Clk samples these signals. Look-Up Read/Write control signal sampled rising edge LU_Clk. Write Read Coprocessor Response (CRB). Results from external coprocessor sent specified thread's Coprocessor stored into Results register.
LU_R_Wrt
cam_cp_response(13:0)
Table 2-5. SRAM Interface Pins
Signal SCH_Clk Description SRAM Clock input. period (133 MHz). Type Output CMOS Output CMOS Input/Output CMOS Output CMOS
SCH_Addr(18:0)
SRAM Address signals sampled rising edge LU_Clk.
SCH_Data(17:0)
Data bus. When used SRAM input, rising edge SCH_Clk samples these signals. Read/Write control signal sampled rising edge SCH_Clk. Write Read
SCH_R_Wrt
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Figure 2-2. SRAM Timing Diagram
Outputs
XX_Clk (MAX) XX_Addr (MIN)
tDWE (MAX)
tDWE (MIN)
XX_R_Wrt
tDCKON
tDCKOFF
XX_Data
(MAX)
(MIN)
Inputs
+VDD/2 Notes: Data Invalid
Output Load ohms
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-6. SRAM Timing Diagram Legend (for Figure 2-2)
NP4GS3B (R2.0) Symbol tDWE tDCKON tDCKOFF Symbol Description Minimum (ns) Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Read/Write Output Delay Data Output Delay Data Output Turn Data Output Turn Input Data Setup Time Input Data Hold Time Maximum (ns) Minimum (ns) Maximum (ns) NP4GS3C (R3.x)
Note: delays measured with slew time measured from input voltage.
2.1.4 DRAM Interface Pins pins described here interface with DRAM implement data store, control store, PowerPC store. control, read, write timing diagrams (Figure 2-3, Figure 2-4, Figure 2-5) apply tables this section.
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Figure 2-3. Control Timing Diagram
dy_nclk dy_clk (MAX) dx_Addr (MIN)
(MAX) dx_WE
(MIN)
tDCS (MAX) dx_CS
tDCS (MIN)
tDBA (MAX) dy_BA
tDBA (MIN)
tDRAS (MAX) dy_RAS
tDRAS (MIN)
tDCAS (MAX) dy_CAS
tDCAS (MIN)
+VDD/2
Notes: D0,D1,D2,D3,D4,D6,DS0,DS1 DA,DB,DC,DD,DE
Data Invalid
Output Load ohms
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Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-4. Read Timing Diagram
dy_nclk dy_clk
tCSS
dx_dqs
tDQSQ (MIN) tDQSQ (MAX) dx_dq
tDQSQ (MIN) tDQSQ (MAX)
+VDD/2
Notes: D0,D1,D2,D3,D4,D6,DS0,DS1
DA,DB,DC,DD,DE Data Invalid
Ouput Load ohms
Physical Description
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Figure 2-5. Write Output Timing Diagram
dy_nclk dy_clk
tCSD
dx_dqs
dx_dq
d6_ByteEn
+VDD/2 Notes: DS0, Data Invalid
Ouput Load ohms Byte enablement only.
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-7. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values
DS0,
NP4GS3B (R2.0) Symbol tDCS tDRAS tDCAS tCSD tCSS tDQSQ Symbol Description Minimum (ns) Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Clock Strobe Input Skew Data Input Skew 0.45 0.45 -1.6 0.55 0.55 Maximum (ns) Minimum (ns) 0.45 0.45 -2.0 0.55 0.55 Maximum (ns) NP4GS3C (R3.x)
Note: delays measured with skew time measured from 10-90% input voltage. measurements made with Test Load ohms dx_dqs descriptions DS0, DS1, interfaces (Section 2.1.4.2 page Section 2.1.4.4 page describe association data strobe data. This association dependent setting Strobe_cntl DRAM configuration register described Section 13.1.2 page 462.
Physical Description
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Table 2-8. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values 4-bit
Interface Mode.
NP4GS3B (R2.0) Symbol tDCS tDRAS tDCAS tCSD tCSS Symbol Description Minimum (ns) Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Byte Enable Strobe Setup Time Byte Enable Strobe Hold Time Clock Strobe Input Skew Data Input Skew d6_data_00-03 Data Input Skew d6_data_04-07 Data Input Skew d6_data_08-11 tDQSQ Data Input Skew d6_data_12-15 Data Input Skew d6_parity_00 Data Input Skew d6_parity_01 0.45 0.45 -1.5 0.55 0.55 Maximum (ns) Minimum (ns) 0.45 0.45 -2.0 0.55 0.55 Maximum (ns) NP4GS3C (R3.x)
Note: delays measured with slew time measured from 10-90% input voltage. measurements made with Test Load ohms
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-9. Timing Diagram Legend (for Figure 2-3, Figure 2-4, Figure 2-5) Values 16-bit
Interface Mode.
Symbol Symbol Description NP4GS3B (R2.0) Minimum (ns) tDCS tDRAS tDCAS tCSD tCSS Clock Cycle Time Clock Pulse Width High Clock Pulse Width Address Output Delay Write Enable Output Delay Chip Select Output Delay Bank Address Output Delay Output Delay Output Delay dy_clk dx_dqs Strobe Output Delay Data Strobe Output Setup Time Data Strobe Output Hold Time Byte Enable Strobe Setup Time Byte Enable Strobe Hold Time Clock Strobe Input Skew Data Input Skew d6_data_00-07 Data Input Skew d6_data_08-15 tDQSQ Data Input Skew d6_parity_00 Data Input Skew d6_parity_01 0.45 0.45 -1.5 0.55 0.55 Maximum (ns) NP4GS3C (R3.x) Minimum (ns) 0.45 0.45 -2.1 0.55 0.55 Maximum (ns)
Note: delays measured with slew time measured from 10-90% input voltage. measurements made with Test Load ohms
2.1.4.1 Interface Pins These pins interface with SDRAM used implement control stores. Table 2-10. Interface Pins (Page
Signal Shared Signals DB_Clk positive output differential pair. MHz. Common memory devices. negative output differential pair. MHz. Common memory devices. Output SSTL2 Output SSTL2 Output SSTL2 Description Type
DB_Clk
DB_RAS
Common address strobe (common D1).
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Table 2-10. Interface Pins (Page
Signal DB_CAS Description Common column address strobe (common D1). Type Output SSTL2 Output SSTL2
DB_BA(1:0) Signals D3_Addr(12:0)
Common bank address (common D1).
address
Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS
D3_DQS(1:0)
data strobes
D3_Data(15:0)
data
D3_WE
write enable
D3_CS Signals D2_Addr(12:0)
chip select
address
Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS
D2_DQS(1:0)
data strobes
D2_Data(15:0)
data
D2_WE
write enable
D2_CS Signals D1_Addr(12:0)
chip select
address
Output CMOS Input/Output SSTL2
D1_DQS(1:0)
data strobes
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-10. Interface Pins (Page
Signal D1_Data(15:0) data Description Type Input/Output SSTL2 Output CMOS Output CMOS
D1_WE
write enable
D1_CS
chip select
Table 2-11. Memory Pins
Signal D0_0 D0_1 Shared Signals DE_Clk positive output differential pair. MHz. Common D0_0/1 memory devices. Output SSTL2 Output SSTL2 Output CMOS Output CMOS Output CMOS Output CMOS Input/Output SSTL2 Input/Output SSTL2 Output CMOS Output CMOS Description Type
DE_Clk
negative output differential pair. MHz. Common D0_0/1 devices.
DE_RAS
Common address strobe
DE_CAS
Common column address strobe
DE_BA(1:0)
Common bank address
D0_Addr(12:0)
address
D0_DQS(3:0)
data strobes
D0_Data(31:0)
data
D0_WE
write enable
D0_CS
chip select
2.1.4.2 D4_0 D4_1 Interface Pins These pins interface with DRAM used implement control store.
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Table 2-12. D4_0 D4_1 Interface Pins
Signal DD_Clk Description positive output differential pair. MHz. Common D4_0/1 memory devices. Type Output SSTL2 Output SSTL2 Output CMOS Output CMOS Output CMOS Output CMOS
DD_Clk
negative output differential pair. MHz. Common D4_0/1 memory devices.
DD_RAS
Common address strobe
DD_CAS
Common column address strobe
DD_BA(1:0)
Common bank address
D4_Addr(12:0)
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0 data
D4_DQS(3:0)
Input/Output SSTL2
D4_Data(31:0)
Input/Output SSTL2 Output CMOS Output CMOS
D4_WE
write enable
D4_CS
chip select
2.1.4.3 D6_x Interface Pins These pins interface with SDRAM used implement PowerPC store. Table 2-13. D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins (Page
Signal DA_Clk Description positive output differential pair. MHz. Common memory devices. Type Output SSTL2 Output SSTL2 Output SSTL2
DA_Clk
negative output differential pair. MHz. Common memory devices.
DA_RAS
Common address strobe (common D6).
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-13. D6_5, D6_4, D6_3, D6_2, D6_1, D6_0 Memory Pins (Page
Signal DA_CAS Description Common column address strobe (common D6). Type Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2 Output SSTL2
DA_BA(1:0)
Common bank address (common D6).
D6_WE
Common write enable (common D6).
D6_Addr(12:0)
address
D6_CS
chip select data strobes. Data bits associated with strobe bits follows: D6_DRAM_Size `0xx' D6_DRAM_Size `1xx' 15:12 15:8 11:8 data byte enables byte masking write Data masked when D6_ByteEn high. Data bits associated with byte enable follows: 15:8 parity signals, byte. Must separate chips allow byte write capability. Data bits associated with parity bits follows: 15:8 data strobe parity signals
D6_DQS(3:0)
Input/Output SSTL2
D6_Data(15:0)
Input/Output SSTL2 Input/Output SSTL2
D6_ByteEn(1:0)
D6_Parity(1:0)
Input/Output SSTL2 Input/Output SSTL2
D6_DQS_Par(1:0)
2.1.4.4 Interface Pins These pins interface with DRAM used implement data stores. Table 2-14. Interface Pins
Signal Shared Signals DC_Clk positive output differential pair. MHz. Common memory devices. negative output differential pair. MHz. Common memory devices. Output SSTL2 Output SSTL2 Description Type
DC_Clk
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Table 2-14. Interface Pins
Signal DC_RAS Description Common address strobe (common DS0). Type Output SSTL2 Output SSTL2 Output SSTL2
DC_CAS
Common Column address strobe (common DS0).
DC_BA(1:0) Signals DS1_Addr(12:0)
Common bank address (common DS0).
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0 data
Output CMOS
DS1_DQS(3:0)
Input/Output SSTL2
DS1_Data(31:0)
Input/Output SSTL2 Output CMOS Output CMOS
DS1_WE
write enable
DS1_CS Signals DS0_Addr(12:0)
chip select
address data strobes. Data bits associated with strobe bits follows: Strobe_cntl `01' Strobe_cntl `00' 31:24 23:16 15:8 31:0 data
Output CMOS
DS0_DQS(3:0)
Input/Output SSTL2
DS0_Data(31:0)
Input/Output SSTL2 Output CMOS Output CMOS
DS0_WE
write enable
DS0_CS
chip select
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Physical Description
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PowerNP NP4GS3 Network Processor
2.1.5 Interface Pins These pins allow Physical Multiplexer (PMM) interface with physical layer devices. NP4GS3 different sets pins Ten-Bit (TBI), Gigabit Media-Independent (GMII), Serial MediaIndependent (SMII), Packet over SONET (POS) interfaces. Table 2-15. Interface Pins
Signal DMU_A(30:0) Description Define first four interfaces configured TBI, SMII, GMII, POS. Table 2-16: Interface Multiplexing page directions definitions. Define second four interfaces configured TBI, SMII, GMII, POS. Table 2-16: Interface Multiplexing page directions definitions. Define third four interfaces configured TBI, SMII, GMII, POS. Table 2-16: Interface Multiplexing page directions definitions. Define fourth four interfaces configured TBI, SMII, GMII, Debug, POS. Table 2-16: Interface Multiplexing page directions definitions. Receive last byte position (valid 32-bit only) provides position last byte within final word packet transfer. This signal valid only when Rx_EOF high. Type V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL Input V-tolerant LVTTL
DMU_B(30:0)
DMU_C(30:0)
DMU_D(30:0)
Rx_LByte(1:0)
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Table 2-16. Interface Multiplexing
Mode Pin(s) DMU_A, DMU_B, DMU_C DMU_D GMII Interface Type SMII Debug (DMU_D only) 8-Bit RxAddr(1) RxAddr(0) TxAddr(1) TxAddr(0) TxSOF Tx_Valid_Byte Tx_Data(7:0) Rx_Data(7:0) Tx_Clk Tx_En Tx_Er Rx_Valid_Byte Tx_Byte_Credit Rx_Clk Rx_DV Rx_Er CPDetect CPF) Input Tx_Data(0:7) Rx_Data(0:7) Tx_Clk Tx_Data(8) Tx_Data(9) Rx_Data(8) Rx_Data(9) Rx_Clk1 Rx_Clk0 Sig_Det CPDetect CPF) Input Activity Output Tx_Data(9:2) Rx_Data(9:2) Tx_Data(1) Tx_Data(0) Rx_Data(1) Rx_Data(0) Sync Sync2 CPDetect CPF) Input Debug(23:16) Debug(15:8) Debug(7) Debug(6) Debug(5) Debug(4) Debug(3) Debug(2) Debug(1) Debug(0) TxEOF TxData(7:0) RxData(7:0) TxEn TxPFA RxPFA RxVal RxEOF RxErr RxEnb
(24:17) (16:9)
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Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-6. NP4GS3 Clock Connections
GMII Interface
oscillator
PowerNP clock125 DMU_*(8) DMU_*(3) Tx_Clk Rx_Clk
GMII port)
SMII Interface
PowerNP
oscillator
DMU_*(8) DMU_*(3)
Note: trace lengths inputs will matched card.
SMII ports)
SMII ports)
Interface
PowerNP Clock_Core 53.3 oscillator
oscillator
clock125
asynchronous interface DMU_*(8) Tx_Clk DMU_*(3) Rx_Clk1 62.5 DMU_*(2) Rx_Clk0 62.5
ports)
Notes: Each figure above illustrates single applies four busses. "DMU_*" labels represent four busses (DMU_A, DMU_B, DMU_C, DMU_D).
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Figure 2-7. NP4GS3 Clock Connections (POS Overview)
Single (applies A-D)
PowerNP
DMU_*(8)
DMU_*(3) oscillator
TxClk
RxClk
Note: trace lengths inputs will matched card.
AFramer (except OC-48)
PowerNP
DMU_A(8) DMU_A(3) DMU_B(8) DMU_B(3) DMU_C(8) DMU_C(3) DMU_D(8) DMU_D(3)
oscillator
TxClk
RxClk
Note: trace lengths inputs will matched card.
AFramer (OC-48)
2.1.5.1 Pins Table 2-17. Interface Pins: Debug (DMU_D Only)
Signal Description When DMU_D configured debug bus, signals internal NP4GS3 available observed externally. This mode supported only when directed Network Processor Application Engineer. recommended that board designs provide attachment scope probes observe this interface which runs 133MHz. Type Output V-tolerant LVTTL
Debug (23:0)
Table 2-18. Parallel Data 8B/10B Position Mapping (TBI Interface)
Parallel Data 8B/10B Position
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Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-19. Interface Pins: Mode
Signal Tx_Data(9:0) Description Transmit data. Data PHY, synchronous Tx_Clk. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(9:0)
Receive data. Data from PHY, synchronous Rx_Clk1 Rx_Clk0. (Data switches double frequency Rx_Clk1 Rx_Clk0.)
Rx_Clk1
Receive Clock, 62.5 MHz. Rx_Data valid rising edge this clock.
Rx_Clk0
Receive Clock, 62.5 MHz. This signal degrees phase with Rx_Clk1. Rx_Data valid rising edge this clock.
Sig_Det
Signal Detect. Signal asserted indicate that physical media valid. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (page 531) when Blade_Reset signal deasserted. After configuration, this signal driven network processor indicate status interface. interface data pass state (link down) interface data pass state (occurs when auto-negotiation complete, when idles detected disabled)) pulse interface data pass state either receiving transmitting. line pulses once frame transmitted received maximum rate 8Hz. clock Transmit clock PHY. During operation, network processor drives this signal indicate that transmit receive progress this interface.
CPDetect
Input/Output V-tolerant LVTTL
Tx_Clk
Output V-tolerant LVTTL
Note: Table 2-16: Interface Multiplexing page directions (I/O) definitions.
Physical Description
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PowerNP NP4GS3 Preliminary Network Processor
Figure 2-8. Timing Diagram
Transmit Timings tXCK tXCH Tx_Clk (MAX) (MIN) Tx_Data tXCL
Receive Timings
tRCK tRCH tRCL
Rx_Clk0 tRDH Rx_Data tRDS tRCK tRCL Rx_Clk1 tRDH Rx_Data tRDS tRCH tRSH
+VDD/2 Notes: tRSS Data Invalid
Output Load ohms
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-20. Timing Diagram Legend (for Figure 2-8)
Symbol tXCK tXCH tXCL tRCK tRCH tRCL tRDS tRDH tRDS tRDH Tx_Clk Transmit Cycle Time Tx_Clk Pulse Width High Tx_Clk Pulse Width Tx_Data_(7:0) Output Delay Rx_Clk0/Rx_Clk1 Receive Cycle Time Rx_Clk0/Rx_Clk1 Pulse Width High Rx_Clk0/Rx_Clk1 Pulse Width Rx_Data_(9:0) Setup Time Clk0 Rx_Data_(9:0) Hold Time Clk0 Rx_Data_(9:0) Setup Time Clk1 Rx_Data_(9:0) Hold Time Clk1 Symbol Description Minimum (ns) Maximum (ns)
Note: delays measured with slew time measured from 10-90% input voltage.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
2.1.5.2 GMII Pins Table 2-21. Interface Pins: GMII Mode
Signal Tx_Data(7:0) Description Transmit Data. Data PHY, synchronous Tx_Clk. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(7:0)
Received Data. Data from PHY, synchronous Rx_Clk. Transmit data Enabled PHY, synchronous Tx_Clk. frame transmission Active frame transmission Transmit Error, synchronous Tx_Clk. error detected Informs that detected error Receive valid data, synchronous Rx_Clk. Data invalid Byte data (from PHY) Rx_Data valid. standard GMII connection, this signal tied card. Transmit next data value, asynchronous. send next data byte Asserted. indicates that next Tx_Data value sent. standard GMII connection, this signal tied card. Transmit valid data, synchronous Tx_Clock Data invalid Byte data (from Network Processor) Tx_Data valid. Receive Medium clock generated PHY. Receive Data Valid (from PHY), synchronous Rx_Clk. frame transmission. Active frame transmission. Receive Error, synchronous Rx_Clk. error detected Informs that detected error transmit clock PHY. During operation, network processor drives this signal indicate that transmit progress this interface. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (page 531) when Blade_Reset signal deasserted.
Tx_En
Tx_Er
Rx_Valid_Byte
Tx_Byte_Credit
Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Tx_Valid_Byte
Rx_Clk
Rx_DV
Rx_Er
Tx_Clk
CPDetect
Note: NP4GS3 supports GMII Full-Duplex Mode only. Table 2-16: Interface Multiplexing page directions (I/O) definitions.
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-9. GMII Timing Diagram
Transmit Timings tXCH Tx_Clk (MAX) Tx_Data tDEN (MAX) Tx_En tDER (MAX) Tx_Er tDVB (MAX) Tx_Valid_Byte tDBV (MIN) tDER (MIN) tDEN (MIN) (MIN) tXCL
Receive Timings tRCH Rx_Clk tRDH Rx_Data tRDS tRVH Rx_Valid_Byte tRVS tREH Rx_Er tRES tRDVH Rx_DV tRDVS tRCL
Notes: Data Invalid
Output Load ohms
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Table 2-22. GMII Timing Diagram Legend (for Figure 2-9)
Symbol tXCH tXCL tRCH tRCL tDER tDVB tDEN tRDS tRDH tRVS tRVH tRES tREH tRDVS tRDVH Tx_Clk Cycle Time Transmit Clock Pulse Width High Transmit Clock Pulse Width Receive Clock Pulse Width High Receive Clock Pulse Width Tx_data Output Delay Tx_Er Output Delay Tx_Valid_Byte Output Delay Tx_En Output Delay Rx_data Setup Time Rx_data Hold Time Rx_Valid_Byte Setup Time Rx_Valid_Byte Hold Time Rx_Er Setup Time Rx_Er Hold Time Rx_DV Setup Time Rx_DV Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
2.1.5.3 SMII Pins Table 2-23. Interface Pins: SMII Mode
Signal Tx_Data(9:0) Description Transmit Data. Data contains streams serial transmit data. Each serial stream connected unique port. Synchronous common clock (Clk). Received Data. Data from contains streams serial receive data. Each serial stream connected unique port. Synchronous common clock (Clk). Asserted Tx_Clk cycle once every Tx_Clk cycles. Assertion indicates beginning 10-bit segment both Tx_Data Rx_Data. Type Output V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
Rx_Data(9:0)
Sync
Sync2
Logically identical Sync provided fanout purposes. This must pulled indicate when Control Point active this interface. Otherwise, this signal should pulled high (inactive). state signal captured Data Mover Unit (DMU) Configuration (see 13.25 Data Mover Unit (DMU) Configuration Registers page 531) when Blade_Reset signal deasserted.
CPDetect
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-10. SMII Timing Diagram
Transmit Timings (MAX) Tx_Data (MAX) Sync tDS2 (MAX) Sync2 tDS2 (MIN) (MIN) (MIN)
Receive Timings Rx_Data +VDD/2
Notes: Data Invalid
Output Load ohms
Table 2-24. SMII Timing Diagram Legend (for Figure 2-10)
Symbol tDS2 Cycle Time Pulse Width High Pulse Width Tx_data_(9:0) Output Delay Sync Output Delay Sync2 Output Delay Rx_data_(9:0) Setup Time Rx_data_(9:0) Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
2.1.5.4 Pins Table 2-25. Interface Pins POS32 Mode
Pin(s) (24:17) (16:9) DMU_A TxPADL(1) TxPADL(0) TxSOF TxEOF TxData(31:24) RxData(31:24) TxEn TxPFA RxPFA RxVal RxEOF RxErr RxEnb Single Pins (not associated with DMU) Rx_LByte(1:0) Rx_LByte(1) Rx_LByte(0) TxData(23:16) RxData(23:16) TxData(15:8) RxData(15:8) TxData(7:0) RxData(7:0) DMU_B DMU_C DMU_D
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-26. Signals
Signal RxAddr(1:0) RxData (7:0) 8-bit mode (31:0) 32-bit mode Description Receive address selects particular port framer data transfer. Valid rising edge Clk. Receive data carries frame word that read from Framer's FIFO. RxData transports frame data 8-bit format. RxData[7:0] [31:0] updated rising edge Clk. clock provides timing Framer interface. must cycle lower instantaneous rate. Receive read enable controls read access from Framer's receive interface. framer's addressed FIFO selected falling edge RxEnb. Generated rising edge Clk. Receive end-of-frame marks last word frame RxData. Updated rising edge Clk. Receive packet error indicates that received packet contains error must discarded. Only asserted last word packet (when RxEOF also asserted). Updated rising edge Clk. Receive valid data output indicates receive signals RxData, RxEOF, RxErr, Rx_LByte valid from framer. Updated rising edge Clk. Receive padding length indicates number padding bytes included last word packet transferred RxData. Only used when network processor configured 32-bit mode. Updated rising edge Clk. Rx_LByte(1:0) (32-bit mode) packet ends RxData(7:0) (RxData DDDD) packet ends RxData(15:8) (RxData DDDP) packet ends RxData(23:16) (RxData DDPP) packet ends RxData(31:24) (RxData DPPP) Receive polled frame-available input indicates that framers polled receive FIFO contains data. Updated rising edge Clk. Transmit UTOPIA data carries frame word that written framer's transmit FIFO. Considered valid written framer's transmit FIFO only when transmit interface selected using TxEnb. Sampled rising edge Clk. Transmit write enable controls write access transmit interface. framer port selected falling edge TxEnb. Sampled rising edge Clk. Transmit address uses TxEnb select particular FIFO within framer data transfer. Sampled rising edge Clk. Transmit start-of-frame marks first word frame TxData. Sampled rising edge Clk. Transmit end-of-frame marks last word frame TxData. Sampled rising edge Clk. Transmit padding length indicates number padding bytes included last word packet transferred TxData. Sampled rising edge Clk. When configured 32-bit mode last word contain zero, one, three padding bytes only TxPADL[1:0] used. TxPADL[1:0] (32-bit mode) packet ends TxData[7:0] (TxData DDDD) packet ends TxData[15:8] (TxData DDDP) packet ends TxData[23:16] (TxData DDPP) packet ends TxData[31:24] (TxData DPPP) Transmit polled frame-available output indicates that polled framer's transmit FIFO free available space NP4GS3 write data into framer's FIFO. Updated rising edge Clk. Type V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL
RxEnb
RxEOF
RxErr
RxVal
Rx_LByte(1:0)
V-tolerant LVTTL
RxPFA TxData (7:0) 8-bit mode (31:0) 32-bit mode TxEn TxAddr(1:0) TxSOF TxEOF
V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL V-tolerant LVTTL
TxPADL (1:0)
V-tolerant LVTTL
TxPFA
V-tolerant LVTTL
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Figure 2-11. Transmit Timing Diagram
(MAX) TxData tDXA (MAX) TxAddr tDRA (MAX) RxAddr tDSOF (MAX) TxSOF tDEOF (MAX) TxEOF tDEN (MAX) TxEN tDPADL (MAX) TxPADL tDREN (MAX) RxEnb +VDD/2 Notes: Output Load ohms Data Invalid tDREN (MIN) tDPADL (MIN) tDEN (MIN) tDEOF (MIN) tDSOF (MIN) tDRA (MIN) tDXA (MIN) (MIN)
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-12. Receive Timing Diagram
tRXH RxData tRXS tRPFH RxPFA tRPFS tTPFH RxErr tTPFS tRVH RxVal tRVS
tREOFH RxEOF tREOFS tTPFH TxPFA tTPFS tRPADH RxPADL tRPADS +VDD/2 Notes: Data Invalid
Output Load ohms
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Table 2-27. Timing Diagram Legend (for Figure 2-11 Figure 2-12)
Symbol tDXA tDRA tDSOF tDEOF tDEN tDPADL tDREN tRXS tRXH tRVS tRVH tRERS tRERH tREOFS tREOFH tRPFS tRPFH tTPFS tTPFH tRPADS tRPADH Cycle Time Clock Width High Clock Width Tx_data_(31:0) Output Delay Tx_ADDR_(1:0) Output Delay Rx_ADDR_(1:0) Output Delay TxSOF Output Delay TxEOF Output Delay TxEn Output Delay TxPADL_(1:0) Output Delay RxEnb Output Delay Rx_data_(31:0) Setup Time Rx_data_(31:0) Hold Time RxVal Setup Time RxVal Hold Time RxErr Setup Time RxErr Hold Time RxEOF Setup Time RxEOF Hold Time RxPFA Setup Time RxPFA Hold Time TxPFA Setup Time TxPFA Hold Time RxPADL Setup Time RxPADL Hold Time Symbol Description Minimum (ns) Maximum (ns)
delays measured with slew time measured from 10-90% input voltage.
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
2.1.6 Pins These pins interface with bus. Table 2-28. Pins (Page
Signal PCI_Clk Description Clock Signal (See PCI_Speed field below) Type Input (in)/ Input/Output (t/s) Input/Output (t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Input/Output (s/t/s) Output (t/s) Input (t/s) Input (in) Input/Output (s/t/s) Input/Output (o/d) Output (o/d) Input/Output (t/s)
PCI_AD(31:0)
Multiplexed Address Data Signals
PCI_CBE(3:0)
Command/Byte Enable Signals
PCI_Frame
Frame Signal
PCI_IRdy
Initiator (Master) Ready Signal
PCI_TRdy
Target (Slave) Ready Signal
PCI_DevSel
Device Select Signal
PCI_Stop
Stop Signal
PCI_Request
Request Signal
PCI_Grant
Grant Signal
PCI_IDSel
Initialization Device Select Signal
PCI_PErr
Parity Error Signal
PCI_SErr
System Error Signal
PCI_IntA
Level Sensitive Interrupt
PCI_Par
Parity Signal. Covers data/address four command/BE signals.
Note: I/Os configured multi-point operation.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Table 2-28. Pins (Page
Signal Description Speed. Controls Acceptable Frequency Asynchronous Range setting PLB/ clock ratio. PLB:PCI Mode 2:1. Acceptable Frequency Asynchronous Range 34.5 66.6 PLB:PCI Mode 3:1. Acceptable Frequency Asynchronous Range 23.5 44.5 External Non-maskable Interrupt active polarity interrupt programmable PowerPC. External Maskable Interrupt active polarity interrupt programmable PowerPC. Type
PCI_Speed
Input V-tolerant
PCI_Bus_NM_Int
Input Input
PCI_Bus_M_Int
Note: I/Os configured multi-point operation.
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
Page
PowerNP NP4GS3 Network Processor
Figure 2-13. Timing Diagram
Outputs
PCI_Clk tVAL
tOFF
Inputs
VDD/2
Notes: Data Invalid
Output Load ohms
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Table 2-29. Timing Diagram Legend (for Figure 2-13)
Symbol tVAL tOFF Cycle Time Clock Width High Clock Width Worst Case Output Delay Turn Output Delay Turn Output Delay Input Setup Time Input Hold Time Symbol Description Minimum (ns) Maximum (ns)
Note: delays measured with slew time measured from 10-90% input voltage.
2.1.7 Management Interface Pins signals from these pins translated into various "host" buses external field-programmable gate array (FPGA) Serial/Parallel Manager (SPM). Table 2-30. Management Pins
Signal MG_Data Description Serial Data. Supports Address/Control/Data protocol. Type Input/Output V-tolerant Output V-tolerant Input V-tolerant
MG_Clk
33.33 clock
MG_nIntr
Rising-edge sensitive interrupt input
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Figure 2-14. Timing Diagram
Outputs
MG_Clk (MAX) (MIN)
MG_Data
Inputs MG_Data
VDD/2
Notes:
Data Invalid
Output Load ohms
Table 2-31. Timing Diagram Legend (for Figure 2-14)
Symbol Cycle Time Clock Pulse Width High Clock Pulse Width Data Output Delay Data Setup Time Data Hold Time Symbol Description Minimum (ns) 14.4 14.4 15.6 15.6 Maximum (ns)
Note: mg_nintr asynchronous input timed. delays measured with slew time measured from 10-90% input voltage.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
2.1.8 Miscellaneous Pins Table 2-32. Miscellaneous Pins (Page
Signal Description positive input differential pair. 50.6875 62.5 MHz. Generates Packet Routing Switch clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. on-chip differential terminator ohms present between this complement pin. negative input differential pair. 50.6875 62.5 MHz. positive input differential pair. 50.6875 62.5 MHz. Generates Packet Routing Switch clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. on-chip differential terminator ohms present between this complement pin. negative input differential pair. 50.6875 62.5 MHz. Selects which DASL ports carries network traffic. Port carries network traffic Port carries network traffic 53.33 oscillator generates /133 clock domains. Required have cycle-to-cycle jitter ±150 Duty Cycle tolerance must ±10%. oscillator. Required have cycle-to-cycle jitter Duty Cycle tolerance must This clock required only when supporting GMII modes. Reset NP4GS3 signal must driven active minimum ensure proper reset NP4GS3. input clocks (Switch_Clock_A, Switch_Clock_A, Switch_Clock_B, Switch_Clock_B, Core_Clock, Clock125 use, PCI_Clk) must running prior activation this signal. NP4GS3 operational driven active when both NP4GS3 Ingress Egress Macros have completed their initialization. remains active until subsequent Blade_Reset issued. Testmode(1:0) JTAG_TRst Functional Mode, including concurrent JTAG interface RISCWatch CABWatch operations. Debug Mode Debug mode must indicated Testmode debug (DMU_D) output gated from probe. JTAG Test Mode LSSD Test Mode Type Input LVDS (see page 581) Input LVDS (see page 581) Input LVDS (see page 581) Input LVDS (see page 581) Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Input V-tolerant LVTTL Output (o/d) V-tolerant LVTTL
Switch_Clock_A
Switch_Clock_A
Switch_Clock_B
Switch_Clock_B
Switch_BNA
Core_Clock
Clock125
Blade_Reset
Operational
Input CMOS
JTAG test reset. normal functional operation, this must connected same card source that connected Blade_Reset input. When JTAG interface used JTAG test functions, this controlled JTAG interface logic card. JTAG test mode select. normal functional operation, this should tied either high. JTAG test data out. normal functional operation, this should tied either high.
Input V-tolerant LVTTL Input V-tolerant LVTTL Output V-tolerant LVTTL Input V-tolerant LVTTL
JTAG_TMS
JTAG_TDO
JTAG_TDI
JTAG test data normal functional operation, this should tied either high.
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Table 2-32. Miscellaneous Pins (Page
Signal JTAG_TCk Description JTAG test clock. normal functional operation, this should tied either high. These pins serve +1.8 Volt supply critical noise-sensitive portion phaselocked loop (PLL) circuits. serves analog each circuit. prevent noise these pins from introducing phase jitter outputs, place filters board level isolate these pins from noisy digital pins. Place separate filters each analog prevent noise from being introduced into another. section 2.1.9 Filter Circuit page filter circuit details. These pins serve ground connection critical noise portion phase lock loop (PLL). serves analog each circuit. Each should connected digital ground plane VDDA node filter capacitor shown Figure 2-15: Filter Circuit Diagram page Input thermal monitor (resistor). 2.1.10 Thermal Usage page details thermal monitor usage Output thermal monitor (resistor) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Voltage reference SSTL2 I/Os (approximately four pins side device that contains SSTL2 I/O) Determines location network processor picocode load location. Load from Load from external source (typically Power bus) Determines location Power code start location. Start from Start from Unused signals needed Manufacturing Test. Spare_Tst_Rcvr (9:5,1) should tied card. Spare_Tst_Rcvr (4:2,0) should tied card. This signal, when asserted low, forces embedded PowerPC processor stop processing instructions. normal functional operation, this signal should tied inactive high. Programmable These used chip manufacturing test purposes should left unconnected card. Type Input V-tolerant LVTTL
PLLA_VDD PLLB_VDD PLLC_VDD
Input PLL_VDD
PLLA_GND PLLB_GND PLLC_GND Thermal_In Thermal_Out VRef1(2), VRef2(8,7,6)
Input PLL_GND Thermal Thermal Input VRef 1.25 Input VRef 1.25 Input VRef 1.25 Input V-tolerant Input V-tolerant Input CMOS Input V-tolerant LVTTL Input/Output CMOS 2.5V
VRef1(1), VRef2(5,4,3)
VRef1(0), VRef2(2,1,0)
Boot_Picocode
Boot_PPC
Spare_Tst_Rcvr(9:0)
C405_Debug_Halt
PIO(2:0) PGM_GND PGM_VDD
termination network details signals contained PowerNP NP4GS3 Card Layout Guidelines.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
Table 2-33. Signals Requiring Pull-Up Pull-Down
Signal Name Function Value
Signals requiring connection that same value applications Testmode(1:0) JTAG_TDI JTAG_TMS JTAG_TCk C405_Debug_Halt Spare_Tst_Rcvr (9:5, Spare_Tst_Rcvr (4:2, Signals requiring connection that varies across different applications Multicast_Grant_A, Multicast_Grant_B RES_Data, RES_sync PCI_Speed MG_nIntr MG_Data Boot_Picocode Boot_PPC Switch_BNA Pull-up system device drives this signal Pull-down other system device drives this signal Choose down based system speed Pull-down system device drives this signal Pull-down when external module attached Choose down based picocode load location Choose down based code load location Pull-up system device drives this signal Pull when system diagnostics uses SRAM hold information through software controlled reset (see Software Controlled Reset Register (Soft_Reset) page 485). Pull down using 32-bit mode. Pull-down Pull-up Pull-up Pull-up Pull-up Pull-down Pull-up
LU_R_WRT, SCH_R_WRT
Rx_LByte(1:0)
Signals which have connection, also require pull-up pull-down Operational DMU_A(0), DMU_B(0), DMU_C(0), DMU_D(0) DMU_A(30:29), DMU_B(30:29), DMU_C(30:29), DMU_D(30:29) DMU_A(4), DMU_B(4), DMU_C(4), DMU_D(4) D3_DQS(1:0), D2_DQS(1:0), D1_DQS(1:0) D0_DQS(3:0), D4_DQS(3:0), D6_DQS(3:0) DS0_DQS(3:0), DS1_DQS(3:0) CPDetect 8-bit mode. RxAddr (1:0) mode. RxVal Pull-up control point blade then pull-down, otherwise pull-up Pull-down Pull-down Pull-down Pull-down Pull-down
Note: addition signals listed this table, interface signals that used particular application should pulled their inactive state (for control signals) down ground (for data signals). This prevents extraneous switching circuitry, which cause current surges that could affect other signals. Pull-down resistors should range 300-1000 signals being actively driven, eight signals connected single pull-down. this done, resistance value that pull-down should kept close range.
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
2.1.9 Filter Circuit VDDA voltage supply analog circuits PLL. Noise VDDA causes phase jitter output PLL. VDDA brought package isolate from noisy internal digital signal. little noise expected board level, then VDDA connected directly digital plane. most circumstances, however, prudent place filter circuit VDDA shown below. Note: wire lengths should kept short possible minimize coupling from other signals. impedance ferrite bead should much greater than that capacitor frequencies where noise expected. Many applications have found that resistor does better reducing jitter than ferrite bead does. resistor should kept value lower than Experimentation best determine optimal filter design specific application. Note: filter circuit used PLLA PLLB, second filter circuit should used PLLC. Figure 2-15. Filter Circuit Diagram
Ferrite Bead Digital (via board) VDDA PLL)
2.1.10 Thermal Usage thermal monitor consists resistor connected between pins PADA PADB. 25°C this resistance estimated 1500 ohms. published temperature coefficient resistance this technology 0.33% determine actual temperature coefficient, Measurement Calibration page Figure 2-16. Thermal Monitor
Thermal PADA PADB
Note: There electrostatic discharge (ESD) diode PADA PADB.
Physical Description
Page
np3_ds_sec02_phys.fm.11 January 2003
PowerNP NP4GS3 Preliminary Network Processor
2.1.10.1 Temperature Calculation chip temperature calculated from chip (Rmeasured Rcalibrated) where: measured resistance measured between PADA PADB test temperature. calibrated resistance measured between PADA PADB known temperature. calibrated known temperature used measure calibrated. 2.1.10.2 Measurement Calibration this thermal monitor accurately, must first calibrated. calibrate, measure voltage drop different known temperatures package while device dissipating little (less than Tcalibrated
power. Apply wait fixed time where approximately Keep short minimize heating effects thermal monitor resistance. Then measure Next, turn change package temperature. Reapply Idc, wait again measure
temperature coefficient
-Idc
where: temperature change, voltage drop, applied current, Vsupply Maximum
PADA Thermal PADB
Maximum measure voltage drop
np3_ds_sec02_phys.fm.11 January 2003
Physical Description
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PowerNP NP4GS3 Network Processor
Clocking Domains
Figure 2-17. Clock Generation Distribution
Switch Fabric Card 28.4G Packet Routing Switch Switch Fabric Card 28.4G Packet Routing Switch
frequency lock Switch_Clk_A MHz)
Switch_Clk_B MHz)
Switch Blade
DASL-A
DASL-B
NP4GS3 9.09 4.54-5 Packet Routing Switch Clock Domain 9.09 4.54-5 Packet Routing Switch Clock Domain Clock_Core
Divide
Divide
36.3 Divide 3.75
36.3 53.3
Core, DDR, Clock Domain
SMII, TBI, GMII Clock Domain Rx_Clk Tx_Clk Devices Note: Switch_Clk_A frequencies shown illustration purposes. These clocks range from 50.6875 62.5 MHz. Clock125 TBI, GMII DMU_*(03) SMII
NP4GS3 Clock Connections page NP4GS3 Clock Connections (POS Overview) page related clock information.
Physical Description np3_ds_sec02_phys.fm.11 January 2003
Page
PowerNP NP4GS3 Preliminary Network Processor
Figure 2-18. Pins Diagram
Corner
Signal Test Viewed through package Test Ground Note: illustrative purposes
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