TMPR3904AF System RISC) GENERAL DESCRIPTION TMPR3904AF

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TMPR3904AF System RISC) GENERAL DESCRIPTION TMPR3904AF

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INTEGRATED CIRCUIT
TMPR3904AF
System RISC)
GENERAL DESCRIPTION
TMPR3904AF called TX3904A hereinafter) standard micro controller 32bit RISC Microprocessor TX39 family. TX3904A uses TX39 Processor Core CPU. TX39 Processor Core RISC core Toshiba developed based R3000A architecture MIPS Technologies, Inc. micro-controllers that embedded, besides TX39 Processor Core, TX3904A built-in peripheral circuits such memory controllers, controllers, serial ports, timers/counters.
FEATURES
Built-in TX39 Processor Core Toshiba uniquely developed this basis R3000A architecture MIPS. Instruction cache 4KB/Data cache Built-in debug support unit DRAM Controller Four-bank two-channel configuration Fast page mode/Hyper page (EDO) mode support Controller Two-bank two-channel configuration Mask ROM, EPROM, E2PROM, Flash Memory, SRAM support Page mode support Controller Independent four channels Single address mode/Dual address mode Interrupt Controller Internal nine sources, external eight sources Non-maskable interrupt (NMI)
TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, observe standards safety, avoid situations which malfunction failure TOSHIBA product could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent products specifications. Also, please keep mind precautions conditions forth TOSHIBA Semiconductor Reliability Handbook. products described this document subject foreign exchange foreign trade control laws. information contained herein subject change without notice.
information contained herein presented only guide application products. responsibility assumed TOSHIBA infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights TOSHIBA others.
EJC-TMPR3904AF-1 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
Timer/Counter 24-bit counter three channels Watchdog timer mode support Serial Two-channel UART Ports Exclusive port: channel; shared port: channels 16-bit Support Power Supply Voltage: 3.3V Power Consumption: 900mW (3.3V, operation, Typ) Maximum Operation Frequency: Package: plastic
R3000A trademark MIPS Group, division Silicon Graphics, Inc.
EJC-TMPR3904AF-2 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSTEM CONFIGURATION
TMPR3904AF BLOCK DIAGRAM
TX39 Processor Core I-Cache TX39 D-Cache
SYSCLK A[31:24]/P A[23:1] [3:0]* D[31:0] BSTART LAST* ACK* BUSERR* RESET* HAVEIT*/PIO1[2] NMI* HALF* [3:0]* BOOT16 TEST* ENDIAN CLKEN PLLOFF* PIO0[7:0]
Debug[7:0]
DMAC0(2ch.)
DMAC1(2ch.)
[1:0] DACK[1:0] DONE* [3:2]/P DACK[3:2]/PIO1[5:4] RAS1,0[3:0]* CAS[3:0]* OE1*,OE0* CE1,0[1:0]* SWE1*,SWE0* INT[7:0] XOUT SIN0 SOUT0 CTS0* RTS0* SCLK SIN1 SOUT1 CTS1* RTS1*
EBIF
DRAMC
ROMC
Bridge
SIO0
TMR0
TIMOUT1 TIMIN1 TIMOUT2 TIMIN2
TMR1 TMR2
SIO1
EJC-TMPR3904AF-3 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
PINS
ASSIGNMENT Signal LAST* R/W* BE[3]* BE[2]* BE[1]* BE[0]* RAS0[0]* RAS0[1]* RAS0[2]* RAS0[3]* RAS1[0]* RAS1[1]* RAS1[2]* RAS1[3]* CAS[0]* CAS[1]* CAS[2]* CAS[3]* TOUT[0] TOUT[1] Signal TOUT[2] TOUT[3] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] Signal A[19] A[20] A[21] A[22] A[23] A[24] A[25] A[26] A[27] A[28] A[29] A[30] A[31] CE0[0]* CE0[1]* CE1[0]* CE1[1]* OE1* OE0* SWE0* SWE1*
TSTO1
Signal TSTO2 BOOT16 HALF* ENDIAN BUSGNT* BUSREL* DACK[0] DACK[1] DACK[2] DACK[3] DONE* DREQ[0] DREQ[1] DREQ[2] DREQ[3] HAVEIT* BUSREQ* SCS[3]* SCS[2]* SCS[1]* SCS[0]* PIO0[0] PIO0[1] PIO0[2]
EJC-TMPR3904AF-4 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
Signal PIO0[3] PIO0[4] PIO0[5] PIO0[6] PIO0[7] TIMOUT2 TIMOUT1 TIMIN2 TIMIN1 SCLK SIN1 SIN0 CTS1* CTS0* SOUT1 SOUT0 RTS1* RTS0* D[31] D[30] D[29]
Signal D[28] D[27] D[26] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11]
Signal D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] NMI* INT[0] INT[1] INT[2] INT[3] INT[4] INT[5] INT[6]
Signal INT[7] PCST[2] PCST[1] PCST[0] DCLK SDAO DBGE* SDI* DRESET* TEST* RESET* ACK* BUSERR* BSTART* SYSCLK PLLOFF* CLKEN VDDP VSSP XOUT
Active-low signal
EJC-TMPR3904AF-5 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
FUNCTIONS tolerant Name input Function System Interface SYSCLK System Clock Outputs clock with frequency either equal half that TX39 Processor Core. Address bus. output when TX3904A A[31:1] master, input otherwise. (PIO2[7:0]) A[31:24] shared with PIO2. BE[3:0]* Byte Enable Indicates valid data positions data D[31:0]. output when TX3904A master, input otherwise. BE[3]* D[31:24] BE[2]* D[23:16] BE[1]* D[15:8] BE[0]* D[7:0] D[31:0] Data bus. D[15:0] used 16-bit mode. SCS[3:0]* System Chip Select Asserts when accessing address range that internal register. R/W* Read/Write Indicates operation being executed either read write. output when TX3904A master, input otherwise. High: Read Low: Write BSTART* Start Asserts during first clock period operation. output when TX3904A master, input otherwise. LAST* Last Indicates that last operation. output when TX3904A master, input otherwise. ACK* Acknowledge Slave devices inform master that operation finished. input when TX3904A master, output otherwise.
tolerant input Available, Available
EJC-TMPR3904AF-6 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
tolerant input BUSERR* Name
Function Error Informs errors. input when TX3904A master, output otherwise. Reset Initializes TX3904A setting this signal SYSCLK more.
RESET*
Clock
Crystal Input Connect crystal oscillator. XOUT Crystal Output Connect crystal oscillator. PLLOFF* signal halt oscillation TX3904A built-in clock generator. CLKEN Clock Enable signal enable TX3904A internal clock. External Master Interface Request BUSREQ* Changes when external master requests ownership TX39 Processor Core. (PIO1[1]) that shared with PIO1. BUSGNT* Grant Asserted when TX39 Processor Core informs that releasing ownership response BUSREQ*. (PIO1[0]) that shared with PIO1. HAVEIT* Have Indicates TX3904A that external master ownership. (PIO1[2]) that shared with PIO1. BUSREL* Release Asserted when TX39 processor core requests external master release ownership. (PIO1[3]) that shared with PIO1. Interrupt Signals NMI* Maskable Interrupt Non-maskable interrupt input.
tolerant input Available, Available
EJC-TMPR3904AF-7 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
Name INT[7:0]
tolerant input
Function Interrupt Request External interrupt request signals. active level level sensed/edge triggered designated chip configuration register. Address Strobe signals DRAM. Column Address Strobe signals DRAM. Write Enable Write enable signal DRAM. Output Enable Output enable signals ROM. Chip Enable Chip select signals ROM. SRAM Write Enable Write enable signals SRAM Flash ROM. Request external device requests transfer. DREQ[3:2] shared with PIO1. Acknowledge Acknowledge signals transfer request through DREQ. DACK[3:2] shared with PIO1. Done Input: input terminate data transfer. Output: Notification that transfer ended. This signal asserted during SYSCLK period when transfer ends.
Memory Interface RAS0[3:0]* RAS1[3:0]* CAS[3:0]*
OE0* OE1* CE0[1:0]* CE1[1:0]* SWE0* SWE1* Interface DREQ[3:0]
(PIO1[7:6]) DACK[3:0]
(PIO1[5:4]) DONE*
tolerant input Available, Available
EJC-TMPR3904AF-8 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
tolerant input Timer/Counter TIMOUT2 TIMOUT1 TIMIN2 TIMIN1 Serial Port SIN1 SIN0 SOUT1 SOUT0 CTS1* CTS0* RTS1* RTS0* SCLK Name Port PIO0[7:0]
Function
Timer Output Output signals timer. Timer Input External signals timer count. Serial Input Data input signals serial I/O. Serial Output Data output signals serial I/O. Clear Send Control signals serial I/O. Request Send Control signals serial I/O. Serial Clock Input Clock input serial I/O. Port0 signal Port0. Input/Output each bit. Debug signal external real time debug system. DBGE*, SDI*, DRESET* pulled internally.
Debug Interface PCST[2:0] DCLK SDAO DBGE* SDI* DRESET* Others BOOT16
Boot 16-bit Sets memory width channel-0 controller. either high according width boot ROM. High: bits Low: bits
tolerant input Available, Available
EJC-TMPR3904AF-9 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
Name HALF*
ENDIAN
TEST* TOUT[3:0], TSTO1, TSTO2
tolerant Function input Half Speed Mode Designates half speed mode. low, TX3904A becomes half speed mode that frequency operation becomes half operation frequency TX39 Processor Core. either high low. Sets Endian immediately after reset. either high low. High: Endian Low: Little Endian Test signal tests. high. Test output signal tests. Leave open.
tolerant input Available, Available
EJC-TMPR3904AF-10 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXMUM RATINGS Parameter Supply voltage Input voltage XIN, PLLOFF*, CLKEN, DBGE*, SDI*, DRESET*, TEST*, RESET*, BOOT16, HALF*, ENDIAN, TIMIN Other inputs Storage temperature Maximum power dissipation Symbol VIN1 Rating -0.3 -0.3 0.3V Unit
VIN2 TSTG
-0.3 5.3V
Note: Using specifications higher than maximum ratings cause permanent damage device. normal operation, under recommended operating conditions. Exceeding recommended operating conditions affect reliability device.
RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage Operating temperature Symbol Condition Min. Max. Unit
EJC-TMPR3904AF-11 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
CHARACTERISTICS Parameter Low-level input voltage Symbol
70°C, 3.3V 0.3V, Condition Min. Max. Unit
VIL1 VIL2 except High-level input VIH1 voltage VIH2 except Low-level output IOL1 0.4V current IOL2 0.4V 16.0 IOL3 0.4V High-level output IOH1 2.4V -4.0 current IOH2 2.4V -8.0 IOH3 2.4V -16.0 Input leakage current IIH1 IIH2 (7),(8) IIL1 (6),(8) IIL2 -320 Operating current 3.6V, 66MHz PCST[2:0], DCLK, SDAO, SYSCLK, SCS[3:0]*, SOUT0, SOUT1, CTS0*, CTS1*, BE[3:0]*, BSTART*, BUSERR*, ACK*, LAST*, R/W*, BUSGNT*, BUSREL*, BUSREQ*, HAVEIT*, DREQ[3:2], DACK[3:2], PIO0[7:0], DONE*, RTS0*, RTS1*, TIMOUT1, TIMOUT2, RAS0[3:0]*, RAS1[3:0]*, CAS[3:0]*, OE0*, OE1*, CE0[1:0]*, CE1[1:0]*, SWE0*, SWE1* D[31:0], A[31:1], Input pins except below DBGE*, SDI*, DRESET*, TEST*
EJC-TMPR3904AF-12 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
CRYSTAL OSCILLATOR CHARACTERISTICS 5.4.1 Crystal Oscillator Conditions
TMPR3904AF TMPR3904F
XOUT ROUT
X'tal
COUT
Parameter Crystal Oscillator frequency Output register External condenser Clock generator Rising time Falling time
Symbol ROUT CIN,COUT
Recommended value 4.125 8.25 5(1) 5(1)
Unit
reference. clock generator manufacture.
5.4.2 Electrical Specifications Parameter Oscillation start time Symbol tSTA
70°C, 3.3V 0.3V, Condition f=4.1258.25MHz MIN. TYP. MAX. Unit
500µs 10ms
EJC-TMPR3904AF-13 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
CHARACTERISTICS Symbol tsys SYSCLK Signal
70°C, 3.3V 0.3V, 50pF) Description Full speed mode Half speed mode High Level Level High Level (Half speed mode) Level (Half speed mode) Delay Delay (High Low) Delay (Low High) Setup Hold Setup Hold Delay Setup Hold Delay Delay Setup Hold Delay Active Hi-Z Hi-Z active Setup (Full speed mode) Hold (Full speed mode) Setup Min. Max. Unit
SYSCLK SYSCLK SYSCLK SYSCLK A[31:1] BE[3:0]*, R/W*, BSTART*, LAST* BE[3:0], R/W*, BSTART*, LAST* D[31:0] D[31:0] ACK*, BUSERR* ACK*, BUSERR* D[31:0] BUSREQ* BUSREQ* BUSGNT* ACK* HAVEIT* HAVEIT* BUSREL* A[31:1], BE[3:0], R/W*, BSTART*, LAST* A[31:1], BE[3:0], R/W*, BSTART*, LAST* A[31:1], BE[3:0], R/W*, BSTART*, LAST* A[31:1], BE[3:0], R/W*, BSTART*, LAST* RESET*, INT[7:0]*, NMI*
EJC-TMPR3904AF-14 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
70°C, 3.3V 0.3V, 50pF) Symbol Signal RESET*, INT[7:0]*,NMI* RESET* CLKEN SYSCLK PLLOFF* RAS1[3:0]*, RAS0[3:0]* CAS[3:0]* CE1[3:0]*, CE0[3:0]* OE1*, OE0* SWE1*, SWE0* DREQ[3:0] DREQ[3:0] DACK[3:0] TIMIN1, TIMIN2 TIMOUT1,TIMOUT2 SCLK PIO0[7:0] PIO0[7:0] PIO0[7:0] SCS[3:0]* A[13:1] A[13:1] BSTART* Description Min. Max. tsys/2 -t49 Unit tsys tsys tsys
Hold Reset time stabilization time upon reset 500(2) Delay Delay Delay
Delay Setup Hold Delay External timer clock Timer output External baud rate clock Delay Setup Hold Delay address output delay Column address output delay width driven external master(1) SYSCLK-BSTART* SYSCLK-BSTART* delay (Half speed mode) A[31:1], BE[3:0], R/W*, Hold (Half speed mode) BSTART*, LAST* GCLK-SYSCLK GCLK-SYSCLK delay (Half speed mode)
Both this specification setup/hold time must satisfied same time when external master drives BSTART*. This specification does include oscillation start time (tSTA). Note: Load capacitance(CL) A[31:1], D[31:0] 100pF.
EJC-TMPR3904AF-15 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
5.5.1 Definition characteristics
tsys 2.0V 0.8V 2.0V 0.8V
SYSCLK
Output
SYSCLK 2.2V 0.8V 2.2V 0.8V
Input
Output delay Output (active Hi-Z) Output (Hi-Z active) Input setup Input hold
EJC-TMPR3904AF-16 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
5.5.2 Timing diagram
SYSCLK A[31:1] BE[3:0]* BSTART* LAST*
R/W* SCS[3:0]* ACK* D[31:0]
Read operation
Note: SCS[3:0]* asserted only when master accessed area.
EJC-TMPR3904AF-17 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK A[31:1] BE[3:0]* BSTART* LAST* R/W* SCS[3:0]* ACK* D[31:0]
Write operation
Note: SCS[3:0]* asserted only when master accessed area.
EJC-TMPR3904AF-18 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK A[31:1] BE3:0]* BSTART LAST* RASnm* CASn* COLUMN
D[31:0]
Read operation from DRAM
EJC-TMPR3904AF-19 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK A[31:1] BE3:0]* BSTART LAST* RASnm* CASn* D[31:0] COLUMN
Write operation DRAM
EJC-TMPR3904AF-20 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK A[31:1] BE[3:0]* BSTART LAST* CEnm* OEn*
SWE* D[31:0]
Read operation from ROM/FLASH/SRAM
EJC-TMPR3904AF-21 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK A[31:1] BE[3:0]* BSTART LAST* CEnm*
OEn* SWE* D[31:0]
Write operation FLASH/SRAM
EJC-TMPR3904AF-22 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK BUSREQ* BUSGNT* HAVEIT* A[31:1] BE[3:0]* BSTART* LAST* R/W* Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z
TX3904A cycle
External master cycle
Note period from asserting BUSREQ* replying BUSGNT* varies status TX3904A. Note When external master uses on-chip DRAMC ROMC, external master must stop driving A[31:1] BE[3:0]* rising BSTART*.
Release ownership External master cycle (Full speed mode)
EJC-TMPR3904AF-23 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK BUSREQ BUSGNT* HAVEIT* Hi-Z A[31:1] BE[3:0]* Hi-Z
Hi-Z BSTART* Hi-Z LAST* Hi-Z R/W*
External master cycle
TX3904A cycle
Regaining ownership
EJC-TMPR3904AF-24 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK tsys GCLK (Int. clock)
GCLKH (Int. clock) BSTART* A[31:1] Hi-Z BE[3:0]* Hi-Z Hi-Z Hi-Z
LAST*
R/W*
Note When external master uses on-chip DRAMC ROMC, external master must stop driving A[31:1] BE[3:0]* rising BSTART*.
External master cycle (Half speed mode
EJC-TMPR3904AF-25 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK tsys GCLK (Int. clock)
GCLKH (Int. clock) BSTART* A[31:1] Hi-Z Hi-Z
BE[3:0]* Hi-Z Hi-Z
LAST*
R/W*
Note When external master uses on-chip DRAMC ROMC, external master must stop driving A[31:1] BE[3:0]* falling BSTART*.
External master cycle (Half speed mode
EJC-TMPR3904AF-26 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
SYSCLK RESET*
Reset
SYSCLK CLKEN RESET*
include X'tal oscilation start time (tsta)
Power-on Reset
EJC-TMPR3904AF-27 14-Dec-1998 TOSHIBA CORPORATION
INTEGRATED CIRCUIT
TOSIBA RISC PROCESSOR
TMPR3904AF
PACKAGE DIMENSION
QFP208-P-2828 Unit:
EJC-TMPR3904AF-28E 27-Mar-1998 TOSHIBA CORPORATION

TMPR3904AF System RISC) GENERAL DESCRIPTION TMPR3904AF

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