FEATURES MX10F202FC (80C51 with memory LCD) 80C51 core 3.3V volta

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FEATURES MX10F202FC (80C51 with memory LCD) 80C51 core 3.3V volta

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MX10F202FC
FEATURES MX10F202FC (80C51 with memory LCD)
80C51 core 3.3V voltage range 16MHz clock frequency bytes memory code memory bytes internal data power consumption digits driver/controller Four general purpose ports standard 16-bit Timers On-chip Watch Timer channel outputs UART interrupt sources PQFP package Single clock dual clock compatibility
Features list
80C51 core 3.3V operation voltage range 16MHz clock frequency bytes memory code memory More than times program/erase cycles More than years data retention bytes internal data operation current Power saving modes User friendly power control active mode current Idle mode Sleep mode Power down mode, wake external interrupts RESET driver/controller Max. 16-digits display duty 1:1(static), 1:2, selectable multiplexing rate backplane driver, segment driver directly drive capability with display memory VLCD control driving voltage, (VLCD-VSS) general purpose ports Provide software capability standard 16-bit Timers (Timer 0,1) On-chip Watch Timer (WDT) channel outputs UART interrupt sources interrupt vectors external sources internal sources(Timer0,Timer1,watch Timer UART) PQFP package Single clock dual clock single clock mode 2~16MHz system clock CPU,Timer0/1,WDT,UART dual clock mode 2~16MHz system clock CPU,Timer0/1,WDT,UART; while 32.768KHz sub-system clock watch timer. system clock either crystal activated EMC(Electro-Magnetic Compatibility) improved
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MX10F202FC
PINNING
XTAL3 XTAL4 P15/PWM1 P14/PWM0
MX10F202FC
P37/INT3 P36/INT2 P35/T1 P34/T0 P33/INT1 P32/INT0 P31/TxD P30/RxD
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VLCD RESET XTAL1 XTAL2
Fig.1 Pinning
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MX10F202FC
Table. Description SYMBOL BP0-BP3 S00-S31 P00-P07 P20-P27 P10-P17 P30-P37 P32-P33, P36-P37 RESET XTAL1 XTAL2 XTAL3 XTAL4 TEST/VPP \QFP 71~74 75-79,83-100, 2-10 22-29 42-48,51 56-63 DESCRIPTION Backplane drive output line Segment drive output line Port:8-bit open drain bidirectional Port Port: 8-bit quasi-bidirectional Port with internal pull-up Quasi-bidirectional lines also channel also channel Quasi-bidirectional lines also UART Receive also UART Transmit also external interrupt also Timer0 external input also Timer1 external input 18,69 13,20,67 reset input Positive power supply Ground XTAL connection input XTAL connection output 32.768KHz, XTAL input 32.768KHz, XTAL output oscillator resistor connection input Supply power programming erasing
31-38
VLCD driver power supply Note: avoid 'Latch-up' effect power-on voltage time )must higher than +0.5 lower Vss-0.5V respectively generation Port alternative function carried automatically associated Special Function Register (SFR) properly written
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MX10F202FC
INT0/1/2/3
VLCD
PWM0 PWM1
XTAL1 XTAL2 RESET
T0/T1 16-bit Counter
Program Memory 16KB
Data Memory 512x8
Watch Timer
Serial Port
8-bit internal
Parallel Ports
Unit
S00-S31
Alternative Function Port3
Fig.2 Block Diagram
Internal
LCON
Freq Duty
BIAS
ENLCD
Segment Display Register
Ext.CLK ider
LCD_CL
BP0_SEG[31:0]
BP3_SEG[31:0]
Timing/Duty Control, Voltage Selector
Backplane Gen.
Segment Gen.
BP_Output [1:0]
Seg_Output [1:0]
VLCD
BIAS Gen.
Driver
Seg. Driver
SEG31 SEG30.SEG0
Panel
Fig.3 Driver Block Diagram
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MX10F202FC
FUNCTIONAL DESCTIPTION
General MX10F202FC stand-alone high-performance power microcontroller designed many applications which need code programmability. Flash EPROM offers customers program device themselves. This feature increases flexibility many applications, only development stage, also mass production stage. addition 80C51 standard functions, MX10F202FC provides number dedicated hardware functions. MX10F202FC control-oriented with on-chip program data memory. execute program with internal memory bytes. MX10F202FC four software selectable modes reduced activity power reduction active power control, idle, sleep, Power-down. idle mode freezes while allowing RAM, Timers, serial ports, interrupt system other peripherals continue functioning. Power-down mode saves contents freezes oscillator causing other chip functions inoperative. Power-down mode terminated external reset ,and addition either four external interrupts. sleep mode behaves like power down mode, with oscillator still turning sleep mode terminated power down mode does. Instruction Execution MX10F202FC uses powerful instruction 80C51. Additional SFRs incorporated control on-chip peripherals. instruction consists single-byte, two-bytes, three-bytes instructions. When using 16MHz oscillator, instructions execute instructions execute Multiply divide instructions execute
MEMORY ORGANIZATION
Central Processing Unit (CPU) manipulates operands three memory spaces; these bytes internal data memory (RAM), byte auxiliary data memory (AUX-RAM) byte internal program memory (EEPROM). Program Memory program memory address space MX10F202FC comprises internal external memory space. MX10F202FC byte program memory on-chip. Program Protection user choose security lock memory, program content protected from reading chip. Internal Data Memory internal data memory divided into three physically separated parts: byte RAM, bytes AUXRAM, bytes special function register area (SFR). These parts addressed follows (see Fig.4 Table. addressed directly indirectly 80C51. Address pointers selected register bank. only addressed indirectly Address pointers selected register bank. AUX-RAM indirectly addressable external data memory locations with MOVX instructions. Address pointers selected register bank DPTR. When executing from internal program memory, access AUX_RAM will affect ports P0,P2,P3.6 P3.7. SFRs only addressed directly address range from 255.
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Table. Internal data memory access LOCATION AUX-RAM Special Function Register (SFR) ADDRESSED DIRECT INDIRECT INDIRECT only INDIRECT only with MOVX DIRECT only
Fig. shows internal memory address space. Table shows Special Function Register (SFR) memory map. Location lower area devided into four 8-bit register banks. Only these banks enabled time. next bytes, locations through contain directly addressable locations. stack located anywhere internal byte RAM. stack depth only limited available internal space bytes. registers except Program Counter four 8-byte register banks reside address space. Register Direct Register-Indirect Immediate Base-Register plus Index-Register-Indirect. first three methods used addressing destination operands. Most instructions have 'destination source' field that specifies data type, addressing methods operands involved. operations other than MOVs, destination operand also source operand. Access memory addresses follows: Register four 8-byte register banks through Direct Register-Indirect addressing. bytes internal through Direct Register-Indirect addressing. Bytes 0-127 internal only addressed indirectly data RAM. through direct addressing address location 128-255.
OVERLAPPED SPACE with different access schemes
INTERNAL DATA MEMORY
internal program memory
INDIRECT ONLY -DIRECT INDIRECT MAIN SFRs AUX-RAM SFRs Direct only AUXILIARY through MOVX access
PROGRAM MEMORY
Fig. Internal program data memory address space
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MX10F202FC
Table. Registers Symbol PCON TCON TMOD SCON SBUF LCON LCD0 LCD1 LCD2 LCD3 LCD4 INTCON LCD5 LCD6 LCD7 LCD8 LCD9 LCDA LCDB LCDC LCDD LCDE LCDF IEN1 EBTCON PCON1 PWM0 PWM1 PWMP (WDT)
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Direct Address(ex)
Reset Value 1111,1111 0000,0111 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 1111,1111 0000,0000 xxxx,xxxx 1111,1111 0000,0000 1111,1111 x000,0000 x001,1100 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 0000,0000 xx00,0000 xxxx,xx00 xxxx,001x 0000,0000 x000,0100 xxxx,xx00 0000,0000 0000,0000 0000,0000 1111,1111
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facilities
MX10F202FC bits port, port which open drain, three bits ports, port 1/2/3, which quasi bidirectional ports. These four ports fully compatible standard 80C51's port 0/1/2/3. Port1: pins configured individually provide outputs. Port3: pins configured individually provide: external interrupt inputs (external interrupt 0/1/2/3); external inputs Timer/ counter Timer /counter1, UART receive transmit. Port pins which used alternate functions used normal bidirectional pins. generation Port Port alternate function carried automatically writing associated with proper value.
oscillator penods strong pull-up
PORT 1,2,3
from port latch
input data read port INPUT BUFFER
Fig. buffers MX10F202FC (Ports 1,2,3)
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Timer/Counter
MX10F202FC's Timer/Counter fully compatible standard 80C51's. MX10F202FC's contains 16-bit Timer/counters, Timer Timer Timer Timer programmed carry following functions: measure time intervals pulse durations count events generate interrupt requests. Timer Timer Timers each have control TMOD that selects Timer counter function corresponding Timer. Timer function, register incremented every machine cycle. Thus, think counting machine cycles. Since machine cycle consists oscillator periods, count rate 1/12 oscillator frequency. counter function, register incremented response HIGH-to-LOW transition corresponding samples, when transition shows HIGH cycle next cycle, counter incremented. Thus, takes machine cycles oscillator periods) recognize HIGH-to-LOW transition. There restrictions duty cycle external input signal, ensure that given level sampled least once before changes, should held least full machine cycle. Timer Timer programmed independently operate four modes (refer table Mode 8-bit Timer/counter with devided-by-32 prescaler Mode 16-bit Timer/counter Mode 8-bit Timer/counter with automatic reload Mode Timer :one 8-bit Timer/counter 8-bits Timer. Timer :stopped. When Timer Mode Timer programmed operate Modes cannot interrupt request flag generate interrupt. However, overflow from Timer used pulse Serial Port transmission-rgate generator. With crystal, counting frequency these Timer/counters follows: Timer function, Timer incremented frequency 1.33 (oscillator frequency divided 12). counter function, frequency handling range external inputs 0.66 (oscillator frequency divided 24). Both internal external inputs gated Timer second external source directly measuring pulse duration. Timers started stopped under software control. Each sets interrupt request flag when overflows from logic logic (respectively, automatic reload value), with exception Mode previously described. TMOD TIMER/COUNTER MODE CONTROL REGISTER This register located address 89H. Table. TMOD (89H) GATE (MSB) TIMER
GATE TIMER
(LSB)
keep above table with following table
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Table. Description TMOD bits MNEMONIC TIMER GATE POSITION TMOD.7 FUNCTION Timer gating control when set, Timer/counter enabled only while 'Int1' high 'tr1' control set. when cleared, Timer/counter enabled whenever 'tr1' control set. Timer counter selector: cleared Timer operation (input from internal system clock). counter operation (input from 'T1' input pin). Operation mode: table Operation mode: table Timer gating control: when set, Timer/Counter enabled only while 'Int0' high 'tr0' control set. when cleared, Timer/counter enabled whenever 'tr0' control set. Timer counter selector: cleared Timer operation (input from internal system clock). counter operation (input from 'T0' input pin). Operation mode: table Operation mode: table
TIMER GATE
TMOD.6 TMOD.5 TMOD.4 TMOD.3
TMOD.2 TMOD.1 TMOD.0
Table. TMOD operating modes FUNCTION 8-bit Timer/counter 'THx' with 5-bit prescaler. 16-bit Timer/counter 'THx' 'TLx' cascaded, there prescaler. 8-bit autoload Timer/counter 'THx' holds value which reloaded into 'TLx' each time overflows. Timer 8-bit Timer/counter controlled standard Timer control bits. 8bit Timer controlled Timer control bits. Timer Timer/counter stopped.
TCON TIMER/COUNTER CONTROL REGISTER This register located address 88H. Table. TCON (88H) (MSB)
(LSB)
keep above table with following table
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Table. Description TCON bits MNEMONIC POSITION FUNCTION TCON.7 Timer overflow flag hardware Timer/Counter overflow. Cleared when interrupt processed. TCON.6 Timer overflow flag hardware Timer/Counter overflow. Cleared when interrupt processed. TCON.5 Timer overflow flag: hardware Timer/Counter overflow. Cleared when interrupt processed. TCON.4 Timer control set/cleared software turn Timer/counter ON/OFF. TCON.3 Interrupt edge flag: hardware when external interrupt detected. Cleared when interrupt processed. TCON.2 Interrupt type control set/cleared software specify falling edge/LOW level triggered external interrupt. TOCN.1 Interrupt edge flag: hardware when external interrupt detected. Cleared when interrupt processed. TOCN.0 Interrupt type control bit: set/cleared software tospecify falling edge/LOW level triggered external interrupt.
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Interrupt system
MX10F202FC contains 8-source external interrupts, Timer Timer1, watch timer UART structures with priority levels. Each External interrupts INT0, INT1, INT2, INT3 either level-activated transition-activated depending bits TCON IT2, INTCON SFR. flags that actually generate these interrupts bits IE0, TCON IE2,IE3 INTCON. When external interrupt generated, corresponding request flag cleared hardware when service routine vectored interrupt transitionactivated. interrupt level-activated external source hold request active until requested interrupt actually generated. Then deactive request before interrupt service routine completed, otherwise another interrupt will generated. Timer Timer Interrupts generated TF1, which rollover their respective Timer/counter register (except Timer Mode serial interface). When Timer interrupt generated, flag that generated cleared on-chip hardware when service routine vectored INTERRUPT ENABLE REGISTER This register located address A8H. Table. (A8H) (MSB) keep above table with following table
(LSB)
Table. Description bits MNEMONIC POSITION FUNCTION IE.7 Disable interrupt Low, disabled. High, each interrupt source individually enabled disabled setting clearing enable bit. IE.6 Enable Disable External interrupt Low, disabled High, enabled IE.5 Enable Disable External Interrupt Low, disabled High, enabled IE.4 Enable Disable UART interrupt. Low, disabled High, enabled IE.3 Enable Disable Timer1 overflow interrupt. IE.2 Enable Disable External interrupt Low, disabled High, enabled IE.1 Enable disable Timer0 overflow interrupt. IE.0 Enable Disable External interrupt Low, disabled High, enabled
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IEN1 INTERRUPT ENABLE REGISTER Table. IEN1 (E8H) Enable Disable Watch Timer interrupt.
INTERRUPT PRIORITY REGISTER This register located address B8H. Table. (B8H)
(LSB)
keep above table with following table Table. Description bits MNEMONIC POSITION FUNCTION IP.7 RESERVED IP.6 Define External interrupt interrupt priority level. High, assign high priority level. IP.5 Define External interrupt interrupt priority level. High, assign high priority level. IP.4 Define interrupt priority level UART. IP.3 Define Timer1 overflow interrupt priority level. IP.2 Define External interrupt interrupt priority level. High, assign high priority level. IP.1 Define Timer0 overflow interrupt priority level. IP.0 Define External interrupt interrupt priority level. High, assign high priority level.
INTERRUPT PRIORITY REGISTER Table. (F8H) Define Watch Timer interrupt priority level.
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Table. INTCON (C0H)
Table. Description INTCON bits IE3/2 External interrupt edge flag. when exteranl interrupt detected, cleared when interrupt processed. IT3/2 External interrupt type control bit. Set/cleared specify falling edge/low level triggered external interrupt. Watch timer overflow interrupt flog. when watch timer overflow occurred, cleared warm/cold reset. Watch timer enable bit. Set/ cleared Table. INTERRUPT VECTORS PRIORITY WITHIN LEVELS source name Priority Within Level Ext. interrupt0 1(Highest) Timer0 overflow Ext. interrupt1 Timer1 overflow UART interrupt Ext. interrupt2 Ext. interrupt3 Watch timer overflow
Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH
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Watch Timer
watch timer module (see Fig. clocked 32.768KHz external crystal, generates interrupt request every second. This value derived from ftimer fosc (256x64). watch timer consists 8-bit timer register 6-bit timer registers WTH. register triggered 32.768KHz external crystal, register increases value while overflow occurs. When overflow occurs, INTCON High automatically interrupt request sent microcontroller. Both timer registers loaded values software. Therefore time interval watch timer interrupt request adjusted. This allows watch timer send interrupt request more frequently some special application. both hardware software, only cleared software. 32.768KHz external oscillator gated INTCON. cleared, watch timer registers will hold their values. idle sleep states watch timer remains active, wakes microcontroller while watch timer overflow (i.e. HIGH) occurs. Since this module clocked 32.768KHz external crystal, this module disabled consumes power there such crystal connected chip.
Internal
32.768K
(8-bit) Load
(6-bit) Load
(1-bit) Load
Interrupt Request
Write WTF, WTL,
Fig. Watch Timer
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drivers
module includes pixel memory drive directly backplanes segments outputs. Thus, common digit-typed LCD, MX10F202FC have maximum digits display. Control Register (LCON) Since MX10F202FC several possible clocking alternatives 16MHz system clock with possible second 32.768KHz sub-system clock, programmers need this register proper frame scan rate. Table. LCON (BAH) LCDF2 LCDF1 LCDF0
Bias
ENLCD
LCDF2,LCDF1,LCDF0: Selection frame scan frequency Table. Frame scan freq (Hz) Fclk (ext. clk) 16Mhz 12Mhz 8Mhz 4Mhz 2Mhz 1Mhz :0.5Mhz 32Khz Divider Select Fclk/2^18 Fclk/(2^16*3) Fclk/2^17 Fclk/2^16 Fclk/2^15 Fclk/2^14 Fclk/2^13 Fclk/2^9 Duty Duty Duty Static
Note Dual clock mode writing "111". MD1,MD0: Mode bits, determine multiplex rate. Table. static Backplanes (BP0) (BP0,1) (BP0,1,2) (BP0,1,2,3) Pixel Digits
Bias: voltage bias generator. High, bias 1/2(VLCD-VSS) Low, bias 1/3(VLCD-VSS)
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Table. Drive Mode static Bias static Voff(rms) 0.354 0.333 0.333 0.333 Von(rms) 0.791 0.745 0.638 0.577 Contrast infinity 2.236 2.236 1.915 1.732
ENLCD: Enable/Disable Low, segment backplanes drivers level. High, enable digits display possible.
segment display register contain on/off information segments Table. Register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LCD0 SEG1 SEG0 LCD1 SEG3 SEG2 LCD2 SEG5 SEG4 LCD3 SEG7 SEG6 LCD4 SEG9 SEG8 LCD5 SEG11 SEG10 LCD6 SEG13 SEG12 LCD7 SEG15 SEG14 LCD8 SEG17 SEG16 LCD9 SEG19 SEG18 LCDA SEG21 SEG20 LCDB SEG23 SEG22 LCDC SEG25 SEG24 LCDD SEG27 SEG26 LCDE SEG29 SEG28 LCDF SEG31 SEG30
Bit0
drive mode waveform used control voltage level backplane segment outputs Static drive mode multiplex drive mode with bias multiplex drive mode with bias multiplex drive mode with bias multiplex drive mode with bias
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SEG0 SEG5 SEG1 SEG6 SEG4 SEG2 SEG7 SEG3 COM0
ENLCD
VLCD
display data area address ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1
SEG0
VLCD
SEG4
VLCD
SEG7 (Note) don't care
VLCD
COM0
VLCD
COM0-SEG0 (Selected)
-VLCD
VLCD
COM0-SEG4 (Non-Selected)
-VLCD
Fig. Static Drive
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COM0 SEG3 SEG0
SEG2 SEG1 COM1
ENLCD
VLCD
display data area address **01 **01 **11 **10
SEG0
VLCD
SEG1
(Note) don't care SEG2
VLCD VLCD
SEG3
VLCD
COM0
VLCD
COM1
VLCD
COM0-SEG1 (Selected)
VLCD
COM0-SEG2 (Non-Selected)
Fig. Duty (1/2 Bias) Drive
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COM0 SEG3 SEG0
SEG2 SEG1 COM1
ENLCD
VLCD
SEG0
VLCD
SEG1
VLCD
SEG2 display data area address **01 **01 **11 **10 SEG3
VLCD
VLCD
COM0
VLCD
COM1
VLCD
COM0-SEG1 (Selected)
-(VLCD VSS) VLCD
COM0-SEG2 (Non-Selected)
-(VLCD VSS)
Fig. Duty (1/3 Bias) Drive
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SEG1 SEG2 SEG0 COM0
COM1 COM2
ENLCD
SEG0
VLCD VLCD
SEG1
VLCD
display data area address *111 *010 **** **01
SEG2
VLCD
COM0
VLCD
(Note) don't care COM1
VLCD
COM2
VLCD
COM0-SEG1 (Selected)
-VLCD VLCD
COM0-SEG2 (Non-Selected)
-VLCD
Fig. Duty (1/2 Bias) Drive
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SEG1 SEG2 SEG0 COM0
COM1 COM2
ENLCD
SEG0
VLCD
VLCD
display data area address *111 *010
SEG1
VLCD
SEG2 **** **01
VLCD
(Note) don't care COM0
VLCD
COM1
VLCD
COM2
VLCD
COM0-SEG1 (Selected)
-VLCD VLCD
COM0-SEG2 (Non-Selected)
-VLCD
Fig. Duty (1/3 Bias) Drive
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COM0 SEG1 COM1
COM2 SEG0 COM3
ENLCD
SEG0
VLCD
SEG1
VLCD
VLCD
COM0
VLCD
display data area address 10110101
COM1
VLCD
COM2
VLCD
COM3
COM0-SEG0 (Selected)
VLCD
-VLCD
VLCD
COM0-SEG1 (Non-Selected)
-VLCD
Duty (1/3 Bias) Drive
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MX10F202FC
Power saving modes active power control, idle, sleep power down modes
order enable lowest power consumption system application, MX10F202FC user friendly power control mechanism follows Active power control used turn un-used peripherals specific applications. instance, UART might used audio application, then programmer disable save power. Idle mode used turn 80C51 during certain conditions. Sleep mode used turn whole system except possibly watch Timer. Power down mode turn whole system. PCON Power Control Register (PCON) PCON (87H) SMOD SCEER
SMOD Doubl band rate UART. SLEEP Sleep mode bit. Setting activates sleep mode, could terminated terminate pull down mode. Watch load enable. This flag must prior loading cleaned when loaded. CF1/CF0 general-prepose flag bit. Power down bit. Setting activates power down mode. idle mode bit. Setting activates idle mode. Active power control mode PCON1 POWER CONTROL REGISTER Table. PCON1 (F1H) UARTD WDTD PWMD
LCDD
Table. Description PCON1 bits Timer0/1 Disable bit. Setting shut-down Timer0/1. UARTD: UART Disable bit. Setting shut-down UART. WDTD WatchDog Timer Disable bit. Setting shut-down WDT. PWMD Pulse Width Modulation Disable bit. Setting shut-down PWM. Watch Timer Disable bit, Setting shu-down must write LCDD Disable bit. Setting shut-down relative modules.
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oscillator function
MX10F202FC provides oscillator function application that does need very accurate system clock frequency save cost crystal oscillator. shown Fig. oscillator function system clock source, suggested 50K~200K connected between ground. XTAL1 connected ground internal clock system failed. When system clock source comes from crystal oscillator, suggested connect VDD. following table shows approximately relationship between oscillator clock frequency resistor value. Table. oscillator reference table Resistor Value ohm) oscillator clock frequency (MHz) 12~14 9~11 10~12 7.5~9 9~10 6.5~8 6~7.5 ~7.5 5.5~6.5 ~6.5 5.2~5.8 4.7~5.3
XTAL1
XTAL1
XTAL2 Resistor
XTAL2
Fig. System clock connection oscillator system clock source, crystal oscillator system clock source.
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Clock system
MX10F202FC possible clocking schemes with four combinations follows System clock External 16MHz crystal (XTAL1,XTAL2) oscillator with external resister (RCP) XTAC1 connected External 16MHz crystal (XTAL1,XTAL2) oscillator with external resister (RCP) XTAC1 connected Sub-system clock XTAL3 connected XTAL3 connected 32.768KHzcrystal (XTAL3,XTAL4) 32.768KHz crystal (XTAL3,XTAL4)
Single clock mode
Dual clock mode
interaction between power saving modes clock system listed follows Single clock System clock System clock System clock active except watch Timer Individual peripheral disabled corresponding active power control 80C51 stopped wake interrupt stopped except LCD, system oscillator. wake external interrupts, 1)All stopped wake external interrupts RESET Dual clock System clock System clock Sub-system clock active Individual peripheral disabled corresponding active power control 80C51 stopped wake interrupt stopped except watch Timer, LCD, sub-system oscillator. wake external interrupts,watch Timer RESET stopped wake external interrupts RESET
80C51 Timer0/1, WDT, UART Active mode Power control active mode Idle mode Sleep mode
Power down mode
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Watchdog Timer
Watchdog Timer (WDT) Fig.14 consists 11-bit prescaler 8-bit Timer formed Timer incremented every derived from system clock frequency following formula fTimer fclk (2048)). 8-bit Timer increments every 2048 cycles on-chip oscillator. When Timer overflow occurs, microcontroller reset. internal RESET signal inhibited when external kept into high impedance, matter XTAL-clock running not. prevent system reset Timer must reloaded time application software. processor suffers hardware software malfunction, software will fail reload Timer. This failure will result overflow thus prevent processor from running control. This time interval determined 8-bit reload value that written into register Watchdog time interval [T3] 2048 oscillator frequency watch-dog Timer only reloaded condition flag (SFR PCON been previously high software. moment counter loaded automatically cleared. idle state watchdog Timer reset circuitry remain active. watchdog Timer controlled watchdog enable signal (SFR EBTCON level enables watchdog Timer. HIGH level disable watchdog Timer.
Internal
fCLK/12
Prescaler (11-bit) Clear
Timer (8-bit) LOAD LOADEN
reset circuitry
Write
Clear PCON.
LOADEN PCON.
Internal
Fig. Watchdog Timer
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Pulse Width Modulated Outputs
MX10F202FC contains pulse width modulated output channels (see Figure. 15). These channels generate pulses programmable length interval. repetition frequency defined 8-bit prescaler PWMP, which supplies clock counter. prescaler counter common both channels. 8-bit counter counts modulo 255, i.e., from inclusive. value 8-bit counter compared contents registers: PWM0 PWM1. Provided contents either these registers greater than counter value, corresponding PWM0 PWM1 output LOW. contents these registers equal less than counter value, output will HIGH. pulse-width-ratio therefore defined contents registers PWM0 PWM1. pulse-width-ratio range programmed increments 1/255. Buffered outputs used drive motors. rotation speed motor would proportional contents PWMn. outputs also configured dual DAC. this application, outputs must integrated using conventional operational amplifier circuitry. resulting output voltages have accurate, external buffers with their analog supply should used buffer outputs before they integrated. repetition frequency fPWM, PWMn outputs give
fPWM
fOSC PWMP)
This gives repetition frequency range 123Hz 31.4KHz (fOSC 16MHz). fOSC 24MHz, frequency range 184Hz 47.1KHz. loading registers with either FFH, channels will output constant HIGH level, respectively. Since 8-bit counter counts modulo 255, never actually reach value registers when they loaded with FFH. When compare register (PWM0 PWM1) loaded with value, associated output updated immediately. does have wait until current counter period. Both PWMn output pins driven push-pull drivers. These pins used other purpose. function enabled setting EBTCON 2,3. After reset, EBTCON need P1.4 P1.5 output, otherwise P1.4& P1.5 general ports. Prescaler frequency control register PWMP Reset Value PWMP (FEH) PWMP.0-7 Prescaler dividsion factor PWMP
Reading PWMP gives current reload value. actual count prescaler cannot read. Reset Value
PWM0 (FCH) PWM1 (FDH)
PWM0/1.0-7} Low/high ratio PWMn
EBTCON (EBH)
(PWMn) PWMn)
PWM0E
PWM1E
PWM1E Selection P1.4 function either output port line, After reset PWM1E low, P1.4 normal port line. PWM0E Selection P1.5 function either output port line, After reset PWM0E low, P1.5 normal port line. After reset, set, disable.
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PWM0
8-BIT COMPARATOR tOSC
OUTPUT BUFFER
PWM0
Internal
PRESCALER PWMP
8-BIT COUNTER
8-BIT COMPARATOR
OUTPUT BUFFER
PWM1
PWM1
Fig. Functional Diagram Pulse Width Modulated Outputs
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MX10F202FC
UART
This module fully compatible standard 80C51's UART.
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MX10F202FC
Program Memory
Features kilobyte electrically erasable internal program momory. Programming erasing voltage Volt (re) programming mechanism EPROM like parallel programming protocol Parallel programming Byte programming typical) Chip erase less than second typical minimum erase/program cycles Advanced CMOS flash memory technology security protect internal code. General Description MX10F202FC's memory stores memory contents even after erase program cycles. cell designed optimize erase programming mechanisms. addition, combination advanced tunnel oxide processing internal electric fields erase programming operations produces reliable cycling. MX10F202FC uses Volt supply perform Program/Erase algorithms. PROGRAMMING PROGRAM VERIFY MX10F202FC byte programmable using 10us programming pulse requires separate program verify pulse read data check program not. typical programming time each bytes about 10ms room temperature.
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MX10F202FC
PROGRAMMING SPECIFICATION
Parallel Programming Mode parallel programming works EPROM-like programming protocol. MX10F202FC provides times cycles endurance. MX10F202FC needs 11.5~12.5 Volt supply perform Program/Erase operation. Specially note that LOCK used security protection. LOCK programmed, then PGMVFY, ERSVFY normal READ disabled from parallel programming mode. LOCK LOCK used this chip.
4.5/5.5V
0000 11.5V 12.5V PCEB POEB PWEB A[13:0] MS[3:0] RESET BP[3:0] P2[5:0] P1[7:0] P26, P37, P31, P0[7:0] Q[7:0] XTAL2 XTAL1
MX10F202FC
Table. Description NAME P25~P20, P17~P10 P07~ P26, P37, P31, SYMBOL PA13~PA8, PA7~PA0 Q[7:0] PCEB POEB PWEB MS[3:0] FUNCTION Address Input Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Program Supply Voltage Flash Mode Selection Power Supply Voltage (5V) Ground
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MX10F202FC
Table. parallel programming modes External Module Standby Normal Read Initialize Chip Erase Program Erase Verify Program Verify LOCK Erase Verify LOCK Verify LOCK Read Read DeviceID Note PVPP P2[5:0] P1[7:0] PCEB POEB PWEB PA[13:0] PA[13:0] P26, P37, P0[7:0] P31, MS[3:0] PUOUT[7:0] PDOUT[7:0] FF,00 0000 Data 1110 0001 0011 0100 0101 0110 1001 1011 1111 1111 FF,00 FF,00 FF,00 Data Data FF,00 LOCK[3:1] LOCK[3:1] P0[7:0] D[7:0] Lock[3:1]
0.5sec pulse 0.5sec pulse 10us pulses 10us pulse PA[13:0] PA[13:0] PA[13:0] PA[1:0] PA[1:0]=00 PA[1:0]=00 PA[1:0]=00 PA[1:0]=01
Lock[i]
MftID(C2H) DeviceID(0DH)
Program lock bits, program LOCK [1:0] Program lock bits, program LOCK [1:0] Program lock bits, program LOCK [1:0] Verify erased LOCK bits [1:0] Verify programmed LOCK bits [1:0] Read Manufacture Device [1:0] Manufacture (C2H) [1:0] Device (0DH)
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MX10F202FC
PROGRAM PROGRAM VERIFY FLOWCHART
START
First Address
VDD=
Program 10us pulse Program Verify Increment Address Last Address Fail Normal Read Pass Pass Device Fail x=x+1 X=20
Fail Device
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MX10F202FC
ERASE VERIFY FLOWCHART
START
VDD=
Program array zero 16KB) LOCK
Chip Erase (0.5s)
Erase Verify LOCK
Erase Verify Array (16KB) pass Pass Device
fail x=x+1
Fail Device
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
PROGRAM LOCK PROGRAM VERIFY LOCK FLOWCHART
START
LOCK Address [1:0]
VDD=
Program LOCK 10us pulse Program Verify LOCK Fail x=x+1
X=20
Pass Pass Device
Fail Device
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
Timing diagram Read signature Normal read operations
ADDRESS
MS[3:1]
tMSCE DATA Device
tMSCE
Min. Max. unit
tMSCE
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REV. 0.1, FEB. 2003
MX10F202FC
Timing Diagram Erase Erase Verify Array Operation
Min. Max. unit
tVPS
tCES
tMSCE
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
Timing Diagram Erase Erase Verify LOCK Operation
tVPS Min. Max. unit
tCES
tMSCE
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REV. 0.1, FEB. 2003
MX10F202FC
Timing Diagram Program Program Verify Operation
Min. Max. unit
tVPS
tCES
tMSCE
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
Timing Diagram Program LOCK Program Verify LOCK Operation
[1:0]
[1:0]
0110
1011
Min. Max. unit
tVPS
tCES
tMSCE
Note xxxx, LOCK [3], LOCK [2], LOCK [1],
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MX10F202FC
Limiting Value
SYMBOL VVPP IOL(max) Tstg Tamb PARAMETER Supply voltage Input voltage (all inputs) Voltage Maximum Storage temperature Operating ambient temperature(for devices) -0.5 UNIT
ELEECTRICAL CHARACTERISTICS
SYMBOL Supply PARAMETER Normal operation supply voltage Operation supply current CONDITIONS MIN. fOSC=16MHZ fOSC=12MHZ fOSC=4MHZ fOSC=16MHZ fOSC=12MHZ fOSC=4MHZ fOSC=16MHZ fOSC=12MHZ fOSC=4MHZ fOSC=16MHZ fOSC=12MHZ fOSC=4MHZ fOSC=16MHZ fOSC=12MHZ fOSC=4MHZ VDD=2.7V 3.3V VDD=3V 0.7VDD TYP. MAX. UNIT
Supply current idle mode
ISLP
Supply current single sleep mode
IDSLP
Supply current dual sleep mode
Supply current power-down mode
Inputs RINP VIH1
Input resistance RESET Input leakage current; RESET Input high voltage XTAL1, XTAL3, RESET PORTS P0~P3 Input voltage Input high voltage, except XTAL1, XTAL3, Logical input current Logical transition current
kohm VDD+0.5
VIN=0.4V, VDD=3V VIN=1.2V
-0.5 0.2VDD +0.9
0.2VDD-0.1 VDD+0.5 -300
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MX10F202FC
Outputs P0~P3 SYMBOL PARAMETER CONDITIONS Output voltage VDD=2.7V, IOL=1mA Output high voltage VDD=2.7V, IOH=- level output sink current VO<0.4V, VDD=3V High level pull-up output source current Strong pull-up VO=VDD-0.4V, VDD=3V Weak pull-up VO=VDD-0.4V, VDD=3V capacitance (except
MIN.
TYP.
MAX.
VDD-0.7
UNIT
DRIVER CHARACTERISTICS
SYMBOL Supply VLCD PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
operation supply voltage voltage component; backplane segment drivers driver outputs Output impedance BP0~BP3 Output impedance S0~S31 fLCD scan frequency
Ratio: 1:1, 1:2, Ratio:
kohm kohm
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MX10F202FC
OSCILLATOR CHARACTERISTICS 100kohm 40kohm
9.36 9.19 6.48 6.15 15.98 14.81 14.29 10.95 10.12 8.99
Fosc
100Kohm 40Kohm
CHARACTERISTICS
SYMBOL PARAMETER System (CPU) clock Oscillator frequency 32.768KHz Oscillator fxtal 32.768KHz Oscillator frequency CONDITIONS MIN. 32.768 TYP. MAX. UNIT
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MX10F202FC
PACKAGE INFORMATION
100-PIN PQFP
ITEM
MILLIMETERS 24.80 20.00 14.00 18.80 12.35 [REF] [REF] [REF] [Typ.] [Typ.] 2.40 [Typ.] 1.20 [Typ.] [Typ.] max. 2.75 min. 3.30 max.
INCHES .976 .016 .787 .005 .551 .005 .740 .016 .486 [REF] .033 [REF] .023 [REF] .012 [Typ.] .026 [Typ.] .094 [Typ.] .047 [Typ.] .006 [Typ.] .004 max. .108 .006 .004 min. .130 max.
NOTE: Each lead centerline located within .25mm[.01 inch] true position [TP] maximum material condition.
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
REVISION DESCRIPTION Modify Table. INTCON (C8H) (C0H) Correct Typing error PAGE DATE SEP/06/2002 NOV/11/2002
P/N:PM0762
REV. 0.1, FEB. 2003
MX10F202FC
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688 FAX:+886-3-563-2888
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CHICAGO OFFICE:
TEL:+1-847-963-1900 FAX:+1-847-963-1909
http //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves right change product specifications without notice.

FEATURES MX10F202FC (80C51 with memory LCD) 80C51 core 3.3V volta

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