Three-PLL VCXO Programmable Clock Generator April 2000 Featu

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Three-PLL VCXO Programmable Clock Generator April 2000 Featu

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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Features
Description
volt operation (contact factory volt) Fully user programmable C-bus serial interface Three high-resolution, low-jitter PLLs optimized frequency synthesis Additional multiplier generation highfrequency VCXO function from inexpensive fundamental mode crystals CMOS clock outputs Integrated VCXO circuitry fine-tuning (typically +/100ppm) output frequencies control inputs modify device power-up function (see text) Package: 16-pin (0.150") SOIC Custom default frequency patterns, pinouts, packages available. Contact your local Sales Representative more information.
FS6477 CMOS clock generator designed minimize cost component count variety electronic systems. especially well suited digital video/audio systems such digital set-top boxes.
Figure Configuration
XOUT XTUNE CLK_F/S1 CLK_E/S0
CLK_A CLK_B CLK_C CLK_D MODE
FS6477
Figure Block Diagram
XOUT XTUNE
VCXO Multiplier
CLK_A CLK_B
Divider Array
CLK_C CLK_D CLK_E/S0
I2C-bus Interface
Device Control
CLK_F/S1 MODE
FS6477
Intel Pentium registered trademarks Intel Corporation. Non-linear spread spectrum modulation profile licensed under Patent 5488627, Lexmark International, Inc. This document contains information product. Specifications information herein subject change without notice.
ISO9001
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
Advance Information Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active-low
April 2000
TYPE DIUO DIUO
NAME XOUT XTUNE CLK_F/S1 CLK_E/S0 MODE CLK_D CLK_C CLK_B CLK_A Serial interface data input/output Power supply (3.3V nominal) Ground
DESCRIPTION
Voltage-controlled crystal oscillator feedback Voltage-controlled crystal oscillator drive VCXO control voltage input clock output control input clock output control input Device MODE select (see text) clock output Ground clock output clock output Power supply 3.3V) clock output Serial interface clock input
Functional Block Description
Voltage-Controlled Crystal Oscillator (VCXO)
Figure Typical VCXO Characteristic
VCXO Deviation XTUNE Input (typical)
Deviation -100 -150 -200 V(XTUNE) volts
VCXO provides tunable, low-jitter frequency reference rest FS6477 system components. Load capacitors internal FS6477. external components (other than crystal itself) required operation VCXO. Continuous fine-tuning VCXO frequency accomplished varying voltage XTUNE pin. oscillator operates crystal resonator parallel-resonant mode. "Pulling" crystal oscillation frequency accomplished altering effective load capacitance presented crystal. actual amount that changing load capacitance alters oscillator frequency will depend characteristics crystal well oscillator circuit itself. Specifically, motional capacitance crystal (usually referred crystal manufacturers C1), static capacitance crystal (C0), load capacitance (CL) oscillator determine "pulling" capability crystal oscillator circuit.
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000 simple formula obtain peak-to-peak "pulling" capability crystal oscillator
ppm)
compares frequencies input will drive faster slower) until both frequencies equal. When this condition been met:
where extremes applied load capacitance. EXAMPLE: crystal with following parameters used. With 0.02pF, 6pF, 10pF, 20pF, tuning range (peak-to-peak)
which re-arranged:
0.025
Multiplier
simple Phase-Locked Loop multiplies output frequency VCXO eight programmable PLLs Post Dividers. below description operation.
3.3.1 Reference Divider Reference Divider designed phase jitter. divider accepts output reference oscillator provides divided-down frequency PFD. Reference Divider 8-bit divider, programmed modulus from programming equivalent binary value. divide-by-256 also achieved programming eight bits 00h. 3.3.2 Feedback Divider Feedback Divider based dual-modulus divider (also called dual-modulus prescaler) technique. permits division integer value between 16383. Selected values below also permitted (see Table).
Phase Locked Loops
shown Figure each consists Reference Divider, Phase-Frequency Detector (PFD), charge pump, internal Loop Filter, Voltage-Controlled Oscillator (VCO), Feedback Divider. This standard phase- frequency-locked loop architecture that multiplies reference frequency desired frequency ratio integers. This frequency multiplication exact.
Table Feedback Modulus Below
FBKDIV[2:0] FBKDIV[13:3] 00000000001
Figure Diagram
LFTC
00000000010 00000000011 00000000100 00000000101
fVCO
REFDIV[7:0]
Loop Filter
fREF Reference Divider
(NR)
PhaseFrequency Detector
Charge Pump
DOWN FBKDIV[10:0]
Voltage Controlled Oscillator
00000000110 00000000111
FEEDBACK DIVIDER MODULUS
Feedback Divider (NF)
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
3.3.3 Post Divider Post Divider actually constructed cascade three programmable dividers, shown Figure
April 2000 applications where frequencies must achieved exactly. changes overall device frequency equation
Figure Post Divider
POSTCTL_x [3:0]
Note that nominal 50/50 duty factor always preserved (even selections which have modulus).
Control
Post Divider Post Divider
POST DIVIDER (NP)
Device Control Overview
Post Divider
fOUT
modulus overall combination controlled appropriate register bits (see Table Post Divider performs some useful functions. First, allows operated narrower range speeds compared output frequencies that needed many applications. Second, extra integer denominator permits more flexibility programming loop many
FS6477 contains internal that holds four different device configurations. When MODE LOW, bi-directional pins (CLK_E/S0 CLK_F/S1) made INPUTS voltage levels applied those pins select which those four states made active. When MODE taken HIGH, levels those pins latched, both bi-directional pins made OUTPUTS. desired configuration loaded into registers interface time. configuration will become applied PLLs Post Dividers until appropriate SWAP bits have been "1".
Table Programmable Register
Note: programmable registers cleared (set "0") power-up.
REGISTER OUTPUT POSTDIVA POSTDIVB POSTDIVC POSTDIVD PLLC PLLPD_C POSTPD_A POSTPD_B POSTPD_C POSTPD_D PLLSRC_C PLLB PLLPD_B PLLSRC_B PLLA PLLPD_A PLLSRC_A FUNCTION SWAP BANK BIT7 (MSB) SWAP_7 BIT6 SWAP_6 BIT5 SWAP_5 BIT4 SWAP_4 BIT3 SWAP_3 BIT2 SWAP_2 BIT1 SWAP_1 BIT0 (LSB) SWAP_0
REFDIV_A[7:0] FBKDIV_A[7:0] LFTC_A CP_A FBKDIV_A[10:8] REFDIV_B[7:0] FBKDIV_B[7:0] LFTC_B CP_B FBKDIV_B[10:8] REFDIV_C[7:0] FBKDIV_C[7:0] LFTC_C CP_C FBKDIV_C[10:8] POSTCTL_A[3:0] POSTCTL_B[3:0] POSTCTL_C[3:0] POSTCTL_D[3:0] Reserved CLKCTL_D Reserved CLKCTL_C Reserved CLKCTL_B Reserved CLKCTL_A POSTSRC_A[1:0] POSTSRC_B[1:0] POSTSRC_C[1:0] POSTSRC_D[1:0] Reserved CLKCTL_F Reserved CLKCTL_E
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Table Device Default Frequencies
FS6477-01 F(CLK_A) 9.37500 12.50000 18.75000 37.50000 FREQUENCIES ASSUME 13.5MHz REFERENCE (10MHz F_REF 15MHz) F(CLK_B) 9.37500 12.50000 18.75000 37.50000 F(CLK_C) 9.37500 12.50000 18.75000 37.50000 F(CLK_D) 27.00000 27.00000 27.00000 27.00000 Always F(CLK_D) Always F(CLK_D) F(CLK_E) F(CLK_F)
Table Swap Bits
NAME SWAP_0 SWAP_1 SWAP_2 SWAP_3 SWAP_4 SWAP_5 SWAP_6 SWAP_7 DESCRIPTION Enable PLL_A Control Bits Enable PLL_B Control Bits Enable PLL_C Control Bits Enable POSTDIV_A Control Bits Enable POSTDIV_B Control Bits Enable POSTDIV_C Control Bits Enable POSTDIV_D Control Bits Enable Output Control Bits
Table Post-Divider Control Bits
NAME DESCRIPTION POST-Divider ConTroL Value [0000] [0001] [0010] [0011] [0100] [0101] POSTCTL_x[3:0] [0110] [0111] [1000] [1001] [1010] [1011] [1100] A-Counter Value M-Counter Value [1101] [1110] [1111] POST-Divider SouRCe Crystal Oscillator PLL_M PLL_A PLL_B PLL_C Post-Divider Operates Post-Divider Powered Down (Output STOPPED) Divide-by
Table Control Bits
NAME REFDIV_x [7:0] FBKDIV_x [10:0] DESCRIPTION REFerence DIVider FeedBacK DIVider FBKDIV_A[2:0] FBKDIV_A[10:3]
Charge Pump control CP_x Loop Filter Time Constant LFTC_x reference SouRCe PLLSRC_x Crystal Oscillator Mulltiplier (Crystal Oscillator Operates Powered-Down (Output STOPPED) POSTPD_x POSTSRC_x[3:0]
[00]
[01] [10] [11]
POST-Divider Power-Down
Power-Down PLLPD_x
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
Advance Information Table Output Control Bits
NAME CLKCTL_x DESCRIPTION ClocK ConTroL Output STOPPED Output RUNS
April 2000 4.1.3 STOP Data Transfer high transition line while held high indicates STOP condition. commands device must followed STOP condition. 4.1.4 Data Valid state line represents valid data line stable duration high period line after START condition occurs. data line must changed only during period signal. There clock pulse data bit. Each data transfer initiated START condition terminated with STOP condition. number data bytes transferred between START STOP conditions determined master device, continue indefinitely. However, data that overwritten device after first sixteen bytes will overflow into first register, then second, first-in, firstoverwritten fashion. 4.1.5 Acknowledge When addressed, receiving device required generate Acknowledge after each byte received. master device must generate extra clock pulse coincide with Acknowledge bit. acknowledging device must pull line during high period master acknowledge clock pulse. Setup hold times must taken into account. master must signal data slave generating acknowledge last byte that been read (clocked) slave. this case, slave must leave line high enable master generate STOP condition.
I2C-bus Control Interface
This device read/write slave device meeting Philips C-bus specifications except "general call." controlled master device that generates serial clock SCL, controls access, generates START STOP conditions while device works slave. Both master slave operate transmitter receiver, master device determines which mode activated. device that sends data onto defined transmitter, device receiving data receiver. C-bus logic levels noted herein based percentage power supply (VDD). logic-one corresponds nominal voltage VDD, while logic-zero corresponds ground (VSS).
Conditions
Data transfer only initiated when busy. During data transfer, data line (SDA) must remain stable whenever clock line (SCL) high. Changes data line while clock line high will interpreted device START STOP condition. following conditions defined C-bus protocol. 4.1.1 Busy Both data (SDA) clock (SCL) lines remain high indicate busy. 4.1.2 START Data Transfer high transition line while input high indicates START condition. commands device must preceded START condition.
I2C-bus Operation
programmable registers accessed randomly sequentially this bi-directional wire digital inter2 face. device accepts following C-bus commands. 4.2.1 Slave Address After generating START condition, master broadcasts seven-bit slave address followed bit. address device
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write sixteen bytes data into addressed register before register address pointer overflows back beginning address. acknowledge device between each byte data must occur before next data byte sent. Registers updated every time device sends acknowledge host. register update does wait STOP condition occur. Registers therefore updated different times during Sequential Register Write. 4.2.5 Sequential Register Read Procedure Sequential read operations allow master read from each register order. register pointer automatically incremented after each read. This procedure more efficient than Random Register Read several registers must read. perform read procedure, that transmitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits sixteen bytes data starting with initial addressed register. register address pointer will overflow initial register address larger than zero. After last byte data, master does acknowledge transfer does generate STOP condition. master generates STOP condition.
April 2000 4.2.2 Random Register Write Procedure Random write operations allow master directly write register. initiate write procedure, that transmitted after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write eight bits data into addressed register. final acknowledge returned device, either STOP repeated START condition occurs during Register Write, data that been transferred ignored. 4.2.3 Random Register Read Procedure Random read operations allow master directly read from register. perform read procedure, that transmitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits eight-bit word. master does acknowledge transfer does generate STOP condition. 4.2.4 Sequential Register Write Procedure Sequential write operations allow master write each register order. register pointer automatically incremented after each write. This procedure more efficient than Random Register Write several registers must written. initiate write procedure, that transmitted after seven-bit device address logic-low. This
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
Advance Information Figure Random Register Write Procedure
DEVICE ADDRESS REGISTER ADDRESS DATA
April 2000
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge STOP Condition Acknowledge From device host
Figure Random Register Read Procedure
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command STOP Condition Acknowledge
Figure Sequential Register Write Procedure
DEVICE ADDRESS REGISTER ADDRESS DATA DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device host
Figure Sequential Register Read Procedure
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command Acknowledge
Data Acknowledge STOP Command
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage (VSS ground) Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL
MIN. VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage Ambient Operating Temperature Range SYMBOL CONDITIONS/DESCRIPTION 3.3V MIN. TYP. MAX. UNITS
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Three-PLL VCXO Programmable Clock Generator
Advance Information Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical. Negative currents indicate current flows device.
April 2000
PARAMETER Overall Supply Current, Dynamic, Un-Loaded Outputs Supply Current, Dynamic, Loaded Outputs Supply Current, Fully Powered Down Serial Interface (SCL, SDA) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current Low-Level Output Sink Current (SDA) XTUNE Input Equivalent Input Impedance Equivalent Input Termination Clock Outputs (CLK_x) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Short Circuit Source Current Short Circuit Sink Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDL POSTPD_x PLLPD_x
Vhys 0.4V, 3.0V
VDD*0.75 VSS-0.3 VDD*0.33 VDD*0.5
VDD+0.3 VDD*0.25
RXTUNE
VDD*0.5
ISCH ISCL
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Table Timing Specifications
Unless otherwise stated, 3.3V 10%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Voltage-Controlled Crystal Oscillator (VCXO) Crystal Frequency Crystal Load Capacitance VCXO Minimum Capacitance VCXO Maximum Capacitance Phase-Locked Loops Output Frequency Frequency Clock Outputs (CLK_x) Duty Cycle (when supplied PLL) Duty Cycle (when supplied VCXO) Rise Time Fall Time Jitter, Long Term (when supplied PLL) Jitter, Long Term (when supplied VCXO) Jitter, Period (peak-peak) (when supplied PLL) Jitter, Period (peak-peak) (when supplied VCXO) tj(LT) tj(LT) tj(P) tj(P)
Ratio pulse width measured from rising edge next falling edge VDD*0.5) clock period Ratio pulse width measured from rising edge next falling edge VDD*0.5) clock period
center frequency Typical VXTUNE Typical VXTUNE
fVCO
0.3V 3.0V; 10pF 3.0V 0.3V; 10pF
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
Advance Information Table Serial Interface Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data typical.
April 2000
PARAMETER Clock frequency free time between STOP START time, START (repeated) Hold time, START time, data input Hold time, data input Output data valid from clock Rise time, data clock Fall time, data clock High time, clock time, clock time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO
CONDITIONS/DESCRIPTION
STANDARD MODE MIN. 1000 MAX.
UNITS
Minimum delay bridge undefined region fall-ing edge avoid unintended START STOP SDA, SDA,
Figure Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Data Transfer Sequence
tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
tBUF
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Package Information
Table 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS INCHES MIN. 0.061 0.004 0.055 0.013 0.0075 0.386 0.150 0.230 0.010 0.016 MAX. 0.068 0.0098 0.061 0.019 0.0098 0.393 0.157 0.244 0.016 0.035 MILLIMETERS MIN. 1.55 0.102 1.40 0.33 0.191 9.80 3.81 5.84 0.25 0.41 MAX. 1.73
0.249 1.55 0.49 0.249 9.98 3.99 6.20 0.41 0.89
RADII: 0.005" 0.01"
typ.
SEATING PLANE
0.050
1.27
BASE PLANE
Table 16-pin SOIC (0.150") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air 16-pin 0.150" SOIC Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk SYMBOL CONDITIONS/DESCRIPTION flow Corner lead Center lead lead adjacent lead lead TYP. UNITS °C/W
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FS6477-01
Three-PLL VCXO Programmable Clock Generator
April 2000
Ordering Information
Device Ordering Codes
DEVICE NUMBER PACKAGE TYPE 16-pin (0.150") SOIC (Small Outline Package) 16-pin (0.150") SOIC (Small Outline Package) OPERATING TEMPERATURE RANGE (Commercial) (Commercial) SHIPPING CONFIGURATION Tape Reel Tubes
ORDERING CODE
11825-804 11825-814
FS6477-01 FS6477-01
DATE
Revision Information
PAGE DESCRIPTION This document contains information product. Specifications information herein subject change without notice.
Purchase components American Microsystems, Inc., sublicensed Associated Compa2 nies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. Copyright 2000 American Microsystems, Inc. Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
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Three-PLL VCXO Programmable Clock Generator April 2000 Featu

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