FLASH MEMORY 512K FEATURES Single read, program, erase

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FLASH MEMORY 512K FEATURES Single read, program, erase

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DS05-20860-6E
FLASH MEMORY
512K
FEATURES
Single read, program, erase Minimizes system level power requirements Simultaneous operations Read-while-Erase Read-while-Program Compatible with JEDEC-standard commands Uses same software commands E2PROMs Compatible with JEDEC-standard worldwide pinouts (Pin compatible with MBM29LV800TA/BA) 48-pin TSOP(1) (Package suffix: PFTN Normal Bend Type, PFTR Reversed Bend Type) 48-ball FBGA (Package suffix: PBT) Minimum 100,000 program/erase cycles High performance maximum access time Sector erase architecture byte, four bytes, byte, fourteen bytes. combination sectors concurrently erased. Also supports full chip erase. Boot Code Sector Architecture sector Bottom sector Embedded EraseAlgorithms Automatically pre-programs erases chip sector Embedded ProgramAlgorithms Automatically writes verifies data specified address Data Polling Toggle feature detection program erase cycle completion Ready/Busy output (RY/BY) Hardware method detection program erase cycle completion Automatic sleep mode When addresses remain stable, automatically switch themselves power mode. write inhibit Erase Suspend/Resume Suspends erase operation allow read another sector within same device (Continued)
Embedded Eraseand Embedded Programare trademarks Advanced Micro Devices, Inc.
(Continued) Sector protection Hardware method disables combination sectors from program erase operations Sector Protection function Extended sector protection command Fast Programming Function Extended Command Temporary sector unprotection Temporary sector unprotection RESET pin.
PACKAGES
48-pin plastic TSOP
Marking Side
48-pin plastic TSOP
Marking Side
(FPT-48P-M19)
(FPT-48P-M20)
48-pin plastic FBGA
(BGA-48P-M12)
GENERAL DESCRIPTION
MBM29DL800TA/BA 8M-bit, V-only Flash memory organized bytes bits each words bits each. MBM29DL800TA/BA offered 48-pin TSOP(1) 48-ball FBGA packages. These devices designed programmed in-system with standard system supply. 12.0 required write erase operations. devices also reprogrammed standard EPROM programmers. MBM29DL800TA/BA provide simultaneous operation which read data during program/erase. simultaneous operation architecture provides simultaneous operation dividing memory space into banks. device allow host system program erase bank, then immediately simultaneously read from other bank. standard MBM29DL800TA/BA offer access times allowing operation high-speed microprocessors without wait states. eliminate contention devices have separate chip enable (CE), write enable (WE), output enable (OE) controls. MBM29DL800TA/BA command compatible with JEDEC standard E2PROMs. Commands written command register using standard microprocessor write timings. Register contents serve input internal state-machine which controls erase programming circuitry. Write cycles also internally latch addresses data needed programming erase operations. Reading data devices similar reading from 12.0 Flash EPROM devices. MBM29DL800TA/BA programmed executing program command sequence. This will invoke Embedded Program Algorithm which internal algorithm that automatically times program pulse widths verifies proper cell margin. Typically, each sector programmed verified about seconds. Erase accomplished executing erase command sequence. This will invoke Embedded Erase Algorithm which internal algorithm that automatically preprograms array already programmed before executing erase operation. During erase, devices automatically time erase pulse widths verify proper cell margin. sector typically erased verified second. already completely preprogrammed.) devices also feature sector erase architecture. sector mode allows each sector erased reprogrammed without affecting other sectors. MBM29DL800TA/BA erased when shipped from factory. devices feature single power supply operation both read write functions. Internally generated regulated voltages provided program erase operations. detector automatically inhibits write operations loss power. program erase detected Data Polling DQ7, Toggle feature DQ6, RY/BY output pin. Once program erase cycle been completed, devices internally reset read mode. Fujitsu's Flash technology combines years EPROM E2PROM experience produce highest levels quality, reliability, cost effectiveness. MBM29DL800TA/BA memories electrically erase entire chip bits within sector simultaneously Fowler-Nordhiem tunneling. bytes/words programmed byte/word time using EPROM programming mechanism electron injection.
PRODUCT LINE
Part Ordering Part
+0.3 -0.3
MBM29DL800TA/MBM29DL800BA
+0.6 -0.3
Address Access Time (ns) Access Time (ns) Access Time (ns)
BLOCK DIAGRAM
Bank Address (A-1)
Cell Matrix (Bank
X-Decoder RY/BY Status
RESET BYTE
State Control Command Register
X-Decoder
Y-Gating Data Latch
Bank Address
Cell Matrix (Bank
Y-Gating Data Latch
ASSIGNMENTS
TSOP(1) N.C. N.C. RESET N.C. N.C. RY/BY (Marking Side) BYTE 15/A-1 DQ14 DQ13 DQ12 DQ11 DQ10
MBM29DL800TA/MBM29DL800BA Normal Bend
(FPT-48P-M19) RY/BY N.C. N.C. RESET N.C. N.C. (Marking Side) DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 BYTE
MBM29DL800TA/MBM29DL800BA Reverse Bend
(FPT-48P-M20)
(Continued)
(Continued)
FBGA
(Top View)
Marking side
(BGA-48P-M12)
RY/BY N.C. N.C. DQ10 DQ11
RESET N.C. N.C. DQ12
DQ14 DQ13
BYTE DQ15/A-1
DESCRIPTION
Name A-1, DQ15 RY/BY RESET BYTE N.C. Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Ready/Busy Output Hardware Reset Pin/Temporary Sector Unprotection Selects 8-bit 16-bit mode Internal Connection Device Ground Device Power Supply Function
LOGIC SYMBOL
RESET BYTE RY/BY
DEVICE OPERATION
MBM29DL800TA/BA User Operations Table (BYTE VIH) Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*3 Standby Output Disable Write (Program/Erase) Enable Sector Protection*2, Verify Sector Protection Temporary Sector Unprotection*5 Reset (Hardware)/Standby DQ15 Code Code DOUT High-Z High-Z Code High-Z RESET
MBM29DL800TA/BA User Operations Table (BYTE VIL) Operation Auto-Select Manufacturer Code*1 Auto-Select Device Code*1 Read*3 Standby Output Disable Write (Program/Erase) Enable Sector Protection*2, Verify Sector Protection Temporary Sector Unprotection Reset (Hardware)/Standby Legend: VIL, VIH, VIH, DQ15/ RESET Code Code DOUT High-Z High-Z Code High-Z
Pulse input.
CHARACTERISTICS" voltage levels.
Manufacturer device codes also accessed command register write sequence. "MBM29DL800TA/BA Command Definitions Table". Refer section Sector Protection. VIL, initiates write operations. also used extended sector protection.
MBM29DL800TA/BA Command Definitions Table Command Sequence
Read/Reset Read/Reset Write Cycles Req'd
First Second Third Fourth Fifth Sixth Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data XXXh 2AAh 555h 2AAh AAAh 555h 2AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h XXXh XXXh 555h AAAh 555h AAAh 555h AAAh 555h AAAh XXXh XXXh XXXh 555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh 555h AAAh
Word Byte Word Byte Word
555h AAAh 555h
Autoselect
Byte Word Byte Word Byte Word Byte
Program
2AAh 555h 2AAh 555h
555h AAAh
Chip Erase
Sector Erase
Erase Suspend Erase Resume
Fast Mode Fast Program Reset from Fast Mode Extended Sector Protect*2
555h AAAh 555h AAAh
Word Byte Word Byte Word Byte Word Byte
This command valid during Fast Mode. This command valid while RESET=VID. This data "00h" also acceptable. Notes bits address commands except Program Address (PA), Sector Address (SA), Bank Address (BA). operations defined "MBM29DL800TA/BA User Operations Tables (BYTE BYTE VIL)". =Address memory location read =Address memory location programmed Addresses latched falling edge write pulse. =Address sector erased. combination A18, A17, A16, A15, A14, A13, will uniquely select sector. =Bank Address (A16 A18) =Data read from location during read operation. =Data programmed location Data latched rising edge write pulse. =Sector address protected. sector address (SA) (A6, =Sector protection verify data. Output protected sector addresses output unprotected sector addresses. system should generate following address patterns: Word Mode: 555h 2AAh addresses Byte Mode: AAAh 555h addresses Both Read/Reset commands functionally equivalent, resetting device read mode. command combinations described "MBM29DL800TA/BA Command Definitions Table" illegal.
MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table Type Manufacture's Code Byte MBM29DL800TA Word Device Code Byte MBM29DL800BA Word Sector Protection Sector Addresses 22CBh 01h*2 224Ah A-1*1 Code (HEX)
Byte mode. Byte mode, DQ14 High-Z DQ15 A-1, lowest address. Outputs protected sector addresses outputs unprotected sector addresses. Extended Autoselect Code Table Type Manufacturer's Code
(B)*
Code
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 A-1/0
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
MBM29DL800TA Device Code MBM29DL800BA
22CBh 224Ah (B)*
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
A-1/0
Sector Protection (B): Byte mode (W): Word mode HI-Z: High-Z
Byte mode, DQ14 High-Z DQ15 A-1, lowest address.
FLEXIBLE SECTOR-ERASE ARCHITECTURE
bytes, four bytes, bytes, fourteen bytes Individual-sector, multiple-sector, bulk-erase capability Individual multiple-sector protection user definable.
byte
byte
FFFFFh 7FFFFh FBFFFh 7DFFFh byte F3FFFh 79FFFh byte F1FFFh 78FFFh byte Bank byte EDFFFh 76FFFh byte EBFFFh 75FFFh byte E3FFFh 71FFFh Bank byte DFFFFh 6FFFFh byte CFFFFh 67FFFh byte BFFFFh 5FFFFh byte AFFFFh 57FFFh byte 9FFFFh 4FFFFh byte 8FFFFh 47FFFh byte 7FFFFh 3FFFFh byte Bank byte 5FFFFh 2FFFFh byte 4FFFFh 27FFFh byte 3FFFFh 1FFFFh Bank byte 2FFFFh 17FFFh byte 1FFFFh 0FFFFh byte 0FFFFh 07FFFh byte 00000h 00000h MBM29DL800TA Sector Architecture byte byte byte byte byte byte 6FFFFh 37FFFh byte byte byte byte byte byte byte byte byte byte byte EFFFFh 77FFFh byte byte byte byte
FFFFFh 7FFFFh EFFFFh 77FFFh DFFFFh 6FFFFh CFFFFh 67FFFh BFFFFh 5FFFFh AFFFFh 57FFFh 9FFFFh 4FFFFh 8FFFFh 47FFFh 7FFFFh 3FFFFh 6FFFFh 37FFFh 5FFFFh 2FFFFh 4FFFFh 27FFFh 3FFFFh 1FFFFh 2FFFFh 17FFFh 1FFFFh 0FFFFh 1BFFFh 0DFFFh 13FFFh 09FFFh 11FFFh 08FFFh 0FFFFh 07FFFh 0DFFFh 06FFFh 0BFFFh 05FFFh 03FFFh 01FFFh 00000h 00000h MBM29DL800BA Sector Architecture
Sector Address Table (MBM29DL800BA) Sector Address Bank Sector Bank Address SA21 SA20 SA19 SA18 SA17 SA16 SA15 Bank SA14 SA13 SA12 SA11 SA10 Bank 16/8 32/16 0E000h 0FFFFh 0C000h 0DFFFh 08000h 0BFFFh, 04000h 07FFFh 00000h 03FFFh 07000h 07FFFh 06000h 06FFFh 04000h 05FFFh, 02000h 03FFFh 00000h 01FFFh 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16/8 80000h 8FFFFh 70000h 7FFFFh 60000h 6FFFFh 50000h 5FFFFh 40000h 4FFFFh 30000h 3FFFFh 20000h 2FFFFh 1C000h 1FFFFh 40000h 47FFFh 38000h 3FFFFh 30000h 37FFFh 28000h 2FFFFh 20000h 27FFFh 18000h 1FFFFh 10000h 17FFFh 0E000h 0FFFFh 64/32 64/32 64/32 64/32 64/32 64/32 64/32 F0000h FFFFFh E0000h EFFFFh D0000h DFFFFh C0000h CFFFFh B0000h BFFFFh A0000h AFFFFh 90000h 9FFFFh 78000h 7FFFFh 70000h 77FFFh 68000h 6FFFFh 60000h 67FFFh 58000h 5FFFFh 50000h 57FFFh 48000h 4FFFFh Sector Size (Kbytes/ Kwords) Address Range Address Range
18000h 1BFFFh, 0C000h 0DFFFh, 14000h 17FFFh 0A000h 0BFFFh 12000h 13FFFh 10000h 11FFFh 09000h 09FFFh 08000h 08FFFh
Note address range A18: byte mode (BYTE VIL). address range A18: word mode (BYTE VIH).
Sector Address Table (MBM29DL800TA) Sector Address Bank Sector Bank Address Bank SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank SA18 SA19 SA20 SA21 16/8 32/16 F0000h F1FFFh F2000h F3FFFh F4000h F7FFFh, F8000h FBFFFh FC000h FFFFFh 78000h 78FFFh 79000h 79FFFh 7A000h 7BFFFh, 7C000h 7DFFFh 7E000h 7FFFFh 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 16/8 70000h 7FFFFh 80000h 8FFFFh 90000h 9FFFFh A0000h AFFFFh B0000h BFFFFh C0000h CFFFFh D0000h DFFFFh E0000h E3FFFh E4000h E7FFFh, E8000h EBFFFh EC000h EDFFFh EE000h EFFFFh 38000h 3FFFFh 40000h 47FFFh 48000h 4FFFFh 50000h 57FFFh 58000h 5FFFFh 60000h 67FFFh 68000h 6FFFFh 70000h 71FFFh 72000h 73FFFh, 74000h 75FFFh 76000h 76FFFh 77000h 77FFFh 64/32 64/32 64/32 64/32 64/32 64/32 64/32 00000h 0FFFFh 10000h 1FFFFh 20000h 2FFFFh 30000h 3FFFFh 40000h 4FFFFh 50000h 5FFFFh 60000h 6FFFFh 00000h 07FFFh 08000h 0FFFFh 10000h 17FFFh 18000h 1FFFFh 20000h 27FFFh 28000h 2FFFFh 30000h 37FFFh Sector Size (Kbytes/ Kwords) Address Range Address Range
Note address range A18: byte mode (BYTE VIL). address range A18: word mode (BYTE VIH).
FUNCTIONAL DESCRIPTION
Simultaneous Operation
MBM29DL800TA/BA have feature, which capability reading data from bank memory while program erase operation progress other bank memory (simultaneous operation), addition conventional features (read, program, erase, erase-suspend read, erase-suspend program). bank selection selected bank address (A16 A18) with zero latency. MBM29DL800TA/BA have banks which contain Bank Bank fourteen sectors). simultaneous operation execute multi-function mode same bank. "Simultaneous Operation Table" shows combination possible simultaneous operation. Simultaneous Operation Table Case Bank Status Read mode Read mode Read mode Read mode Autoselect mode Program mode Erase mode Bank Status Read mode Autoselect mode Program mode Erase mode Read mode Read mode Read mode
erase operation also supended read from program sector being erased.
Read Mode
MBM29DL800TA/BA have control functions which must satisfied order obtain data outputs. power control should used device selection. output control should used gate data output pins device selected. Address access time (tACC) equal delay from stable addresses valid output data. chip enable access time (tCE) delay from stable addresses stable valid data output pins. output enable access time delay from falling edge valid data output pins. (Assuming addresses have been stable least tACC-tOE time.) When reading data without changing addresses after power-up, necessary input hardware reset change from
Standby Mode
There ways implement standby mode MBM29DL800TA/BA devices, using both RESET pins; other RESET only. When using both pins, CMOS standby mode achieved with RESET inputs both held Under this condition current consumed less than During Embedded Algorithm operation, active current (ICC2) required even "H". device read with standard access time (tCE) from either these standby modes. When using RESET only, CMOS standby mode achieved with RESET input held "L"). Under this condition current consumed less than Once RESET taken high, device requires wake time before outputs valid read access. standby mode outputs high impedance state, independent input.
Automatic Sleep Mode
There function called automatic sleep mode restrain power consumption during read-out MBM29DL800TA/BA data. This mode used effectively with application requested power consumption such handy terminals. activate this mode, MBM29DL800TA/BA automatically switch themselves power mode when MBM29DL800TA/BA addresses remain stably during access fine necessary control mode. Under mode, current consumed typically (CMOS Level). During simultaneous operation, active current (ICC2) required. Since data latched during this mode, data read-out continuously. addresses changed, mode canceled automatically MBM29DL800TA/BA read-out data changed addresses.
Output Disable
With input logic high level (VIH), output from devices disabled. This will cause output pins high impedance state.
Autoselect
autoselect mode allows reading binary code from devices will identify manufacturer type. This mode intended programming equipment purpose automatically matching devices programmed with corresponding programming algorithm. This mode functional over entire temperature range devices. activate this mode, programming equipment must force (11.5 12.5 address identifier bytes then sequenced from devices outputs toggling address from VIH. addresses DON'T CARES except (A-1). (See "MBM29DL800TA/BA User Operations Tables (BYTE BYTE VIL)" sDEVICE OPERATION.) manufacturer device codes also read command register, instances when MBM29DL800TA/BA erased programmed system without access high voltage pin. command sequence illustrated "MBM29DL800TA/BA Command Definitions Table" sDEVICE OPERATION). (Refer Autoselect Command section.) Word VIL) represents manufacturer's code (Fujitsu 04h) word VIH) represents device identifier code (MBM29DL800TA MBM29DL800BA mode; MBM29DL800TA 224Ah MBM29DL800BA 22CBh mode). These bytes/words given "MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" "Extended Autoselect Code Table" sDEVICE OPERATION). identifiers manufactures device will exhibit parity with defined parity bit. order read proper device codes when executing autoselect, must VIL. (See "MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" "Extended Autoselect Code Table" sDEVICE OPERATION.) case applying since both Bank Bank enters Autoselect mode, simultenous operation executed.
Write
Device erasure programming accomplished command register. contents register serve inputs internal state machine. state machine outputs dictate function device. command register itself does occupy addressable memory location. register latch used store commands, along with address data information needed execute command. command register written bringing VIL, while VIH. Addresses latched falling edge whichever happens later; while data latched rising edge whichever happens first. Standard microprocessor write timings used. Refer Write Characteristics Erase/Programming Waveforms specific timing parameters.
Sector Protection
MBM29DL800TA/BA feature hardware sector protection. This feature will disable both program erase operations number sectors through 21). sector protection feature enabled using programming equipment user's site. devices shipped with sectors unprotected. Alternatively, Fujitsu program protect sectors factory prior shiping device. activate this mode, programming equipment must force address control (suggest 11.5 VIL, VIL, VIH. sector addresses (A18, A17, A16, A15, A14, A13, A12) should sector protected. "Sector Address Tables (MBM29DL800TA/BA)" sFLEXIBLE SECTOR-ERASE ARCHITECTURE define sector address each twenty (22) individual sectors. Programming protection circuitry begins falling edge pulse terminated with rising edge same. Sector addresses must held constant during pulse. "(13) Waveforms Sector Protection" sTIMING DIAGRAM "(5) Sector Protection Algorithm" sFLOW CHART sector protection waveforms algorithm. verify programming protection circuitry, programming equipment must force address with VIH. Scanning sector addresses (A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical code device output protected sector. Otherwise devices will read unprotected sector. this mode, lower order addresses, except DON'T CARES. Address locations with reserved Autoselect manufacturer device codes. requires apply byte mode. also possible determine sector protected system writing Autoselect command. Performing read operation address location XX02h, where higher order addresses (A18, A17, A16, A15, A14, A13, A12) desired sector address will produce logical protected sector. "MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" "Extended Autoselect Code Table" sDEVICE OPERATION Autoselect codes.
Temporary Sector Unprotection
This feature allows temporary unprotection previously protected sectors MBM29DL800TA/BA devices order change data. Sector Unprotection mode activated setting RESET high voltage During this mode, formerly protected sectors programmed erased selecting sector addresses. Once taken away from RESET pin, previously protected sectors will protected again. "(14) Temporary Sector Unprotection Timing Diagram" sTIMING DIAGRAM "(6) Temporary Sector Unprotection Algorithm" sFLOW CHART.
RESET Hardware Reset
MBM29DL800TA/BA devices reset driving RESET VIL. RESET pulse requirement kept (VIL) least order properly reset internal state machine. operation process being executed will terminated internal state machine will reset read mode after RESET driven low. Furthermore, once RESET goes high, devices require additional before will allow read access. When RESET low, devices will standby mode duration pulse data output pins will tri-stated. hardware reset occurs during program erase operation, data that particular location will corrupted. Please note that RY/BY output signal should ignored during RESET pulse. "(9) RESET/RY/BY Timing Diagram" sTIMING DIAGRAM timing diagram. Refer Temporary Sector Unprotection additional functionality.
COMMAND DEFINITIONS
Device operations selected writing specific address data sequences into command register. Writing incorrect address data values writing them improper sequence will reset devices read mode. Some commands required Bank Address (BA) input. When command sequences inputed bank being read, commands have priority than reading. "MBM29DL800TA/BA Command Definitions Table" sDEVICE OPERATION defines valid register command sequences. Note that Erase Suspend (B0h) Erase Resume (30h) commands valid only while Sector Erase operation progress. Moreover both Read/Reset commands functionally equivalent, resetting device read mode. Please note that commands always written DQ15 bits ignored.
Read/Reset Command
order return from Autoselect mode Exceeded Timing Limits (DQ5 Read/Reset mode, Read/ Reset operation initiated writing Read/Reset command sequence into command register. Microprocessor read cycles retrieve array data from memory. devices remain enabled reads until command register contents altered. devices will automatically power-up Read/Reset state. this case, command sequence required read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that spurious alteration memory content occurs during power transition. Refer Read Characteristics Waveforms specific timing parameters.
Autoselect Command
Flash memories intended applications where local alters memory contents. such, manufacture device codes must accessible while devices reside target system. PROM programmers typically access signature codes raising high voltage. However, multiplexing high voltage onto address lines generally desired system design practice. device contains Autoselect command operation supplement traditional PROM programming methodology. operation initiated writing Autoselect command sequence into command register. Autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains bank address (BA) Autoselect command. Then manufacture device codes read from bank, actual data memory cell read from another bank. Following command write, read cycle from address (BA)00h retrieves manufacture code 04h. read cycle from address (BA)01h returns device code (MBM29DL800TA MBM29DL800BA mode; MBM29DL800TA 224Ah MBM29DL800BA 22CBh mode). (See "MBM29DL800TA/BA Sector Protection Verify Autoselect Codes Table" "Extended Autoselect Code Table" sDEVICE OPERATION.) manufacturer device codes will exhibit parity with defined parity bit. Sector state (protection unprotection) will informed address (BA)02h ((BA)04h Scanning sector addresses (A18, A17, A16, A15, A14, A13, A12) while (A6, will produce logical device output protected sector. programming verification should performed verify sector protection protected sector. (See "MBM29DL800TA/BA User Operations Tables (BYTE BYTE VIL)" sDEVICE OPERATION.) manufacture device codes allowed reading from selected bank. read manufacture device codes sector protection status from non-selected bank, necessary write Read/Reset command sequence into register then Autoselect command should written into bank read. software (program code) Autoselect command stored into Frash memory, device manufacture codes should read from other bank where contain software.
terminate operation, necessary write Read/Reset command sequence into register, also write Autoselect command during operation, execute after writing Read/Reset command sequence.
Byte/Word Programming
devices programmed byte-by-byte word-by-word) basis. Programming four cycle operation. There "unlock" write cycles. These followed program set-up command data write cycles. Addresses latched falling edge whichever happens later data latched rising edge whichever happens first. rising edge (whichever happens first) begins programming. Upon executing Embedded Program Algorithm command sequence, system required provide further controls timings. device will automatically provide adequate internally generated program pulses verify programmed cell margin. system determine status program operation using (Data Polling), (Toggle Bit), RY/BY. Data Polling Toggle must performed memory location which being programmed. automatic programming operation completed when data equivalent data written this which time devices return read mode addresses longer latched. (See "Hardware Sequence Flags Table".) Therefore, devices require that valid address devices supplied system this particular instance time. Hence, Data Polling must performed memory location which being programmed. commands written chip during this period will ignored. hardware reset occurs during programming operation, impossible guarantee data being written. Programming allowed sequence across sector boundaries. Beware that data cannot programmed back "1". Attempting either hang device result apparent success according data polling algorithm read from Read/Reset mode will show that data still "0". Only erase operations convert "0"s "1"s. "(1) Embedded ProgramAlgorithm" sFLOW CHART illustrates Embedded ProgramAlgorithm using typical command strings operations.
Chip Erase
Chip erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed chip erase command. Chip erase does require user program device prior erase. Upon executing Embedded Erase Algorithm command sequence devices will automatically program verify entire memory zero data pattern prior electrical erase (Preprogram function). system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. chip erase begins rising edge last whichever happens first command sequence terminates when data (See Write Operation Status section.) which time device returns read mode. Chip Erase Time; Sector Erase Time sectors Chip Program Time (Preprogramming) "(2) Embedded EraseAlgorithm" sFLOW CHART illustrates Embedded EraseAlgorithm using typical command strings operations.
Sector Erase
Sector erase cycle operation. There "unlock" write cycles. These followed writing "set-up" command. more "unlock" write cycles then followed Sector Erase command. sector address (any address location within desired sector) latched falling edge whichever happens later, while command (Data=30h) latched rising edge which happens first. After time-out from rising edge last sector erase command, sector erase operation will begin. Multiple sectors erased concurrently writing cycle operations "MBM29DL800TA/BA Command Definitions Table" sDEVICE OPERATION. This sequence followed with writes Sector Erase command addresses other sectors desired concurrently erased. time between writes must less than otherwise that command will accepted erasure will start. recommended that processor interrupts disabled during this time guarantee this condition. interrupts re-enabled after last Sector Erase command written. time-out from rising edge last whichever happens first will initiate execution Sector Erase command(s). another falling edge whichever happens first occurs within time-out window timer reset. (Monitor determine sector erase timer window still open, section DQ3, Sector Erase Timer.) command other than Sector Erase Erase Suspend during this time-out period will reset devices read mode, ignoring previous command string. Resetting devices once execution begun will corrupt data sector. that case, restart erase those sectors allow them complete. (Refer Write Operation Status section Sector Erase Timer operation.) Loading sector erase buffer done sequence with number sectors 21). Sector erase does require user program devices prior erase. devices automatically program memory locations sector(s) erased prior electrical erase (Preprogram function). When erasing sector sectors remaining unselected sectors affected. system required provide controls timings during these operations. system determine status erase operation using (Data Polling), (Toggle Bit), RY/BY. sector erase begins after time from rising edge whichever happens first last sector erase command pulse terminates when data (See Write Operation Status section.) which time devices return read mode. Data polling Toggle must performed address within sectors being erased. Multiple Sector Erase Time; [Sector Erase Time Sector Program Time (Preprogramming)] Number Sector Erase case multiple sector erase across bank boundaries, read from bank (read-while-erase) performe. "(2) Embedded EraseAlgorithm" sFLOW CHART illustrates Embedded EraseAlgorithm using typical command strings operations.
Erase Suspend/Resume
Erase Suspend command allows user interrupt Sector Erase operation then perform data reads from programs sector being erased. This command applicable ONLY during Sector Erase operation which includes time-out period sector erase. Erase Suspend command will ignored written during Chip Erase operation Embedded Program Algorithm. Writting Erase Suspend command (B0h) during Sector Erase time-out results immediate termination time-out period suspension erase operation. Writing Erase Resume command (30h) resumes erase operation. bank addresses sector being erasing suspending should when writting Erase Suspend Erase Resume command.
When Erase Suspend command written during Sector Erase operation, device will take maximum suspend erase operation. When devices have entered erase-suspended mode, output will Hi-Z will logic "1", will stop toggling. user must address erasing sector reading determine erase operation been suspended. Further writes Erase Suspend command ignored. When erase operation been suspended, devices default erase-suspend-read mode. Reading data this mode same reading from standard read mode except that data must read from sectors that have been erase-suspended. Successively reading from erase-suspended sector while device erase-suspend-read mode will cause toggle. (See section DQ2.) After entering erase-suspend-read mode, user program device writing appropriate command sequence Program. This program mode known erase-suspend-program mode. Again, programming this mode same programming regular Program mode except that data must programmed sectors that erase-suspended. Successively reading from erase-suspended sector while devices erase-suspend-program mode will cause toggle. erasesuspended Program operation detected RY/BY output pin, Data polling Toggle (DQ6) which same regular Program operation. Note that must read from Program address while read from address within bank being erase-suspended. resume operation Sector Erase, Resume command (30h) should written bank being erase suspended. further writes Resume command this point will ignored. Another Erase Suspend command written after chip resumed erasing.
Extended Command
Fast Mode MBM29DL800TA/BA Fast Mode function. This mode dispenses with initial unclock cycles required standard program command sequence writing Fast Mode command into command register. this mode, required cycle programming cycles instead four cycles standard program command. write erase command this mode.) read operation also executed after exiting this mode. exit this mode, necessary write Fast Mode Reset command into command register. first cycle must contain bank address. (Refer "(8) Embedded ProgramAlgorithm Fast Mode" sFLOW CHART Extended algorithm.) active current required even during Fast Mode. Fast Programming During Fast Mode, programming executed with cycles operation. Embedded Program Algorithm executed writing program set-up command (A0h) data write cycles (PA/PD). (Refer "(8) Embedded ProgramAlgorithm Fast Mode" sFLOW CHART Extended algorithm.) Extended Sector Protection addition normal sector protection, MBM29DL800TA/BA Extended Sector Protection extended function. This function enable protect sector forcing RESET write commnad sequence. Unlike conventional procedure, necessary force control timing control pins. only RESET requires sector protection this mode. extended sector protect requires RESET pin. With this condition, operation initiated writing set-up command (60h) into command register. Then, sector addresses pins (A18, A17, A16, A15, A14, A12) (A6, should sector protected (recommend other addresses pins), write extended sector protect command (60h). sector typically protected verify programming protection circuitry, sector addresses pins (A18, A17, A16, A15, A14, A12) (A6, should write command (40h). Following command write, logical device output will produce protected sector read operation. output data logical "0", please repeat write extended sector protect command (60h) again. terminate operation, necessary RESET VIH.
Write Operation Status
Detailed "Hardware Sequence Flags Table" status flags that determine status bank current mode operation. read operation from bank where operate Embedded Algorithm returns data memory cell. These bits offer method determining whether Embedded Algorithm completed properly. information address sensitive. This means that address from erasing sector consectively read, then will toggle. However, will toggle address from nonerasing sector consectively read. This allows user determine which sectors erasing which not. status flag output from bank (non-busy bank) executing Embedded Algorithm. example, there bank (busy bank) which executing Embedded Algorithm. When read sequence <busy bank>, <non-busy bank>, <busy bank>, toggling case [3]. case [2], data memory cell outputted. erase-suspend read mode with same read sequence, will toggled [3]. erase suspend read mode, toggled [3]. case [2], data memory cell outputted.
Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm Progress Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode Data Toggle Toggle Data Toggle Toggle Toggle Toggle Toggle*1 Toggle Data
Data Data
Successive reads from erasing erase-suspend sector cause toggle. Reading from non-erase suspend sector address indicates logic bit.
Data Polling
MBM29DL800TA/BA devices feature Data Polling method indicate host that Embedded Algorithms progress completed. During Embedded Program Algorithm attempt read devices will produce complement data last written DQ7. Upon completion Embedded Program Algorithm, attempt read device will produce true data last written DQ7. During Embedded Erase Algorithm, attempt read device will produce output. Upon completion Embedded Erase Algorithm attempt read device will produce output. flowchart Data Polling (DQ7) shown "(3) Data Polling Algorithm" sFLOW CHART. programming, Data Polling valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Data Polling valid after rising edge sixth write pulse write pulse sequence. Data Polling must performed sector address within sectors being erased protected sector. Otherwise, status valid. program address falls within protected sector, Data Polling active approximately then that bank returns read mode. After erase command sequence written, sectors selected erasing protected, Data Polling active approximately then bank returns read mode. Once Embedded Algorithm operation close being completed, MBM29DL800TA/BA data pins (DQ7) change asynchronously while output enable (OE) asserted low. This means that devices driving status information instant time then that byte's valid data next instant time. Depending when system samples output, read status valid data. Even device completed Embedded Algorithm operation valid data, data outputs still invalid. valid data will read successive read attempts. Data Polling feature only active during Embedded Programming Algorithm, Embedded Erase Algorithm sector erase time-out. (See "Hardware Sequence Flags Table".) "(6) Waveforms Data Polling during Embedded Algorithm Operations" sTIMING DIAGRAM Data Polling timing specifications diagrams.
Toggle
MBM29DL800TA/BA also feature "Toggle method indicate host system that Embedded Algorithms progress completed. During Embedded Program Erase Algorithm cycle, successive attempts read toggling) data from devices will result toggling between zero. Once Embedded Program Erase Algorithm cycle completed, will stop toggling valid data will read next successive attempts. During programming, Toggle valid after rising edge fourth write pulse four write pulse sequence. chip erase sector erase, Toggle valid after rising edge sixth write pulse write pulse sequence. Toggle active during sector time out. programming, sector being written protected, toggle will toggle about then stop toggling without data having changed. erase, devices will erase selected sectors except ones that protected. selected sectors protected, chip will toggle toggle about then drop back into read mode, having changed none data. Either toggling will cause toggle. addition, Erase Suspend/Resume command will cause toggle. system determine whether sector actively erasing erase-suspended. When bank actively erasing (that Embedded Erase Algorithm progress), toggles. When bank enters Erase Suspend mode, stops toggling. Successive read cycles during erase-suspend-program cause toggle.
operate toggle function properly, must high when bank address changed. "(7) Waveforms Toggle during Embedded Algorithm Operations" sTIMING DIAGRAM Toggle timing specifications diagrams.
Exceeded Timing Limits
will indicate program erase time exceeded specified limits (internal pulse count). Under these conditions will produce "1". This failure condition which indicates that program erase cycle successfully completed. Data Polling only operating function devices under this condition. circuit will partially power down device under these conditions approximately mA). pins will control output disable functions described "MBM29DL800TA/BA User Operations Tables (BYTE BYTE VIL)" sDEVICE OPERATION). failure condition also appear user tries program blank location without erasing. this case devices lock never complete Embedded Algorithm operation. Hence, system never reads valid data never stops toggling. Once devices have exceeded timing limits, will indicate "1." Please note that this device failure condition since devices were incorrectly used. this occurs, reset device with command sequence.
Sector Erase Timer
After completion initial sector erase command sequence sector erase time-out will begin. will remain until time-out complete. Data Polling Toggle valid after initial sector erase command sequence. Data Polling Toggle indicates device been written with valid erase command, used determine sector erase timer window still open. high ("1") internally controlled erase cycle begun; attempts write subsequent commands device will ignored until erase operation completed indicated Data Polling Toggle ("0"), device will accept additional sector erase commands. insure command been accepted, system software should check status prior following each subsequent Sector Erase command. were high second status check, command have been accepted. "Hardware Sequence Flags Table".
Toggle
This toggle along with DQ6, used determine whether devices Embedded Erase Algorithm Erase Suspend. Successive reads from erasing sector will cause toggle during Embedded Erase Algorithm. devices erase-suspended-read mode, successive reads from erase-suspended sector will cause toggle. When devices erase-suspended-program mode, successive reads from byte address non-erase suspended sector will indicate logic bit. different from that toggles only when standard program Erase, Erase Suspend Program operation progress. behavior these status bits, along with that DQ7, summarized follows: example, used together determine erase-suspend-read mode progress. (DQ2 toggles while does not.) also "Hardware Sequence Flags Table" "(16) DQ6" sTIMING DIAGRAM. Furthermore, also used determine which sector being erased. When device erase mode, toggles this read from erasing sector. operate toggle function properly, must high when bank address changed.
Reading Toggle Bits DQ6/DQ2
Whenever system initially begins reading toggle status, must read least twice determine whether toggle toggling. Typically, system would note store value toggle after first read. After second read, system would compare value toggle with first. toggle toggling, this indicates that device completed program erase operation. system read array data following read cycle. However, after initial read cycles, system determines that toggle still toggling, system also should note whether value high (see "the section DQ5") system should then determine again whether toggle toggling, since toggle have stopped toggling just went high. toggle longer toggling, device successfully completed program erase operation. still toggling, device complete operation successfully, system must write reset command return reading array data. remaining scenario that system initially determines that toggle toggling gone high. system continue monitor toggle through successive read cycles, determining status described previous paragraph. Alternatively, choose perform other system tasks. this case, system must start beginning algorithm when returns determine status operation (See "(4) Toggle algorithm" sFLOW CHART) Toggle Status Table Mode Program Erase Erase-Suspend Read (Erase-Suspended Sector) Erase-Suspend Program Toggle Toggle Toggle Toggle*1 Toggle
Successive reads from erasing erase-suspend sector cause toggle. Reading from non-erase suspend sector address indicates logic bit.
RY/BY Ready/Busy
MBM29DL800TA/BA provide RY/BY open-drain output indicate host system that Embedded Algorithms either progress been completed. output low, devices busy with either program erase operation. output high, devices ready accept read/ write erase operation. When RY/BY low, devices will accept additional program erase commands. MBM29DL800TA/BA placed Erase Suspend mode, RY/BY output will high. During programming, RY/BY driven after rising edge fourth write pulse. During erase operation, RY/BY driven after rising edge sixth write pulse. RY/BY will indicate busy condition during RESET pulse. Refer "(8) RY/BY Timing Diagram during Program/Erase Operations" "(9) RESET/RY/BY Timing Diagram" sTIMING DIAGRAM detailed timing diagram. RY/BY pulled high standby mode. Since this open-drain output, pull-up resistor needs connected VCC; multiples devices connected host system more than RY/BY parallel.
Byte/Word Configuration
BYTE selects byte (8-bit) mode word (16-bit) mode MBM29DL800TA/BA devices. When this driven high, devices operate word (16-bit) mode. data read programmed
DQ15. When this driven low, devices operate byte (8-bit) mode. Under this mode, DQ15/A-1 becomes lowest address DQ14 bits tri-stated. However, command cycle always 8-bit operation hence commands written DQ15 bits ignored. Refer "(10) Timing Diagram Word Mode Configuration" "(11) Timing Diagram Byte Mode Configuration" "(12) BYTE Timing Diagram Write Operations" sTIMING DIAGRAM timing diagram.
Data Protection
MBM29DL800TA/BA designed offer protection against accidental erasure programming caused spurious system level signals that exist during power transitions. During power devices automatically reset internal state machine Read mode. Also, with control register architecture, alteration memory contents only occurs after successful completion specific multi-bus cycle command sequences. devices also incorporate several features prevent inadvertent write cycles resulting form power-up power-down transitions system noise.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than (typically VLKO, command register disabled internal program/erase circuits disabled. Under this condition device will reset read mode. Subsequent writes will ignored until level greater than VLKO. users responsibility ensure that control pins logically correct prevent unintentional writes when above Embedded Erase Algorithm interrupted, there possibility that erasing sector(s) cannot used.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) will initiate write cycle.
Logical Inhibit
Writing inhibited holding VIL, VIH, VIH. initiate write cycle must logical zero while logical one.
Power-Up Write Inhibit
Power-up devices with will accept commands rising edge internal state machine automatically reset read mode power-up.
Sector Protection
Device user able protect each sector individually store protect data. Protection circuit voids both program erase commands that addressed protected sectors. commands program erase addressed protected sector ignored (see "Sector Protection" FUNCTIONAL DESCRIPTION)
ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with respect Ground pins except RESET RESET Power Supply Voltage*1 Voltage defined basis Minimum voltage input pins -0.5 During voltage transitions, input pins undershoot -2.0 periods Maximum voltage input pins +0.5 During voltage transitions, input pins overshoot +2.0 periods Minimum input voltage RESET pins -0.5 During voltage transitions, RESET pins undershoot -2.0 periods Voltage difference between input supply voltage (VIN-VCC) does exceed +9.0 Maximum input voltage RESET pins +13.0 which overshoot +14.0 periods WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings. Symbol Tstg VIN, VOUT Rating -0.5 -0.5 -0.5 +125 VCC+0.5 +13.0 +5.5 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature Power Supply Voltages* Voltage defined basis Note: Operating ranges define those limits between which functionality devices guaranteed. WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representatives beforehand. Symbol Part Value +3.0 +2.7 +3.6 +3.6 Unit
MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
+0.6 -0.5 -2.0
Figure
Maximum Undershoot Waveform
+2.0 +0.5 +2.0
Figure
Maximum Overshoot Waveform
+14.0 +13.0 +0.5
Note This waveform applied RESET.
Figure
Maximum Overshoot Waveform
CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current Symbol ILIT Conditions VCC, VOUT VCC, RESET 12.5 VIL, VIH, f=10 Active Current ICC1 VIL, VIH, Active Current Current (Standby) Current (Standby, Reset) Current (Automatic Sleep Mode) Active Current (Read-While-Program) Active Current (Read-While-Erase) Active Current (Erase-Suspend-Program) Input Voltage Input High Voltage Voltage Autoselect Sector Protection (A9, RESET) Output Voltage Output High Voltage Lock-Out Voltage ICC2 ICC3 ICC4 ICC5 VIL, Max, RESET Max, RESET Max, RESET VIL, VIL, VIL, -2.0 -100 Byte Word Byte Word Byte Word Byte Word Value -1.0 -1.0 -0.5 11.5 VCC-0.4 +1.0 +1.0 VCC+0.3 12.5 0.45 Unit
ICC6 ICC7 ICC8 VOH1 VOH2 VLKO
current listed includes both operating current frequency dependent component. active while Embedded Algorithm (program erase) progress. This timing only Sector Protection operation Autoselect mode. Applicable only applying. Automatic sleep mode enables power mode when address remain stable Embedded Algorithm (program erase) progress. MHz)
CHARACTERISTICS
Read Only Operations Characteristics Parameter Read Cycle Time Address Output Delay Chip Enable Output Delay Output Enable Output Delay Chip Enable Output High-Z Output Enable Output High-Z Output Hold Time From Addresses, Whichever Occurs First RESET Read Mode BYTE Switching High tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Symbols JEDEC
Standard
Value (Note) Test Setup Unit
tACC tREADY tELFL tELFH
Note: Test Conditions: Output Load: 1TTL gate (MBM29DL800TA/BA-70) 1TTL gate (MBM29DL800TA/BA-90 Input rise fall times: Input pulse levels: Timing measurement reference level Input: Output:1.5
IN3064 Equivalent Device Under Test Diodes IN3064 Equivalent
Notes: including capacitance (MBM29DL800TA/BA-70) including capacitance (MBM29DL800TA/BA-90)
Figure
Test Conditions
Write/Erase/Program Operations Parameter Write Cycle Time Address Setup Time Address Setup Time During Toggle Polling Address Hold Time Address Hold Time from High During Toggle Polling Data Setup Time Data Hold Time Output Enable Hold Time Read Toggle Data Polling tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL Byte Word tWHWH1 tWHWH2 Symbol
JEDEC Standard
Value
Unit
tASO tAHT tOEH tCEPH tOEPH tGHWL tGHEL tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVLHT tWPP tOESP
High During Toggle Polling High During Toggle Polling Read Recover Time Before Write Read Recover Time Before Write Setup Time Setup Time Hold Time Hold Time Write Pulse Width Pulse Width Write Pulse Width High Pulse Width High Programming Operation Sector Erase Operation Setup Time Rise Time Voltage Transition Time Write Pulse Width
Setup Time Active
(Continued)
(Continued)
Parameter Setup Time Active Recover Time From RY/BY RESET Pulse Width RESET Hold Time Before Read BYTE Switching Output High-Z BYTE Switching High Output Active Program/Erase Valid RY/BY Delay
Delay Time from Embedded Output Enable
Symbol
JEDEC Standard
Value
Unit
tCSP tFLQZ tFHQV tBUSY tEOE
This does include preprogramming time. This timing Sector Protection operation.
ERASE PROGRAMMING PERFORMANCE
Limits Parameter Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time Program/Erase Cycle 100,000 cycle Excludes programming time prior erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
TSOP(1) CAPACITANCE
Value Parameter Input Capacitance Output Capacitance Control Capacitance Symbol COUT CIN2 Test Setup VOUT Unit
Notes Test conditions +25°C, DQ15/A-1 capacitance stipulated output capacitance.
FBGA CAPACITANCE
Value Parameter Input Capacitance Output Capacitance Control Capacitance Symbol COUT CIN2 Test Setup VOUT Unit
Notes Test conditions +25°C, DQ15/A-1 capacitance stipulated output capacitance.
TIMING DIAGRAM
Switching Waveforms
WAVEFORM
INPUTS Must Steady Change from Change from Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing State Unknown Center Line HighImpedance "Off" State
Waveforms Read Operations
Address
Address Stable
tACC
tOEH
Outputs
High-Z
High-Z Output Valid
Waveforms Hardware Reset/Read Operations
Address
tACC
Address Stable
RESET
Outputs
High-Z
Output Valid
Alternate Controlled Program Operations
Cycle Address
555h
Data Polling
tGHWL tWPH tWHWH1
DOUT DOUT
Data
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. addresses differ from mode.
Alternate Controlled Program Operations
Cycle
Data Polling
Address
555h
tGHEL tCPH tWHWH1
Data
DOUT
Notes:
address memory location programmed. data programmed byte address. output complement data written device. DOUT output data written device. Figure indicates last cycles four cycle sequence. These waveforms mode. (The addresses differ from mode.)
Waveforms Chip/Sector Erase Operations
Address
555h
2AAh
555h
555h
2AAh
tGHWL tWPH
chip Erase 10h/
Data
tVCS
sector address Sector Erase. Addresses 555h (Word) Chip Erase. Note These waveforms mode. addresses differ from mode.
Waveforms Data Polling during Embedded Algorithm Operations
tOEH
Data Valid Data High-Z
tWHWH1
Data tBUSY
Output Flag tEOE
Valid Data
High-Z
RY/BY
Valid Data (The device completed Embedded operation).
Waveforms Toggle during Embedded Algorithm Operations
Address
tAHT tASO tAHT
tCEPH
tOEH
tOEPH tOEH
6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
Stop
Toggling
Output Valid
RY/BY
stops toggling (The device completed Embedded operation).
RY/BY Timing Diagram during Program/Erase Operations
Rising edge last pulse
Entire programming erase operations
RY/BY
tBUSY
RESET/RY/BY Timing Diagram
RESET
RY/BY
tREADY
(10) Timing Diagram Word Mode Configuration
BYTE
DQ14
tELFH
Data Output (DQ7 DQ0) tFHQV
Data Output (DQ14 DQ0)
DQ15 /A-1
DQ15
(11) Timing Diagram Byte Mode Configuration
BYTE
tELFL
DQ14
Data Output (DQ14 DQ0)
Data Output (DQ7 DQ0)
tACC
DQ15 /A-1
DQ15 tFLQZ
(12) BYTE Timing Diagram Write Operations
Falling edge last signal
BYTE
Input Valid
(13) Waveforms Sector Protection
A18, A17, A15, A13,
SPAX
SPAY
tVLHT
tVLHT tWPP tVLHT tVLHT
tOESP
tCSP
Data
tVCS
SPAX:Sector Address initial sector SPAY: Sector Address next sector Note byte mode.
(14) Temporary Sector Unprotection Timing Diagram
tVCS RESET
tVIDR tVLHT
tVLHT RY/BY
Program Erase Command Sequence
tVLHT
Unprotection period
(15) Bank-to-bank Read/Write Timing Diagram
Read
Command
Read
Command
Read
Read
Address
(555H)
tACC
(PA)
tAHT
(PA)
tCEPH
tGHWL tOEH
Note
Valid read from erase-suspendedValid sector. Valid Valid
Output Intput (A0H) Output Intput (PD)
Valid Output
Status
Note This example Read Bank Embedded Algorithm (program) Bank BA1: Address corresponding Bank BA2: Address corresponding Bank
(16)
Enter Embedded Erasing
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ2* Toggle with
read from erase-suspended sector.
(17) Extended Sector Protection Timing Diagram
tVCS
RESET tVIDR Address
tVLHT
SPAX
SPAX
SPAY
TIME-OUT
Data
SPAX Sector Address protected SPAY Next Sector Address protected TIME-OUT Time-Out window (Min)
FLOW CHART
Embedded ProgramAlgorithm EMBEDDED ALGORITHM
Start
Write Program Command Sequence (See below) Embedded Program Algorithm program
Data Polling
Verify Data
Increment Address
Last Address
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
Notes sequence applied mode. addresses differ from mode.
Embedded EraseAlgorithm EMBEDDED ALGORITHM
Start
Write Erase Command Sequece (See below)
Data Polling
Data Erasure Completed
Embedded Erase Algorithm program
Chip Erase Command Sequence (Address/Command): 555h/AAh
Individual Sector/Multiple Sector Erase Command Sequence (Address/Command): 555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Additional sector erase commands optional.
Sector Address/30h
Notes sequence applied mode. addresses differ from mode.
Data Polling Algorithm
Start
Read Byte (DQ7 DQ0) Addr.
Data? Read Byte (DQ7 DQ0) Addr.
Byte address programming sector addresses within sector being erased during sector erase multiple sector erases operation sector addresses within sector being protected during chip erase operation
Data? Fail
Pass
rechecked even because change simultaneously with DQ5.
Toggle Algorithm
Start
Read Addr. Read Addr.
Bank address being executed Embedded Algorithm.
Toggle Read Twice Addr.
Toggle Program/Erase Operation Complete. Write Reset Command
Program/Erase Operation Complete
Read toggle twice determine whether toggling. Recheck toggle because stop toggling changes "1".
Sector Protection Algorithm
Start
Setup Sector Addr. (A18, A17, A16, A15, A14, A13, A12)
PLSCNT
VID, VID, VIL, RESET VIL, Activate Pulse
Increment PLSCNT
Time
VIH, should remain VID)
PLSCNT Remove from Write Reset Command
Read from Sector Addr. SPA, VIH,
Data 01h? Protect Another Sector?
Device Failed
Remove from Write Reset Command
Sector Protection Completed
byte mode.
Temporary Sector Unprotection Algorithm
Start
RESET
Perform Erase Program Operations
RESET
Temporary Sector Unprotection Completed
protected sectors unprotected. previously protected sectors protected once again.
Extended Sector Protection Algorithm
Start
RESET
Wait
Device Operating Temporary Sector Unprotection Mode
Extended Sector Protection Entry? Setup Sector Protection Write XXXh/60h
PLSCNT
Sector Protection Write SPA/60h VIL, VIH, VIL)
Increment PLSCNT
Time
Verify Sector Protection Write SPA/40h VIL, VIH, VIL)
Setup Next Sector Address
Read from Sector Address VIL, VIH, VIL) PLSCNT Remove from RESET Write Reset Command Data 01h? Protection Other Sector Remove from RESET Write Reset Command
Device Failed
Sector Protection Completed
Embedded ProgramAlgorithm Fast Mode FAST MODE ALGORITHM
Start
555h/AAh
2AAh/55h
Fast Mode
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data?
Fast Program
Increment Address
Last Address Programming Completed
(BA) XXXh/90h Reset Fast Mode XXXh/F0h
Notes sequence applied mode. addresses differ from mode.
ORDERING INFORMATION
Part MBM29DL800TA-70PFTN MBM29DL800TA-90PFTN MBM29DL800TA-70PFTR MBM29DL800TA-90PFTR MBM29DL800TA-70PBT MBM29DL800TA-90PBT MBM29DL800BA-70PFTN MBM29DL800BA-90PFTN MBM29DL800BA-70PFTR MBM29DL800BA-90PFTR MBM29DL800BA-70PBT MBM29DL800BA-90PBT Package 48-pin plastic TSOP (FPT-48P-M19) (Normal Bend) 48-pin plastic TSOP (FPT-48P-M20) (Reverse Bend) 48-pin plastic FBGA (BGA-48P-M12) 48-pin plastic TSOP (FPT-48P-M19) (Normal Bend) 48-pin plastic TSOP (FPT-48P-M20) (Reverse Bend) 48-pin plastic FBGA (BGA-48P-M12) Access Time Bottom Sector Sector Sector Architecture
MBM29DL800
PFTN
PACKAGE TYPE PFTN 48-Pin Thin Small Outline Package (TSOP) Normal Bend PFTR 48-Pin Thin Small Outline Package (TSOP) Reverse Bend PBT-SF2 =48-Ball Fine Pitch Ball Grid Array Package (FBGA:BGA-48P-M12) SPEED OPTION Product Selector Guide. Device Revision BOOT CODE SECTOR ARCHITECTURE sector Bottom sector
DEVICE NUMBER/DESCRIPTION MBM29DL800 8Mega-bit 8-Bit 16-Bit) CMOS Flash Memory V-only Read, Program, Erase
PACKAGE DIMENSIONS
48-pin plastic TSOP (FPT-48P-M19)
LEAD
Note1 Values include resin protrusion. Resin protrusion gate protrusion +0.15 (.006) (each side) Note2 Pins width pins thickness include plating thickness.
INDEX
Details part
0.25(.010)
0~8°
0.60±0.15 (.024±.006)
20.00±0.20 (.787±.008) 18.40±0.20 (.724±.008)
12.00±0.20 (.472±.008)
1.10 -0.05
+0.10
.043 -.002 (Mounting height)
0.10±0.05 (.004±.002) (Stand height)
0.22±0.05 (.009±.002)
+.004
0.10(.004)
0.50(.020)
0.17 -0.08 .007 -.003
+0.03 +.001
0.10(.004)
2002 FUJITSU LIMITED F48029S-c-5-6
Dimensions (inches) 48-pin plastic TSOP (FPT-48P-M20)
LEAD
Note1 Values include resin protrusion. Resin protrusion gate protrusion +0.15 (.006) (each side) Note2 Pins width pins thickness include plating thickness.
INDEX
Details part 0.60±0.15 (.024±.006)
0~8° 0.25(.010)
0.17 -0.08
+0.03 +.001
0.10(.004)
.007 -.003 0.50(.020)
0.22±0.05 (.009±.002)
0.10(.004)
0.10±0.05 (.004±.002) (Stand height)
18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008)
1.10 -0.05
+0.10 +.004
.043 -.002 (Mounting height) 12.00±0.20(.472±.008)
2002 FUJITSU LIMITED F48030S-c-5-6
Dimensions (inches) (Continued)
(Continued) 48-pin plastic FBGA (BGA-48P-M12)
9.00±0.20(.354±.008) 1.05 -0.10 .041 -.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off)
+0.15 +.006
5.60(.220) 0.80(.031)TYP
INDEX 6.00±0.20 (.236±.008) 4.00(.157)
C0.25(.010)
0.10(.004)
2001 FUJITSU LIMITED B48012S-c-3-3
Dimensions (inches)
FUJITSU LIMITED
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated accompanying fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), requiring extremely high reliability (i.e., submersible repeater artificial satellite). Please note that Fujitsu will liable against and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
F0211 FUJITSU LIMITED Printed Japan

FLASH MEMORY 512K FEATURES Single read, program, erase

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