Monolithic 12-Bit Quad AD664 CONFIGURATIONS 44-Pin Package A
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FEATURES Four Complete Voltage Output DACs Data Register Readback Feature "Reset Zero" Override Multiplying Operation Double-Buffered Latches Surface Mount Packages MIL-STD-883 Compliant Versions Available APPLICATIONS Automatic Test Equipment Robotics Process Control Disk Drives Instrumentation Avionics PRODUCT DESCRIPTION
Monolithic 12-Bit Quad AD664
CONFIGURATIONS 44-Pin Package
AD664 four complete 12-bit, voltage-output DACs monolithic chip. Each double-buffered input latch structure data readback function. read write operations occur through single microprocessor-compatible port. port accommodates 12-bit parallel words allowing simple interfacing with wide variety microprocessors. reset zero control provided allow user simultaneously reset outputs zero, regardless contents input latch. DACs placed transparent mode allowing immediate response outputs input data. analog portion AD664 consists four cells, four output amplifiers, control amplifier switches. Each cell inverting R-2R type. output current from each switched on-board application resistors output amplifier. output range each cell programmed through digital port unipolar bipolar range, with gain times reference voltage. DACs operated from single external reference. functional completeness AD664 results from combination Analog Devices' BiMOS process, laser-trimmed thin-film resistors double-level metal interconnects.
PRODUCT HIGHLIGHTS
28-Pin Package
asynchronous RESET control returns outputs zero volts. DAC-to-DAC matching performance specified tested. Linearity error specified room temperature maximum grades. performance guaranteed monotonic over full operating temperature range. Readback buffers have tristate outputs. Multiplying-mode operation allows with fixed variable, positive negative external references. AD664 available versions compliant with MILSTD-883. Refer Analog Devices Military Products Databook current AD664/883B data sheet detailed specifications.
AD664 provides four voltage-output DACs chip offering highest density 12-bit function available. output range each fully independently programmable. Readback capability allows verification contents internal data registers. REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD664-SPECIFICATIONS unless otherwise noted)
Model RESOLUTION ANALOG OUTPUT Voltage Range1 Versions Versions Output Current Load Resistance Load Capacitance Short-Circuit Current ACCURACY Gain Error Unipolar Offset Bipolar Zero3 Linearity Error4 Linearity TMIN TMAX Differential Linearity Differential Linearity TMIN TMAX Gain Error Drift Unipolar Mode Bipolar Mode Bipolar Mode Unipolar Offset Drift Unipolar Mode Bipolar Zero Drift Bipolar Mode Bipolar Mode REFERENCE INPUT Input Resistance Voltage Range6 POWER REOUIREMENTS VIH, VIH, /VEE Total Power ANALOG GROUND CURRENT7 MATCHING PERFORMANCE Gain8 Offset9 Bipolar Zero10 Linearity11 CROSSTALK Analog Digital DYNAMIC PERFORMANCE Settling Time OffBitsOn, GAIN VREF Settling Time -10VREF GAIN Bits Glitch Impulse MULTIPLYING MODE PERFORMANCE Reference Feedthrough Reference Bandwidth POWER SUPPLY GAIN SENSITIVITY 11.4 VVCC16.5 -16.5 VVEE-11.4 VVLL5.5
(VLL VREF
JN/JP/AD/AJ/SD KN/KP/BD/BJ/BE/TD/TE
Units Bits
2.02
2.02 2.02
Volts Volts
-3/4 -3/4 Monotonic Temperatures 2.02 11.4 -600 -1.5 2.02 16.5 +600
-1/2 -3/4 -1/2 Monotonic Temperatures
FSR5/°C FSR/°C FSR/°C FSR/°C FSR/°C FSR/°C Volts Volts Volts
nV-sec
ppm/% ppm/% ppm/%
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AD664
Model DIGITAL INPUTS Data Inputs DGND CS/DS0/DS1/RST/RD/LS MS/TR12 DGND QS0/QSl/QS2 DGND DIGITAL OUTPUTS Sink Source TEMPERATURE RANGE JN/JP/KN/KP AD/AJ/BD/BJ/BE SD/TD/TE JN/JP/AD/AJ/SD KN/KP/BD/BJ/BE/TD/TE Units
Volts Volts Volts Volts
+125
NOTES minimum power supply ±12.0 required operation. minimum power supply ±11.4 required operation. Voltage exeeed maximum. Bipolar zero error difference from ideal output volts) actual output voltage with code applied inputs. Linearity error defined maximum deviation actual output from ideal output straight line drawn from F.S. LSB). means Full-Scale Range range range. minimum power supply 12.0 required reference voltage. Analog Ground Current input code dependent. Gain error matching largest difference gain error between DACs package. Offset error matching largest difference offset error between DACs package. Bipolar zero error matching largest difference bipolar zero error between DACs package. Linearity error matching difference worst ease linearity error between DACs package. 44-pin versions only. *Specifications same JN/JP/AD/AJ/SD. Specifications subject change without notice. Specifications shown boldface tested production units final electrical test. Results from those tests used calculate outgoing quality levels. specifications guaranteed, although only those shown boldface tested production units.
ABSOLUTE MAXIMUM RATINGS*
DGND DGND DGND Soldering +300°C, Power Dissipation 1000 AGND DGND Reference Input VREF VREF (VCC
Digital Inputs -0.3 Analog Outputs Indefinite Shorts VCC, VLL,
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Unused devices must stored conductive foam shunts. protective foam should discharged destination socket before devices removed.
WARNING!
SENSITIVE DEVICE
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AD664
Figure 44-Pin Block Diagram
FUNCTIONAL DESCRIPTION
AD664 combines four complete 12-bit voltage output converters with fast, flexible digital input/output port monolithic chip. available forms, 44-pin version shown Figure 28-pin version shown Figure
44-Pin Versions
tions. This register also read back check contents. RESET-TO-ZERO feature allows DACs reset volts strobing single pin.
Each offers flexibility, accuracy good dynamic performance. R-2R structure fabricated from thin-film resistors which laser-trimmed achieve linearity guaranteed monotonicity. output amplifier combines best features bipolar devices achieve good dynamic performance offset. Settling time under each output drive load. Short-circuit protection allows indefinite shorts VLL, VCC, GND. output span resistor pins available separately. This feature allows user insert current-boosting elements increase drive capability system, well overcome parasitics. Digital circuitry implemented CMOS logic. fast, power, digital interface allows AD664 interfaced with most microprocessors. Through this interface, wide variety features each chip accessed. example, input data each programmed 16-bit words. double-buffered input structure this latch allows four DACs updated simultaneously. readback feature allows internal registers read back through same digital port, either 12-bit words. When disabled, readback drivers placed high impedance (tristate) mode. TRANSPARENT mode allows input data pass straight through both ranks input registers appear with minimum delay. placed transparent mode time, four made transparent once. MODE SELECT feature allows output range mode DACs selected data inputs. internal mode select register stores selec-
Figure 28-Pin Block Diagram
28-Pin Versions
28-pin versions dedicated versions 44-pin AD664. Each offers reduced features from those offered 44-pin version. This accommodates reduced number package pins available. Data written read with 12-bit words only. Output range mode select functions also available 28-pin versions. alternative, users specify either (unipolar, VREF) models (bipolar, -VREF VREF) models depending application requirements. Finally, transparent mode available 28-pin versions.
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AD664
Table Transfer Functions
Mode Gain 000000000000 100000000000 VREF/2 111111111111 VREF 000000000000 100000000000 VREF 111111111111 VREF
Mode 000000000000 VREF/2 100000000000 111111111111 VREF/2 000000000000 VREF 100000000000 111111111111 +VREF
Gain
DEFINITIONS SPECIFICATIONS LINEARITY ERROR: Analog Devices defines linearity error maximum deviation actual, adjusted output from ideal analog output straight line drawn from LSB) combination. This also referred relative accuracy. AD664 laser-trimmed typically maintain linearity errors less than LSB. MONOTONICITY: said monotonic output either increases remains constant increasing digital inputs such that output will always nondecreasing function input. versions AD664 monotonic over their full operating temperature range. DIFFERENTIAL LINEARITY: Monotonic behavior requires that differential linearity error less than both 25°C well over temperature range interest. Differential nonlinearity measure variation analog value, normalized full scale, associated with change digital input code. example, full-scale output, change digital input code should result 2.44 change analog output (VREF Gain 1/4096 2.44 mV). actual use, however, change input code results change only 0.61 (1/4 LSB) analog output, differential nonlinearity error would -1.83 -3/4 LSB. GAIN ERROR: gain error measure difference between output span ideal actual device.
UNIPOLAR OFFSET ERROR: Unipolar offset error difference between ideal output actual output when input loaded with "0s" MODE unipolar. BIPOLAR ZERO ERROR: Bipolar zero error difference between ideal output actual output when input code loaded with rest bits MODE bipolar. SETTLING TIME: Settling time time required output reach remain within specified error band about final value, measured from digital input transition. CROSSTALK: Crosstalk change output caused change more other outputs. capacitive thermal coupling between outputs. REFERENCE FEEDTHROUGH: portion reference signal that appears output when input bits low. Feedthrough capacitive coupling between reference input output. specified decibels particular frequency. REFERENCE BANDWIDTH: frequency reference input signal which amplitude full-scale output response falls from ideal response. GLITCH IMPULSE: Glitch impulse undesired output voltage transient caused asymmetrical switching times switches DAC. These transients specified their area nV-sec) voltage time characteristic.
CONFIGURATIONS 28-Pin Package 44-Pin Package
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AD664
ANALOG CIRCUIT CONSIDERATIONS Grounding Recommendations
greater than both external reference inverted external reference.
Output Considerations
AD664 pins, designated ANALOG DIGITAL ground. analog ground "high quality" ground reference point device. unique internal design resulted analog ground current. This greatly simplifies management ground current associated induced voltage drops. analog ground should connected analog ground point system. external reference external loads should also returned analog ground. digital ground should connected digital ground point circuit. This returns current from logic portions AD664 circuitry ground. Analog digital grounds should connected point system. there possibility that this connection broken otherwise disconnected, then diodes should connected between analog digital ground pins AD664 limit maximum ground voltage difference.
Power Supplies Decoupling
Each output source sink current external load. Short-circuit protection limits load current maximum load current Load capacitance accommodated with effect stability. Should application require additional output current, current boosting element inserted into output loop with sacrifice accuracy. Figure details this method.
AD664 requires three power supplies proper operation. powers logic portions device requires volts. power remaining portions circuitry require respectively. must also minimum volts greater then maximum reference output voltages anticipated. Decoupling capacitors should used power supply pins. Good engineering practice dictates that bypass capacitors located near possible package pins. should bypassed digital ground. should decoupled analog ground.
Driving Reference Input
Figure Current-Boosting Scheme
AD664 output voltage settling time maximum. Figure shows output voltage settling time with fixed reference, gain bits switched from
reference input AD664 have impedance Therefore, external reference voltage must able source load current. Suitable choices include AD586, AD587 8.192 AD689. architecture AD664 derives inverted version reference voltage some portions internal circuitry. This means that power supplies must least
Figure Settling Time; Bits Switched from
Alternately, Figure shows settling characteristics when reference switched input bits remain fixed. this case, bits "on," gain reference switched from
Figure Recommended Circuit Schematic
Figure Settling Time; Input Bits Fixed, Reference Switched
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Multiplying Mode Performance
Figure illustrates typical open-loop gain phase performance output amplifiers AD664.
GAIN
operating mode data. registers double-buffered allow simultaneous updating outputs. Register data read back verify respective contents. digital port also allows transparent operation. Data from input pins sent directly through both ranks latches DAC.
PHASE
100k FREQUENCY
Figure Gain Phase Performance AD664 Outputs
Crosstalk
PHASE MARGIN Degrees
GAIN
Figure Typical Output Noise
Crosstalk spurious signal output caused change output more other DACs. Crosstalk induced capacitive, thermal load current induced feedthrough. Figure shows typical crosstalk. output volts. outputs switch loads from first disturbance output caused digital feedthrough from input data lows. second disturbance caused analog feedthrough from other outputs.
Partial address decoding performed DS0, DS1, QS0, address bits. QS0, allow 44-pin versions AD664 addressed 4-bit nibble, 8-bit byte 12-bit parallel words. provides simple method reset output voltages zero. advantages speed software overhead.
INPUT DATA
general, types data will input registers AD664, input code data mode select data. Input code data sets inputs while mode select data sets gain range each DAC. versatile port AD664 allows many different types data input schemes. example, input code just DACs loaded output updated. input codes four DACs written, outputs updated. same applies MODE SELECTION. mode just many DACs rewritten user choose immediately update outputs wait until later time transfer mode information outputs. user also write both input code mode information into their respective first ranks then update second ranks once.
Figure Output Crosstalk
Output Noise
Wideband output noise shown Figure This measurement made with noise bandwidth, gain bits total noise approximately fifth visual peak-to-peak noise.
DIGITAL INTERFACE
Table shows, AD664 makes wide variety operating modes available user. These modes accessed programmed through high speed digital port quad DAC. On-board registers program store input codes
Finally, transparent operation allows data transferred from inputs outputs using single control line. This feature useful, example, situation where DACs used converter. register could connected directly using transparent mode operation. Another this feature would during system calibration where endpoints transfer function each would measured. example, full-scale voltages each were measured, then making four DACs transparent putting "1s" input port, four DACs would full-scale. This requires less software overhead than loading each register individually.
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Table AD664 Digital Truth Table
Function Load Rank (data) DACA DACB DACC DACD Load Rank (data) Readback Rank (data) Reset Transparent1 DACs DACA DACB DACC DACD Mode Select1, Rank Rank Readback Mode1 Update Rank Mode
DS1, Select
QS0, Select Quad Select Quad Select Quad Select Quad Select Quad
NOTES Don't Care. 44-pin versions only. Allow AD664 addressed 4-bit nibble, 8-bit byte 12-bit parallel words. write occurs.
following sections detail timing requirements various data loading schemes. timing specifications shown assume
Load Update Output
this first example, object simply change output four DACs AD664 chip. procedure select address bits that indicate programmed, pull LATCH SELECT (LS) low, pull CHIP SELECT (CS) low, release then release When goes low, data enters first rank input latch. soon goes high, data transferred into second rank produces output voltage. During this transfer, should held high.
Preloading First Rank
Figure Update Output Single
SYMBOL tLS* (ns) TMIN TMAX (ns)
this case, object load data into first rank DACs output. previous case, address data inputs placed appropriate pins. then brought then asserted. Note that this situation, however, goes high before goes high. input data prevented from getting second rank affecting output voltage.
*FOR WIDTH MUST INCREASED SAME AMOUNT THAT GREATER THAN
Figure Update Output Single Timing
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Figure Preload First Rank Registers
Load Update Multiple Outputs
Figure 10a. Preload First Rank
SYMBOL (ns) TMIN TMAX (ns)
following examples demonstrate ways update outputs. first method involves doing data transfers during long period. Note that this case, shown Figure returns high before goes high. Data hold time, relative address change, This updates outputs DACs simultaneously.
Figure 10b. Preload First Rank Timing
This allows user "preload" data strobe into output latch some future time. user could this reproducing sequence signals illustrated next section.
Update Second Rank
Figure Update Outputs
Assuming that input code previously been placed into first rank input latches, user update output simply pulling while keeping high. Address data needed this case. reality, second ranks being updated this procedure, only those which receive data different from that already there would manifest change. Updating second rank does change contents first rank.
second method involves doing assertion (low) toggle separately each DAC. basically series preload operations (Figure 10). this case, illustrated Figure signals shown. One, labeled goes high before returns high. This transfers "new" input word outputs sequentially. second signal, labeled Alternate stays until returns high. Using this sequence loads first ranks with each "new" input word doesn't update outputs. then update outputs simultaneously would require signals illustrated Figure
Figure Update Second Rank
same options that exist individual input loading also exist multiple input loading. That user choose update first second ranks registers preload first ranks then update them future time.
Preload Multiple First Rank Registers
Figure Load Update Multiple DACs
SELECTING GAIN RANGE MODES (44-PIN
first ranks input registers preloaded VERSIONS) with input data without disturbing second rank data. AD664's mode select feature allows user configure This done transferring data into first rank bringgain ranges output modes each four DACs. while low. must return high before On-board switches take place eight external relays This prevents data from first rank from getting into that would normally required accomplish this task. second rank. simple second rank update cycle shown switches programmed mode select word entered Figure would move "preloaded" information data port. mode select word eight-bits wide DACs. REV.
AD664
occupies topmost eight bits input word. last four bits input word "don't cares." Figure shows format MODE SELECT word. first four bits determine gain range DAC. When gain output spans voltage times reference. When gain output spans voltage times reference. next four bits determine mode DAC. When UNIPOLAR, output goes from REF. When BIPOLAR mode selected, output goes from -REF/2 REF/2 -REF REF.
Preloading Mode Select Register
Mode data written into first rank mode select latch without changing modes currently being used. This feature useful when user wants preload mode information anticipation strobing that future time. Figure illustrates correct sequence timing control signals accomplish this task. This allows user "preload" data strobe into output latch some future time. user could this reproducing sequence signals illustrated Figures 17d.
Figure Mode Select Word Format
Load Update Mode
this next example, object load mode information DACs into first rank latches then immediately update second rank. This done putting mode information (8-bit word length) onto databus. Then pulled low. Following that, pulled low. This loads mode information into first rank latches. then brought high. This action updates second rank latches (and, therefore, outputs). load cycle ends when brought high. reality, this load cycle really updates modes DACs, effect only change modes those DACs whose mode select information actually changed.
Figure 17a. Preload Mode Select Register
Figure 17b. Preload Mode Select Register Timing
DATA INPUT/OUTPUT BITS ADDRESS QS0,QS1,QS2 DS0,DS1
Figure 17c. Update Second Rank Mode Select Latch
SYMBOL (ns) TMIN TMAX (ns)
Figure 16a. Load Update Mode
(ns) TMIN TMAX (ns)
SYMBOL tLS*
Figure 17d. Update Second Rank Mode Select Latch Timing
Transparent Operation (44-Pin Versions)
*FOR WIDTH MUST INCREASED SAME AMOUNT THAT GREATER THAN
Figure 16b. Load Update Mode Timing
Transparent operation allows data from inputs AD664 transferred into registers without intervening step being latched into first rank latches. modes transparent operation exist, "partially transparent" mode "fully transparent" mode. "partially transparent" mode, DACs transparent while remaining three continue data latched into their respective input registers. Both modes require 12-bit wide input word! -10- REV.
AD664
Fully transparent operation thought simultaneous load data from Figure where replacing with causes DACs loaded once. Fully transparent mode achieved asserting lows QS0, QS1, QS2, while keeping high addition Figure illustrates necessary timing relationships. Fully transparent operation will also work with tied (enabled).
OUTPUT DATA
types outputs obtained from internal data registers AD664 chip, mode select input code data. Readback data same forms which entered; 12-bit wide words bits only 28-pin versions).
Data Readback
DATA INPUT/ OUTPUT BITS
DATA VALID
input code readback data obtained setting address (DS0, DS1) Quads (QS0, QS1, QS2) address pins bringing pins low. timing diagram code readback operation appears Figure
Figure 18a. Fully Transparent Mode
SYMBOL tTS* (ns) TMIN TMAX (ns)
Figure 20a. Input Code Readback
25°C (ns) TMIN TMAX (ns)
SYMBOL
*FOR WIDTH MUST INCREASED SAME AMOUNT THAT GREATER THAN
Figure 18b. Fully Transparent Mode Timing
Partially transparent operation thought preloading first rank Figure without requiring additional pulse from Figure partially transparent mode achieved setting QS0, QS1, QS2, while keeping high. address transparent asserted DS1. Figure illustrates necessary timing relationships. Partially transparent operation will also work with tied (enabled).
DATA INPUT/ OUTPUT BITS ADDRESS QS0, QS1, DS0, DS1, DATA VALID
Figure 20b. Input Code Readback Timing
Mode Data Readback Mode data read back similar fashion. setting QS0, QS1, while setting high, mode select word presented port pins. Figure shows timing diagram readback mode select data register.
ADDRESS VALID
Figure 19a. Partially Transparent
SYMBOL 25°C (ns) TMIN TMAX (ns)
Figure 21a. Mode Data Readback
(ns) TMIN TMAX (ns)
SYMBOL
Figure 19b. Partially Transparent Mode Timing
Figure 21b. Mode Readback Timing
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AD664
Output Loads
Readback timing tested with output loads shown Figure
AD664
100nF
AD664
Figure Power-On Reset
obvious from inspection that scheme shown Figure only appropriate systems which otherwise used. Should user wish pin, additional logic gate included combine power-on reset with reset signal.
INTERFACING AD664 MICROPROCESSORS
Figure Output Loads
Asynchronous Reset Operation
AD664 easy interface with wide variety popular microprocessors. Common architectures include processors with dedicated 8-bit data address buses, 8-bit over which data address multiplexed, 8-bit data 16-bit address partially muxed, separate 16-bit data address buses. AD664 addressing accomplished through either memory-mapped techniques. memory-mapped schemes, AD664 appears host microprocessor memory. Standard memory addressing techniques used select AD664. schemes, AD664 treated external device host. Dedicated pins used address AD664.
MC6801 Interface
asynchronous reset signal shown Figure asserted time. minimum pulse width (tRW) required. reset feature designed return outputs volts regardless mode range selected. 44-pin versions, modes reset unipolar span (gain input codes rewritten "0s." Previous code mode information erased.
Figure 23a. Asynchronous Reset Operation
Figures 25a-25d, illustrate various methods that used connect AD664 popular MC6801 microprocessor. each these cases, MC6801 intended configured expanded, nonmultiplexed mode operation. this mode, MC6801 address bytes external memory over 8-bit data (Port 8-bit address (Port buses. Eight general-purpose lines (Port also available. On-board provide program data storage space. Figure 25a, three least significant address bits (P40, P42) employed select appropriate on-chip addresses various input registers AD664. Three lines (P17, P15) used select various operating features AD664. E(nable) combined produce appropriate signal. This addressing scheme leaves five most significant address bits five lines free other tasks system. Figure shows another interface AD664 MC6801. Here we've used least significant address lines select AD664 features registers. This purely memorymapped scheme while illustrated Figure uses some memory-mapping well some dedicated pins. Figure 25b, address lines eight lines remain free other system tasks.
Figure 23b. Asynchronous Reset Operation Timing
28-pin versions AD664, mode remains unchanged, appropriate input code rewritten reset output voltage volts. 44-pin versions, previous input data erased. power-up, AD664 activated either read write modes. While device level this will produce problems, system level may. Analog Devices recommends addition simple power-on reset scheme system where possibility unknown start-up state could problem. simplest version this scheme illustrated Figure
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AD664
Expansion scheme employed Figure results that shown Figure 25c. Here, AD664s connected MC6801, providing total eight 12-bit, software programmable DACs. Again, three least significant bits address used select on-chip registers AD664. well fourth address bit, decoded provide appropriate signals. Four address five lines remain uncommitted. slightly more sophisticated approach system expansion illustrated Figure 25d. Here, 74LS138 (1-of-8 decoder) used address eight AD664s connected MC6801. three least significant address bits used select on-chip register DAC. next three address bits used select appropriate AD664. gate 74LS138 output.
Figure 25a. Simple AD664 MC6801 Interface
Figure 25b. Alternate AD664 MC6801 Interface
Figure 25c. Interfacing AD664s MC6801
REV.
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AD664
schemes Figure illustrate some trade-offs which designer make when configuring system. example, designer lines instead address bits vice versa. This decision influenced other tasks system expansion requirements. He/she also choose implement only subset features available. Perhaps isn't really needed. Tying that input VLOGIC frees another address bit. same consideration applies mode select. these cases shown tied VLOGIC, because MC6801 cannot provide 12-bit-wide input word required transparent mode. situations where transparent operation isn't required, mode select also needed, designer consider specifying version device (either version). Each schemes illustrated Figure operates with MC6801 clock rates including MHz. Similar schemes derived other 8-bit microprocessors microcontrollers such 8051/8086/8088/6502, etc. such scheme developed 8051/AD664 illustrated Figure
8051 Interface
Figure shows AD664 combined with 8051 µcontroller chip. Three LSBs address provide quad select signals. Control signals from Port select various operating modes such readback, mode select reset well providing signal. Read write signals from 8051 decoded provide signal.
Figure 25d. Interfacing Eight AD664s MC6801
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AD664
Interface
Figure illustrates simple interface between AD664. three least significant address bits used select Quad DAC. next address bits used this scheme, 12-bit input word requires load cycles, 8-bit word 4-bit word. Another write
required transfer word words previously written second rank. 12-bit-wide word again requires least read cycles; MSBs four LSBs. page select signal produces strobe address from 300H 31FH.
Figure AD664 8051 Interface
Figure AD664 Interface
*IBM trademark International Business Machines Corp.
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AD664
Table details memory locations addresses used this interface.
Table III. Memory
REGISTER SELECTED Illegal Address Mode Select, Rank Illegal Address Mode Select, Rank Illegal Address Mode Select, Rank Illegal Address Mode Select, Rank Mode Select, Rank
LSBs, Rank MSBs, Rank LSBs, Rank MSBs, Rank LSBs, Rank MSBs, Rank LSBs, Rank MSBs, Rank Rank
Note: Shaded registers readable.
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following Basic routine produces four output voltage ramps from AD664. Line numbers through define hardware addresses first second ranks registers well first second ranks mode select register. Program variables initialized line numbers through 130. Line number writes "0s" first rank and, then, second rank mode select register. Line numbers through calculate output voltages. Finally line numbers through update first, then second ranks input registers. Hardware registers read with "INP" instruction. example, contents register accessed with following mand: Line# INP(DACA).
REM-AD664 LISSAJOUS PATTERNS-REM -ASSIGN HARDWARE ADDRESSES-DACA DACB DACC DACD DAC2ND MODE1 769: MODE2 -INITIALIZE VARIABLES-X 128: CY3= -INITIALIZE MODES GAINS-OUT MODE1,0: MODE2,0 -CALCULATE VARIABLES-X FX*CX FY1*CY1 FY2*CY2 FY3*CY3 THEN 255: GOTO THEN THEN 255: GOTO THEN THEN 255: GOTO THEN THEN 255: GOTO THEN -SEND DATA-OUT DACA,X DACB,Yl DACC,Y2 DACD,Y3 DAC2ND,0 -LOOP BACK-GOTO
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AD664
Simple AD664 MC68000 Interface Figure shows AD664 connected MC68000. this memory-mapped scheme, "left-justified" data written 12-bit input word. Four address bits used perform on-chip selection well various operating features. signal controls function system reset controls RST. This scheme converted write "right-justified'' data connecting data inputs DATA bits through respectively. Other options include controlling QS0, pins with provide write 8-bit input read 8-bit output words.
Figure AD664 MC68000 Interface
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AD664
Figure AD664 "Tester-per-Pin" Architecture
APPLICATIONS AD664 "Tester-Per-Pin" Architecture
some software where previous example would require only single reset strobe signal! Drawing scaling achieved taking advantage AD664's software programmable gain settings. example, size drawing created with gain settings then size drawing created simply resetting gains redrawing object. Conversely, size drawing created with gains reduced size simply changing gains redrawing. same principal applies conversion from size size size size. multiplying capability AD664 provides another scaling option. Changing reference voltage provides proportional change drawing size. Inverting reference voltage would invert drawing. Swapping digital input data from channel channel would rotate drawing degrees.
Figure shows AD664 used single channel digital test system. this scheme, AD664 supplies four individual output voltages. provided VHIGH VLOW inputs AD345 driver I.C. digital output levels. others routed inputs AD96687 dual comparator supply reference levels readback features. This approach replicated give many channels stimulus/ readback tester pins. AD664 particularly appropriate choice large-scale system because power requirements (under ease power supply cooling requirements. Analog ground currents less make ground current management task simpler. DACs driven from same system reference will track over time temperature. Finally, small board area required AD664 (and AD345 AD96687) allows high functional density. Plotters Figure block diagram control section microprocessor-controlled plotter. this conceptual exercise, DACs used X-channel drive used Y-channel drive. Each provides either coarse fine movement control respective channel. This approach offers increased resolution over some other approaches. designer take advantage reset feature AD664 following manner. system designed such that "HOME" position galvanometer, beam, head similar mechanism) results when outputs DACs zero, then system software required home pen. simple reset signal sufficient. Similarly, transparent feature could used same end. code sent DACs same time send home position. course, this would require REV.
Figure Plotter Block Diagram
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AD664
ORDERING GUIDE
Modell AD664JN-UNI AD664JN-BIP AD664JP AD664KN-UNI AD664KN-BIP AD664KP AD664AD-UNI AD664AD-BIP AD664AJ AD664BD-UNI AD664BD-BIP AD664BJ AD664BE AD664SD-UNI AD664SD-BIP AD664TD-UNI AD664TD-BIP
Temperature Range +70°C +70°C +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C
Output Range +VREF -VREF +VREF Programmable +VREF -VREF +VREF Programmable +VREF -VREF +VREF Programmable +VREF -VREF +VREF Programmable Programmable +VREF -VREF +VREF +VREF -VREF +VREF
Gain Error
Linearity Error 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.75
Package Options2 N-28 N-28 P-44A N-28 N-28 P-44A D-28 D-28 J-44 D-28 D-28 J-44 E-44A D-28 D-28 D-28 D-28
NOTES details grade package offerings screened accordance with MIL-STD-883, refer Analog Devices Military Products Databook current AD664/883B data sheet. Ceramic DIP; Leadless Ceramic Chip Carrier; Leaded Chip Carrier; Plastic DIP; Plastic Leaded Chip Carrier.
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
D-28 28-Pin Ceramic Package
N-28 28-Lead Plastic
E-44A 44-Pin Package
J-44 J-Leaded Chip Carrier
P-44A 44-Lead Plastic Leaded Chip Carrier (PLCC)
PRINTED U.S.A.
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