CS4100 CS4100 family adaptive differential pulse code modulators

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CS4100 CS4100 family adaptive differential pulse code modulators

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ADPCM Speech Coders
CS4100
CS4100 family adaptive differential pulse code modulators (ADPCMs) designed provide high performance solutions broad range applications requiring speech compression decompression. These application specific virtual components (ASVCs) support 1024 duplex channels, each which independently selectable encoding decoding, fully compliant with G.726, G.726a, G.727 G.727a standards. CS4100 series ASVCs available both ASIC programmable logic versions that have been handcrafted Amphion optimal performance while minimizing power consumption silicon area.
CODER FEATURES
Fully Compliant with Standards G.721, G.723, G.726, G.726a, G.727 G.727a Supports Large Number Simultaneous Channels: -CS4110: duplex/16 simplex -CS4120: duplex/64 simplex -CS4125: duplex/128 simplex -CS4130: duplex/256 simplex -CS4180: duplex/1024 simplex4 -CS4190: duplex/1024 simplex5 -CS4191: 1024 duplex/2048 simplex Online Configurable Different Compression Rates, µ-law A-law each Encoding Decoding Channel Burst Mode Continuous Operation Ease Integration -Tapeout-Readyfirm-IP targeted netlist -Simple core interface easy integration into larger systems
METRICS SPECIFICATIONS
Logic ~20k Gates Memory: 4.5-288 Kbits Single-Port SRAM1 Kbits Dual-Port SRAM (CS4180) Operating Frequency: 2-49 MHz2 Total Area3 0.32 (CSO4110) 0.41 (CSO4120) 0.51 (CSO4125) 0.73 (CSO4130) (CSO4190TK) (CSO4191TK)
APPLICATIONS
Wireless Telecommunications DECT phones Digital cellular Satellite Communications Wired Telecommunications Videoconferencing Voicemail systems PBXs
Applies CS4110-30 CS4190. Amount memory dependent upon maximum number channels supported. example, duplex channel CSO4110 uses 4.48 Kbits while duplex channel CSO4130 uses 71.68 Kbits. Operating frequency dependent upon maximum number channels supported. example, duplex channel CS4110 runs 2.048 (min.) while duplex channel CS4130 runs 32.768 minimum. Calculation assumes logic density gates/mm2; SRAM density Kbits/mm2 plus area overhead memory peripheral circuitry. Celerity CSC4180AA CSC4180XV versions support duplex/768 simplex channels, Celerity CSC4180X2 version supports duplex/1024 simplex channels. Refers Optima version. Celerity version supports duplex/768 simplex channels (CSC4190XE) duplex/512 simplex channels (CSC4190AA).
CS4100
ADPCM Speech Coders
SPEECH COMPRESSION
digital communications systems, speech coding (compression decompression) used reduce rate speech signal with minimal, noticeable degradation. Without such coding, typical voice channel would require 12-bit precision sampling rate 8000 times second, equivalent data rate Kbits/second. less sensitive errors high volume levels than volumes, logarithmic quantization reduce this data rate Kbits/second with very little degradation; standard techniques European A-law American µ-law PCM, both found CCITT G.711 standard. data rate further reduced through ADPCM, which transmits only error between actual signal adaptively predicted signal. current standards, G.726 G.727, support data rates Kbits/second down little Kbits/second while maintaining "toll quality" speech. CS4100 cores designed provide 1024 duplex channels speech coding respectively, compliant with G.726 G.727 standards well extensions found G.726a G.727a. cores capable processing both burst continuous data streams, with flexibility assign channel encode decode arbitrarily. implementation latency (ranging from clock cycle CS4180 clock cycles CS4110-30) simple core interface allows easy integration into larger systems.
PCM/uniform input/output. Each member Amphion's ADPCM family been tested verified fully compliant using standard test vectors.
LOGARITHMIC PCM/UNIFORM EXPANDER
This block converts input signal from 8-bit µlaw logarithmic format 13-bit A-law 14-bit µ-law uniform signal. This decoding performed according G.711 standard.
LOGARITHMIC PCM/UNIFORM COMPRESSOR
This block converts output signal from either 13-bit A-law 14-bit µ-law uniform format 8-bit µ-law logarithmic signal. This encoding performed according G.711 standard.
ADPCM TRANSCODING ENGINE
primary encoding decoding operations CS4100 ASVC take place within ADPCM transcoding engine. When encoding, difference between uniform input signal with prediction this signal calculated. difference signal then passed adaptive quantizer where binary digits assigned value, following quantization methods stipulated G.726 G.727 standards. result ADPCM signal transmission. current ADPCM signal then used predict next signal estimate. inverse adaptive quantizer output added current input signal estimate determine reconstructed version input signal. This signal output adaptive quantizer then used adaptive predictor determine estimate next input signal, which then back determine next difference signal. When decoding, reverse procedure performed. First, ADPCM signal inversely quantized; then resulting signal added prediction this signal, forming reconstructed signal. inversely quantized signal reconstructed signal used adaptive predictor determine signal estimate next iteration. This reconstructed signal converted signal before passing through additional block needed synchronous coding adjustment. This block prevents cumulative distortion occurring synchronous tandem codings. This when signal converted from ADPCM back ADPCM. idea that when signal converted resulting ADPCM signal same every stage. output signal from this block resulting decoded output codec.
CS4100 FUNCTIONAL DESCRIPTION OPERATION
Amphion ADPCM core consists primary sections: ADPCM transcoding engine, logarithmic PCM/uniform expander, uniform PCM/logarithmic compressor, channel configuration control, coding states storage memory, illustrated Figure core operates input sample time, using clock cycles1 complete encoding decoding. Multichannel coding implemented time-multiplexing basis. input/output channel multiplexing serial to/from parallel conversion circuitry added suit target system required. CS4100 cores have channel addressing modes: flexible mode duplex mode2. duplex mode, half channels encode half decode. flexible mode allows each channel set, reset, individually. Within each these modes core encode data from three types format, specified standard G.711, 5-bit ADPCM format. These 8-bit µ-law Alaw logarithmic PCM, 14-bit µ-law uniform 13-bit Alaw uniform PCM. core also decode data from 5-bit ADPCM format three types format. cores on-line configurable terms compression rate law3 allow on-the-fly selection
clock cycles CS4110-30 cores, clock cycle CS4180 clock cycles CS4190/91. CS4180 operates flexible mode only. Compression rate selected on-the-fly CS4180.
G726
Coding control
Reset Configuration
MODE**
Data input
Logarithmic input
A-law/µ-law
Uniform/ non-uniform
input Expander Uniform input
A-law/ µ-law
Uniform/ non-uniform
Data output
ADPCM Engine
ADPCM output signal Uniform output signal output Compressor
ADPCM input signal
output signal Logarithmic output signal
BSY** ESI** DSI** Status outputs
STE*
Memory
Scan Test Enable only ASIC implementation **Does apply CS4180
Figure Input/Outputs Amphion ADPCM Cores
CODING STATES STORAGE MEMORY
ADPCM algorithm requires from states1 each encoding decoding channel (i.e., bits duplex channel). These states stored memory ADPCM core. reduce width data CS4110-30 enable core complete encoding decoding operation clock cycles, memory organized bits wide. This enables storage channel words, words duplex channel. CS4180 CS4190/91, memory organized bits wide (respectively) words (where number channels), allowing PRODUCT NUMBER
CS4110 CS4120 CS4125 CS4130 CS4180 CS4190 CS4191
compete encoding decoding operations (CS4180) (CS4190/91) clock cycles. Total memory requirements members CS4100 family found Table CS4110-30 ASVCs, core reads coding states from memory first clock cycles clock cycle operation period. last clock cycles, core writes update states back memory. CS4180, memory operations take place clock cycle; CS4190/91, these memory read write operations take clock cycle each clock cycle operation period.
MEMORY REQUIREMENT
4.544 Kbits 18.176 Kbits 36.352 Kbits 72.704 Kbits 209.250 Kbits 288.768 Kbits 577.536 Kbits
Table Coding States Storage Memory
CS4110-30 states channel, CS4180 uses CS4190 4191 282.
CS4100
ADPCM Speech Coders
CONFIGURATION CONTROL
8-bit wide determines compression rate each channel. function each listed Table Note that bits only used duplex mode specify compression rate encoding; note that these bits apply CS4180. input signal G726 used specify whether G.726 G.727 use; when high core operates G.726 standard, indicates G.727. Duplex (that channels split evenly between encode decode) flexible channel addressing modes selected static MODE input. When MODE high, core operates duplex mode when MODE core operates flexible mode. latter case, each channel operate either encoding decoding channel. Note that CS4180 operates flexible mode only.
ENCODING/DECODING OPERATION
Encoding decoding data sample started asserting data strobe signal (DSS). input select signal defines whether core performs encoding decoding operation. When HIGH, core performs encoding input taken. When core will decode input taken. Input signal specifies type encoding input data decoding output data, input specifies channel data belongs described previous sections. ADPCM core requires clock cycles CS4180, CS4190/91 CS4110-30, respectively) complete encoding decoding operation data sample output indicator de-asserted after rising edge 16th) cycle (note: output indicator does apply CS4180, which completes operations single clock cycle). then asserted after rising edge start next operation. encoding decoding timing diagrams depicted Figure Figure respectively, CS4110-30 Figures CS4190/91. CS4180 completes operations single clock cycle.
BITS
DESCRIPTION
Control Values µ-law
CONTROL CHOICE
A-law Even inversion performed A-law inversion inversion performed µ-law bits bits bits bits
Selects either A-law µ-law encoding duplex mode
Controls whether even inversion/all inversion performed A-law/µ-law encoding operations duplex mode Control Values
[5:4]
Controls number bits ADPCM output word when encoding duplex mode Control Values Selects either A-law µ-law decoding duplex mode encoding/decoding flexible mode Controls whether even inversion/all inversion performed A-law/µ-law decoding operations duplex mode encoding/decoding flexible mode Control Values Controls number bits ADPCM output word when encoding duplex mode number bits ADPCM input word ADPCM output word flexible mode.
µ-law
A-law
Even inversion performed A-law inversion inversion performed µ-law
[1:0]
bits
bits
bits
bits
Table Codec Configuration Control Word
CS4110-30 CS4190/91, should noted that: core should configured before encoding decoding operation started. When core busy indicator HIGH, asserting control signal ignored. Other input control signals, namely, EDC, CHN, PCM, G726 latched clock rising edge when HIGH LOW. Input data also latched clock rising edge when HIGH LOW. output data registered. encoding status indicator indicates internal encoding state core. When goes LOW, core completed predictor state update. When returns HIGH, encoding output available. decoding status indicator (DSI) indicates internal decoding state core. When goes LOW, core completed predictor state update. When returns HIGH, decoding output available. When encoding decoding operation completed, signal returns core waits asserted start next operation. Encoding decoding performed order. Output signals encode status indicator (ESI) decode status indicator (DSI) indicate encoding decoding status, respectively. From cycle when codec picks
input data, goes `0'. cycle when encoding/decoding output available, corresponding signal returns `1'. Both signals after reset before first input.
CHANNEL SELECTION
input specifies channel with which input data associated when core performing coding operation with which word applied when core performing channel reset configuration. flexible mode, channel either encoding decoding channel number fully specified CHN.
GLOBAL RESET CONFIGURATION
asynchronous global reset signal, RST, resets channels configures them with same compression rate law; reset activated when asserted. also resets registers core interrupts encoding/decoding operation core performing. Global configuration core performed using input described earlier. reset configuration process starts first rising clock edge after been de-asserted continues either cycles (CS4110-30) cycles (CS4180-90), where number simplex channels (where each duplex channel considered simplex channels). Reset occurs clock cycle CS4180.
PIN/PORT DESCRIPTION
Table gives descriptions input output ports (shown graphically Figure CS4100 ADPCM codecs. Unless otherwise stated, signals active high least significant bit.
S[13:0] ID[4:0] G726 MODE* EW[1:0] CFG[7:0] (Only ASIC)
*Does apply CS4180 Figure ADPCM Core Pinouts.
CHN[3:0] CS4110 CHN[5:0] CS4120 CHN[6:0] CS4125 CHN[7:0] CS4130 CHN[9:0] CS4180/CS4190 CHN[10:0] CS4191
CS4100 ADPCM
I[4:0] SD[13:0] BSY* ESI* DSI*
CS4100
SIGNAL
ADPCM Speech Coders
WIDTH (Bits)
DESCRIPTION
Clock input, rising edge active Global reset configuration symbol, active high, asynchronous clock Synchronous individual channel reset configuration signal, active high Selects between modes operation ADPCM core, duplex flexible modes High: duplex mode Low: flexible mode Input data strobe signal, active high, encoding/decoding started when asserted Selects encode decode operation: High: encode Low: decode Logarithmic uniform selection control signal High: logarithmic Low: uniform Logarithmic uniform input word encoding S[13:0]: µ-law uniform input S[13:1]: A-law uniform input S[7:0]: Logarithmic input ADPCM input word decoding ID[4:3]: ADPCM word, ID[4:2]: ADPCM word, ID[4:1]: ADPCM word, ID[4:0]: ADPCM word, Specifies G.726 G.727 operation High: G.726 standard Low: G.727 standard Specifies number G.727 enhancement bits "00": bits "01": "10": bits "11": bits Specifies channel with which input data associated when core performing coding operation performing channel reset. Width bits CS4110, bits CS4120, bits CS4125 bits CS4130 Duplex mode: channel encoding/decoding, channel number specified CHN[3:1] CS4110 core CHN[5:1] CS4120 core CHN[6:1] CS4125 core CHN[7:1] CS4130 core CHN[9:1] CS4180 CS4190 cores CHN[10:1] CS4191 core (the ignored core) flexible mode, channel coding either encoding decoding channel number fully specified CHN.
MODE (CS4110-30, CS4190/91)
S[13:0]
Kbits/sec Kbits/sec Kbits/sec Kbits/sec
data data data data
rate rate rate rate
G726
EW[1:0]
CHN[3-10:0]
4/6/7/8/ 9/10/11
Table Input Output Descriptions (Continued page
SIGNAL CFG[7:0]
WIDTH (Bits)
DESCRIPTION Channel configuration word defined CFG(7): selects either A-law (CFG(7)=1), µ-law (CFG(7)=0) encoding duplex mode CFG(6): controls whether even inversion performed A-law encoding operations. Even inversion 8-bit input data performed when CFG(6)
CFG(5:4): controls number bits ADPCM output word when encoding duplex mode Encoding compress rates: Kbit/s Kbit/s Kbit/s Kbit/s
CFG(3):
selects either A-law (CFG(3)=1), µ-law (CFG(3)=0) decoding duplex mode encoding/decoding flexible mode controls whether even inversion performed A-law decoding operations duplex mode encoding/decoding flexible mode. Even inversion 8-bit input data 8-bit output data performed when CFG(2)
CFG(2):
CFG(1:0): controls number bits ADPCM output word when encoding duplex mode number bits ADPCM input word ADPCM output word flexible mode Decoding compress rates: Kbit/s Kbit/s Kbit/s Kbit/s ADPCM output word I[4:3]: ADPCM I[4:2]: ADPCM I[4:1]: ADPCM I[4:0]: ADPCM
I[4:0]
output, output, output, output,
Kbit/s Kbit/s Kbit/s Kbit/s
SD[13:0]
Logarithmic uniform output word from decoding SD[13:0]: µ-law uniform output SD[13:1]: A-law uniform output SD[7:0]: Logarithmic output Core busy indicator, active high, ignored when active Encoding status indicator Decoding status indicator Scan test enable (Optima Coresonly) During scan test memory block must bypassed perform test During test, high, bypassing memory. During normal operation core,
BSY* (CS4110-30, CS4190) ESI* (CS4110-30, CS4190) DSI* (CS4110-30, CS4190)
Table Input Output Descriptions
*Does apply CS4180
CS4100
ADPCM Speech Coders
CS4110-30 Timing
G726 clock cycles
Figure Encoding Timing Characteristics CS4110-30
G726
clock cycles
Figure Decoding Timing Characteristics CS4110-30
CS4190/CS4191 Timing
G726
clock cycles
Figure Encoding Timing CS4190/CS4191
G726
clock cycles
Figure Decoding Timing CS4190/CS4191
CS4100
ADPCM Speech Coders
AVAILABILITY IMPLEMENTATION INFORMATION OPTIMACORES
applications that require high performance, cost high integration ASIC, Amphion delivers Optima Cores series multimedia ASVCs that pre-optimized Amphion experts targeted silicon technology. Choose from off-the-shelf versions CSO4100 family available many popular ASIC foundry silicon supplier technologies Amphion port cores technology your choice.
PRODUCT
SILICON VENDOR
PRODUCT NAME/PROCESS 0.18-micron using Artisan standard cell libraries 0.18-micron using Artisan standard cell libraries 0.18-micron using Artisan standard cell libraries 0.18-micron using Artisan standard cell libraries 0.18-micron using Artisan standard cell libraries 0.18-micron using Artisan standard cell libraries
PERFORMANCE
LOGIC GATES
MEMORY AREA (mm2)* 0.12
AVAILABILITY
CSO4110TK
TSMC
duplex channels 2.048 duplex channels 8.192 duplex channels 16.384 duplex channels 32.768 duplex channels 49.152 1024 duplex channels 98.304
19.6K
CSO4120TK
TSMC
19.8K
0.20
CSO4125TK
TSMC
19.8K
0.31
CSO4130TK
TSMC
19.8K
0.52
CSO4190TK
TSMC
26.7K
2.05
CSO4191TK
TSMC
26.7K
Based SRAM density Kbits/mm2 plus area overhead memory peripheral circuitry. Consult your local Amphion representative product specific performance information, current availability individual products, lead times Optima core porting.
Table Optima Cores
CELERITY CORES
ASIC prototyping projects requiring fast time market programmable logic solution, Amphion's Celerity Core solutions offer silicon-aware performance tuning found Amphion products, combined with rapid design times offered today's leading programmable logic solutions. SILICON VENDOR
Altera
PRODUCT
PROGRAMMABLE LOGIC PRODUCT
Apex FPGA
PERFORMANCE
duplex channels 2.048 duplex channels 2.048 duplex channels 8.192 duplex channels 8.192 duplex channels 16.384 duplex channels 16.384 simplex channels 4.092 simplex channels 4.092 duplex channels 24.576
DEVICE RESOURCES USED
4294 Logic Elements 1669 SLICEs Block RAMs 4302 Logic Elements 1688 SLICEs Block RAMs 4307 Logic Elements 1869 SLICEs Block RAMs 6336 Logic Elements 2369 SLICEs* Block RAMS 7178 Logic Elements
AVAILABILITY
CSC4110AA
CSC4110XV
Xilinx
Virtex FPGA
CSC4120AA
Altera
Apex FPGA
CSC4120XV
Xilinx
Virtex FPGA
CSC4125AA
Altera
Apex FPGA
CSC4125XV
Xilinx
Virtex FPGA
CSC4180AA
Altera
Apex FPGA
CSC4180XE
Xilinx
Virtex-E FPGA
CSC4190AA
Altera
Apex FPGA
CSC4190XE
Xilinx
Virtex-E FPGA
duplex channels 36.864
2721 SLICEs Block RAMs
Table Celerity Cores *Not resources every slice used.
CS4100
ADPCM Speech Coders
PERFORMANCE ADVANTAGE AMPHION ASVCs
performance cost tradeoffs between general- fixed-purpose solutions substantial grows with every generation silicon process technology. difference between general-purpose solutions (microprocessor) intrinsic computational efficiency silicon nearly three orders magnitude. This reason that Amphion fixed-purpose ASVCs deliver thousand time improvement performance when compared conventional implementations using general-purpose, software-programmable microprocessors. Using proprietary techniques directmapped implementations digital signal processing functions algorithms hardware, Amphion's ASVCs provide well-thought-out design approach that will continue provide extraordinary performance advantages future, well time-to-market advantages, because they off-the-shelf.
Application Specific Virtual Component (ASVC)
MiPS WATTS
1000X Difference
Processors
0.25 0.13 0.07
Feature Size
Figure Amphion ASVCs Outperform DSPs 1000X
Amphion continues expand family ASVC solutions. http://www.amphion.com current list products.
ABOUT AMPHION
Amphion leading supplier speech coding, video/image processing channel coding ASVCs system-on-a chip (SoC) solutions telecommunications/Internet, consumer/communications wireless markets.
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SALES AGENTS
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Amphion, Amphion logo, "Virtual Components Converging World", "The Multimedia ASVC Company", Optima, Celerity, Tapeout-Ready, TestReady AutoMode trademarks Amphion Semiconductor Ltd. 2001 Amphion Semiconductor Ltd.
02/01 Publication DS4100-b

CS4100 CS4100 family adaptive differential pulse code modulators

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