AC108SU single 8-port 10/100Mbps integrated Layer switch. addition Lay

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AC108SU single 8-port 10/100Mbps integrated Layer switch. addition Lay

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AC108SU 3.3V 10/100- TX/FX Ports Switch
AC108SU single 8-port 10/100Mbps integrated Layer switch. addition Layer switch engine, AC108SU integrated eight ports 10/100 TX/FX transceiver. device used 8-port unmanaged stand-alone switch, used 24-port switch when three units cascaded together. AC108SU supports cost SGRAM SDRAM external interface. support memory size from Mbytes Mbytes. AC108SU supports serial EEPROM applications specific configuration. popular serial EEPROM such 93C46 used conjunction with AC108SU.
Gbps NuCleus
EEPROM
ADDRESS TABLE
EEPROM
10/100 Switch Engine
AC108SU 3.3V 10/100- TX/FX Ports Switch
Features
Hardware selectable 1.25:1 transformer. Integrated eight 10/100 100FX switch with transceiver. Bridge function supports store forward algorithm. Supports hashing algorithm. Supports address entries. Build-in Self-learning Self-routing, Aging capabilities. Supports wire-speed filtering with forwarding rate 148,800 pps. IEEE 802.3u Auto-Negotiation compliant. Supports Mbytes memory that utilizes cost SGRAM SDRAM memory. Supports IEEE 802.3x full half duplex flow control. Cascadable ports. Built arbitrator that requires external component. Programmable matrix. Supports popular cost serial EEPROM (93C46). power CMOS, 3.3V, 0.35 technology. Broadcast Storm detection Power self-test. package.
Port Stand Alone Switch SGRAM SDRAM
AC108SU
Port
Port Stand Alone Switch
SGRAM SDRAM
AC108SU
SGRAM SDRAM
AC108SU
SGRAM SDRAM
AC108SU
Port
Port
Port
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AC108SU 3.3V 10/100- TX/FX Ports Switch
DIAGRAM AC108SU
VIEW
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AC108SU 3.3V 10/100- TX/FX Ports Switch
DESCRIPTION
multi-function pins will designated Bold type number. Designers must assure that they have identified modes operation prior final design. NOTES: assignment shown below description table subject change without notice. user advised contact Altima Communications Inc. before implementing design based information provided this data sheet.
10/100BASE-TX/FX MEDIA CONNECTIONS
Name RXP_FXIP[7:0] RXP_FXIP_7 RXP_FXIP_6 RXP_FXIP_5 RXP_FXIP_4 RXP_FXIP_3 RXP_FXIP_2 RXP_FXIP_1 RXP_FXIP_0 RXN_FXIN[7:0] RXN_FXIN_7 RXN_FXIN_6 RXN_FXIN_5 RXN_FXIN_4 RXN_FXIN_3 RXN_FXIN_2 RXN_FXIN_1 RXN_FXIN_0 Negative signal differential receive inputs port through This signal connected magnetic mode. Negative signal PECL receive inputs port through This signal connected fiber transceiver. ports configured either 10/100 100FX port. 100FX enabled EEPROM only. enable extended register must `1'. default mode. Refer EEPROM table more details. Note: 10/100TX functionality tested, only 100FX functionality port tested tester. BGA# Type Description Positive signal differential receive inputs port through This signal connected magnetic mode. Positive signal PECL receive inputs port through This signal connected fiber transceiver. enabled EEPROM only. enable extended register must `1'. default mode. Refer EEPROM table more details.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name TXP_FXOP[7:0] TXP_FXOP_7 TXP_FXOP_6 TXP_FXOP_5 TXP_FXOP_4 TXP_FXOP_3 TXP_FXOP_2 TXP_FXOP_1 TXP_FXOP_0 TXN_FXON[7:0] TXN_FXON_7 TXN_FXON_6 TXN_FXON_5 TXN_FXON_4 TXN_FXON_3 TXN_FXON_2 TXN_FXON_1 TXN_FXON_0 SDCM Common voltage threshold level setting. requires volts input order function. volts derived from simple resistor divider network. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Signal Detect Port Follows apps note termination. Negative signal differential outputs port through This signal connected magnetic mode. Negative signal PECL outputs port through This signal connected fiber transceiver, when enabled serial EEPROM. BGA# Type Description Positive signal differential outputs port through This signal connected magnetic mode. Positive signal PECL outputs port through This signal connected fiber transceiver, when enabled serial EEPROM.
SDP7 SDP6 SDP5 SDP4 SDP3/ANA_T3 SDP2/ANA_T2 SDP1/ANA_T1
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name SDP0/ANA_T0 IBREF BGA# Type Description Signal Detect Port Follows apps note termination. Reference bias resistor. tied external (1%) resistor which should connected analog ground resistor.
BACKPLANE INTERFACE
Name CH0_0 CH0_1 CH1_0 CH1_1 CH2_0 CH2_1 CH3_0 CH3_1 CH4_0 CH4_1 CH5_0 CH5_1 CH6_0 CH6_1 CH7_0 CH7_1 CH8_0 CH8_1 BGA# Type Description
I/O, Channel data bus. These 2-bit wide data bus, which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name CH9_0 CH9_1 CH10_0 CH10_1 CH11_0 CH11_1 CH12_0 CH12_1 CH13_0 CH13_1 CH14_0 CH14_1 CH15_0 CH15_1 CH16_0 CH16_1 CH17_0 CH17_1 CH18_0 CH18_1 CH19_0 CH19_1 BGA# Type Description
I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name CH20_0 CH20_1 CH21_0 CH21_1 CH22_0 CH22_1 CH23_0 CH23_1 BGA# Type Description
I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane. I/O, Channel data bus. These 2-bit wide data which synchronous Mhz. SYS_CLK. These pins tied channel data second third device. These signals will become high-Z clock period after data been forwarded backplane.
SERIAL EEPROM
Name PROM_CLK/MDC BGA# Type PROM_DO/MDIO PROM_DI PROM_CS Description Serial EEPROM clock output. This signal connected 93C46 pin. After data been read from EEPROM, this signal becomes signal. Serial EEPROM data output. This signal connected 93C46 pin. After data been read from EEPROM, this signal becomes MDIO signal. Serial EEPROM data input. This signal connected 93C46 pin. Serial EEPROM chip select. This signal connected 93C46 pin.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
DISPLAY
Name LED_LN[4:0] LED_LN4 LED_LN3 LED_LN2 LED_LN1 LED_LN0 BGA# Type Description Enable corresponding display line display matrix, active output.
48mA LED_LN4: Programmable display. LED_LN3: Default display switch utilization. programmed display other functions serial EEPROM. LED_LN2: Default display Link/Activity. programmed display other functions serial EEPROM. LED_LN1: Default display Duplex/Collision. programmed display other functions serial EEPROM. LED_LN0: Default display Speed. programmed display other functions serial EEPROM.
LED_DATA[7:0] LED_DATA7 LED_DATA6 LED_DATA5 LED_DATA4 LED_DATA3 LED_DATA2 LED_DATA1 LED_DATA0
Output display information each column display matrix. Active high output.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
EXTERNAL MEMORY CONFIGURATION
Name MCFG[1:0] MCFG1 MCFG0 BGA# Type Description Memory Configuration Pins. These signals either pulled ground, depending memory size. MCFG1 MCFG0 Invalid mode. 512K SGRAM (total: 2MB) SGRAM SDRAM (total: 4MB) SDRAM 2pcs (total: 4MB) Reserved buffer test. Memory Configuration
SGRAM SDRAM INTERFACE
Name MEM_BA MEM_WE MEM_RAS MEM_CAS MEM_CLK MEM_CLKD BGA# Type Description Bank Address. This signal connected SGRAM/SDRAM bank address pin. Memory address write enable. This signal active connected SGRAM/SDRAM write enable pin. Memory address strobe. This signal active connected SGRAM/SDRAM address strobe pin. Memory column address strobe. This signal active connected SGRAM/SDRAM column address strobe pin. Memory clock signal. This signal connected SGRAM/SDRAM clock pin. Memory clock second SDRAM. When using SDRAMs connect MEM_CLKD DRAM connect MEM_CLK other DRAM.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name MEM_D[31:0] MEM_D31 MEM_D30 MEM_D29 MEM_D28 MEM_D27 MEM_D26 MEM_D25 MEM_D24 MEM_D23 MEM_D22 MEM_D21 MEM_D20 MEM_D19 MEM_D18 MEM_D17 MEM_D16 MEM_D15 MEM_D14 MEM_D13 MEM_D12 MEM_D11 MEM_D10 MEM_D9 MEM_D8 MEM_D7 MEM_D6 MEM_D5 BGA# Type Description
I/O, Memory data signals. These pins connected external memory data pins.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
MEMORY INTERFACE
Name MEM_D4 MEM_D3 MEM_D2 MEM_D1 MEM_D0 MEM_A[10:0] MEM_A10 MEM_A9 MEM_A8 MEM_A7 MEM_A6 MEM_A5 MEM_A4 MEM_A3 MEM_A2 MEM_A1 MEM_A0 BGA# Memory address pins. These signals connected external memory address pins. Note: Some pins unused depending memory configuration. 512K SGRAM: MEM_A10 unused. SGRAM SDRAM: address pins used. SDRAM pcs.): address pins used. Type Description Memory data signals. These pins connected external memory data pins.
CLOCK/RST/SYS INTERFACE
Name SYS_CLK BGA# Type Description System clock. clock oscillator with used drive this pin. This signal will synchronous other SYS_CLK pins when more than AC108SU used. Test clock. This signal tied ground normal operation. clock. Mhz. Clock oscillator with used drive this pin. This signal will synchronous other PHY_CLK pins when more than AC108SU used. Active reset signal. When this pulled low, will reset entire device. Transformer configuration. Pulled signal ground will configure device type transformer. Pulled signal high will configure device 1.25:1 type transformer.
TST_CLK PHY_CLK
RESET_N XFM_CFG
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AC108SU 3.3V 10/100- TX/FX Ports Switch
TEST MODE
Name TST1_MII TST2_MII TST3_MII TST4_MII TST5_MII TST6_MII TST7_MII TST8_MII SYS_ERR TEST[4:0] TEST4 TEST3 TEST2 TEST1 TEST0 BGA# Type Description Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. Reserved factory testing only. normal operation, pull this ground Ohms. System error. This signal active high used general purpose such output. Test mode, testing purpose only. Pulled Ohms normal operation 00000: Normal operation Others: Reserved factory test mode.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
COMMAND
Name CMD[4:0] CMD4 CMD3 CMD2 CMD1 CMD0 CF_N I/O, Command Framing. indicate whether command valid bus. more than AC108SU board, this signal tied together. This requires Ohms pull Vcc. Valid command bus. Invalid command bus. BUSY_N I/O, Command busy signal. When destination port monitors command from want reject command, destination port will drive this signal low, command will accepted. more than AC108SU board, this signal tied together. This requires Ohms pull Vcc. I/O, Command request from SLAVE MASTER. This active signal. When AC108SU configured MASTER mode, this becomes input signal. there second device board, should then connected same second device. This requires Ohms pull When AC108SU configured SLAVE mode, this becomes output signal. this device second chip, then should connect master. this device third chip, then should connect master. Figure stand alone mode, pull this high through resistor. BGA# Type Description
I/O, Command Bus. Bi-directional 5-bit wide data which synchronous SYS_CLK. CMD4 most significant bit. default, these pins inputs. After transmitting command, data will tri-stated clock cycle before returning input mode. This data used transfer signaling protocol (ie. Port auto-setup, channel setup) between Nucleus backplane. These signals bused together when more than AC108SU board. Each these pins required Ohms pull Vcc.
REQ_N_S1/REQ_N
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name REQ_N_S2/NC BGA# Type Description Command request from SLAVE MASTER. This active signal. When AC108SU configured MASTER mode, this becomes input signal. This should pulled high Ohms other device connected When AC108SU configured SLAVE mode, this requires Ohms pull Figure stand alone mode, pull this high through resistor. ACK_N_S1/ACK_N Acknowledge from SLAVE MASTER. represents successful acknowledgement from command bus. When AC108SU configured MASTER mode, this output signal. When AC108SU configured SLAVE mode, this becomes input signal. this device second chip, then should connect master. this device third chip, then should connect master. ACK_N_S2/NC Acknowledge from SLAVE MASTER. represents successful acknowledgement from command bus. When AC108SU configured MASTER mode, this output signal. there third device, should then connected third device. When AC108SU configured SLAVE mode, this left unconnected. MSTR_N/SLAVE Master Slave selected. Pulled high directly will place device SLAVE mode. Pulled ground will MASTER mode. There only master system. stand alone mode, this ground.
POWER GROUND
Name Power BGA# Type Digital Total digital pins. Description
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name BGA# Type Power Ground Ground Total ground pins. Analog Total Analog pins. Description
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name BGA# Type Description
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AC108SU 3.3V 10/100- TX/FX Ports Switch Name BGA# Type Description
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AC108SU 3.3V 10/100- TX/FX Ports Switch
FUNCTIONAL DESCRIPTION
AC108SU single chip 10BASE-T/100BASE-TX/FX twisted pairs 100FX switch controller with eight built-in transceivers. AC108SU also supports serial EEPROM interface, which allow users configure setting each individual port. device supports 93C46 serial EEPROM. AC108SU expansion structure (patent pending) cascadable 24-port switch application. AC108SU provides highest integration chip solution cost effective switch system. device also includes Altima's patent pending power management technology. built-in power management function power-down individual port when it's cable detected). Power management reduces power consumption improves device's long-term reliability.
CLOCKS, RESET POWER MANAGEMENT FUNCTIONS
AC108SU requires clock sources. clock required portion, drives PHY_CLK input pin. clock required back plane portion. This clock will drive SYS_CLK input pin. Both clock sources need CMOS level have +/-100 rating. AC108SU generate 137.5 output clock SGRAM interface. SGRAM clock rating needs greater than MHz.
AC108SU reset ways: During initial power-on. Hardware reset: logic signal pulse width applied pin. During reset, mode pins will latched EEPROM data read memory will initialized, internal state machine will reset known state. completion reset sequence, ports enabled frame reception transmission. Power Management: device built-in energy detect circuitry that power down unused circuitry when cable connected. Energy Detect (ED) circuitry constantly monitoring incoming signal from media enable unused circuitry once cable connected. While power management enabled, device configured 100TX mode cable connected, transmitter outputs Norma Link Pulses (NLP) rather than MLT-3. Once link transmitter output switch from MLT-3. 10BT mode, transmit output regardless link status. Auto-Negotiation mode, transmit outputs Fast Link Pulses (FLP).
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AC108SU 3.3V 10/100- TX/FX Ports Switch
TRANSCEIVER FUNCTION
TRANSMIT FUNCTION
100Base-TX mode, transformer, with link Transceiver transmits MLT3 signal cable isolation. MLT3 data three level signal data. This data will scrambled when transmitted media. MLT3 data synchronous clock. 100Base-FX mode, transceiver will bypass scrambler NRZI MLT3 encoder. output data NRZI PECL signal. This PECL level signal will then drive Fiber-transceiver. 10Base-T mode, Manchester code will generated 10Base-T core logic, which will then synthesized through output wave-shaping driver. This will help reduce emission, which eliminate need external filter.
SCRAMBLER
100Base-TX mode, internal 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce electromagnetic emission twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function: [n-11] [n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmit frequency range, thus eliminating peaks single frequency. emission further reduced assigning unique scramble seed each port.
PARALLEL SERIAL NRZI MLT3 CONVERSION
internal 5-bit data then clocked into Transceiver's shift register with clock, clocked with clock convert into serial stream. Both clocks generated on-chip clock synthesizer, they sync each other. serialized data further converted from NRZI format, which produces transition every Logic transition Logic further reduce emission, NRZI data converted MLT-3 signal. effect offers reduction emissions over un-converted NRZI signals, thus increases output signals' margin operating within Class limit. Whenever there transition occurring NRZI data, there corresponding transition MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information.
MULTIMODE TRANSMIT DRIVER
multimode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal 100Base-FX mode, Manchester coded signal 10Base-T mode. slew rate transmitted MLT-3 signal controlled eliminate high frequency component. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. 100Base-FX mode, filtering performed. transmit driver utilizes current drive output which well balanced produces noise PECL signal. PECL voltage level produced with resistive terminations.
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AC108SU 3.3V 10/100- TX/FX Ports Switch 10BaseT mode, high frequency pre-emphasis performed which extend cable-driving distance without need external filter. FLP/NLP also drive through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level built-in bandgap reference external resistor connected RIBB output pin. resistor sets output current modes operation. Each TXOP/N output open drain device, which source resistance maximum current rating 100TX mode. 10BT mode, output driver draws These values derived from transformer. 1.25:1 transformer used, output current will 100TX mode 10BT mode.
CLOCK SYNTHESIZER
transceiver also includes on-chip clock synthesizer that generates 125MHz internally, externally clock backplane signals. clock generator uses fully differential cell that induces very jitter. Zero Dead Zone Phase Detection method implemented this design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. On-chip loop filter eliminates need external components avoids external noise pickup.
RECEIVE FUNCTION
100Base-TX mode, receive function implements reverse order function that transmit path. includes receiver with adaptive equalization restoration, MLT-3 NRZI conversion, data clock recovery MHz, NRZI conversion, Serial-to-Parallel conversion, de-scrambling. receiver circuit starts with bias differential RX+/- inputs, follows with low-pass filter filter high frequency noise from transmission channel media. amplification ratio slicer's threshold on-chip bandgap reference. 100Base-FX mode, signal will received through PECL receiver, directly passed clock recovery data/clock extraction. mode, descrambler decipher will bypassed. 10Base-T mode, signal will first pass through order lowpass filter, which will filter noise from cable, board, transformer. This will eliminate need 10Base-T external filter.
ADAPTIVE EQUALIZER
Each eight transceivers designed accommodate maximum cable length meters CAT5 cable. meters CAT-5 cable, such AT&T 1061, attenuation MHz. typical attenuation 100-meter cable worst case attenuation around 24-26 defined TP-PMD. amplitude phase distortion from cable will cause inter-symbol interference (ISI) which makes clock data recovery impossible. Adaptive equalizer done closely match inverse transfer function twist-pair cable. This variable equalizer that changes equalizer frequency response accordance cable length. cable length estimated based comparisons incoming signal strength against some known cable characteristics. equalizer monotonically frequency response, will tune itself automatically cable length compensate amplitude phase distortion incurred from cable.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
LINK MONITOR
Signal levels detected through squelch detection circuitry. signal detect (SD) circuit follows equalizer will asserted high whenever peak detector detects post-equalized signal with peak ground voltage level larger than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detects asserted. gets de-asserted approximately after energy level consistently less than from peak ground. 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Transceiver pin. 10Base-T mode, link-pulse detection circuit wills constantly monitors RXIP/RXIN pins presence valid link pulses.
BASELINE WANDER COMPENSATION
100Base-TX data stream always balanced. transformer blocks component incoming signal, thus offset differential receives inputs wander. shift signal levels, coupled with non-zero rise fall times serial stream cause pulse-width distortion. Thus creating jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. Transceiver implemented patent-pending restoration circuit, unlike traditional implementation; does need feedback information from slicer clock recovery. This will only simplify system/circuit design also eliminate random/systematic offset receive path. 10BaseT 100Base-FX modes, baseline wander correction circuit required therefore will bypassed.
CLOCK/DATA RECOVERY
equalized MLT-3 signal will pass through slicer circuit that will then convert NRZI format. Transceiver uses mixed-signal phase locked loop (PLL) extract clock information incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input while receive clock locked incoming data streams. When initial lock achieved, switches lock data stream, extracts clock from that framing recover data. recovered clock also used generate internal RX_CLK. requires external components operation high noise immunity jitter. provides fast phase align (lock) data transition data/clock acquisition time after power-on less than transitions. maintain lock run-lengths data bits absence signal transitions.
DECODER/DE-SCRAMBLER
de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler will acquire lock with data stream recognizing IDLE bursts more bits locking de-ciphering Linear Feedback Shift Register (LFSR). Stream cipher de-scrambler used 100Base-FX 10Base-T modes.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
AUTO-NEGOTIATION MISCELLANEOUS FUNCTIONS
Each transceiver contains ability negotiate mode operation over twisted pair using autonegotiation mechanism defined clause IEEE 802.3u specification. Auto-negotiation disabled EEPROM. transceiver automatically chooses mode operation detecting incoming signal. During auto-negotiation, contents will sent link partner through series fast link pulse (FLP). When auto-negotiation enabled, device will send during following conditions: power link loss, restart command. same time, device will monitor incoming data determine mode operation. Parallel detection circuit will enabled soon either 10BaseT idle 100Base-TX idle detected. mode operation gets configured based technology incoming signal. When device received burst from link partner with identical link code words (ignoring acknowledge bit), will store these code words Reg. wait next identical code word. Once device detects second code word, will configure itself highest technology that common both ends. technology priorities 100Base-TX, full duplex, 100Base-TX, half-duplex, 10Base-T, full duplex, 10Base-T half-duplex.
PARALLEL DETECTION
Transceiver also check 10Base-T 100Base-TX idle symbol. either detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems.
FAR-END FAULT MODE ONLY
Auto-negotiation provides remote fault capability detecting asymmetric link failure. Since 100Base-FX systems auto-negotiation, alternative, in-band-signaling scheme, Far-End-Fault used signal remote fault conditions. stream consecutive ones followed logic zero. This pattern repeated times. Far-end Fault will signaled under conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets transmit Far-end fault (Reg. 21.7). Far-End-Fault mechanism enabled 100Base-FX mode disabled 100Base-TX 10Base-T modes.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
SWITCH FUNCTION
BACKPLANE
transmit data back plane 2-bit code group rate. This data transferred from AC108SU another command data line. units cascaded together, giving ports design. command data consists wide, CMD[4:0], command frame, request acknowledge signals. command data will bused together when more than unit installed. Refer Figure reference.
Figure
RES_PK8
REQ_N_S2/NC (B6)
ACK_N_S2/NC (C6)
REQ_N_S2/NC (B6)
ACK_N_S2/NC (C6)
REQ_N_S2/NC (B6)
REQ_N_S1/REQ_N (A5)
ACK_N_S1/ACK_N (B5)
REQ_N_S1/REQ_N (A5)
ACK_N_S1/ACK_N (B5)
ACK_N_S2/NC (C6)
CMD[4:0]
CH[23:0]
CMD[4:0]
CH[23:0]
CMD[4:0]
REQ_N_S1/REQ_N (A5)
MASTER/SLAVE
MASTER/SLAVE
ACK_N_S1/ACK_N (B5)
BUSY_N (B2)
CF_N (A2)
BUSY_N (B2)
CF_N (A2)
BUSY_N (B2)
CF_N (A2)
CH[23:0] MASTER/SLAVE
BACKPLANE INTERFACE
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AC108SU 3.3V 10/100- TX/FX Ports Switch
MEMORY INTERFACE
AC108SU offers 32-bit SGRAM/SDRAM data 11-bit address interface. external memory used store packets headers transmit receive. device supports memory configuration Mbytes Mbytes. Each port memory area. more efficient purpose, AC108SU implements ring buffer structure. Four pointers used this memory structure each port. After reset, start pointer pointer will define fixed memory region dependent memory configuration. write pointer read pointer same start pointer. While packet stored buffer, write pointer will increase. While packet removed from memory, read pointer will increase. calculating difference write pointer read pointer decide whether flow control should active not.
START pointer WRITE READ pointers will wrap around while reaching pointer
READ pointer
WRITE pointer
pointer
Each good packet stored memory will attached 16-bit packet header. packet header used indicate packet length status. memory structure packet structure appeared following. Packet format buffer
Packet Header DATA2 DATA3
DATA0 DATA4
DATA1 DATA5
FLOW CONTROL
Flow control method which will restrict flow incoming packets reduce chances system resources being exhausted. While AC108SU non-blocking, wire speed switch, limitations occur within memory during periods packet flooding (ex. Broadcast packet storms). device implements different flow controls methods. full duplex mode, IEEE 802.3x flow control used; while half duplex collision back pressure scheme implemented. 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com)
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AC108SU 3.3V 10/100- TX/FX Ports Switch AC108SU supports both full half duplex flow control mechanisms. half duplex mode port will collide with incoming data alleviate incoming traffic alert link partner that packet successfully received. Half duplex flow control turn ON/OFF EEPROM. full duplex mode, 10/100 ports will IEEE 802.3x full duplex flow control. This sends flow control packet link partners that will then stop transmit packets time specified. addition, flow control packet received AC108SU, then will transmit packets amount time specified. Full duplex flow control turn ON/OFF result auto negotiation described IEEE 802.3ab-1999 Annex28B.
FORWARDING SCHEME
switch supports Store-and-forward scheme only. does support Cut-Through-Forward. With Store-andforward, incoming packet should completely received buffer without error before sent out.
ADDRESS TABLE
AC108SU equipped with entry internal address table. implemented internal SRAM. Each entry 64-bit width with following format:
B61-56 B55-48 B47-40 B39-32 B31-24 B23-16 B15-8 B7-0
where 47-0 55-48 61-56
Aging
PORT
MAC5
MAC4
MAC3
MAC2
MAC1
MAC0
address Port number corresponding this address Aging counter. When aging timer expired, this counter will increase. this counter overflow, corresponding entry aged out. Valid bit. this valid entry. Static Bit. Always
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AC108SU 3.3V 10/100- TX/FX Ports Switch
ADDRESS RECOGNITION
exclusive addressing algorithm used shown following formula Index[15:0] MAC[47:32] MAC[31:16] MAC[15:0] Since address table entries. Only bits needed index.
ROUTING DECISION
record empty, packet will broadcasted treated unknown frame. Otherwise, record read, compared with current addresses same, port number decided, packet forwarded assigned port. address collision occurred, different address, incoming packet unknown packet also. Learning Process Address learning process composed (source address) packets addressing algorithm described above. switch will check each incoming packet integrity from network side backplane side. packet error-free buffer available, packet will compared with contents from hashed address table. address port number same, aging time revised. same address with different port number, port number re-assigned. When entry collided, address lookup table will updated. Otherwise, address port number incoming packet will entries empty recordAging Time switch automatically examine status address lookup table. round robin speed, checking timer depended aging time. default mode, switch aging time configurable with every seconds unit fast aging time seconds unit. Aging time also enable disable depending system requirement. When enabled, this guaranty requiring free spaces that released from occupied address entries.
NuCleus Backplane
support high port count application, AC108SU implements 4.2Gbit/sec backplane names NuCleus. With this high bandwidth backplane, three AC108SU cascaded together support 24-port non-block fullduplex Ethernet Fast Ethernet switch. AC108SU must configured master, other slaves. extra component required NuCleus's architecture.
(HEAD-OF-LINE) PROTECTION
(Head-of-Line) Blocking occurs when congested port blocks traffic destined uncongested port. This often occurs switch architectures with input queue port. switch exhibits blocking, traffic stream forwarded both uncongested congested ports result buffer overflow. With flow control enabled, switch should exhibit frame loss irrespective Blocking. AC108SU implements mechanism overcome avoid Blocking lost packets uncongested port when flow control enabled. HOL_PRO_EN Switch Control Register enable blocking protection.Broadcast Storm Filtering Broadcast storm occurs when network device abnormally generates broadcast multicast packets network continuously. Since switch layer-2 network equipment, when receives broadcast multicast packet from network, will forward other ports switch. port switch receives many broadcast multicast packets finite time interval, performance overall network will drop dramatically. AC108SU implements mechanism detect broadcast storm event. broadcast multicast packets number stored receive buffer exceeds upper threshold level, then switch will enter broadcast filtering state that
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AC108SU 3.3V 10/100- TX/FX Ports Switch particular port. Once this state, incoming packet broadcast/multicast type, then packet will dropped. However, incoming packet unicast type, then packet will forwarded. switch will return normal operation soon multicast packets buffer dropped below threshold value. enable broadcast storm filtering, register one. [10:11] register will threshold level.
POWER INTERNAL SELF TEST Upon power after reset goes inactive, AC108SU will take approximately seconds self test. power self test will ensure MAC, switch circuit, backplane, external memory operate properly. following picture describes packet flow test. After about seconds testing, unit will return normal mode, start receive transmit packets. Each pair ports will transmit receive predefined packets from another. packet does match during test, LED_ERR will turn port basis.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
EXTERNAL DIAGNOSTIC LOOPBACK TEST During power test pins TST[4:0] [10000], AC108SU will perform external diagnostic loopback test. This test will allow user verify that MAC, swithc, backplane, external memory, PHY, transformer cable working properly. following picture describes packet flow test. After about seconds testing, unit will return normal mode, start receive transmit packets. Each pair ports will transmit receive predefined packets from another. packet does match during test, error will latched inside unit. programming (see port program table), error displayed LED.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
REGISTER WRITE FROM EPROM
AC108SU fully programmed using external EPROM. EPROM supported wire type that provides DATA signal such 93C46 (64x16) other compatible devices.
After reset during chip initialization, device will read contents EPROM overwrite values into registers. EPROM must organized into blocks each register starting address incrementing last address. Within each register value, order reading from down
system designer able register defaults then PROM required. this case PROMDATA must tied high board. AC108SU will then keep register default values.
CONTROLLER
AC108SU's LEDs provide visual indication switch port status. Ports each have separate which provide port status information. Each these LEDs fully programmable with default state. default operation each contained following table. Port Default Operation LED_LN Speed Indicator each port 10Mb/s link 100Mb/s Blinks RX_ERR (cable problem) diagnostic error (when running diagnostic) Full/Half/Collision Duplex each port port half duplex link BLINK port half duplex collision occurred port full duplex Link/Activity Indicator each port Indicates that port does have link BLINK Link present receive transmit activity occurring media Link present without activity LEDUtil[7:0] bits LED_PROM function connecting LED_DATA[7] LED_ERR function connecting LED_DATA[6] LED_BS function connecting LED_DATA[5] LED_Util[9:8] function connecting LED_DATA[1:0]
Default Operation
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AC108SU 3.3V 10/100- TX/FX Ports Switch
addition default operation, each port LED's programmed through registers. These registers using serial EPROM. blink rate also programmed. following table illustrates programmability features within AC108SU. Port Programmability Table Event Link RX_ERR (RER) Speed 100TX default Duplex Full default TX/RX Activity (TRA) Activity (TA) Activity (RA) Auto-Negotiate Active Diagnostic error (DER) Collision Result
Condition A0=RA0&L A1=RA1&RER !RA1 A2=RA2&S !RA2 A3=RA3&D !RA3 A4=RA4&TRA !RA4 A5=RA5&TA !RA5 A6=RA6&RA !RA6 A7=RA7&N !RA7 A8=RA8&DER !RA8 A9=RA9&C !RA9
BLINK Condition B0=RB0 !RB0 B1=RB1 &RER !RB1 B2=RB2 !RB2 B3=RB3 !RB3 B4=RB4 &TRA !RB4 B5=RB5 !RB5 B5=RB6 !RB6 B7=RB7 !RB7 B8=RB8 &DER !RB8 B9=RB9 !RB9 LEDBLINK=(B 0&B1&B )&!LEDOFF
Condition C0=RC0 C1=RC1 &RER !RC1 C2=RC2 C3=RC3 C4=RC4 &TRA C5=RC5 C6=RC6 C7=RC7 C8=RC8 &DER !RC8 C9=RC9 &C+! LEDOFF=(C0&C1&C2&C
LEDON=(A0&A1&A2&A A9)&(!LEDBLINK&!LED OFF)
Each these tables. setting register bits RAx, each programmed provide wide range information. RAx, LED_LN0 register 0x23, 0x22 0x21 accordingly. Register 0x23 represents condition, refers condition column above. Register 0x22 represents BLINK condition, refers BLINK condition column above. Register 0x21 represents condition, refers condition column above. Each bits register 0x21, 0x22 0x23 represents EVENT condition column above.
LEDON evaluates logical then that will turn LEDBLINK evaluates logical then that will blink rate specified Blink Rate Register. LEDOFF evaluates logical then that will turn off. none assert then will remain off. Refer apps notes examples.
addition port LEDs, several other LEDs provided switch. These summarized following table. Switch Definitions Name
Description
LED_PROM
Active high indicates that AC108SU reading EPROM.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
LED_ERR
LED_BS LEDUtil[9:0]
Active high indicates that error occurred. Active high indicates that broadcast storm occurred.
These LEDs form linear graph that indicates total switch bandwidth utilization. number turned indicate total switch bandwidth being used currently according following scale: LED0 Utilization (Default) LED1 Utilization (Default) LED2 Utilization (Default) LED3 Utilization (Default) LED4 Utilization (Default) LED5 Utilization (Default) LED6 Utilization (Default) LED7 Utilization (Default) LED8 Utilization (Default) LED9 Utilization (Default)
threshold values utilization levels customized registers.
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AC108SU 3.3V 10/100- TX/FX Ports Switch
DISPLAY MATRIX
Display uses refresh technique. using display matrix, number ports drive significantly reduced. LED's assigned each port. default mode, LEDs indications are: Speed, Collision, Link/Activity. LED_LN signals reprogrammed serial EPROM, user wishes configure differently.
LED_D0 LED_D1 LED_D2 LED_D3 LED_D4 LED_D5 LED_D6 LED_D7
LED_LN0
LED_LN1
LED_LN2
LED_LN3
LED_LN4
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AC108SU 3.3V 10/100- TX/FX Ports Switch
EEPROM TABLE
EEPROM used configure initial setting switch transceiver. Offset 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C Description Check Pattern Factory Testing Switch Control Reserved Switch Control Reserved Reserved Reserved control register port extended register port control register port extended register port control register port extended register port control register port extended register port control register port extended register port control register port extended register port control register port extended register port control register port extended register port Reserved Reserved Reserved Reserved Reserved Configuration Group Chip configuration Default Value 8888 (Hex) 0000 (Hex) 1EDF (Hex) FFFF (Hex) 00FF (Hex) 0000 (Hex) 0000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 1000 (Hex) 0000 (Hex) 0000 (Hex) 0000 (Hex) 0000 (Hex) 0000 (Hex) 0000 (Hex)
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AC108SU 3.3V 10/100- TX/FX Ports Switch Offset 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Description Reserved Reserved Reserved control register Effect BLINK Effect Effect Effect BLINK Effect Effect Effect BLINK Effect Effect UTIL [1:0] Threshold UTIL [3:2] Threshold UTIL [5:4] Threshold UTIL [7:6] Threshold UTIL [9:8] Threshold Configuration Group Default Value 0000 (Hex) 0000 (Hex) 0000 (Hex) 001A (Hex) 0000 (Hex) 0102 (Hex) 0005 (Hex) 0100 (Hex) 0200 (Hex) 0009 (Hex) 0100 (Hex) 0011 (Hex) 0001 (Hex) 0503 (Hex) 140A (Hex) 5229 (Hex) CDA7 (Hex) FFE6 (Hex)
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AC108SU 3.3V 10/100- TX/FX Ports Switch
REGISTER DESCRIPTION
Offset 0x00 Check Pattern Register Name Description 15:0 Check Pattern Initialize AC108SU. device upon power will read this word checks whether EEPROM existed not. Mode Default 8888H
8888H EEPROM exist, max. address 8880H EEPROM exist, max. address other value EEPROM does exist
Offset 0x01 Factory Test Register Name 15:0 Reserved Description Reserved Mode Default 0000 (hex)
Offset 0x02 Switch Control Register Name Description 15:13 Reserved Reserved Reserved Reserved 11:10 BS_WM_SEL Broadcast storm threshold level setting. High 128, (packets) High (packets) High (packets) High (packets) SELF_TEST_EN Enable/disable power self test. Enable internal self test Disable internal self test WM_CTRL 802.3x watermark control High 24k, High 16k, Note: This used full-duplex mode only. Reserved Reserved FLOW_CHK_DA Check Destination address when received pause frame Don't check when received pause frame. Note: This used full duplex mode only. ONLY_BROADCAS When broadcast storm occurs, drop only broadcast frame. When broadcast storm occurs, drop both broadcast multicast frames. BS_FLT_EN Enable broadcast filtering function. Disable broadcast filtering function. HOL_PRO_EN Enable Head-of-Line blocking protection. Disable Head-of-Line blocking protection Note: flow control enable, this function will disabled. DRIBBLE_ERROR Treats packet with dribble bits error packets.
Mode
Default
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AC108SU 3.3V 10/100- TX/FX Ports Switch Treats packet with dribble bits normal packets. Treats packet size from 1519 1548 bytes normal packet frame size Rejects frame size over 1518 bytes. Reserved
LOOSE_LEN
Reserved
Offset 0x04 Switch Control Register Note These bits used half-duplex mode only Name Description 15:8 Reserved Reserved FLOW_EN_7 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_6 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_5 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_4 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_3 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_2 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_1 Enable flow control half-duplex PORT Disable flow control half-duplex PORT FLOW_EN_0 Enable flow control half-duplex PORT Disable flow control half-duplex PORT
Mode
Default (hex)
CONFIGURATION REGISTERS
Offset 0x08 Control Register Port Bits NAME Reset Reset Normal operation Loopback Internally loop back transmit receive, thus activity cable media will ignored. Normal operation. Speed Select 100Mbps 10Mbps. This will ignored Auto-Negotiation Description Mode RW/SC Default
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits NAME enabled. Auto-Neg Enable Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected Power Down Power down PHY. Normal operation. Isolate Electrical isolation from cable media. Normal operation. Restart AutoNegotiation Duplex Mode Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Collision Test Enable collision test, which issues signal response assertion TX_EN signal. Disable test Reserved 000000 Description Mode Default
Offset 0x09 Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
Offset 0x0A Control Register Port Bits NAME Reset Reset Normal operation
Description
Mode RW/SC
Default
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits NAME Loopback Description Internally loop back transmit receive, thus activity cable media will ignored. Normal operation. Speed Select 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. Auto-Neg Enable Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected Power Down Power down PHY. Normal operation. Isolate Electrical isolation from cable media. Normal operation. Restart AutoNegotiation Duplex Mode Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Collision Test Enable collision test, which issues signal response assertion TX_EN signal. Disable test Reserved 000000 Mode Default
Offset 0x0B Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
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AC108SU 3.3V 10/100- TX/FX Ports Switch Offset 0x0C Control Register Port Bits NAME Reset Reset Normal operation Loopback Internally loop back transmit receive, thus activity cable media will ignored. Normal operation. Speed Select 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. Auto-Neg Enable Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected Power Down Power down PHY. Normal operation. Isolate Electrical isolation from cable media. Normal operation. Restart AutoNegotiation Duplex Mode Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Collision Test Enable collision test, which issues signal response assertion TX_EN signal. Disable test Reserved 000000
Description
Mode RW/SC
Default
Offset 0x0D Extended Control Register Port Bits Name Enable Description Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Mode Default
Reserved Select Scramble Disable
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits 10:0 Name Reserved Enable scramble. Reserved Description Mode Default 00000000
Offset 0x0E Control Register Port Bits NAME Reset Reset Normal operation Loopback
Description
Mode RW/SC
Default
Internally loop back transmit receive, thus activity cable media will ignored. Normal operation.
Speed Select
100Mbps 10Mbps. This will ignored Auto-Negotiation enabled.
Auto-Neg Enable
Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected
Power Down
Power down PHY. Normal operation.
Isolate
Electrical isolation from cable media. Normal operation.
Restart AutoNegotiation Duplex Mode
Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex.
Collision Test
Enable collision test, which issues signal response assertion TX_EN signal. Disable test
Reserved
000000
Offset 0x0F Extended Control Register Port Bits Name Enable
Description
Mode
Default
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise,
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits 10:0 Name Reserved Select Scramble Disable Reserved should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved Description Mode Default 00000000
Offset 0x10 Control Register Port Bits NAME Reset Reset Normal operation Loopback
Description
Mode RW/SC
Default
Internally loop back transmit receive, thus activity cable media will ignored. Normal operation.
Speed Select
100Mbps 10Mbps. This will ignored Auto-Negotiation enabled.
Auto-Neg Enable
Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected
Power Down
Power down PHY. Normal operation.
Isolate
Electrical isolation from cable media. Normal operation.
Restart AutoNegotiation Duplex Mode
Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex.
Collision Test
Enable collision test, which issues signal response assertion TX_EN signal. Disable test
Reserved
000000
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AC108SU 3.3V 10/100- TX/FX Ports Switch Offset 0x11 Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
Offset 0x12 Control Register Port Bits NAME Reset Reset Normal operation Loopback
Description
Mode RW/SC
Default
Internally loop back transmit receive, thus activity cable media will ignored. Normal operation.
Speed Select
100Mbps 10Mbps. This will ignored Auto-Negotiation enabled.
Auto-Neg Enable
Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected
Power Down
Power down PHY. Normal operation.
Isolate
Electrical isolation from cable media. Normal operation.
Restart AutoNegotiation Duplex Mode
Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex.
Collision Test
Enable collision test, which issues signal response assertion TX_EN signal.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits NAME Disable test Reserved 000000 Description Mode Default
Offset 0x13 Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
Offset 0x14 Control Register Port Bits NAME Reset Reset Normal operation Loopback
Description
Mode RW/SC
Default
Internally loop back transmit receive, thus activity cable media will ignored. Normal operation.
Speed Select
100Mbps 10Mbps. This will ignored Auto-Negotiation enabled.
Auto-Neg Enable
Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected
Power Down
Power down PHY. Normal operation.
Isolate
Electrical isolation from cable media. Normal operation.
Restart AutoNegotiation
Restart Auto-Negotiation process. Normal operation.
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits NAME Duplex Mode Full duplex. Half duplex. Collision Test Enable collision test, which issues signal response assertion TX_EN signal. Disable test Reserved 000000 Description Mode Default
Offset 0x15 Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
Offset 0x16 Control Register Port Bits NAME Reset Reset Normal operation Loopback Internally loop back transmit receive, thus activity cable media will ignored. Normal operation. Speed Select 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. Auto-Neg Enable Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. When Auto-Neg. disabled, speed selected Power Down Power down PHY. Description Mode RW/SC Default
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits NAME Normal operation. Isolate Electrical isolation from cable media. Normal operation. Restart AutoNegotiation Duplex Mode Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Collision Test Enable collision test, which issues signal response assertion TX_EN signal. Disable test Reserved 000000 Description Mode Default
Offset 0x17 Extended Control Register Port Bits Name Enable
Description
Mode
Default
10:0
Reserved Select Scramble Disable Reserved
Enable generation detection. Disable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Reserved Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Reserved
00000000
Offset 0x20 Control Register Bits Name 15:8 Reserved Blink Rate Reserved
Description
Mode
Default (hex) (hex)
Sets blink rate speed. default value time Value blink rate
Offset 0x21 Effect Register Bits Name 15:10 Reserved Reserved
Description
Mode
Default 000000
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits Name Control Description These bits represent respectively. Please refer section definitions. Mode Default 00000000
Offset 0x22 Blink Effect Register Bits Name 15:10 Reserved Blink Control Reserved
Description
Mode
Default 000000 01000000
These bits represent respectively. Please refer section definitions.
Offset 0x23 Effect Register Bits Name 15:10 Reserved Control Reserved
Description
Mode
Default 000000 00000001
These bits represent respectively. Please refer section definitions.
Offset 0x24 Effect Register Bits 15:10 Name Reserved Control Reserved These bits represent respectively. Please refer section definitions. Description Mode Default 000000 01000000
Offset 0x25 Blink Effect Register Bits Name 15:10 Reserved Blink Control Reserved
Description
Mode
Default 000000 10000000
These bits represent respectively. Please refer section definitions.
Offset 0x26 Effect Register Bits Name 15:10 Reserved Control Reserved
Description
Mode
Default 000000 00000010
These bits represent respectively. Please refer section definitions.
Offset 0x27 Effect Register Bits Name 15:10 Reserved Reserved
Description
Mode
Default 000000
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AC108SU 3.3V 10/100- TX/FX Ports Switch Bits Name Control Description These bits represent respectively. Please refer section definitions. Mode Default 01000000
Offset 0x28 Blink Effect Register Bits Name 15:10 Reserved Blink Control Reserved
Description
Mode
Default 000000 00000100
These bits represent respectively. Please refer section definitions.
Offset 0x29 Effect Register Bits Name 15:10 Reserved Control Reserved
Description
Mode
Default 000000 00000000
These bits represent respectively. Please refer section definitions.
Offset 0x2A Utilization Threshold Bits 15:8 Name Utilization Threshold Utilization Threshold Description Value represents utilization threshold value that must crossed this turn Value represents utilization threshold value that must crossed this turn Mode Default 0x05 0x03
Offset 0x2B Utilization Threshold Bits 15:8 Name Utilization Threshold Utilization Threshold Description Value represents utilization threshold value that must crossed this turn Value represents utilization threshold value that must crossed this turn Mode Default 0x14 0x0A
Offset 0x2C Utilization Threshold Bits 15:8 Name Utilization Threshold Utilization Threshold Description Value represents utilization threshold value that must crossed this turn Value represents utilization threshold value that must crossed this turn Mode Default 0x52 0x29
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AC108SU 3.3V 10/100- TX/FX Ports Switch Offset 0x2D Utilization Threshold Bits Name 15:8 Utilization Threshold Utilization Threshold
Description
Mode
Default 0xCD 0xA7
Value represents utilization threshold value that must crossed this turn Value represents utilization threshold value that must crossed this turn
Table Utilization Threshold Bits 15:8 Name Utilization Threshold Utilization Threshold Description Value represents utilization threshold value that must crossed this turn Value represents utilization threshold value that must crossed this turn Mode Default 0xFF 0xE6
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AC108SU 3.3V 10/100- TX/FX Ports Switch
4B/5B CODE-GROUP TABLE
Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 Idle Control Code 11111 11000 10001 01101 00111 Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 SYMBOL Name (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0101 0101 Undefined Undefined Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Transmit Error; used send HALT codegroup Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
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AC108SU 3.3V 10/100- TX/FX Ports Switch
ELECTRICAL CHARACTERISTICS
NOTE: Please contact factory information this time.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55oC +150oC Supply Referenced GND. -0.5V +5.0V Digital Input Voltage. -0.5V Output Voltage. -0.5V Operating Range Operating Temperature (Ta) +70oC Supply Voltage Range (Vcc) 2.97 3.63V
CHARACTERISTICS
Parameter Power Supply Current with ports active Conditions Base-T, Idle Base-T, Normal activity Base-T, utilization Base-T, Peak 100% utilization Base-TX 10/100 Base-TX, power without cable Power down 1000 1100 1150 1300 Units
Input High Voltage Input Voltage Input Current Input Capacitance Output High Voltage Output Voltage Output Transition Time Output Tristate Leakage Current Output Current High RST* Period
CIin |Ioz| tRSTl 3.45V
3.15V 3.45V, 3.15V 3.45V, 3.15V 3.45V Vcc-0.4
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AC108SU 3.3V 10/100- TX/FX Ports Switch
Transmitter, 100BaseTX (1:1 Transformer Ratio) Parameter Conditions TX+/- Output Current High TX+/- Output Current Transmitter, 10BaseTX (1:1 Transformer Ratio) Parameter Conditions TX+/- Output Current High TX+/- Output Current Transmitter, 100BaseTx (1.25:1 Transformer Ratio) Parameter Conditions TX+/- Output Current High TX+/- Output Current Transmitter, 10BaseT (1.25:1 Transformer Ratio) Parameter Conditions TX+/- Output Current High TX+/- Output Current Receiver 100BaseTX Parameter RX+/- Commonmode input voltage RX+/- Differential input resistance RX+/- Commonmode input current Receiver, 10BaseT Parameter Differential Input Resistance Common-mode Rejection
Units
Units
Units
Units
Conditions
Units
Conditions
Units
Square wave 500kHz
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AC108SU 3.3V 10/100- TX/FX Ports Switch
CHARACTERISTICS
Transmitter, 100Base-TX Parameter Differential Output Voltage, peak-to-peak Differential Output Voltage Symmetry Differential Output Overshoot Rise/Fall time Rise/Fall time imbalance Duty Cycle Distortion MLT3 output jitter Transmitter, 10Base-T Parameter Differential Output Voltage, peak-to-peak Start-of-idle Pulse Width TDTX[3:0] tTXs Time Receiver, 100Base-TX Parameter RXOP/N Differential input voltage, peakto-peak Baseline Wander Tracking Clock Recovery Pullin time Jitter Tolerance (peak-to-peak) Signal Detect TurnSDon Threshold (Post equalized) Signal Detect Assertion Time Signal Detect Deassertion Time |tr, Conditions from each output Vcc, Best-fit over times from each output Vcc, |Vp+|/|Vp-| Percent Vp10 0.98 2.0V 1.02 +250 Units
Deviation from best-fit time-grid, 010101 Sequence Scrambled Idle
Conditions from each output Vcc, pattern below fundamental, ones data
Units
TDTX[3:0] valid TSX_CLK rise time
Conditions
Units
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AC108SU 3.3V 10/100- TX/FX Ports Switch
Receiver, 10BaseT Parameter Clock Recovery Pullin time Jitter Tolerance (peak-to-peak) Input Squelched Threshold Input Un-squelched Threshold
Conditions
Units
Programmable Equalizer, 100Base-TX Parameter Conditions Equalizer Output Voltage Equalizer Output Offset Noise Feed-through Bandwidth Frequency Synthesizer Parameter REFCLK Frequency frefclk CLK_125 Frequency fclk125 TX_CLK, Clock Duty Cycle Clock Jitter Charge-Pump Current Ifsqp Gain Loop-Filter Voltage VCtrl Loop-Filter BWPLL Acquisition Time SGRAM Interface Parameter MCLK Frequency N_RAS/N_CAS/N_ output delay MA[10:0]/MBA output delay MD[31:0] output delay MD[31:0] input setup time requirement
Units Vp-p mVrms
Conditions
Units MHz/V
Conditions SYS_CLK Related MCLK Related MCLK Related MCLK Related MCLK
0.52 0.52 0.52 0.96
137.5
3.15 3.15 3.15
Units
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AC108SU 3.3V 10/100- TX/FX Ports Switch NuCleus Backplane Parameter CHxx data output delay CMD[5:0] output delay
Conditions Related SYS_CLK, AC108SU cascade Related SYS_CLK, AC108SU cascade
4.48 4.05
10.81 15.57
Units
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AC108SU 3.3V 10/100- TX/FX Ports Switch
PACKAGE FOOTPRINT BOTTOM VIEW
27.00+0.20 24.13
1.27
1.27
0.75+0.15(272x)
24.13
27.00+0.20 0.56 2.33+0.13
1.17
0.60+0.10
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AC108SU 3.3V 10/100- TX/FX Ports Switch
REVISION HISTORY
Rev. Date Oct.12, 1999 Oct. 1999 First draft. Changed signal names with following numbers: IBREF A16, CH7_1 LED_LN4 C13, LED_LN3 A13, LED_LN2 Indicates MEM_WE signal active signal. Changed number ACK_N_S1 signal ACK_N_S2 Assign pin. Nov. 1999 power ground pins. Total power pins Total ground pins another test factory diagnostic purpose only. TEST4 Nov. 1999 SDCM signal function, A18. further clarification command data descriptions. Dec.06, 1999 Dec.15, 1999 Re-do assignment. Please ignore before version 1.4. definition serial EEPROM reversed. PROM_DO signal input, output. Changed definition REQ& pins. Changed Figure implementation. Mar.06, 2000 Swap memory address from MEM_A0 MEM_A3. MEM_A0 V15. MSTR_N/SLAVE (pin requires direct pull ground chip configured Master. MCFG[0:1] pins must ground instead pull up/down. XFM_CFG (pin B16) must ground instead pull up/down. CF_N REQ_N_S2/NC REQ_N_S1/REQ_N CDM[0:4] each these pins requires Ohms pull Note: Schematic that previously designed using Version data sheet must apply these changes order chip work properly. April 2000 April 2000 This device longer support 1Mbytes SGRAM. device support from Mbytes only. Characteristic. Correct package view. Note: previous version package drawing instead BOTTOM view. 1.8.6 2000 Correct Clock Synthesizer description LED_LN[4:3] description Comments
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AC108SU single 8-port 10/100Mbps integrated Layer switch. addition Lay

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