AC108R family fully integrated multi port dual speed hubs with support
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AC108 RM/RU/RN Ultra Power 10/100 Bridge Repeater GENERAL DESCRIPTION
AC108R family fully integrated multi port dual speed hubs with support SRAM interface, single port, both 100M cascadable buses, stacking capability SNMP RMON statistics. AC108RM port, management, stack AC108RU port, management, stack AC108RN port, management, stack
10/100 10/100TX 100FX ports Embedded PHYs Half Duplex FEFI 100FX 100M connection Very small package 272PBGA footprint Very power (Total) Selectable drivers 1.25:1 transformers allowing additional power reduction Cable Detect mode 1.4W (Total) Power Down mode (Total) Fully compliant with IEEE 802.3 802.3u HDLC Management (RMON/SNMP) test labs (future) Stackable ports Non-blocking 10/100M bridge with controller switching engine SRAM support external buffer memory 512K Unique, port, scrambler seed reduced emissions Baseline Wander Compensation Highly efficient outputs Cable length indicator Reverse polarity detection correction with settable Register indication interrupts port
AC108R products fully compliant IEEE 802.3(u) Class Repeaters. device provides ports Base-T/100 Base-TX interface. ports support either auto-negotiation (ANEG), parallel detection selected media when configure accordingly. Port supports 100BASE-FX fiber media PECL interfaces. interface connected compliant either 100M. Once port's technology set, port automatically connects internal repeaters, operating Mbps other Mbps. integrated back-planes, operating Mbps Mbps, allow port expansion ports. internal port switch connects either 100M repeater segments, 100M segment with isolated port External SRAM used address table packet buffering. 32-bit SNMP RMON management counters accessible high-speed serial management bus.
BLOCK DIAGRAM
AC108RM/RU/RN
AC108RM only AC108RM/RU only
Address Management
SRAM Controller
Port Serial Counter
Port
Bridge
10BT Repeater
Stack !0/100 Stacking Control
100TX Repeater EEPROM Access Control Display Control
FIFO Ctrl Stack FIFO Ctrl
10/100 segment switching logic
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100/FX
AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
General Description.1 Features Block Diagram.1 Diagram AC108RM/RU/RN.5 Descriptions.6 (Media Dependent Interface) Pins (TX).6 (Media Dependent Interface) Pins (FX).7 (Media Independent Interface) Pins Serial Configuration Prom 100Mbps Stacked back-plane (Stack Master mode).8 100Mbps Internal Repeater Bus.8 10Mbps Stacked back-plane (Stack Master mode).9 10Mbps Internal Repeater Bus.9 Serial Management port Display.10 Control Setup.11 Clock, Reset Misc.11 SRAM Interface.12 Power Ground.13 Functional Description.14 Interface.14 SMI.14 Interrupt.14 Carrier Sense RX_DV.15 Media Interface 10Base-T.15 Transmit Function Receive Function.15 Link Monitor.15 100Base-TX.15 Transmit Function Parallel Serial, NRZI, MLT3 Conversion Receive Function.16 Baseline Wander Compensation.16 Clock/Data Recovery Decoder/De-scrambler.17 Link Monitor.17 100Base-FX.17 Transmit Function Receive Function.17 Link Monitor.17 Far-End-Fault-Insertion (FEFI).17 10Base-T/100Base-TX/FX Multi-Mode Transmit Driver.18 Adaptive Equalizer.18 Clock Synthesizer.18 Jabber (Heartbeat).18 Reverse Polarity Detection Correction.18 Inter-Repeater Interface.19 Internal Repeater Bus.19 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100M Internal Repeater Initialization Setup.19 Hardware Configuration.19 Software Configuration.19 LEDs.19 Auto-Negotiation Parallel Detection.20 Diagnostics.20 Loopback Operation.20 Cable Length Indicator.21 Reset Power.21 Clock.21 BRIDGE FUNCTION.21 Buffer Interface.21 Forwarding Scheme Address Recognition Network Management Media Access Control.22 Buffer Management Buffer Allocation.22 Register Descriptions.23 Global Registers Repeater MIB.27 100XCVR Counters RMON Statistic Counter.28 Port Last Address Registers.28 Port Authorized Address Registers.29 Search Address Registers.29 Port Status Registers Port Enable Control Register.30 Interrupt Registers Repeater Configuration Register.31 Miscellaneous Registers.32 Bridge Configuration Register Bridge Configuration Register Effect with Port Enable Event.32 Effect with Partition/Isolation Event.33 Effect with Link Event.33 Effect with Activity (CRS) Event.33 Effect with Auto-Negotiating Event.34 Effect with Speed100 Event.34 Register Control Mode.34 Registers Control Register.35 Status Register.36 Identifier Register.36 Identifier Register.36 Auto-Negotiation Advertisement Register.37 Auto-Negotiation Link Partner Ability Register.37 Auto-Negotiation Expansion Register.37 Auto-Negotiation Next Page Transmit Register.38 Extended Control Register.38 Auto-Negotiation Test Register. 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Receive Error Counter.39 EEPROM Table 4B/5B Code-Group Table ELECTRICAL CHARACTERISTICS.42 Absolute Maximum Ratings Operating Range.42 Total Power Consumption Characteristics.42 REFCLK XTAL Pins.43 Characteristics LED/CFG Pins.43 BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics Digital Timing Characteristics Power Reset Management Data Interface.45 100Base-TX/FX Transmit System Timing 100Base-TX/FX Receive System Timing.46 10Base-T Transmit System Timing.47 10Base-T Receive System Timing 100Mbps Internal Stacked Repeater Receive Transmit System Timing.50 10Mbps Internal Stacked Repeater Receive Transmit System Timing.50 SRAM Read Cycle SRAM Write Cycle SRAM Write Cycle Application Termination Application Termination.55
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater DIAGRAM AC108RM/RU/RN
Bottom VIEW Standard Ground Digital Analog
27.00+0.20 24.13
1.27
1.27
0.75+0.15(272x)
24.13 27.00+0.20 0.56 2.33+0.13
1.17
0.60+0.10
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater Descriptions
Many pins these devices have multiple functions. multi-function pins will designated bolding number. separate descriptions these pins will listed proper sections. Designers must assure that they have identified modes operation prior final design. NOTES: assignment shown below description table subjected change without notice. user advised contact Altima Communications Inc. before implement design based information provided this data sheet. Signals types: input output high impedance (Media Dependent Interface) Pins (TX) Name RXIP_7 RXIP_6 RXIP_5 RXIP_4 RXIP_3 RXIP_2 RXIP_1 RXIP_0 RXIN_7 RXIN_6 RXIN_5 RXIN_4 RXIN_3 RXIN_2 RXIN_1 RXIN_0 TXOP_7 TXOP_6 TXOP_5 TXOP_4 TXOP_3 TXOP_2 TXOP_1 TXOP_0 TXON_7 TXON_6 TXON_5 TXON_4 TXON_3 TXON_2 TXON_1 TXON_0 Type Description Receiver Input Positive both 10Base-T 100Base-TX. pull with pull down with analog signal Active Signal
Receiver Input Negative both 10Base-T 100Base-TX.
Transmitter Output Positive both 10Base-T 100Base-TX.
Transmitter Output Negative both 10Base-T 100Base-TX.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
(Media Dependent Interface) Pins (FX) Name FXIP_7 FXIN_7 FXOP_7 FXON_7 SDP7 SDN7 Type Description Receiver Input Positive 100Base-FX. Receiver Input Negative 100Base-FX. Transmitter Output Positive 100Base-FX. Transmitter Output Negative 100Base-FX. Signal Detect Positive. Signal Detect Negative.
(Media Independent Interface) Pins Name MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXCLK MII_TXEN MII_TXER MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXCLK MII_RXDV MII_RXER MII_CRS MII_COL MII_SPDSEL Type Description Transmit Data. will source TXD[3:0] synchronous with MII_TXCLK when TX_EN asserted.
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MII_TXEN, MII_TXD[3:0], MII_TXER. Transmit Enable. Indicates presented valid data MII_TXD[3:0]. Transmit Error. Indicates presented invalid data MII_TXD[3:0]. will generate error symbol wire. Receive Data. will source RXD[3:0] synchronous with MII_RXCLK when RX_EN asserted.
Transmit Clock. Continuous (25MHz/2.5MHz) clock output used synchronize MII_RXEN, MII_RXD[3:0], MII_RXER. Receive Data-Valid. presented valid recovered MII_RXD[3:0]. Receive Error. Indicates received invalid symbol data. Carrier Sense. Active when carrier been sensed. During full duplex mode, only responses received carrier. Collision Detection. Active when collision detected. port speed selection.
Serial Configuration Prom Name PROM_CS PROM_CLK PROM_OUT PROM_IN Type Description PROM chip select. (For with 93C46 serial EEPROM) PROM Clock. PROM Data Out. PROM Data
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100Mbps Stacked back-plane (Stack Master mode) Name 100CRSU_IN* 100CRSD_IN* 100CRSU_OUT* Type Description 100M Carrier Sense Active when carrier sensed from upper stacks. Only ChipID needs connected. 100M Carrier Sense Down Active when carrier sensed from lower stacks. Only ChipID needs connected. 100M Carrier Sense Out. Active when receive activity detected current stack. This daisy chained with upper stack. last stack leave this unconnected. 100M Carrier Sense Down Out. Active when receive activity detected current stack. This daisy chained with lower stack. last stack leave this unconnected. 100M Collision. Active when collision detected. 100COLBP* pins stack must tied together. pull 3.3v first stack. This monitored detect collisions other devices. Carrier Sense BackPlane. Active when detected. 100CRSBP* pins stack must tied together. This monitored detect other devices. 100M Output-enable. Control enable external buffer. 100M Direction. Control direction external buffer. 0=Input (default), 1=Output.
100CRSD_OUT*
100COLBP*
100CRSBP*
I,O,U
100OE* 100DIR
100Mbps Internal Repeater Name M100COL_LOCAL* M100ACTO* M100ACTI_0* M100ACTI_1* M100ACTI_2* M100COL_SYS* M100CRS_SYS* MS100D4 MS100D3 MS100D2 MS100D1 MS100D0 MS100D_EN* MS100D_CLK Type I/O,Z,U I/O,U I/O,U I/O,U I/O,U I/O,U Description 100M Local Collisions. Input ChipID Active indicate collision other ChipIDs. Output ChipID signal local activity. (see next signals) Connected from ChipID ChipID M100ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M100ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M100ACTO* sense activities. Open other ChipIDs. ChipID will drive this same 100COLBP* indicate local collision. ChipID will drive this same 100CRSBP* indicate local activity. Multiple/Stacked Data Group. Transmit receive data descrambled data groups multiple devices. Data sampled rising edge MS100D_CLK driven falling edge MS100D_CLK. Multiple/Stacked Data Enable. Active when data valid. Multiple/Stacked Data Clock bi-directional non-continuous recovered clock synchronizing with MS100D[4:0], MS100D_EN*.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
10Mbps Stacked back-plane (Stack Master mode) Name 10CRSU_IN* 10CRSD_IN* 10CRSU_OUT* Type Description Carrier Sense Active when carrier sensed from upper stacks. Only ChipID needs connected. Carrier Sense Down Active when carrier sensed from lower stacks. Only ChipID needs connected. Carrier Sense Out. Active when receive activity detected current stack. This daisy chained with upper stack. last stack leave this unconnected. Carrier Sense Down Out. Active when receive activity detected current stack. This daisy chained with lower stack. last stack leave this unconnected. Collision. Active when collision detected. 10COLBP* pins stack must tied together. pull 3.3v first stack. This monitored detect collisions other devices. Carrier Sense BackPlane. Active when detected. 100CRSBP* pins stack must tied together. This monitored detect other devices. Output-enable. Control enable external buffer. Direction. Control direction external buffer. 0=Input (default), 1=Output.
10CRSD_OUT*
10COLBP*
10CRSBP*
I/O,U
10OE* 10DIR
10Mbps Internal Repeater Name M10COL_LOCAL* M10ACTO* M10ACTI_0* M10ACTI_1* M10ACTI_2* M10COL_SYS* M10CRS_SYS* MS10D Type I/O,Z, I/O,U I/O,U I/O,U Description 100M Local Collisions. Input ChipID Active indicate collision other ChipIDs. Output ChipID signal local activity. (see next signals) Connected from ChipID ChipID M10ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M10ACTO* sense activities. Open other ChipIDs. Connected from ChipID ChipID M10ACTO* sense activities. Open other ChipIDs. Chip will drive this same 10COLBP* indicate local collision. Chip will drive this same 10CRSBP* indicate local activity. Multiple/Stacked Data Group. Transmit receive data 10BT multiple devices. Data sampled rising edge MS10D_CLK driven falling edge MS10D_CLK. Multiple/Stacked Data Enable. Active when data valid. Multiple/Stacked Data Clock bi-directional non-continuous recovered clock synchronizing with MS10D, MS10D_EN*.
MS10D_EN* MS10D_CLK
I/O,U
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Serial Management port Name RECONFIG SER_MATCH SERCLK ARBIN ARBOUT INT* MGR_PRES* Display Name LED_LN7 LED_LN6 LED_LN5 LED_LN4 LED_LN3 LED_LN2 LED_LN1 LED_LN0 LED_DATA7 LED_DATA6 LED_DATA5 LED_DATA4 LED_DATA3 LED_DATA2 LED_DATA1 LED_DATA0 Type Description Enable corresponding display line display matrix, active output. detail program connect LEDs Setup section. Type Description Re-arbitration. When this toggles (0-1-0), "RequestID" will sent Agent restart arbitration hubID. Active High output indicated serial address match occurred. Serial Receive sampled rising edge SERCLK Serial Transmit driven falling edge SERCLK. When driven, tri-stated. Clock serial management interface. Daisy Chain Arbitration input This signal requires Ohms pulled low. Daisy Chain Arbitration output. Default high upon power Interrupt. Manager Present.
I/O,D
Output display information each column display matrix. Active high output. pins shared with reset-read configuration pins, test pins EEPROM interface. value applied reset-read pins only valid reset cycle. EEPROM interface active after reset cycle. Once data EEPROM read same pins used display.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Control Setup Name Mode[0] Mode[1] Type Description Mode Mode Domain Domain Rptr 100M Rptr (Master) Rptr 100M Rptr (Stand Alone) Port 100M Rptr Illegal configuration. Pulled down through resistor. assign chip devices single box. only device must assigned with ChipID=0. Pulled down through resistor. Reference bias resistor. Connected analog ground through (1%) resistor. Select mode Port 0=TX, 1=FX
ChipID[0] ChipID[1]
IBREF FX_SEL7 Clock, Reset Misc. Name RESET*
Type
Description Reset initial defaulted state. 25MHz-System-clock reference input. This shall connected external 25MHz-clock source. Multiple devices should synchronous same external clock source. Read during reset. normal mode, test reserved reserved normal mode, test
RAMTest[0] RAMTest[1]
I/O,D
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
SRAM Interface SRAM Interface designed support cost 2*32K*8 2*64K*8 asynchronous memory. Name CE0* CE1* RAM_SIZE[1] RAM_SIZE[0] RAMA_17 RAMA_16 RAMA_15 RAMA_14 RAMA_13 RAMA_12 RAMA_11 RAMA_10 RAMA_9 RAMA_8 RAMA_7 RAMA_6 RAMA_5 RAMA_4 RAMA_3 RAMA_2 RAMA_1 RAMA_0 RAMD_15 RAMD_14 RAMD_13 RAMD_12 RAMD_11 RAMD_10 RAMD_9 RAMD_8 RAMD_7 RAMD_6 RAMD_5 RAMD_4 RAMD_3 RAMD_2 RAMD_1 RAMD_0 Type I/O,U Description Chip Enable SRAM chip. CE0* inverted from CE1*. Chip Enable SRAM chip. CE1* inverted from CE0*. Global Write, active signal. Output Enable, active signal. External SRAM size chip, Read during Reset. 128k invalid 256k 512k SRAM Address output.
I/O,D
SRAM Data Input Output
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Power Ground Name Power A8,A14 D6,D10,D13,D16 U7,U9,U11,U13 C8,C10,C12,C14 F17-18 A2-5,A20 B2-5,B18-20 C4,C11,C18 D8,D9,D12,D17,D18 E17-18 G17-18 J9-12, J17-18 K4,K9-12 L9-12,L17-18 M9-12 R1,R20 U4,U8,U15,U17-20 V8,V18-20 W2-3,W5,W18-20 Y1-3,Y5,Y15,Y17,Y19-20 B16, C15, D15, V17, W17, Type VCCD Description Digital Total digital pins.
Power
VCCA
Analog Total digital pins.
Ground
Ground Total ground pins.
Total Connect pins
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater FUNCTIONAL DESCRIPTION
AC108R single chip 10/100Mbps repeater controller with bridge function. device provides 10BASE-T/100BASE-TX twisted pair interface ports supporting ANEG, parallel detection force media operation. Upon technology selection, each port logically attached either internal 10Mbps repeater internal 100Mbps repeater. ports running same speed will repeat among themselves. 100M stacking buses available allow port expansion ports collision domain each speed AC108R. addition internal repeaters AC108R includes built-in 2-segment switch connection between 100M repeater segments, between 100M repeater isolated port depending setting Mode[1:0] bits. SNMP RMON statistic gathered through high speed HDLC serial management interface Intelligent applications. AC108R's ultra power architecture consumes maximum 3.3Volts when ports running 100Base-TX full speed. built-in power management function will power down individual ports when cable detected which helps further drive down power consumption improve long-term reliability. Functions: 4B/5B MLT3 NRZI Manchester Encoding Decoding Clock Data Recovery Stream Cipher Scrambling De-Scrambling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg)/Parallel Detection 10Mbps 100Mbps repeating port switching connection HDLC Management Interface SNMP/RMON statistics tables
INTERFACE
Media Independent Interface (MII) wire MAC/Phy interface described 802.3u. purpose interface allow layer devices attach variety Physical Layer devices through common interface. operates either 100Mbps 10Mbps, dependant speed Physical Layer. With clocks running either MHz, data clocked between Phy, synchronous with Enable Error signals. data received from transmitted internal repeater determined MII_SPDSEL pin. receipt valid data from wire interface, RX_DV will active signaling that valid data will presented RXD[3:0] pins speed RX_CLK. transmission data from MAC, TX_EN presented indicating presence valid data TXD[3:0]. TXD[3:0] sampled synchronous TX_CLK during time that TX_EN valid. Serial Management Interface (SMI) provides system access SNMP, RMON port status registers device. single, daisy chain connection read and/or write registers multiple devices. interface consists digital signals; clock data. HDLC formatted packets, with start/stop flag, header field error checking, reads writes. Zero-bit insertion/removal used. Operation speed range from Mbps. Interrupt INTR will asserted whenever selectable interrupt events occur. Assertion state programmable either high through INTR_LEVL register bit. Selection made setting appropriate Interrupt Mask register. When INTR goes active,
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
interface required read Interrupt Status register determine which event caused interrupt. Status bits read only clear read. When INTR asserted, held high impedance state. Carrier Sense RX_DV Carrier sense asserted asynchronously pins soon activity detected receive data stream port connected repeater which connected. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10Base-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. Since device always half duplex mode, activated during both transmission reception data. incoming serial stream. Serial Parallel logic used generate 4-bit (MII) data. Link Monitor 10-Base-T link-pulse detection circuit will constantly monitor RXIP/RXIN pins presence valid link pulses. absence valid link pules, Link Status will cleared Link will de-assert.
100BASE-TX
When configured 100Base-TX mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function 100Base-TX mode, transmit function converts synchronous 4-bit (MII) data pair Mbps differential serial data streams. serial data transmitted over network twisted pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. transmit data transmitted from TXD[3:0] signals. 4B/5B encoder replaces first nibbles preamble from frame with /J/K/ code-group pair Start-ofStream Delimiter (SSD), following onset TX_EN signal. 4B/5B encoder appends /T/R/ code-group pair End-of-Stream Delimiter (ESD) transmission place first IDLE code-groups that follow negation TX_EN signal. encapsulated data stream converted from 4-bit nibbles 5-bit code-groups. During inter-packet gap, when there data present, continuous stream IDLE code-groups transmitted. When TX_ER asserted while TX_EN active, Transmit Error code-group substituted translated code word. 4B/5B encoding bypassed when Scramble Disable set. 100Base-TX mode, 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes
MEDIA INTERFACE
10BASE-T
When configured 10Base-T mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function Parallel Serial logic used convert 4-bit (MII) data into serial stream. serialized data goes directly Manchester encoder where synthesized through output waveshaping driver. waveshaper reduces emission filtering harmonics, therefore eliminating need external filter. Receive Function received signal passes through low-pass filter, which filters noise from cable, board, transformer. This eliminates need 10Base-T external filter. Manchester decoder converts
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
plain text stream using stream periodic sequence 2047 bits generated recursive linear function: X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmitted frequency range, thus eliminating peaks single frequency. repeater applications, where ports transmit same data simultaneously, signal energy spread further using non-repeating sequence each Phy, i.e., scrambled seed unique each different based address. Parallel Serial, NRZI, Conversion MLT3 also added determine whether there signal energy media. This useful powersaving mode. amplification ratio slicer's threshold on-chip bandgap reference. Baseline Wander Compensation 100Base-TX data stream always balanced. transformer blocks components incoming signal, thus offset differential receive inputs drift. shifting signal level, coupled with non-zero rise fall times serial stream cause pulse-width distortion. This creates jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. This implements patent-pending restoration circuit. Unlike traditional implementation, circuit does need feedback information from slicer clock recovery circuit. This design simplifies circuit design eliminates random/systematic offset receive path. 10BaseT 100BaseFX modes, baseline wander correction circuit required, therefore disabled. Clock/Data Recovery equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate MII_RXCLK (MII). requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock runlengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, will switch lock MII_TXCLK. This provides continuously running MII_RXCLK (MII). interface, data RXD[4:0] synchronized RX_CLK.
5-bit data clocked into Phy's shift register with clock, clocked with clock convert into serial stream. serial data converted from NRZI format, which produces transition Logic transition Logic further reduce emissions, NRZI data converted MLT-3 signal. conversion offers reduction emissions. This allows system designers meet Class limit. Whenever there transition occurring NRZI data, there corresponding transition occurring MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transitions incoming NRZI data setting count up/down direction MLT-3 data. Asserting FX_SEL high will disable this encoding. Receive Function
100Base-TX receive path functions inverse transmit path. receive path includes receiver with adaptive equalization restoration front end. also includes MLT-3 NRZI converter, data clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, 5B/4B decoder. receiver circuit starts with bias differential RX+/- inputs, followed with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Decoder/De-scrambler de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler acquires lock data stream recognizing IDLE bursts more bits locks frequency de-ciphering LFSR. Once lock acquired, device operate with inter-packet-gap (IPG) However, before lock acquired, de-scrambler needs minimum consecutive idles between packets order acquire lock. de-ciphering logic also tracks number consecutive errors received while RX_DV asserted. Once error counter exceeds limit currently consecutive errors, logic assumes that lock been lost, de-cipher circuit resets itself. process regaining lock will start again. Stream cipher de-scrambler used 100Base-FX 10Base-T modes. Link Monitor Signal level detected through squelch detection circuitry. signal detect (SD) circuit allows equalizer assert high whenever peak detector detects post-equalized signal with peak ground voltage greater than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detect signal stay gets de-asserted approximately after energy level drops consistently below from peak ground. link signal forced during local loopback operation (Loopback register set) forced high when remote loopback taking place (EN_RPBK set). forced 100Base-TX mode, when cable unplugged valid signal detected receive pair, link monitor enters "link fail" state NLP's transmitted. When valid signal detected minimum period time, link monitor enters Link Pass State transmits MLT-3 signal.
100BASE-FX
When port configured 100Base-FX mode, either through hardware configuration software configuration (100Base-FX does support ANeg) will support features parameters industry standards. Transmit Function serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive Fiber-transmitter. Receive Function 100Base-FX mode, signal received through PECL receiver inputs, directly passed clock recovery circuit data/clock extraction. mode, scrambler/de-scrambler cipher function bypassed. Link Monitor 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Phy's pin. Far-End-Fault-Insertion (FEFI) ANeg provides mechanism inform link partner that remote fault occurred. However, ANeg disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This pattern repeated times. FEFI will signal under conditions: When activity received from link partner When clock recovery circuit detects signal error lock error When management entity sets transmit FarEnd-Fault bit. FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
10BASE-T/100BASE-TX/FX
Multi-Mode Transmit Driver multi-mode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal 100Base-FX mode, Manchester coded signal 10Base-T mode. 100Base-FX mode, filtering performed. transmit driver utilizes current drive output which well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BaseT mode, high frequency pre-emphasis performed extend cable-driving distance without external filter. pulses also drive through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level builtin bandgap reference external resistor connected RIBB pin. resistor sets output current modes operation. TXOP/N outputs open drain devices with serial source resistance max. When transformer used, current rating 2Vp-p MLT-3 signal, 5Vp-p Manchester signal. 1.25:1 transmit transformer output driver power reduction. This will decrease drive current 100Base-TX operation, 10Base-T operation. Adaptive Equalizer designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT5 cable this length typically attenuation MHz. typical attenuation 100meter cable worst case cable attenuation around 24-26 defined TPPMD specification. amplitude phase distortion from cable cause inter-symbol interference (ISI) which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability changes equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable. Clock Synthesizer includes on-chip clock synthesizer that generate clocks 100Base-TX circuitry. also generates clocks 10BaseT ANeg circuitry. clock generator uses fully differential cell that introduces very jitter. Zero Dead Zone Phase Detection method implemented design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. on-chip loop filter eliminates need external components minimizes external noise sensitivity. Only external clock source required reference clock. After power-on reset, clock synthesizer generates clock output until 100Base-X operation mode selected. Jabber (Heartbeat) After transmitter exceeds jabber timer (46mS), transmit loopback functions will disabled signal asserted. After TX_EN goes more than transmitter will reactivate gets de-asserted. Setting Jabber Disable will disable jabber function. When test enabled, pulse with 515BT asserted after each transmitted packet. enabled 10Base-T default, disabled Test Inhibit. Reverse Polarity Detection Correction Certain cable plants have crossed wiring twisted pairs; reversal TXIN TXIP. Under normal circumstances this would cause receive circuitry reject data. When Auto Polarity Disable cleared, ability detect fact that either NLPs burst FLPs inverted automatically reverse receiver's polarity. polarity state stored Reverse Polarity bit.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Auto Polarity Disable set, then Reverse Polarity written force polarity reversal receiver. pins, labeled LED_DATA[0:7] drive single pulse consistently timed interval. These signals enable signals LEDs. other pins, labeled LED_LN[0:7] drive actual information line. When LED_LN[n] signal true during period that corresponding LED_DATA[n] signal active, then will light. other cases, will light. information contained LED_LN[0:2] programmable (See register descriptions.) default state these outputs follows: LED_LN[7] Alert Coditions LED_DATA[7] Utilization Domain LED_DATA[6] Utilization Domain LED_DATA[5] Collision Domain LED_DATA[4] Collision Domain LED_DATA[3] Memory Domain LED_DATA[2] Memory Domain LED_DATA[1] Partition Domain LED_DATA[0] Partition Domain LED_LN[6] Collision Histogram Domain LED_LN[5] Collision Histogram Domain LED_LN[4] Utilization Histogram Domain LED_LN[3] Utilization Histogram Domain LED_LN[2] Programmable Synchronous LED_Data[n] LED_LN[1] Port Speed Partition Synchronous LED_Data[n] LED_LN[0] Port Link Activity Synchronous LED_Data[n]
INTER-REPEATER INTERFACE
busses provided allow connection between multiple AC108Rs, combinations AC108Rs AC105s. busses connect directly internal repeaters, 100M. necessary CSMA/CD parameters internal repeater busses. addition internal repeater busses, both 100M data transferred between multiple boxes stacked configuration. power reset stack change times, configuration multiple devices occurs.
INTERNAL REPEATER
AC108Rs configured within single box. Chip ID's selected through external pins.
100M INTERNAL REPEATER
INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled either high reset time. combination high values determines power state device. Many these pins multi-function pins which change their meaning when reset ends.
histogram features allow 8-segment graph attached corresponding outputs show utilization percentage specified condition. Collision Histogram event
SOFTWARE CONFIGURATION
Several different states operation chosen through software configuration. Please refer section well Register Descriptions.
Utilization Histogram
AUTO-NEGOTIATION
10/100 Transceiver able either 10Mbps over Twisted Pair Copper (10Base-T), 100Mpbs over Twisted Pair Copper (100Base-TX) 100Mpbs over Fiber Optics (100Base-FX) (port only). Because sections attached
LEDS
AC108Rx intricate, efficient scheme allowing different outputs while only using pins matrix.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
internal repeaters, they will only advertise operate half duplex mode. determine operational state, hardware selects software selects while also supporting AutoNegotiation Parallel Detection. 100Base-FX mode, selection must done through hardware configuration. There support Auto-Negotiation interface. Legitimate operating states are: 10Base-T Half Duplex 100Base-TX Half Duplex 100Base-FX Half Duplex (Port only) hardware configured force above mentioned modes. forcing mode, will only that mode, hence limiting locations where product will operate. able negotiate mode operation twisted pair environment using AutoNegotiation mechanism defined clause IEEE 802.3u specification. ANeg enabled disabled hardware software control. When ANeg enabled, chooses mode operation advertising abilities comparing them with ability received from link partner. configured advertise 100Base-TX 10Base-T operating half duplex. Auto-Negotiation Advertisement Register contains current capabilities each Phy, determined through hardware selects chip defaults. This information sent link partner during ANeg process using Fast Link Pulses (FLPs). string each which particular meaning, total which called Link Code Word. After reset, software change these bits from back from Therefore, hardware priority over software. When ANeg enabled, sends FLPs during following conditions: power link loss restart ANEG command During this period, continually sends FLPs while monitoring incoming FLPs from link partner determine their optimal mode operation. FLPs detected during this phase operation, Parallel Detection mode entered (see below). When receives identical link code words (ignoring acknowledge bit) from link partner, stores these code words, sets acknowledge generated FLPs, waits receive identical code word with acknowledge from link partner. Once this occurs configures itself highest technology that common both ends. technology priorities are: 100Base-TX, half-duplex 10Base-T half-duplex. Once ANeg complete, Auto-Negotiate Complete set, Status Register reflects negotiated speed, enters negotiated transmission reception state. This state will change until link lost reset through either hardware software, restart negotiation (Reg. 0.9) set.
PARALLEL DETECTION
Because there many devices field that support ANeg process, must still communicated with, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect: Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems, while maintaining flexibility Auto-Negotiation.
DIAGNOSTICS
Loopback Operation Local Loopback Remote Loopback provided testing purpose. They enabled through software. Local Loopback routes transmitted data through transmit path back receiving path's clock data recovery module. loopback data presented bits symbol format. This loopback used check operation 5-bit
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
symbol decoder phase locked loop circuitry. Local Loopback, output forced logic TXOP/N outputs tri-stated. Remote Loopback, incoming data passed through equalizer clock recovery, then looped back NRZI/MLT3 converter then transmit driver. This loopback used ensure device's connection media side. also checks operation device's internal adaptive equalizer, phase locked loop circuit, wave-shaper synthesizer. During Remote Loopback, signal detect (SD) output forced logic zero. Cable Length Indicator detect length cable it's attached display result Reg. 20.[7:4]. reading [0000] translates cable used, [0001] translates meter cable, [1111] translates meter cable. cable length value used network manage determine proper connectivity cable manage cable plant distribution Energy detect power saving mode: Energy detect mode turns power select internal circuitry when there live network connected. Energy Detect (ED) circuit always turned monitor there signal energy present media. circuitry also powered ready respond management transaction. transmit circuit still send link pulses with minimum power consumption. valid signal received from media, device will power resume normal transmit/receive operation. (Patent Pending) Reduced Transmit Drive Strength mode: Additional power saving gained level designing with 1.25:1 turns ration magnetic asserting TP125 reset.
CLOCK
clock input must clock oscillator measured MHz-100PPM.
BRIDGE FUNCTION RESET POWER
reset three ways: During initial power Hardware Reset: logic signal pulse width applied RST* pin. Software Reset: Write Control Register. Port always connected repeater core. Port Bridge connected repeater core Mode Port Mode collision domain called Domain "A", Domain respectively. switch engine interface presents 18-bit address memory access. SRAM buffer two-port switch contains address look-up table output data queue. address look-up table consists entries, layers with each entry occupies words; totaling words. remaining memory devoted output data queueing. buffer management, each packet occupies 1.5K, 1536 bytes.
BUFFER INTERFACE
Directly following reset, device will memory test external ram, download initial configuration from EEPROM. power consumption device significantly reduced built-in power management features. Separate power supply lines used power 10BaseT circuitry 100BaseTX circuitry. Therefore, circuits turnedon turned-off independently. When operate 100Base-TX mode, 10Base-T circuitry powered down, vice versa. following power management features supported: Power down mode: This achieved writing Control Register. During power down mode, device still able interface through SMI.
FORWARDING SCHEME
switch supports Store-and-Forward scheme only. does support Cut-Through-Forward. With Store-and-forward, incoming packet must completely received into buffer without error before forwarded.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
ADDRESS RECOGNITION
self-learning bridge function based source address field packets. switch uses 2-layer look-up table hashing. Each port switch engine will read, store compare contents Destination Address (DA) Source Address (SA) incoming packets. matches previously stored same port bridge, then packet will forwarded. does match, then packet will forwarded other port bridge. Broadcast packet will forwarded without comparison. remove possibility tables saturating, entries marked removed after certain period time. reception packet same port with same aging marker revised. Programmable aging time fast aging control supported.
MEDIA ACCESS CONTROL
switch engine implements functions IEEE 802.3 protocol such frame formatting, collision handling, etc. generates 56-bit preamble Start Frame delimiter while packet being sent. half duplex mode, switch will perform required functions CSMA/CD.
BUFFER MANAGEMENT
switch buffering management requires 1.5k, 1536 bytes, memory store packet. buffer size each port decided Mode[1:0] external size[1:0]. Mode sets both sides bridge 100M mode, therefore buffer made equal. other modes assumed that speed port will need more storage outgoing packets. switch uses five pointers control port buffer status. Start Address beginning point memory address each port Address point last entry. These registers determined reset. Read/Write Pointers dynamically changed depending current outgoing incoming packets storage. Packet Counter equal maximum number packets that stored, then buffer full packet dropped. other occurrences, packet stored next available buffer.
NETWORK MANAGEMENT
Management statistics maintained port, repeater switch basis. management information will retrieved through simple HDLC interface. Start Read Write Point
Packet Counter
Address Port Buffer Management
BUFFER ALLOCATION
Buffer Allocation SRAM Size[1:0] Mode[1:0] Lookup Table Maximum Packets Port (IBQA) Maximum Packets Port (IAQB) 00(128K) others Entries 01(256K) others 10(512K) others
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater REGISTER DESCRIPTIONS
internal register sets listed below. Each register contains 32-bit data. addresses shown below hexadecimal. Bold Definitions indicate group heading, Grayed Definitions indicates members Bolded group. Several Bolded groups show members because they same previously define group. Descriptions individual registers follows this table. Bank Base Addresss NOTE: When writing registers recommended that read/modify/write operation performed, unintended bits unwanted states. This applies register, including those with reserved bits. NOTE: registers define SA5-SA4 SA3-SA0 value 12-34-56-78-9a-bc: Example: SA5-SA4 xx-xx-bc-9a Example: SA3-SA0 78-56-34-12 Definition Port Repeater Readable Frame Count Readable Byte Count (Lower) Readable Byte Count (Upper) Count Alignment Error Count Long Frame Count Short Event Count Runt Count Collision Count Late Event Count Very Long Event Count Data Rate Mismatch Count Auto Partition Count Change Count Broadcast Count Multicast Count Port Repeater Port Repeater Port Repeater Port Repeater 100XCVR Counters Port Port Isolate Port Port Isolate Port Port Isolate Port Port Isolate Port Symbol Error Port Symbol Error Port Symbol Error Port Symbol Error Port RMON Statistic Counter Segment Byte Count (Lower) Byte Count (Upper) Packet Count Broadcast Count Type
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Bank Base Addresss Definition Multicast Count Alignment Error Count Undersize Count Oversize Count Fragment Count Jabber Count Collision Count Byte Count 65-127 Byte Count 128-255 Byte Count 256-511 Byte Count 512-1023 Byte Count 1024-1522 Byte Count Used Good Byte Count (Lower) Good Byte Count (Upper)Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Search SA3~SA0 Search SA5~SA4 Search Port Match Register Port Enable Control Register Port Authorized Address Learning Control Register Port Link Status Port Polarity Status Port Partition Status Port Speed Status Port Isolation Status (Fast Ethernet only) Port Change Status Reserved Repeater Configuration Type
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Bank Base Addresss Definition Repeater Serial Configuration Device/Revision Interrupt Status Interrupt Mask Port Status Repeater Reset Register Software Reset Register Bridge Configuration Register Bridge Configuration Register Registers Control Register Status Register Identifier Register Identifier Register Auto-Neg Advertisement Register Auto-Neg Link Partner Register Auto-Neg Expansion Register Auto-Neg Next Page Register Extended Control Register Adaptation Control Register Auto-Neg Test Register Reserved DLOCK Drop Counter Register Receive Error Counter Register Power Management Register Registers Registers Registers Registers Registers EEPROM Address EEPROM Address Registers Registers Effect Register Reserved Effect With Port Enable Event Effect With Partition/Isolation Event Effect With Link Event Effect With Activity (CRS) Event Effect With Autoneg Event Effect With Speed100 Event Ether-Like/Bridge Segment Single Frame Multiple Frame Deferred Transmission Late Frame Excessive Frame Delay Exceeded Discard Frame Type
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Bank Base Addresss Drop Event Count Drop Packet Count Global Register Port Repeater Port Repeater Port Repeater Port Repeater Used 100XCVR Counters Port RMON Statistic Counter Segment Byte Count(Lower) Byte Count(Upper) Packet Count Broadcast Count Multicast Count Alignment Error Count Undersize Count Oversize Count Fragment Count Jabber Count Collision Count Byte Count 65-127 Byte Count 128-255 Byte Count 256-511 Byte Count 512-1023 Byte Count 1024-1522 Byte Count Used Good Byte Count(Lower) Good Byte Count(Upper)Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Port Last SA3~SA0 Port Last SA5~SA4 Used Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Port Authorized SA3~SA0 Port Authorized SA5~SA4 Used Definition Type
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Bank Base Addresss Definition Ether-Like/Bridge Segment Single Frame Multiple Frame Deferred Transmission Late Frame Excessive Frame Delay Exceeded Discard Frame Drop Event Count Drop Packet Count Type
GLOBAL REGISTERS
Repeater Name Readable frame count Description Counts valid (error free) packets. Unicast-only (Reg.0ab) counts packets. Unicast-only (Reg.0ab) counts Unicast Packets only. Counts number Octets valid packets, including preamble framing bits. This counter affected Unicast-only bit.
Readable byte count (lower) Readable byte count (upper) count Alignment error count Long frame count Short event count
Runt count
Collision count Late event count
Very long event count Data rate mismatch count Auto partition count change count Broadcast count Multicast count
Counts valid length, collision-free packets that error, were correctly framed (had integral number octets). Counts valid length, collision-free packets that error were incorrectly framed (had non-integral number octets). Counts packets (good bad) that length greater than 1518 octets. Counts events that lasted less than ShortEventMaxTime. 100M ShortEventMaxTime times, ShortEventMaxTime times. Counts events longer than ShortEventMaxTime, shorter than ValidPacketMinTime; packets longer than ShortEventMaxTime, octets less than bytes. ValidPacketMinTime times. Counts number collisions that occurred, including late collision. Counts number collisions detected after LateEventThreshold. 100M: LateEventThreshold times. 10M: LateEventThreshold times. Counts events that lasted longer than Counts number times incoming data rate mismatched local clock source enough cause FIFO underflow overflow. Counts number times this port been partitioned Auto-partition Algorithm. Counts number times source address changed. Counts number good broadcast packets received this port. Counts number good multicast packets received this port.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100XCVR Counters Name Port Isolate Port Port Isolate Port Port Isolate Port Port Isolate Port Symbol Error Port Symbol Error Port Symbol Error Port Symbol Error Port Description Counts number times port auto isolates.
Counts number time packet contained least symbol error.
RMON Statistic Counter Name Byte count(lower) Byte count(upper) Packet count Broadcast count Multicast count Alignment error count Undersize count Oversize count Fragment count Description number data octets including those good packets octets fields, does include preamble other framing bits. number packets received from network, including good packets. number good broadcast packets received. number good multicast packets received. number valid-length packets that Frame Check Sequence. number well-formed packets that were smaller than octets. number well-formed packets that were longer than 1518 octets. number ill-formed packets less than octets. event without (0-octet oacket, e.g., jamed packets caused collision) will count fragment, matter long number ill-formed packets longer than 1518 octets. ill-formed packet with error. best estimate total number collision this interface. number packets (good bad) that were octets long. number packets (good bad) that were octets long. number packets (good bad) that were octets long. number packets (good bad) that were octets long. number packets (good bad) that were 1023 octets long. number packets (good bad) that were 1024 1518 octets long. total number octets contained valid frames received this segment.
Jabber count Collision count byte count 65-127 byte count 128-255 byte count 256-511 byte count 512-1023 byte count 1024-1518 byte count used Good byte count (lower) Good byte count (upper)
Port Last Address Registers Name Port last SA3~SA0 Port last SA5~SA4 Last received source address. Description
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Port Authorized Address Registers Name Port Authorized SA3~SA0 Port Authorized SA5~SA4 Search Address Registers Name Search SA3~SA0 Search SA5~SA4 Search Port Match Register Description Address used search function. Default 00-00-00-00-00-00 indicate which port matched Search Address. Description Address comparison. (see Port Learn Control Register)
31:9
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port Status Registers Name Port Enable Control Register Description Port Enabled MGR_PRES_ during reset, ports will disabled until management software re-enables them. Otherwise, ports will power enabled. LINK GOOD, default polarity been crossed, default port been partitioned, default 100M, 0:10M, default port been isolated, default source address changed, default Reserved Bits 31:2 Reserved 0=10M, 1=100M 1=Phy Mode (Always
Port Link Status Port Polarity Status Port Partition Status Port Speed Status Port Isolation Status (Fast Ethernet only) Port Change Status Reserved Port Status
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Port Enable Control Register 30:19 17:16 15:14 13:12 11:10 Name LFSR_TEST Reserved RAMBIST_STAT auth_cntl9 auth_cntl8 auth_cntl7 auth_cntl6 auth_cntl5 auth_cntl4 auth_cntl3 auth_cntl2 auth_cntl1 Description Reduce LFSR timer Jabber, Partition. Internal SSRAM BIST Result. 0=Pass, 1=Fail. port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Learn Each Learn first only, then change these bits "10" thus locking down address. Lock. Hardware locked down address, only software write this address. Reserved. Mode Default
Interrupt Registers Name Interrupt Status Interrupt Mask Match 29:8 Default Mask, 0=UnMask Fault Jabber Isolation Partition Change Speed Change Description
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Repeater Configuration Register 31:15 14:13 Name Reserved Mode Description Stack Master Port Bridge Stand Alone Port Stand Alone Port Bridge Port. Port connected bridge port this mode. other bridge port connected segment. Illegal configuration enable Late Event counter. disable Late Event counter. causes Interrupt Status Register, Search Port Match Register, Change status registers auto-clear when read. requires that appropriate register written clear. This done writing bit(s) that cleared. enable statistics gathering, disable. function. disable 100M stack signals external backplane transceiver. enable. disable stack signals external backplane transceiver. enable. Changes definition ReadFrames counter count Unicast packets only. counts unicast only. counts packets. read from Arbit input pin. Writing will reset counters, this will reset after counters have been cleared. Mode Default MODE pins
Late enable Write clear enable
enable Send Isolate Isolate Unicast only
Arbit Input Value Reset Counter Reserved Reserved 100M repeater Partition Alternative
repeater Partition Alternative
un-partition port only when data transmitted from port bit-time without collision. un-partition port when data either transmitted from port received from port bit-time without collision. un-partition port when data either transmitted from port received from port bit-time without collision. un-partition port only when data received from port bit-time without collision
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Miscellaneous Registers Name Repeater Serial Configuration Device/Revision Repeater Reset Register Software Reset Register EEPROM Address EEPROM Address Description This 8-bit register holds user-defined data write this register causes repeater logic Reset. write this register identical hardware reset. Bits 47:16 EEPROM serial number. Bits 15:0 EEPROM serial number.
Bridge Configuration Register 31:15 Name Reserved Disable Switch Disable Aging Fast Aging Enable Aging Timer Description 0=enable, 1=disable switch function 0=enable, 1=disable Aging function Seconds Unit, Seconds Unit This count times Seconds unit equals Aging Timout. 010h Seconds unit 4800 Seconds 010h Seconds unit Seconds Mode Default
Bridge Configuration Register 31:16 15:8 Name Reserved Timer1 Description 10/100M segment adjustment. sign bit. When value 96BT. unit will increase decrease mode mode. 10/100M segment adjustment. sign bit. When value 96BT. unit will increase decrease mode mode. Mode Default
Timer0
Effect with Port Enable Event. 15:12 10:8 Name Blink Rate [3:0] Reserved with Port Enable Event Reserved Blink with Port Enable Event Reserved with Port Enable Event Description blink rate bits [3:0] When Port Enable, turn corresponding 2:0. Mode Default 0000
When Port Enable, blink corresponding 2:0.
When Port Enable, turn corresponding 2:0.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Effect with Partition/Isolation Event. 15:12 10:8 Name Blink Rate [7:4] Reserved with Part/ISO Event Reserved Blink with Part/ISO Event Reserved with Part/ISO Event Description blink rate bits [7:4]. When Partition/Isolation, turn corresponding 2:0. Mode Default 0001
When Partition/Isolation, blink corresponding 2:0.
When Partition/Isolation, turn corresponding 2:0.
Effect with Link Event. 15:11 10:8 Name Reserved with Link Event Reserved Blink with Link Event Reserved with Link Event Description When Link turn corresponding 2:0. Mode Default 00000
When Link blink corresponding 2:0.
When Link turn corresponding 2:0.
Effect with Activity (CRS) Event. 15:11 10:8 Name Reserved with Activity Event Reserved Blink with Activity Event Reserved with Activity Event Description When Activity, turn corresponding 2:0. Mode Default 00000
When Activity, blink corresponding 2:0.
When Activity, turn corresponding 2:0.
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Effect with Auto-Negotiating Event. 15:11 10:8 Name Reserved with Auto-negotiating Event Reserved Blink with Auto-negotiating Event Reserved with Auto-negotiating Event Description When Auto-negotiating, turn corresponding 2:0. Mode Default 00000
When Auto-negotiating, blink corresponding 2:0.
When Auto-negotiating, turn corresponding 2:0.
Effect with Speed100 Event. 15:11 10:8 Name Reserved with Speed100 Event Reserved Blink with Speed100 Event Reserved with Speed100 Event Description When Speed100, turn corresponding 2:0. Mode Default 00000
When Speed100, blink corresponding 2:0.
When Speed100, turn corresponding 2:0.
Register Control Mode. 15:8 Name Data Column Description value shown LED_DATA [7:0]. Control which lane LED_DATA should turned Mode Default
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
REGISTERS
following registers defined each port. register addresses offset addresses. actual address calculated with their base address. base addresses PHY-0 PHY-7 0C0, 0E0, 100, 120, 140, 160, 1A0, respectively. addresses hexadecimal. Control Register Name Reserved Loopback Description Loopback mode, which internally loops transmit receive, thus will ignore activity cable media. Normal operation. 100Mbps 10Mbps. This will ignored Auto-Negotiation enabled. will longer reflect auto-negotiation result. Enable auto-negotiate process (overrides 0.13 0.8) Disable auto-negotiate process. force mode, speed selected 0.13. Power down mode, which puts device low-power stand-by mode, which only react management transaction. Normal operation. Electrical isolation from cable media. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Full duplex supported this chip. will longer reflect auto-negotiation result. Enable collision test, which issues signal response assertion TX_EN signal. Disable test. Mode Default
Speed Select
Auto-Neg Enable
Power Down
(Port depends fxsel mode) (Port depends fxsel mode)
Isolate Restart AutoNegotiation Duplex Mode
Collision Test
Reserved
000000
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Status Register 10:6 Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Auto-Negotiate Complete Remote Fault Description Tied zero indicates 100BaseT4 capability. Tied zero indicates 100BaseTX full duplex support. 100BaseTX with half duplex. Half-Duplex ability. Tied zero indicates 10Base-T full duplex support. 10BaseT with half duplex. 10BaseT Half-Duplex ability. Auto-negotiate process completed, indicates Reg. valid. Auto-negotiate process completed. Remote fault condition detected. remote fault. After this set, will remain until clear reading register management interface. Able perform auto-negotiation function, value determined ANEGA pin. Unable perform auto-negotiation function. Link established, however, link fails, this will become cleared remain cleared until register read management interface. Link down, have been dropped. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. Mode Default 00000
SC/LH
Auto-Negotiate Ability Link Status
SC/LL
Jabber Detect Extended Capability
SC/LH
Identifier Register 15:0 OUI* Name
Description Assigned through bits Organizationally Unique Identifier (OUI), respectively.
Mode
Default 0022 (HEX)
Identifier Register 15:10 Name Model Number Revision Number
Description Assigned through bits OUI. manufacturer's model number; encoded 010001. Four bits manufacturer's revision number. 0001 stands Rev. etc.
Mode
Default 010101 011000 0001
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Auto-Negotiation Advertisement Register 12:10 Name Next Page Acknowledge Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field Description Desire Next Page. Next Page desired. This will internally after receiving consecutive consistent bursts. Remote fault detected. remote fault. future technology. Tied zero indicates 100Base-T4 support. 100BaseTX with full duplex. 100BaseTX full duplex ability. 100BaseTX capable. 100BaseTX capability. 10Mbps with full duplex. 10Mbps with full duplex capability. 10Mbps capable. 10Mbps capability. [00001] IEEE 802.3. Mode Default 00001
Auto-Negotiation Link Partner Ability Register 15:0 Name Technology Description Technology capability field, which indicates technology capability link partner. definition same Reg. 4.15:0. Mode Default 0001(H)
Auto-Negotiation Expansion Register 15:5 Name Reserved Description Mode Default 0000 0000
Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto-Negotiation Able
Fault detected parallel detection logic. This caused unstable link, concurrent link condition. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. link code word been received. contains received link code word located Register Link partner auto-negotiation able. Link partner auto-negotiation able.
SC/LH
SC/LH
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Auto-Negotiation Next Page Transmit Register Name Reserved Message Page ACK2 Description Another Next Page desired. Message page. Un-formatted Page. Acknowledge2. Will comply with message. comply with message. Previous value transmitted Link Code Word equal Previous value transmitted Link Code Word equal Message/Un-formatted Code Field. Mode Default
Toggle
10:0
Code
0001
Extended Control Register Name Repeater Disable Description Repeater mode. only responds receive activity. mode. Disable carrier integrity monitor function. Default when autoneg enable. Once speed 100mbps, this will `0'. Enable generation detection. Enable generation detection. When selected, should enabled. Otherwise, should disabled. Enable mode. Disable mode. Uses 1.25:1 transformer. Uses transformer. Select internal common voltage setting. Select external common voltage setting. Disable scramble. Enable scramble. Mode Default
Enable
TP125 Select Scramble Disable
0/Port depend fxsel
Reserved
0000 0000
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
Auto-Negotiation Test Register. Name loop back Force Send Description Link pulse loop back mode. Normal operation. Force link control state machine send even auto-negotiation mode. Normal operation. Force link integrity state machine link state. Normal operation. Force link monitor link state. Normal operation. Auto-Negotiation result Auto-Negotiation result Auto-Negotiation result full duplex. Auto-Negotiation result half-duplex. Highest state Auto-Negotiation State Machine since reset last read operation. Mode Default
11:10
Force Link Force Link Reserved Arb_Speed
Depends ANeg result Depends ANeg result 0000 Depends ANeg state 1111 Depends ANeg state
Arb_Duplex
Arbitration State High
SC/R
Arbitration State
Lowest state Auto-Negotiation State Machine since reset last read operation.
SS/R
Receive Error Counter 15:0 Name Receive Error Counter Description Number Receive Error Event. Mode Default 0000
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater EEPROM TABLE
Table locations information required initial setup Bridge, Repeater Transceiver. Address Description First Word Port Enable port Authorized Address Learning Mode. Port Authorized Address Learning Mode. Initial Repeater Configuration Registers Initial Repeater Serial Configuration Bridge Configuration Register Bridge Configuration Register Reserved Reserved Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Initialize Port Control Register Initialize Port Extended Control Register Test Control Register Effect with Port Enable Event Effect with Partition/Isolation Event Effect with Link Event Effect with Activity (CRS) Event Effect with AutoNeg Event Effect with Speed100 Event Bits 47:32 EEPROM serial number. Bits 31:16 EEPROM serial number. Bits 15:0 EEPROM serial number. Assign 0BF[17:9] 0BF[8:0] 190[31:16] 190[15:0] 191[15:0]
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater 4B/5B CODE-GROUP TABLE
Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 SYMBOL Name (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle Control Code 0000 0101 0101 Undefined Undefined Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater ELECTRICAL CHARACTERISTICS
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55o +150o Supply Referenced GND. -0.5V +5.0V Digital Input Voltage. -0.5V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature(Ta) +70o Supply Voltage Range(Vcc) 2.97V 3.63V
Total Power Consumption Parameter Supply Current (per port) Symbol Conditions Base-T, Idle Base-T, Normal activity Base-TX Base-FX 10/100 Base-TX, power without cable Power down Mode Mode Mode Units
Supply Current (dual speed hub)
Characteristics Parameter Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance Output Transition Time Tristate Leakage Current Symbol 3.15V 3.45V |Ioz| Conditions VCC-0.4 Units
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
REFCLK XTAL Pins Parameter Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Conditions Units
Characteristics LED/CFG Pins Parameter Output Voltage Output High Voltage Input Current Output Current Symbol Conditions Units
BASE-TX Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance Symbol Trfs Conditions Note Note Note Note 1.02 ±250 Note resistor each output Units
Scrambled Idle Transformer 1.25:1 Transformer
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
BASE-T Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance Symbol Conditions Note Transformer 1.25:1 Transformer Units
Note resistor each output
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater DIGITAL TIMING CHARACTERISTICS
Power Reset Parameter RST* Period Configuration tRST tCONF Conditions Units
tRST
RST* Configuration Pins Power Reset Timing
tCONF
Management Data Interface Parameter CLOCK CLOCK Receive Data Setup Receive Data Hold Transmit Data Delay tMDCL tMDCH tRDS tRDH tTDD Conditions Units
Setup Read Cycle Hold Read Cycle Delay Write Cycle
tMDCL
tMDCH
SER_CLK
tRDS
tRDH
tTDD
Management Data Interface Timing
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100Base-TX/FX Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TX_EN TX_EN sampled TX_EN sampled !TX_EN !TX_EN sampled !CRS !TX_EN sampled !COL Propagation Delay TXD[3:0], TX_EN, TX_ER Setup TXD[3:0], TX_EN, TX_ER Hold !TX_EN TX_EN tCKH tCKL tCSA tCLA tCSD tCLD tTXS tTXH tTX_TX Start Packet tCKL Conditions 39.998 18.000 18.000 Packet 40.000 20.000 20.000 40.002 22.000 22.000 Units
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N(FXTP/N) From rising edge TX_CLK From rising edge TX_CLK
tCKH
TX_CLK
tTXS
TX_EN
tTX_TX tTXH
TXD[3:0] TX_ER
TXOP/N
FXTP/N
tTCSA
tTCSD
tTCLA
100Base-TX/FX Transmit Timing
tTCLD
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100Base-TX/FX Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period /J/K RX_DV assert /J/K assert /J/K assert /T/R !RX_DV /T/R !CRS /T/R !COL Propagation Delay RXD[3:0], RX_DV, RX_ER Setup RXD[3:0], RX_DV, RX_ER Hold tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions 39.998 18.000 18.000 40.000 20.000 20.000 40.002 22.000 22.000 Units
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N(FXRP/N) RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
tCKH
RX_CLK
Start Packet tCKL
Packet
tRDVA
RX_DV
tRDVD tRXS tRXH
RXD[3:0] RX_ER /J/K RXIP/N /T/R
FXRP/N
tRCSA
tRCSD
tRCLA
100Base-TX/FX Receive Timing
tRCLD
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
10Base-T Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TX_EN TX_EN sampled TX_EN sampled !TX_EN !TX_EN sampled !CRS !TX_EN sampled !COL Propagation Delay TXD[3:0], TX_EN, TX_ER Setup TXD[3:0], TX_EN, TX_ER Hold !TX_EN TX_EN tCKH tCKL tTCSA tTCLA tTCSD tTCLD tTXS tTXH tTX_TX Start Packet tCKL Conditions 399.98 180.00 180.00 Packet 400.00 200.00 200.00 400.02 220.00 220.00 Units
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N From rising edge TX_CLK From rising edge TX_CLK
tCKH
TX_CLK
tTXS
TX_EN
tTX_TX tTXH
TXD[3:0] TX_ER
TXOP/N
tTCSA
tTCSD
tTCLA
10Base-T Transmit Timing
tTCLD
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
10Base-T Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period RX_DV !RX_DV !CRS !COL Propagation Delay RXD[3:0], RX_DV, RX_ER Setup RXD[3:0], RX_DV, RX_ER Hold tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions 399.98 180.00 180.00 400.00 200.00 200.00 400.02 220.00 220.00 Units
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
tCKH
RX_CLK
Start Packet tCKL
Packet
tRDVA
RX_DV
tRDVD tRXH
tRXS
RXD[3:0] RX_ER RXIP/N
tRCSA
tRCSD
tRCLA
10Base-T Receive Timing
tRCLD
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
100Mbps Internal Stacked Repeater Receive Transmit System Timing Parameter Conditions Units
MS100D_CLK period MS100D_CLK High period tCKH MS100D_CLK period tCKL /J/K (SOP) Control /T/R (EOP) !Control Control MS100D_CLK MS100D[0:4] Setup MS100D[0:4] Hold Control TXOP/N tCLT !Control !TXOP/N tCHT Control combination following signals: 100CRSU_IN*, 100CRSD_IN*, 100CRSU_OUT*, 100CRSD_OUT*, 100COLBP*, 100CRSBP*, 100OE*, 100DIR*, M100COL_LOCAL*, M100ACT0*, M100ACT1_0*, M100ACT1_1*, M100ACT1_2*, M100COL_SYS*, M100CRS_SYS*, MS100D_EN* Different signals valid different scenarios, active time same. Start Packet
RXIP/N
Packet
Control*
tCKH
MS100D_CLK
tCKL
MS100D[0:4]
tCLT
TXOP/N
tCHT
100Mbps I/SRB Receive Transmit Timing
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
10Mbps Internal Stacked Repeater Receive Transmit System Timing Parameter Conditions Units
MS10D_CLK period MS10D_CLK High period tCKH MS10D_CLK period tCKL /J/K (SOP) Control /T/R (EOP) !Control Control MS10D_CLK MS10D[0:4] Setup MS10D[0:4] Hold Control TXOP/N tCLT !Control !TXOP/N tCHT Control combination following signals: 10CRSU_IN*, 10CRSD_IN*, 10CRSU_OUT*, 10CRSD_OUT*, 10COLBP*, 10CRSBP*, 10OE*, 10DIR*, M10COL_LOCAL*, M10ACT0*, M10ACT1_0*, M10ACT1_1*, M10ACT1_2*, M10COL_SYS*, M10CRS_SYS*, MS10D_EN* Different signals valid different scenarios, active time same. Start Packet
RXIP/N
Packet
Control*
tCKH
MS10D_CLK
tCKL
MS10D[0:4]
tCLT
tCHT
TXOP/N
10Mbps I/SRB Receive Transmit Timing
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
SRAM Read Cycle Parameter Read Cycle Address Valid Output Hold Access High tOEA tOELZ tOEHZ
RAMA 0:17
Conditions
Units
tOELZ
RAMD 0:15
tOEA
tOEHZ
SRAM Read Cycle
SRAM Write Cycle Parameter Write Cycle Pulse Width Address Setup Address Hold from Data Setup Data Hold tASWE tAHWE
RAMA 0:17
Conditions
Units
tAHWE
tASWE
RAMD 0:15
SRAM Write Cycle
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater
SRAM Write Cycle Parameter Pulse Width DATA[n] DATA[n+1] DATA[n] DATA[n] Conditions Units
LED_ LN[7:0] LED_DATA7 LED_DATA6 LED_DATA5 LED_DATA4 LED_DATA3 LED_DATA2 LED_DATA1 LED_DATA0
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation
3.3V
49.9
49.9
AC108Rx TXON TXOP Transformer TXC_P TXC_S TX+_P TX+_S TX-_P TX-_S RX+_P RX-_P RXC_P
IBREF
RX+_S RX-_S RXC_S
RJ45 Unused Unused Unused Unused
RXIP
1000
RXIN
Chassis
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AC108 RM/RU/RN Ultra Power 10/100 Bridged Repeater APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation enable mode, FX_SEL7 must pulled high resistor.
3.3V 69.8 69.8
HFBR-5903 AC108Rx RXVee RXVcc TXVcc TXVee
FXRN
FXRP
FXTP FXTN
FX_SEL7
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