AC104Z-QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-

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AC104Z-QF Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver GENERAL DESCRIPTION
AC104Z-QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented 0.35µm CMOS technology. Multiple modes operation, including normal operation, test mode power saving mode, available through either hardware software control. Features include interfaces, ENDECs, Scrambler/Descrambler, Auto-Negotiation (ANeg) with support parallel detection. transmitter includes dual-speed clock synthesizer that only needs external clock source. chip built-in wave shaping driver circuit both 10Mbps 100Mbps, eliminating need external hybrid filter. receiver adaptive equalizer restoration circuit accurate clock data recovery 100Base-TX signal. also provides on-chip pass filer Squelch circuit 10Base-T signal. interfaces support four ports 10/100 RMII SMII. Media Interfaces 10/100TX/FX. support four ports
SMII RMII interfaces 10/100 Base TX/FX Full Duplex Half Duplex FEFI 100FX Very small package 128PQFP Very power 280mW port) Cable Detect mode 40mW port) Power Down mode 3.3mW port) Selectable drivers 1.25:1 transformers additional power reduction 3.3Volt, 0.35micron CMOS (S/R)MII 5Volt tolerant 2.5Volt capable Fully compliant with IEEE 802.3 802.3u SMII/ RMII test labs Baseline Wander Compensation Multi-Function outputs Cable length indicator Reverse polarity detection correction with Register indication Automatic Forced programmable interrupts Diagnostic registers JTAG Boundary Scan
BLOCK DIAGRAM
Port Port Port Port
.Framer .Carrier Detect .4B/5B .Clock Recov. .Link Monitor .Signal Detect TP_PMD 100TX .MLT-3 .BLW .Stream Cipher
100RX
RXIP/N TXOP/N(0) FXRP/N FXTP/N(0) RXIP/N TXOP/N(1) FXRP/N FXTP/N(1) RXIP/N TXOP/N(2) FXRP/N FXTP/N(2)
SMII/RMII
TXOP/N(3)
10TX
RXIP/N(3)
Interface
JTAG Boundary Scan
10BASE-T
10RX
FXTP/N(3) FXRP/N(3)
Control/Status
Serial Management Interface Registers
Gen. Test/LED Control
AutoNegotiation
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] Drivers
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
General Description. Features Block Diagram. Diagram AC104Z-QF. Descriptions (Media Dependent Interface) Pins SMII (Serial Media Independent Interface) Pins.7 RMII (Reduced Media Independent Interface) Pins.7 (Serial Management Interface) Pins Address Pins.8 Mode Pins Pins Miscellaneous Pins.9 JTAG Pins.9 Power Ground Pins Connect Pins Functional Description.11 Interface.11 RMII SMII.11 SMI.11 Interrupt.12 Carrier Sense RX_DV.12 Media Interface 10Base-T Transmit Function.12 Receive Function Link Monitor.13 100Base-TX Transmit Function.13 Parallel Serial, NRZI, MLT3 Conversion.13 Receive Function Baseline Wander Compensation.14 Clock/Data Recovery Decoder/De-scrambler.14 Link Monitor.14 100Base-FX.14 Transmit Function.15 Receive Function Link Monitor.15 Far-End-Fault-Indication (FEFI).15 10Base-T/100Base-TF/FX Multi-Mode Transmit Driver.15 Adaptive Equalizer.15 Clock Synthesizer.15 Jabber (Heartbeat).16 Reverse Polarity Detection Correction Initialization Setup.16 Hardware Configuration Software Configuration Jumbo Packets LEDs Auto-Negotiation.16 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Parallel Detection.17 Diagnostics.17 Loopback Operation.17 Cable Length Indicator.18 Reset Power.18 Clock.18 Register Descriptions Registers 1-7.19 Registers 8-31 Register Control Register.20 Register Status Register.21 Register Identifier Register.21 Register Identifier Register.21 Register Auto-Negotiation Advertisement Register.22 Register Auto-Negotiation Link Partner Ability Register.22 Register Auto-Negotiation Expansion Register.22 Register Auto-Negotiation Next Page Transmit Register.23 Register Polarity Interrupt Level Register.23 Register Interrupt Control/Status Register.24 Register Test Register.24 Register Cable Measurement Register Register Receive Error Counter Register.24 Register Operation Mode Register.25 Register recent received packet.25 Mode Table Common Registers.26 Common Register (Map port Operation Mode Register.26 Common Register (Map port Test Mode Register.26 Common Register (Map port LEDSPD Setting1 Register.27 Common Register (Map port LEDSPD Setting2 Register.27 Common Register (Map port LEDACT Setting1 Register.27 Common Register (Map port LEDACT Setting2 Register.27 Common Register (Map port LEDDPX Setting2 Register.28 Common Register (Map port LEDDPX Setting2 Register.28 Common Register (Map port Blink Rate Common Register Port Table.28 Common Register Mask Table 4B/5B Code-Group Table Read/Write Sequence Configurations.30 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings.31 Operating Range Total Power Consumption.31 Characteristics REFCLK XTAL Pins Characteristics LED/CFG Pins BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics.33 BASE-FX Transceiver Characteristics.33 BASE-T Link Integrity Timing Characteristics.33 Digital Timing Characteristics Power Reset.34 Management Data Interface 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-TX/FX 10Base-T RMII Transmit System Timing.35 100Base-TX/FX 10Base-T RMII Receive System Timing 100Base-TX/FX 10Base-T SMII Transmit System Timing.37 100Base-TX/FX 10Base-T SMII Receive System Timing.38 Application Termination Application Termination.40 Power ground filtering AC104Z-QF Package drawing AC104Z-QF.42
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
DIAGRAM AC104Z-QF
CVDD RXD[0](0) RXD[1](0) OVDD TX_EN(1) TXD[0](1) TXD(0) TXD[1](1) TXD(1) CGND OGND CRS_DV(1) RX_ER(1) MODE1 RXD[0](1) RXD(0) RXD[1](1) RXD(1) OVDD REFCLK VDD_PLL MCLK_IN MCLK_OUT GND_PLL MDIO TX_EN(2) SYNC OVDD TXD[0](2) TXD(2) TXD[1](2) TXD(3) OGND CRS_DV(2) RX_ER(2) RXD[0](2) RXD(2) RXD[1](2) RXD(3) CVDD TX_EN(3) CGND TXD[0](3)
RX_ER(0) CRS_DV(0) CGND TXD[1](0) TXD[0](0) TX_EN(0) OGND LEDDPX(1) PHYAD[4] LEDACT(1) PHYAD[3] LEDSPD(1) PHYAD[2] LEDDPX(0) LEDACT(0) LEDSPD(0) TP125 INTR RST* GAGND IBREF GAVDD GAVDD AVDD
AC104Z-QF
TRST TXD[1](3) CGND CRS_DV(3) RX_ER(3) PHYAD_ST RXD[0](3) RXD[1](3) OVDD LEDSPD(2) FORCE100 LEDACT(2) MODE0 LEDDPX(2) LEDSPD(3) BURN_IN LEDACT(3) ANEGA LEDDPX(3) SCRAM_EN FXTN(3) FXTP(3) FXRN(3) TST[3] FXRP(3) TST[2] TST[1] SDP(3)/TST[0] FX_EN(3) AVDD
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AVDD RXIN(A) FXRN(0) RXIP(A) FXRP(0) AGND SDP(A) FX_EN(0) AGND TXOP(A) FXTP(0) TXON(A) FXTN(0) AVDD AVDD TXON(B) FXTN(1) TXOP(B) FXTP(1) AGND SDP(B) FX_EN(1) AGND RXIP(B) FXRP(1) RXIN(B) FXRN(1) AVDD AVDD RXIN(C) FXRN(2) RXIP(C) FXRP(2) AGND SDP(C) FX_EN(2) AGND TXOP(C) FXTP(2) TXON FXTN(2) AVDD AVDD TXON(3) TXOP(3) AGND AGND RXIP(3) RXIN(3) AVDD VCMI(2)
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
DESCRIPTIONS
Many pins these devices have multiple functions. multi-function pins will designated bolding number. separate descriptions these pins will listed proper sections. Designers must assure that they have identified modes operation prior final design. NOTES: assignment shown below description table subject change without notice. user advised contact Altima (Media Dependent Interface) Pins Name RXIN(0) RXIN(1) RXIN(2) RXIN(3) RXIP(0) RXIP(1) RXIP(2) RXIP(3) TXON(0) TXON(1) TXON(2) TXON(3) TXOP(0) TXOP(1) TXOP(2) TXOP(3) FXRN(0) FXRN(1) FXRN(2) FXRN(3) FXRP(0) FXRP(1) FXRP(2) FXRP(3) FXTN(0) FXTN(1) FXTN(2) FXTN(3) FXTP(0) FXTP(1) FXTP(2) FXTP(3) Type
Communications Inc. before implementing design based information provided this data sheet. Signals types: inputs outputs high impedance internal pull internal pull down analog signal Active Signal Connect
Description Receiver input Negative both 10Base-T 100Base-TX.
Receiver input Positive both 10Base-T 100Base-TX.
Transmitter output Negative both 10Base-T 100Base-TX.
Transmitter output Positive both 10Base-T 100Base-TX.
Receiver input Negative 100Base-FX.
Receiver input Positive 100Base-FX.
Transmitter output Negative 100Base-FX.
Transmitter output Positive 100Base-FX.
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AC104Z-QF
Name SDP(0) SDP(1) SDP(2) SDP(3)
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Type Description Signal Detect Input. Indicates signal quality status fiber-optic link 100Base-FX mode. When signal quality good, should driven high relative pin. bias level that work pair with SDP[0.3] pins. sets switch threshold SDP[0.3] pins. should externally volt most applications.
SMII (Serial Media Independent Interface) Pins Name TXD(0) TXD(1) TXD(2) TXD(3) RXD(0) RXD(1) RXD(2) RXD(3) SYNC REFCLK Type I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O, Description SMII Transmit Data. will source TXD(n) synchronous with REFCLK.
SMII Receive Data. will source RXD(n) synchronous with REFCLK.
Synchronous with REFCLK indicate start stream. Reference Clock Input MHz-100PPM
RMII (Reduced Media Independent Interface) Pins Name TXD[1:0](0) TXD[1:0](1) TXD[1:0](2) TXD[1:0](3) TX_EN(0) TX_EN(1) TX_EN(2) TX_EN(3) RXD[1:0](0) RXD[1:0](1) RXD[1:0](2) RXD[1:0](3) CRS_DV(0) CRS_DV(1) CRS_DV(2) CRS_DV(3) RX_ER(0) RX_ER(1) RX_ER(2) RX_ER(3) REFCLK 107,108 94,95 75,76 61,66 98,99 88,89 70,71 56,57 Type I/O, I/O, I/O, I/O, I/O,D I/O,D I/O,D I/O,D I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O,D I/O,D Description RMII Transmit Data. will source TXD[1:0](n) synchronous with REFCLK when TX_EN(n) asserted.
RMII Transmit Enable. TX_EN(n) asserted high indicate that valid data transmission presented TXD[1:0](n).
RMII Receive Data. will source RXD[1:0](n) synchronous with REFCLK when CRS_DV(n) asserted.
CRS_DV(n) asserted high when media non-idle.
RMII Receive Error. When RX_ER asserted high, indicates error been detected during frame reception.
Reference Clock Input MHz-100PPM
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
(Serial Management Interface) Pins Name MDIO INTR Type I/O, Description Management Data Input/Output. Bi-directional data interface. external 1.5K pull resistor required specified IEEE-802.3). Management Data Clock. clock sourced transfer MDIO data. Interrupt. Registers polarity sources. INTR high impedance output, pull-up pull-down resistor needed.
Address Pins Name PHYAD_ST PHYAD PHYAD PHYAD Type I/O,D I/O,U I/O,U I/O,U Description reset 0-XXX00, 1-XXX01, 2-XXX10, 3-XXX11 reset 0-XXX01, 1-XXX10, 2-XXX11, 3-XXX00 Address [4:2]. These pins three MSB's address. PHYAD [1:0] internally wired four ports. (See PHYAD_ST) PHYAD will also determine scramble seed. This will help reduce when there multiple ports switching same time.
Mode Pins Name FX_EN(0) FX_EN(1) FX_EN(2) FX_EN(3) TP125 FORCE100 Type AI/O Description Enable (per port). Pulled upon reset will Port(n) mode. Pull above upon reset will port(n) 100FX mode.
SCRAM_EN ANEGA BURN_IN* MODE0 MODE1
I/O,U I/O,D
Transformer Ratio. Pulled upon reset will select transmit transformer ratio 1.25:1. Pulled high transformer. FORCE100: Force 100Base-X Operation. When this signal pulled high ANEGA upon reset, ports will forced 100Base-TX operation. When asserted ANEGA low, ports forced 10Base-T operation. When ANEGA high, FORCE100 effect operation. Scrambler Enable. Pulled upon reset bypasses scrambler. Pulled high enables scrambler. Auto-Negotiation Ability. Asserted high means auto-negotiation enabled while means manual selection through DPLX FORCE100. Burn-In mode. Burn-in mode reliability assurance control. This reserved internal testing only. Mode1 Mode0 SMII SMII with Jumbo Packets RMII Invalid
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AC104Z-QF
Pins
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Name LEDDPX[0] LEDDPX[1] LEDDPX[2] LEDDPX[3] LEDACT LEDACT LEDACT LEDACT LEDSPD[0] LEDSPD[1] LEDSPD[2] LEDSPD[3]
Type
Description
I/O,U Port[n] Duplex LED. Active state indicates Full Duplex Collision Half I/O,U Duplex mode. I/O,U I/O,U I/O,U Port[n] Activity/Link LED. Active state indicates valid link. When there I/O,U receive transmit activity, will toggle between high I/O,U intervals. I/O,U I/O,U Port[n] Speed LED. Active state indicates 100Base-TX mode. I/O,U I/O,U I/O,U (Polarity LEDs determined polarity mode pins. example.)
Miscellaneous Pins Name RST* Type Description Reset. active input will force chip known initialization state. Setting Reg. 0.15 will assert software reset, which same functionality hardware reset. Must tied directly MCLK_OUT. Must tied directly MCLK_IN. Reference Bias Resistor. Must tied analog ground through external (1%) resistor. Test. Outputs during test mode.
MCLK_IN MCLK_OUT IBREF TST[0] TST[1] TST[2] TST[3] JTAG Pins Name TRST
A/I,O
Type Boundary Scan Input Boundary Scan Control Boundary Scan Reset Boundary Scan Clock Boundary Scan Output
Description
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AC104Z-QF
Power Ground Pins Name OVDD OGND CVDD CGND AVDD 121,122 Type Description Digital +3.3V power supply I/O. Digital ground I/O. Digital +3.3V power supply Core logic. Digital ground Core logic. +3.3V power supply Analog circuit.
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
AGND
Ground Analog circuit.
GAVDD GAGND VDD_PLL GND_PLL
+3.3V power supply common analog circuits. Ground common analog circuits. Power supply SMII circuit. Ground SMII circuit.
Connect Pins Name 101, 102, 128, 123, 127, 124,126, Type Connect. Description
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AC104Z-QF Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver 100M mode will read bits from TXD[1:0] FUNCTIONAL DESCRIPTION
AC104Z-QF physical layer device (Phy) integrates 100Base-X 10Base-T functions single four port chip that used Fast Ethernet 10/100 Mbps applications. 100Base-X section consists PCS, PMA, functions 10Base-T section consists Manchester ENDEC transceiver functions. device performs following functions: 4B/5B MLT3 NRZI Manchester Encoding Decoding Clock Data Recovery Stream Cipher Scrambling De-Scrambling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg) SMII RMII connectivity Management Function each cycle REFCLK. mode will read bits data from TXD[1:0] every 10th cycle REFCLK.
Serial Management Interface (SMI) REFCLK shared between ports Phy. This totals pins port plus Phy, whereas pins port.
SMII
Serial Media Independent Interface (SMII) used connect with MAC. obtain their clock, REFCLK, from common source, such clock oscillator. Every REFCLK times, pulse generated SYNC indicate start each serial data word both pins. clock SYNC shared ports within transmitting receiving data individual serial data buses. bits receive CRS, RX_DV, RXD[0:7]. examines line relative SYNC RX_DV set. set, then next eight bits data. During inter-packet time, when RX_DV inactive, follow definitions applied eight data bits: RX_ER (for previous packet) Speed (0=10M, 1=100M) Duplex (0=Half, 1=Full) Link Down, Jabber (0=OK, 1=Error) Upper Nibble (0=Invalid, 1=Valid) False Carrier (0=none, detected) bits transmit TX_ER, TX_EN, RXD[0:7]. examines relative SYNC TX_EN set. set, then next eight bits data.
also provides RMII consortium compatible Reduced Media Independent Interface (RMII) well SMII communicate with Ethernet Media Access Controller (MAC). Selection Mbps operation based settings internal Serial Management Interface registers determined on-chip ANeg logic. device operate Mbps with full duplex half-duplex mode port basis. four ports also configured 100Base-FX.
INTERFACE
RMII
Reduced Media Independent Interface (RMII) mode REFCLK continues used connect with MAC. 125MHz, sampled every 10th cycle obtain their clock from common SYNC. source, such clock oscillator. This clock Serial Management Interface (SMI) shared ports within transmitting REFCLK shared between ports Phy. receiving data individual 2-bit data buses. This totals pins port plus Phy, whereas RXDV muxed together indicate pins port. when there valid data receive bus. 100M mode RXD[1:0] sampled every cycle REFCLK. mode RXD[1:0] sampled every 10th cycle REFCLK. RXER generated indicate receive error MAC. Phy's internal registers accessible only TX_EN generated indicate through 2-wire Serial Management Interface when there valid data transmit bus. 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Interrupt Control Status register determine which event caused interrupt. Status bits read only clear read. When INTR asserted, held high impedance state. Carrier Sense RX_DV Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10Base-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. half duplex mode, activated during transmit receiving data. full duplex mode, activated during data reception only. (SMI). clock input which used latch data instructions Phy. clock speed from MHz. MDIO bi-directional connection used write instructions write data read data from Phy. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than 20ns that data presented synchronous MDC. MDC/MDIO common signal pair ports design. Therefore, each port needs have unique Physical Address. Physical Address using pins defined PHYAD[4:2]. These input signals strapped externally sampled reset negated. PHYAD[1:0] addressed each port internal Phy. Internal addresses either depending polarity PHYAD_ST during reset. During idle, responsible pulling MDIO line high state. Therefore, 1.5K Ohms resistor required connect MDIO line Vcc. PHYAD reprogrammed software. detailed definition Serial Management registers follows. beginning read write cycle, will send continuous bits one's clock rate indicate preamble. zero will follow indicate start frame. read code zero, while write code zero one. These will followed bits indicate address bits indicate register address. Then bits follow allow turn around time. read operation, first will high impedance. Neither station will assert this bit. During second time, will assert this zero. write operation, station will drive first time, zero second time. bits data field then presented. first that transmitted register content. (See Read/Write Sequence) Interrupt INTR will asserted whenever selectable interrupt events occur. Assertion state programmable either high through INTR_LEVL register bit. Selection made setting appropriate upper half Interrupt Control Status register. When INTR goes active, interface required read
MEDIA INTERFACE
10BASE-T
When configured 10Base-T mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function Parallel Serial logic used convert single (SMII) 2-bit (RMII) data into serial stream. serialized data goes directly Manchester encoder where synthesized through output waveshaping driver. waveshaper reduces emission filtering harmonics, therefore eliminating need external filter. Receive Function received signal passes through low-pass filter, which filters noise from cable, board, transformer. This eliminates need 10Base-T external filter. Manchester decoder converts incoming serial stream. Serial Parallel logic used generate single (SMII) 2-bit (RMII) data.
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AC104Z-QF
Link Monitor 10-Base-T link-pulse detection circuit will constantly monitor RXIP/RXIN pins presence valid link pulses. absence valid link pules, Link Status will cleared Link will de-assert.
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmitted frequency range, thus eliminating peaks single frequency. repeater applications, where ports transmit same data simultaneously, signal energy spread further using non-repeating sequence each Phy, i.e., scrambled seed unique each different based address. When Dis_Scrm data scrambling function disabled, 5-bit data stream clocked directly device's sublayer. Parallel Serial, NRZI, MLT3 Conversion 5-bit data clocked into Phy's shift register with clock, clocked with clock convert into serial stream. serial data converted from NRZI format, which produces transition Logic transition Logic further reduce emissions, NRZI data converted MLT-3 signal. conversion offers reduction emissions. This allows system designers meet Class limit. Whenever there transition occurring NRZI data, there corresponding transition occurring MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transitions incoming NRZI data setting count up/down direction MLT-3 data. Asserting FX_SEL high will disable this encoding. slew rate transmitted MLT-3 signal controlled reduce emissions. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. This guaranteed with either 1.25:1 transformer. Receive Function 100Base-TX receive path functions inverse transmit path. receive path includes receiver with adaptive equalization restoration front end. also includes MLT-3 NRZI converter, data clock recovery, NRZI/NRZ conversion, Serial-to-Parallel
100BASE-TX
When configured 100Base-TX mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function 100Base-TX mode, transmit function converts synchronous single (SMII) 2-bit (RMII) data pair Mbps differential serial data streams. serial data transmitted over network twisted pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. transmit data transmitted from signals. 4B/5B encoder replaces first nibbles preamble from frame with /J/K/ code-group pair Start-ofStream Delimiter (SSD), following onset TX_EN signal. 4B/5B encoder appends /T/R/ code-group pair End-of-Stream Delimiter (ESD) transmission place first IDLE code-groups that follow negation TX_EN signal. encapsulated data stream converted from 4-bit nibbles 5-bit code-groups. During inter-packet gap, when there data present, continuous stream IDLE code-groups transmitted. When TX_ER asserted while TX_EN active, Transmit Error code-group substituted translated code word. 4B/5B encoding bypassed when Reg. 21.1 "1", PCSBP strapped high. 100Base-TX mode, 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function:
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Decoder/De-scrambler de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler acquires lock data stream recognizing IDLE bursts more bits locks frequency de-ciphering LFSR. Once lock acquired, device operate with inter-packet-gap (IPG) However, before lock acquired, de-scrambler needs minimum consecutive idles between packets order acquire lock. de-ciphering logic also tracks number consecutive errors received while RX_DV asserted. Once error counter exceeds limit currently consecutive errors, logic assumes that lock been lost, decipher circuit resets itself. process regaining lock will start again. Stream cipher descrambler used 100Base-FX 10Base-T modes. Link Monitor Signal level detected through squelch detection circuitry. signal detect (SD) circuit allows equalizer assert high whenever peak detector detects post-equalized signal with peak ground voltage greater than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detect signal stay gets de-asserted approximately after energy level drops consistently below from peak ground. link signal forced during local loopback operation (Loopback register set) forced high when remote loopback taking place (EN_RPBK set). forced 100Base-TX mode, when cable unplugged valid signal detected receive pair, link monitor enters "link fail" state NLP's transmitted. When valid signal detected minimum period time, link monitor enters Link Pass State transmits MLT-3 signal. conversion, de-scrambler, 5B/4B decoder. receiver circuit starts with bias differential RX+/- inputs, followed with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful powersaving mode. amplification ratio slicer's threshold on-chip bandgap reference. Baseline Wander Compensation 100Base-TX data stream always balanced. transformer blocks components incoming signal, thus offset differential receive inputs drift. shifting signal level, coupled with non-zero rise fall times serial stream cause pulse-width distortion. This creates jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. This implements patent-pending restoration circuit. Unlike traditional implementation, circuit does need feedback information from slicer clock recovery circuit. This design simplifies circuit design eliminates random/systematic offset receive path. 10BaseT 100BaseFX modes, baseline wander correction circuit required, therefore disabled. Clock/Data Recovery equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input (RMII) clock input (SMII) while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock runlengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, will switch lock REFCLK.
100BASE-FX
When port configured 100Base-FX mode, either through hardware configuration
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-FX mode, filtering performed. transmit driver utilizes current drive output which well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BaseT mode, high frequency pre-emphasis performed extend cable-driving distance without external filter. pulses also driven through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level builtin bandgap reference external resistor connected IBREF pin. resistor sets output current modes operation. TXOP/N outputs open drain devices with serial source resistance max. When transformer used, current rating 2Vp-p MLT-3 signal, 5Vp-p Manchester signal. 1.25:1 transmit transformer output driver power reduction. This will decrease drive current 100Base-TX operation, 10Base-T operation. Adaptive Equalizer designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT5 cable this length typically attenuation MHz. typical attenuation 100meter cable worst case 100m cable attenuation around 24-26 defined TPPMD specification. amplitude phase distortion from cable causes inter-symbol interference (ISI) which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability change equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable. Clock Synthesizer includes on-chip clock synthesizer that generates clocks 100Base-TX circuitry. clock generator uses software configuration (100Base-FX does support ANeg) will support features parameters industry standards. Transmit Function serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive Fiber-transmitter. Receive Function 100Base-FX mode, signal received through PECL receiver inputs, directly passed clock recovery circuit data/clock extraction. mode, scrambler/de-scrambler cipher function bypassed. Link Monitor 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Phy's pin. Far-End-Fault-Indication (FEFI) ANeg provides mechanism inform link partner that remote fault occurred. However, ANeg disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This pattern repeated times. FEFI will signal under conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets transmit Far-End-Fault bit. FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset.
10BASE-T/100BASE-TF/FX
Multi-Mode Transmit Driver multi-mode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal 100Base-FX mode, Manchester coded signal 10Base-T mode.
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Many these pins multi-function pins which change their meaning when reset ends. fully differential cell that introduces very jitter. Zero Dead Zone Phase Detection method implemented design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. on-chip loop filter eliminates need external components minimizes external noise sensitivity. Only external (RMII) (SMII) crystal clock source required reference clock. After power-on reset, clock synthesizer generates clock output until 100Base-X operation mode selected. Jabber (Heartbeat) After transmitter exceeds jabber timer (46mS), transmit loopback functions will disabled signal asserted. After TX_EN goes more than transmitter will reactivate gets de-asserted. Setting Jabber Disable will disable jabber function. When test enabled, pulse with 515BT asserted after each transmitted packet. enabled 10Base-T default, disabled Test Inhibit. Reverse Polarity Detection Correction Certain cable plants have crossed wiring twisted pairs; reversal TXIN TXIP. Under normal circumstances this would cause receive circuitry reject data. When Auto Polarity Disable cleared, ability detect fact that either NLPs burst FLPs inverted automatically reverse receiver's polarity. polarity state stored Reverse Polarity bit. Auto Polarity Disable set, then Reverse Polarity written force polarity reversal receiver.
SOFTWARE CONFIGURATION
Several different states operation chosen through software configuration. Please refer section well Register Descriptions. Jumbo Packets FIFOs internal logic have been designed handle Jumbo packets 9000 bytes length. This feature enabled disabled through either hardware software setup. LEDs Each ports individual outputs available indicate dynamic status associated port. These multi-function pins inputs during reset output pins thereafter. level these pins during reset determines their active output states. multi-function pulled during reset select particular function, then that output would become active low, vice versa, therefore circuit must designed accordingly. (See Configuration.) information displayed LEDs determined contents Common Registers. Common Register selections allow each individual turned directly, turned blinked event. possible events Collision, Auto-Negotiation, Full Duplex, 100Base-TX, Activity Link. combination events directed associated with each port. default ports LEDSPD Active=100Mbps LEDACT Active=Link, Blink=Activity LEDDPX Active=FullDuplex, Blink=Collision
AUTO-NEGOTIATION
definition 10/100 Transceiver able either 10Mbps over Twisted Pair Copper (10Base-T), 100Mpbs over Twisted Pair Copper (100Base-TX) 100Mpbs over Fiber Optics (100Base-FX). addition able either half duplex (repeater mode) full duplex. determine operational state, hardware selects software selects while also supporting AutoNegotiation Parallel Detection. 100Base-FX mode, selection must done
INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled either high reset time. combination high values determines power state device.
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
When receives identical link code words (ignoring acknowledge bit) from link partner, stores these code words Reg. sets acknowledge generated FLPs, waits receive identical code word with acknowledge from link partner. Once this occurs configures itself highest technology that common both ends. technology priorities are: 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T half-duplex. through hardware configuration. There support Auto-Negotiation interface. above combinations possible limitations environment 802.3 standards. Legitimate operating states are: 10Base-T Half Duplex 10Base-T Full Duplex 100Base-TX Half Duplex 100Base-TX Full Duplex 100Base-FX Half Duplex 100Base-FX Full Duplex
hardware configured force above mentioned modes. forcing mode, will only that mode, hence limiting locations where product will operate. able negotiate mode operation twisted pair environment using AutoNegotiation mechanism defined clause IEEE 802.3u specification. ANeg enabled disabled hardware (ANEGA pin) software (Reg. 0.12) control. When ANeg enabled, chooses mode operation advertising abilities comparing them with ability received from link partner. configured advertise 100Base-TX 10Base-T operating either full half duplex. Register contains current capabilities, speed duplex, Phy, determined through hardware selects chip defaults. contents Reg. sent link partner during ANeg process using Fast Link Pulses (FLPs). string each which particular meaning, total which called Link Code Word. After reset, software change these bits from back from Therefore, hardware priority over software. When ANeg enabled, sends FLPs during following conditions: power link loss restart ANeg command software
Once ANeg complete, Reg. set, Reg. 1.[14:11] reflects negotiated speed duplex mode, enters negotiated transmission reception state. This state will change until link lost reset through either hardware software, restart negotiation (Reg. 0.9) set.
PARALLEL DETECTION
Because there many devices field that support ANeg process, must still communicated with, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect: Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle
mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems, while maintaining flexibility Auto-Negotiation.
DIAGNOSTICS
Loopback Operation Local Loopback Remote Loopback provided testing purpose. They enabled write either Reg. 0.14 (LPBK) Reg. 21.3 (EN_RPBK).
During this period, continually sends FLPs while monitoring incoming FLPs from link partner determine their optimal mode operation. FLPs detected during this phase operation, Parallel Detection mode entered (see below).
Local Loopback routes transmitted data through transmit path back receiving path's clock data recovery module. loopback data 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
features. Separate power supply lines used power 10BaseT circuitry 100BaseTX circuitry. Therefore, circuits turnedon turned-off independently. When operate 100Base-TX mode, 10Base-T circuitry powered down, vice versa. following power management features supported: Power down mode: This achieved writing Reg. 0.11 pulling PWRDN high. During power down mode, device still able interface through MDC/MDIO management interface. Energy detect power saving mode: Energy detect mode turns power select internal circuitry when there live network connected. Energy Detect (ED) circuit always turned monitor there signal energy present media. circuitry also powered ready respond management transaction. transmit circuit still send link pulses with minimum power consumption. valid signal received from media, device will power resume normal transmit/receive operation. (Patent Pending) Reduced Transmit Drive Strength mode: Additional power saving gained level designing with 1.25:1 turns ration magnetic asserting TP125 reset. presented bits symbol format. This loopback used check operation 5-bit symbol decoder phase locked loop circuitry. Local Loopback, output forced logic TXOP/N outputs tri-stated. Remote Loopback, incoming data passed through equalizer clock recovery, then looped back NRZI/MLT3 converter then transmit driver. This loopback used ensure device's connection media side. also checks operation device's internal adaptive equalizer, phase locked loop circuit, wave-shaper synthesizer. During Remote Loopback, signal detect (SD) output forced logic zero. Cable Length Indicator detect approximate length cable it's attached display result Reg. 20.[7:4]. reading [0000] translates cable used, [0001] translates meter cable, [1111] translates meter cable. cable length value used network manager determine proper connectivity cable manage cable plant distribution
RESET POWER
reset three ways: During initial power Hardware Reset: logic signal pulse width applied RST* pin. Software Reset: Write Reg. 0.15.
CLOCK
clock input must clock oscillator measured MHz-100PPM SMII MHz-100PPM RMII.
power consumption device significantly reduced built-in power management
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
REGISTER DESCRIPTIONS
first seven registers register defined specification. addition these required registers several Altima Communications Inc. specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format): NOTE: When writing registers, recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits.
REGISTERS
Register Description Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Default 1000 7849 0022 5542 01E1 0001 0004 2001
REGISTERS 8-31
Register 8-15 24-27 28-31 LEGEND: Read Write Access Self Clearing Latch until cleared reading Read Only Cleared Read Latch High until Cleared reading Description Reserved Polarity Interrupt Level Register Interrupt Control/Status Register Reserved Test Register Cable Measurement Register Receive Error Count Power Management Register Operation Mode Register Reserved Global Register Default XXXX 1000 0000 XXXX 0000 XXXX 0000 XXFF 0000 XXXX XXXX
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AC104Z-QF
Register Control Register Reg.bit 0.15 0.14 Name Reset Loopback Description reset. This self-clearing. Enable loopback mode. This will loopback ignore activity cable media. Normal operation. 100Mbps 10Mbps. Enable Auto-Negotiate process (overrides 0.13 0.8) Disable Auto-Negotiate process. Mode selection controlled 0.8, 0.13 through mode pin. Power down. blocks except will turned off. Setting PWRDN high will achieve same result. Normal operation. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test. Refer Mode Table Mode RW/SC Default
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
0.13 0.12
Speed Select ANeg Enable
Note Note
0.11
Power Down
0.10
Isolate Restart ANeg Duplex Mode
RW/SC
Note
Collision Test
0.[6:0]
Reserved
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AC104Z-QF
Register Status Register Reg.bit 1.15 1.14 1.13 1.12 1.11 1.[10:7] Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANeg Complete Description Permanently tied zero indicates 100BaseT4 capability. 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half-duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-Negotiate process completed. Reg. valid after this set. Auto-negotiate process completed. Remote fault condition detected. remote fault. This will remain until cleared reading register Able perform Auto-Negotiation function, default value determined ANEGA pin. Unable perform Auto-Negotiation function. Link established. link fails, this will cleared remain until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. Refer Mode Table Register Identifier Register Reg.bit 2.[15:0] OUI* Name Description Mode Default 0022(H) Mode Default Note Note Note Note
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Remote Fault
RO/LH
ANeg Ability
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
Composed through 18th bits Organizationally Unique Identifier (OUI), respectively. Based 0010A9 (Hex) Register Identifier Register Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name Description
Mode
Default 010101 010100 0011
Assigned 19th through 24th bits OUI. Model Number manufacturer's model number. encoded 010001. Revision Four-bit manufacturer's revision number. 0011 stands Rev. Number etc. Based 0010A9 (Hex)
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Register Auto-Negotiation Advertisement Register Reg.bit 4.15 4.14 4.13 4.[12:11] 4.10 Name Next Page Acknowledge Remote Fault Reserved FDFC Description Next Page enabled. Next Page disabled. This will internally after receiving consecutive consistent bursts. Advertises that this device detected Remote Fault. remote fault detected. future technology. Full Duplex Flow Control Advertise that DTE(MAC) implemented both optional control sublayer pause function specified clause annex 802.3u. does support flow control Technology supported. This always 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. [00001] IEEE 802.3. Refer Mode Table Mode Default
4.[4:0]
100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field
Note Note Note Note 00001
Register Auto-Negotiation Link Partner Ability Register Reg.bit 5.[15:0] Name Technology Description Technology capability field, which indicates technology capability link partner. definition same 4.15:0. When this register used Next Page Message, definition same Reg. 7.15:0. Mode Default 0001
Register Auto-Negotiation Expansion Register Reg.bit 6.[15:5] Name Reserved Parallel Detection Fault Description Fault detected parallel detection logic, this fault more than technology detecting concurrent link condition. This only cleared reading Register using management interface. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner Auto-Negotiation capability. Link partner does have Auto-Negotiation capability. Mode RO/LH Default
Link Partner Next Page Able Next Page Able Page Received
RO/LH
Link Partner ANeg-Able
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Register Auto-Negotiation Next Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 17.[10:0] Reserved ACK2 TOG_TX CODE Name Description Another Next Page Transfer desired. other Next Page Transfer desired. Message page. Un-formatted page. Will comply with message. Cannot comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Un-formatted Code Field. Mode Default
Register Polarity Interrupt Level Register Reg.bit 16.[15:14] 16.13 16.12 16.11 Name Reserved TXJAM Reserved Test Inhibit Description Force send pattern Normal operation Disable 10BaseT testing. Enable 10BaseT testing, which will generate pulse following completion packet transmission. Disable Auto Polarity detection/correction. Enable Auto Polarity detection/correction. Reverse Polarity when Reg. 16.5 Normal Polarity when Reg. 16.5 Reg. 16.5 writing this will reverse polarity transmitter. Mode Default
16.[10:6] 16.5 16.4
Reserved Auto Polarity able Reverse Polarity
16.[3:0]
Reserved
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Register Interrupt Control/Status Register Reg.bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Status_ Change_IE R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Status_ Changes R_Fault_Int ANeg _Comp Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Change Interrupt Enable. Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received during ANeg. This when parallel detect fault detected. This when with acknowledge received. This when link status changes. This when remote fault detected. This when ANeg complete. Mode Default
Register Test Register Reg.bit 19.[15:9] 19.8 19.[7:6] 19.[4:2] 19.5 19.4 19.[3:1] Name Reserved TX_FEF Reserved Reserved Watch timer disable Low_pwr_mode Reserved Description Reserved Force transmit Reserved Reserved disable watch timer 1=disable power management Reserved Mode Default 0000000
Register Cable Measurement Register Reg.bit 20.[15:9] 20.[7:4] Name Reserved Cable measurement capability Description Reserved These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Mode Default
20.[3:0]
Reserved
Register Receive Error Counter Register Reg.bit 21.[15:0] Name RX_ER Counter Description Count Receive Error Events Mode Default
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Register Operation Mode Register Reg.bit 23.15 23.14 Name Enable Description enable function function enabled only when this register FX_EN set. port operate mode. port operated mode only when auto-negotiation disabled, speed FX_MODE will default auto-negotiation disable, enable. Reserved Select single ended input signal disable scrambler Reserved Reserved Reserved Reserved Refer Mode Table Register recent received packet Reg.bit 24.[15:0] Mode Table FX_En(n) Force Scram_En ANEGA Condition Port 100Base-FX Port Auto Negotiate 10Base-T 100Base-TX Port Forced 100Base-TX Port Forced 10Base-T Port Forced 100Base-TX (unscrambled) Name system link testing Description Mode Default 0000H Mode Default Note
23.13 23.12 23.11 23.[10:8] 23.7 23.6 23.[5:0]
Reserved Cmsel Scramble Disable Reserved Reserved Reserved Reserved
XXXXXX
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AC104Z-QF
COMMON REGISTERS
Register LEGEND: Read Write Access Self Clearing Latch until cleared reading Read Only Cleared Read Latch High until Cleared reading Description Operation Mode Register(Map Port Test Mode Register (Map Port Reserved LEDSPD Settings1 (Map Port LEDSPD Settings2 (Map Port LEDACT Setting1(Map Port LEDACT Setting2(Map Port LEDDPX Setting1(Map Port LEDDPX Setting2(Map Port Blink Rate(Map Port Default 00X4 1000 XXXX 0000 0000 0002 0100 0020 XXXX 0010
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Common Register (Map port Operation Mode Register Port.Reg.bit 0.28.[15:7] 0.28.[6:4] 0.28.3 0.28.2 Name Reserved Reserved Interrupt Level Select Reserved Reserved Interrupt active Interrupt active high Event select Receive Activity Activity Select 1:1.25 Transformer Description Mode Default 00000000
0.28.1 0.28.0
Reserved Tp125
Common Register (Map port Test Mode Register Port.Reg.bit 0.29.15 0.29.[14:10] 0.29.[9:2] 0.29.1 0.29.0 Name Reserved FIFO Depth Reserved Global Address Enable Reduce Timer Description Reserved 00100 Normal Operation 10111 Jumbo Packet Reserved Write address will write phys chip Normal Operation Reduce timer auto-negotiation testing. Mode Default 00100 00000000
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Common Register (Map port LEDSPD Setting1 Register Port.Reg.bit 2.28.[15:12] 2.28.[11:8] 2.28.[7:0] Name Force Force Mask Blink Description Force Force Common Register Port Table Force off, Force Common Register Port Table Event will cause blink, Masked Common Register Mask Table Mode Default 0000 0000 00000000
Common Register (Map port LEDSPD Setting2 Register Port.Reg.bit 2.29.[15:8] 2.29.[7:0] Name Mask Mask Description Event will turn Masked Common Register Mask Table Event will turn off, Masked Common Register Mask Table Mode Default 00000100 00000000
Common Register (Map port LEDACT Setting1 Register Port.Reg.bit 2.30.[15:12] 2.30.[11:8] 2.30.[7:0] Name Force Force Mask Blink Description Force Force Common Register Port Table Force off, Force Common Register Port Table Event will cause blink, Masked Common Register Mask Table Mode Default 0000 0000 00000010
Common Register (Map port LEDACT Setting2 Register Port.Reg.bit 2.31.[15:8] 2.31.[7:0] Name Mask Mask Description Event will turn Masked Common Register Mask Table Event will turn off, Masked Common Register Mask Table Mode Default 00000001 00000000
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Common Register (Map port LEDDPX Setting2 Register Port.Reg.bit 3.28.[15:12] 3.28.[11:8] 3.28.[7:0] Name Force Force Mask Blink Description Force Force Common Register Port Table Force off, Force Common Register Port Table Event will cause blink, Masked Common Register Mask Table Mode Default 0000 0000 00100000
Common Register (Map port LEDDPX Setting2 Register Port.Reg.bit 3.29.[15:8] 3.29.[7:0] Name Mask Mask Description Event will turn Masked Common Register Mask Table Event will turn off, Masked Common Register Mask Table Mode Default 00001000 00000000
Common Register (Map port Blink Rate Port.Reg.bit 3.30.[15:8] 3.30.[7:0] Name Reserved Blink Rate Description Reserved blink rate. blink rate this number Default Mode Default 00000000 00010000
Common Register Port Table Bits have higher priority than Bits Port Port Port Port Port Port Port Port
Common Register Mask Table Applicable Applicable Applicable Applicable Collision Collision AutoNegotiation AutoNegotiation Full Duplex Full Duplex 100Base-TX 100Base-TX Activity Activity Link Link
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
4B/5B CODE-GROUP TABLE
Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 SYMBOL Name (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle Control Code 0000 0101 0101 Undefined Undefined Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
READ/WRITE SEQUENCE
Read/Write Sequence Pream bits) Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
Read Write
CONFIGURATIONS
Mode Link Transmit Receive Collision Transmit Receive 100M Link 100M Transmit 100M Receive Collision 100M Transmit 100M Receive LEDDPX during collision during collision LEDACT TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE LEDSPD
Multi Function pull Multi Function pulled reset.
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
ELECTRICAL CHARACTERISTICS
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55o +150o Supply Referenced GND. -0.5V +5.0V Digital Input Voltage. -0.5V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature(Ta) -40o +85o Supply Voltage Range(Vcc) 2.97V 3.63V
Total Power Consumption Parameter Supply Current (per port) Symbol Conditions Base-T, Idle Base-T, Normal activity Base-TX Base-FX 10/100 Base-TX, power without cable Power down Units
Characteristics Parameter Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance Output Transition Time Tristate Leakage Current Symbol 3.15V 3.45V |Ioz| Conditions VCC-0.4 Units
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AC104Z-QF
REFCLK XTAL Pins Parameter Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Conditions Units
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
Characteristics LED/CFG Pins Parameter Output Voltage Output High Voltage Input Current Output Current Symbol Conditions Units
BASE-TX Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance Symbol Trfs Conditions Note Note Note Note 1.02 ±250 Note resistor each output Units
Scrambled Idle Transformer 1.25:1 Transformer
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
BASE-T Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance Symbol Conditions Note Transformer 1.25:1 Transformer Units
Note resistor each output
BASE-FX Transceiver Characteristics Parameter Differential Output Voltage High Differential Output Voltage Signal Rise/Fall Time Output Jitter Differential Output Voltage High Differential Output Voltage Common-Mode Input Voltage Input Differential Output Current Sink Symbol Conditions Note Note Note 3.3V ground BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receiver Link Pulse Link Receive Timer Link Receive Timer Link Transmit Period Link Pulse Width Symbol Conditions Units Link Pulses Units
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver DIGITAL TIMING CHARACTERISTICS
Power Reset Parameter RST* Period Configuration tRST tCONF Conditions Units
tRST
RST* Configuration Pins Power Reset Timing
tCONF
Management Data Interface Parameter CLOCK CLOCK MDIO Setup MDIO Hold tMDCL tMDCH Conditions Units
Setup Read/Write Cycle Hold Read/Write Cycle
tMDCL
tMDCH
MDIO
Management Data Interface Timing
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-TX/FX 10Base-T RMII Transmit System Timing Parameter REFCLK period REFCLK High period REFCLK period TX_EN (SOP) !TX_EN (EOP) Propagation Delay TXD[1:0], TX_EN Setup TXD[1:0], TX_EN Hold !TX_EN TX_EN tCKH tCKL tTXS tTXH tTX_TX Conditions 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
From TXD[1:0] TXOP/N(FXTP/N) From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
Packet
tTXS
TX_EN
tTX_TX tTXH
TXD[1:0]
TXOP/N
FXTP/N
TXOP/N 100Base-TX/FX 10Base RMII Transmit Timing
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AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-TX/FX 10Base-T RMII Receive System Timing Parameter REFCLK period REFCLK High period REFCLK period /J/K (SOP) CRS_DV /T/R (EOP) !CRS_DV Propagation Delay RXD[1:0], CRS_DV, RX_ER Setup RXD[1:0], CRS_DV, RX_ER Hold tCKH tCKL tRCSA tRCSD tRDVA tRXS tRXH Conditions 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
From RXIP/N(FXRP/N) RXD[1:0] From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
Packet
tRDVA
CRS_DV
tRDVD tRXS tRXH
RXD[1:0] RX_ER /J/K RXIP/N /T/R
FXRP/N RXIP/N 100Base-TX/FX 10Base-T RMII Receive Timing
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-TX/FX 10Base-T SMII Transmit System Timing Parameter REFCLK period REFCLK High period REFCLK period SYNC rise REFCLK TX_EN (SOP) !TX_EN (EOP) Propagation Delay Setup Hold SYNC SYNC tCKH tCKL tTCS tTXS tTXH Conditions 7.999 3.999 3.999 8.000 8.001 4.001 4.001 Packet Units
From TXOP/N(FXTP/N) From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
tTSC
SYNC
tTXH
tTXS
TXOP/N 100Base-TX
FXTP/N
TXOP/N 10Base-T SMII Transmit Timing
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver
100Base-TX/FX 10Base-T SMII Receive System Timing Parameter REFCLK period REFCLK High period REFCLK period SYNC rise REFCLK /J/K (SOP) CRS_DV /T/R (EOP) !CRS_DV Propagation Delay Setup Hold tCKH tCKL tTCS tRXS tRXH Conditions 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
From RXIP/N(FXRP/N) From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
Packet
tTSC
SYNC
tRXS tRXH
/J/K RXIP/N /T/R
FXRP/N
RXIP/N SMII Receive Timing
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation
3.3V
49.9
49.9
AC104Z-QF
Transformer TXON TXOP IBREF
RJ45 Unused Unused Unused Unused
TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
FX_EN
RXIP
1000
RXIN
Chassis
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation
3.3V 69.8 69.8
HFBR-5903 RXVee RXVcc TXVcc TXVee
AC104Z-QF
FXRN
FXRP FXTP
FXTN
FX_EN
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver POWER GROUND FILTERING AC104Z-QF
Please contact Altima Communications Inc. latest component value recommendation. Ground Power .1uf Components placed from
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104Z-QF
AC104Z-QF
Ultra Power 10/100 Quad SMII/RMII Ethernet Transceiver PACKAGE DRAWING AC104Z-QF
Mechanical Dimensions 3.40 0.25 2.70 0.200 0.07 23.20 0.25 20.0 0.10 18.5 0.10 17.20 0.25 14.00 0.10 12.50 0.10 0.50 0.88 1.60 0.12
2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Alitma Communications Inc. reserves right make changes this document without notice. Document Revision Page

AC104Z-QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-

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