AC104QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-TX

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AC104QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-TX

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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver GENERAL DESCRIPTION
AC104QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented 0.35µm CMOS technology. Multiple modes operation including normal operation, test mode power saving mode available through either hardware software control. Features include interfaces, ENDECs, Scrambler/Descrambler, Auto-Negotiation (ANeg) with support parallel detection. transmitter includes dual-speed clock synthesizer that only needs external clock source. chip built-in wave shaping driver circuit both 10Mbps 100Mbps, eliminating need external hybrid filter. receiver adaptive equalizer restoration circuit accurate clock data ecovery 100Base-TX signal. also provides on-chip pass filer Squelch circuit 10Base-T signal. interfaces support four ports 10/100 RMII. Media Interfaces support ports 10/100TX ports 10/100TX port 100FX.
RMII RMII 5Volt tolerant 2.5Volt capable 10/100 10/100 Full Duplex Half Duplex FEFI 100FX Very small package 100PQFP Very power 280mW port) Cable Detect mode 40mW port) Power Down 3.3mW port) Selectable drivers 1.25:1 transformers additional power reduction 3.3Volt .35micron CMOS Fully compliant with IEEE 802.3 802.3u RMII test labs Baseline Wander Compensation Multi-Function outputs Cable length indicator Reverse polarity detection correction with Register indication Automatic Forced programmable interrupts Diagnostic registers
BLOCK DIAGRAM
Port Port Port Port
.Framer .Carrier Detect .4B/5B .Clock Recov. .Link Monitor .Signal Detect TP_PMD 100TX .MLT-3 .BLW .Stream Cipher
100RX RMII/MII
TXOP/N(0) RXIP/N(0) TXOP/N(1) RXIP/N(1) TXOP/N(2) RXIP/N(2) TXOP/N(3)
10TX
RXIP/N(3)
Interface
10BASE-T
10RX
FXTP/N(3) FXRP/N(3)
Control/Status
Serial Management Interface Registers
Gen. Test/LED Control
AutoNegotiation
PHYAD[4:0]
XTLP/N CKIN TEST[3:0] Drivers
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
REVISION HISTORY REVISION# DATE July 1998 June 2000 Sept 2000 CHANGE Helene CHANGE DESCRIPTION Preliminary Release Final Release Change default value register [15:0] 101010101000001 page Enhance descriptions DPLX SPEED (register 18.11 18.10) page
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
General Description. Features. Block Diagram. Diagram AC104QF. Descriptions. (Media Dependent Interface) Pins.6 RMII (Reduced Media Independent Interface) Pins.7 (Serial Management Interface) Pins Address Pins.8 Mode Pins.8 Pins Power Ground Pins Functional Description. Interface. RMII Interrupt.11 Carrier Sense RX_DV Media Interface 10Base-T Transmit Function.11 Receive Function Link Monitor.11 100Base-TX Transmit Function.11 Parallel Serial, NRZI, MLT3 Conversion.12 Receive Function Baseline Wander Compensation.12 Clock/Data Recovery Decoder/De-scrambler Link Monitor.13 100Base-FX.13 Transmit Function.13 Receive Function Link Monitor.13 Far-End-Fault-Indication (FEFI).13 10Base-T/100Base-TF/FX Multi-Mode Transmit Driver.14 Adaptive Equalizer Clock Synthesizer Jabber (Heartbeat).14 Reverse Polarity Detection Correction Initialization Setup. Hardware Configuration.15 Software Configuration LEDs Auto-Negotiation.15 Parallel Detection.16 Diagnostics.16 Loopback Operation.16 Cable Length Indicator.16 Reset Power. Clock. Register Descriptions. 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Registers 1-7.18 Registers 8-31.18 Register Control Register.19 Register Status Register.20 Register Identifier Register.20 Register Identifier Register.20 Register Auto-Negotiation Advertisement Register.21 Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message.21 Register Auto-Negotiation Expansion Register.22 Register Auto-Negotiation Next Page Transmit Register.22 Register Interrupt Level Control Register.23 Register Interrupt Control/Status Register.23 Register Diagnostic Register.24 Register Power/Loopback Register.24 Register Cable measurement capability Register.24 Register Receive Error Counter.24 Register Mode Control Register.25 Mode Table 4B/5B Code-Group Table Read/Write Sequence. Configurations. ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings.28 Operating Range.28 Total Power Consumption.28 Characteristics REFCLK XTAL Pins Characteristics LED/CFG Pins BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics.29 BASE-FX Transceiver Characteristics.30 BASE-T Link Integrity Timing Characteristics.30 Digital Timing Characteristics Power Reset.31 Management Data Interface 100Base-TX/FX 10Base-T RMII Transmit System Timing 100Base-TX/FX 10Base-T RMII Receive System Timing Application Termination Application Termination.35 Power ground filtering AC104QF.36 Package dimensions AC104QF (100 PQFP)
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver DIAGRAM AC104QF
OVDD RXD[0](0) RXD[1](0) CVDD TX_EN(1) TXD[0](1) TXD[1](1) OGND OGND CRS_DV(1) RX_ER(1) RXD[0](1) RXD[1](1) CVDD REF_CLK MDIO TX_EX(2) OVDD TXD[0](2) TXD[1](2) CGND CRS_DV(2) RX)ER(2) RXD[0](2) RXD[1](2) CVDD TX_EX(3) OGND TXD[0](3)
RX_ER(0) CRS_DV(0) CGND TXD[1](0) TXD[0](0) TX_EN(0) OGND LEDDPX(1) PHYAD[4] LEDACT(1) PHYAD[3] LEDSPD(1) PHYAD[2] LEDDPX(0) FX_DIS LEDACT(0) LEDSPD(0) TP125 INTR RST* GAGND IBREF GAVDD GAVDD AVDD
AC104QF
TXD[1](3) CGND CRS_DV(3) RX_ER(3) PHYAD_ST RXD[0](3) RXD[1](3) OVDD LEDSPD(2) FORCE100 LEDACT(2) LEDDPX(2) LEDSPD(3) BURN_IN* LEDACT(3) ANEGA LEDDPX(3) SCRAM_EN FXTN(3) FXTP(3) FXRN(3) TST[3] FXRP(3) TST[2] SDN(3) TST[1] SDP(3) TST[0] AVDD
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RXIN(0) RXIP(0) AGND AGND TXOP(0) TXON(0) AVDD AVDD TXON(1) TXOP(1) AGND AGND RXIP(1) RXIN(1) AVCC AVCC RXIN(2) RXIP(2) AGND AGND TXOP(2) TXON(2) AVDD AVDD TXON(3) TXOP(3) AGND RXIP(3) RXIN(3)
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver DESCRIPTIONS
Many pins these devices have multiple functions. multi-function pins will designated bolding number. Separate descriptions these pins will listed proper sections. Designers must assure that they have identified modes operation prior final design.
NOTES: assignment shown below description table subject change without notice. user advised contact Altima Communications Inc. before implementing design based information provided this data sheet. Signals types: input output high impedance internally pull internally pull down analog signal Active Signal Connect (Media Dependent Interface) Pins Name RXIN(0) RXIN(1) RXIN(2) RXIN(3) RXIP(0) RXIP(1) RXIP(2) RXIP(3) TXON(0) TXON(1) TXON(2) TXON(3) TXOP(0) TXOP(1) TXOP(2) TXOP(3) FXRP(3) FXRN(3) FXTP(3) FXTN(3) SDP(3) SDN(3) Type AI/O AI/O A/I,O A/I,O Description Receiver input Negative both 10Base-T 100Base-TX.
Receiver input Positive both 10Base-T 100Base-TX.
Transmitter output Negative both 10Base-T 100Base-TX.
Transmitter output Positive both 10Base-T 100Base-TX.
Receiver input Positive 100Base-FX. (Port-3) Receiver input Negative 100Base-FX. (Port-3) Transmitter output Positive 100Base-FX. (Port-3) Transmitter output Negative 100Base-FX. (Port-3) Signal Detect Input (For port only). Indicates signal quality status fiberoptic link 100Base-FX mode. When signal quality good, should driven high relative pin.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
RMII (Reduced Media Independent Interface) Pins Name TXD[1:0](0) TXD[1:0](1) TXD[1:0](2) TXD[1:0](3) TX_EN(0) TX_EN(1) TX_EN(2) TX_EN(3) RXD[1:0](0) RXD[1:0](1) RXD[1:0](2) RXD[1:0](3) CRS_DV(0) CRS_DV(1) CRS_DV(2) CRS_DV(3) RX_ER(0) RX_ER(1) RX_ER(2) RX_ER(3) REFCLK 78,79 68,69 55,56 45,46 Type I/O, I/O, I/O, I/O, I/O,D I/O,D I/O,D I/O,D I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O, I/O, Description RMII Transmit Data. will source TXD[1:0](n) synchronous with REFCLK when TX_EN(n) asserted.
RMII Transmit Enable. TX_EN(n) asserted high indicate that valid data transmission presented TXD[1:0](n).
RMII Receive Data. will source RXD[1:0](n) synchronous with REFCLK when CRS_DV(n) asserted.
CRS_DV(n) asserted high when media non-idle.
RMII Receive Error. When RX_ER asserted high, indicates error been detected during frame reception.
Reference Clock Input MHz-100PPM
(Serial Management Interface) Pins Name MDIO INTR Type I/O, Description Management Data Input/Output. Bi-directional data interface. 1.5K pull resistor required specified IEEE-802.3). Management Data Clock. clock sourced transfer MDIO data. Interrupt. Registers polarity sources. INTR high impedance output, pull-up pull-down resistor needed.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Address Pins Name PHYAD_ST PHYAD PHYAD PHYAD Type I/O,D Description reset 0-XXX00, 1-XXX01, 2-XXX10, 3-XXX11 reset 0-XXX01, 1-XXX10, 2-XXX11, 3-XXX00 Address [4:2]. These pins three MSB's address. PHYAD [1:0] internally wired four ports. (See PHYAD_ST) PHYAD will also determine scramble seed, this will help reduce when there multiple ports switching same time.
Mode Pins Name FX_DIS TP125 FORCE100 Type Description Disable. Pulled upon reset will port 100FX mode. Transformer Ratio. Pulled upon reset will select transmit transformer ratio 1.25:1. Pulled high transformer. FORCE100: Force 100Base-X Operation. When this signal pulled high ANENGA upon reset, ports will forced 100Base-TX operation. When asserted ANENGA low, ports forced 10Base-T operation. When ANENGA high, FORCE100 effect operation. Scrambler Enable. Pulled upon reset will bypass scrambler. Pulled high scrambler enabled. Auto-Negotiation Ability. Asserted high means auto-negotiation enable while means manual selection through FDXEN, F100. Burn-In mode. Burn-in mode reliability assurance control. This reserved internal testing only.
SCRAM_EN ANEGA BURN_IN*
Pins Name LEDDPX[0] LEDDPX[1] LEDDPX[2] LEDDPX[3] LEDACT_LNK[0] LEDACT_LNK[1] LEDACT_LNK[2] LEDACT_LNK[3] LEDSPD[0] LEDSPD[1] LEDSPD[2] LEDSPD[3] Type Description
I/O,U Port[n] Duplex LED. Active state indicates Full Duplex Collision Half I/O,U Duplex mode. I/O,U I/O,U I/O,U Port[n] Activity/Link LED. Active state indicates valid link. When there I/O,U receive transmit activity, will toggle between high I/O,U interval. I/O,U I/O,U Port[n] Speed LED. Active state indicates 100Base-TX mode. I/O,U I/O,U I/O,U Polarity LEDs determined polarity mode pins. example
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Miscellaneous Pins Name RST* Type Description Reset. active input will force known initialization state. reset pulse duration must Setting Reg. 0.15 will assert software reset, which same functionality hardware reset. Reference Bias Resistor. Must tied analog ground through external (1%) resistor. Test. Outputs during test mode.
IBREF TST[0] TST[1] TST[2] TST[3]
A/I,O
Power Ground Pins Name OVDD OGND CVDD CGND AVDD 98,99 Type Digital +3.3V power supply I/O. Digital ground I/O. Digital +3.3V power supply Core logic. Digital ground Core logic. +3.3V power supply Analog circuit. Description
AGND
Ground Analog circuit.
GAVDD GAGND
+3.3V power supply common analog circuits. Ground common analog circuits.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver FUNCTIONAL DESCRIPTION
AC104QF physical layer device (Phy) integrates 100Base-X 10Base-T functions single four port chip that used Fast Ethernet 10/100 Mbps applications. 100Base-X section consists PCS, PMA, functions, 10Base-T section consists Manchester ENDEC transceiver functions. device performs following functions: 4B/5B MLT3 NRZI Manchester Encoding Decoding Clock Data Recovery Stream Cipher Scrambling De-Scramb ling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg) RMII connectivity Management Function when there valid data transmit bus. 100M mode will read bits from TXD[1:0] each cycle REFCLK. mode will read bits data from TXD[1:0] every 10th cycle REFCLK. Serial Management Interface (SMI) shared between ports Phy. This totals pins port plus Phy, whereas pins port.
Phy's internal registers accessible only through 2-wire Serial Management Interface (SMI). clock input which used latch data instructions Phy. clock speed from MHz. MDIO bi-directional connection used write instructions write data read data from Phy. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than 20ns that data presented synchronous MDC. MDC/MDIO common signal pair ports design. Therefore, each port needs have unique Physical Address. Physical Address using pins defined PHYAD[4:2]. These input signals strapped externally sampled reset negated. PHYAD[1:0] addressed each port internal Phy. Internal addresses either depending polarity PHYAD_ST during reset. idle, responsible pull MDIO line high state. Therefore, 1.5K Ohms resistor required connect MDIO line Vcc. PHYAD reprogrammed software. detailed definition Serial Management registers follows.
also provides RMII consortium compatible Reduced Media Independent Interface (RMII) communicate with Ethernet Media Access Controller (MAC). Selection Mbps operation based settings internal Serial Management Interface registers determined on-chip ANeg logic. device operate Mbps with full duplex half-duplex mode port basis. Port also configured 100Base-FX.
INTERFACE
RMII
Reduced Media Independent Interface (RMII) used connect with MAC. beginning read write cycle, obtain their clock from common will send continuous bits source, such clock oscillator. This clock clock rate indicate preamble. zero shared ports within transmitting will follow indicate start frame. read receiving data individual 2-bit data buses. code zero, while write code RXDV muxed together indicate zero one. These will followed bits when there valid data receive bus. indicate address bits indicate register 100M mode RXD[1:0] sampled every cycle address. Then bits follow allow turn around REFCLK. mode RXD[1:0] sampled time. read operation, first will high every cycle REFCLK. RXER generated impedance. Neither station will indicate receive error MAC. assert this bit. During second time, TX_EN generated indicate 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
will assert this zero. write operation, station will drive first time, zero second time. bits data field then presented. first that transmitted register content. (See Read/Write Sequence) Interrupt INTR will asserted whenever selectable interrupt events occur. Assertion state programmable either high through INTR_LEVL register bit. Selection made setting appropriate upper half Interrupt Control Status register. When INTR goes active, interface required read Interrupt Control Status register determine which event caused interrupt. Status bits read only clear read. When INTR asserted, held high impedance state. Carrier Sense RX_DV Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10Base-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. half duplex mode, activated during transmit receiving data. full duplex mode, activated during data reception only. Transmit Function Parallel Serial logic used convert -bit (RMII) 4-bit (MII) data into serial stream. serialized data goes directly Manchester encoder where synthesized through output waveshaping driver. waveshaper reduces emission filtering harmonics, therefore eliminating need external filter. Receive Function received signal passes through low-pass filter, which filters noise from cable, board, transformer. This eliminates need 10Base-T external filter. Manchester decoder converts incoming serial stream. Serial Parallel logic used generate 2-bit (RMII) 4-bit (MII) data. Link Monitor 10-Base-T link-pulse detection circuit will constantly monitor RXIP/RXIN pins presence valid link pulses. absence valid link pules, Link Status will cleared Link will de-assert.
100BASE-TX
When configured 100Base-TX mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function 100Base-TX mode, transmit function converts synchronous 2-bit (RMII) 4-bit (MII) data pair Mbps differential serial data streams. serial data transmitted over network twisted pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. transmit data transmitted from TXD[n:0] signals. 4B/5B encoder replaces first nibbles preamble from frame with /J/K/ code-group pair Start-ofStream Delimiter (SSD), following onset TX_EN signal. 4B/5B encoder appends /T/R/ code-group pair End-of-Stream Delimiter (ESD) transmission place first IDLE
MEDIA INTERFACE
10BASE-T
When configured 10Base-T mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
code-groups that follow negation TX_EN signal. encapsulated data stream converted from -bit nibbles 5-bit code-groups. During inter-packet gap, when there data present, continuous stream IDLE code-groups transmitted. When TX_ER asserted while TX_EN active, Transmit Error code-group substituted translated code word. 4B/5B encoding bypassed when Reg. 21.1 "1", PCSBP strapped high. 100Base-TX mode, 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twis pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function: X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmitted frequency range, thus eliminating peaks single frequency. repeater applications, where ports transmit same data simultaneously, signal energy spread further using non-repeating sequence each Phy, i.e., scrambled seed unique each different based address. When Dis_Scrm data scrambling function disabled, 5-bit data stream clocked directly device's sublayer. Parallel Serial, NRZI, MLT3 Conversion 5-bit data clocked into Phy's shift register with clock, clocked with clock convert into serial stream. serial data converted from NRZI format, which produces transition Logic transition Logic further reduce emissions, NRZI data converted MLT-3 signal. conversion offers reduction emissions. This allows system designers meet Class imit. Whenever there transition occurring NRZI data, there corresponding transition occurring MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transitions incoming NRZI data setting count up/down direction MLT-3 data. Asserting FX_SEL high will disable this encoding. slew rate transmitted MLT-3 signal controlled reduce emissions. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. This guaranteed with either 1.25:1 transformer. Receive Function 100Base-TX receive path functions inverse transmit path. receive path includes receiver with adaptive equalization restoration front end. also includes MLT-3 NRZI converter, data clock recovery, NRZI/NRZ conversion, Serial-to-Parallel conversion, de-scrambler, 5B/4B decoder. receiver circuit starts with bias differential RX+/- inputs, followed with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful powersaving mode. amplification ratio slicer's threshold on-chip bandgap reference. Baseline Wander Compensation 100Base-TX data stream always balanced. transformer blocks components incoming signal, thus offset differential receive inputs drift. shifting signal level, coupled with non-zero rise fall times serial stream cause pulse-width distortion. This creates jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. This implements patent-pending restoration circuit. Unlike traditional implementation, circuit does need feedback information from slicer clock recovery circuit. This design simplifies circuit design eliminates random/systematic offset receive path. 10BaseT 100BaseFX modes, baseline wander correction circuit required, therefore disabled. Clock/Data Recovery equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
data stream data boundaries. transmit clock locked clock input (RMII) clock input (MII) while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate MII_RXC (MII). requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock runlengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, will switch lock REFCLK. This provides continuously running MII_RXC (MII). interface, data RXD[4:0] synchronized RX_CLK. Decoder/De-scrambler de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler acquires lock data stream recognizing IDLE bursts more bits locks frequency de-ciphering LFSR. Once lock acquired, device operate with inter-packet-gap (IPG) However, before lock acquired, de-scrambler needs minimum consecutive idles between packets order acquire lock. de-ciphering logic also tracks number consecutive errors received while RX_DV asserted. Once error counter exceeds limit currently consecutive errors, logic assumes that lock been lost, de-cipher circuit resets itself. process regaining lock will start again. Stream cipher de-scrambler used 100Base-FX 10Base-T modes. Link Monitor Signal level detected through squelch detection circuitry. signal detect (SD) circuit allows equalizer assert high whenever peak detector detects post-equalized signal with peak ground voltage greater than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detect signal stay gets de-asserted approximately after energy level drops consistently below from peak ground. link signal forced during local loopback operation (Loopback register set) forced high when remote loopback taking place (EN_RPBK set). forced 100Base-TX mode, when cable unplugged valid signal detected receive pair, link monitor enters "link fail" state NLP's transmitted. When valid signal detected minimum period time, link monitor enters Link Pass State transmits MLT-3 signal.
100BASE-FX
When port configured 100Base-FX mode, either through hardware configuration software configuration (100Base-FX does support ANeg) will support features parameters industry standards. Transmit Function serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive Fiber-transmitter. Receive Function 100Base-FX mode, signal received through PECL receiver inputs, directly passed clock recovery circuit data/clock extraction. mode, scrambler/de-scrambler cipher function bypassed. Link Monitor 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Phy's pin. Far-End-Fault-Indication (FEFI) ANeg provides mechanism inform link partner that remote fault occurred. However, ANeg disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
pattern repeated times. FEFI will signal under conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets transmit Far-End-Fault bit. FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset. meter cable worst case cable attenuation around 24-26 defined TPPMD specification. amplitude phase distortion from cable cause inter-symbol interference (ISI) which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability changes equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable. Clock Synthesizer includes on-chip clock synthesizer that generate clocks 100Base-TX circuitry. also generates clocks 10BaseT ANeg circuitry. clock generator uses fully differential cell that introduces very jitter. Zero Dead Zone Phase Detection method implemented design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. on-chip loop filter eliminates need external components minimizes external noise sensitivity. Only external (RMII) (MII) crystal clock source required reference clock. After power-on reset, clock synthesizer generates clock output until 100Base-X operation mode selected. Jabber (Heartbeat) After transmitter exceeds jabber timer (46mS), transmit loopback functions will disabled signal asserted. After TX_EN goes more than transmitter will reactivate gets de-asserted. Setting Jabber Disable will disable jabber function. When test enabled, pulse with 515BT asserted after each transmitted packet. enabled 10Base-T default, disabled Test Inhibit. Reverse Polarity Detection Correction
10BASE-T/100BASE-TF/FX
Multi-Mode Transmit Driver multi-mode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal 100Base-FX mode, Manchester coded signal 10Base-T mode. 100Base-FX mode, filtering performed. transmit driver utilizes current drive output which well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. 10BaseT mode, high frequency pre-emphasis performed extend cable-driving distance without external filter. pulses also drive through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level builtin bandgap reference external resistor connected IBREF pin. resistor sets output current modes operation. TXOP/N outputs open drain devices with serial source resistance max. When transformer used, current rating 2Vp-p MLT-3 signal, 5Vp-p Manchester signal. 1.25:1 transmit transformer output driver power reduction. This will decrease drive current 100Base-TX operation, 10Base-T operation. Adaptive Equalizer designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT5 cable this length typically attenuation MHz. typical attenuation 100-
Certain cable plants have crossed wiring twisted pairs; reversal TXIN TXIP. Under normal circumstances this would cause receive circuitry reject data. When Auto Polarity 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications Inc. reserves right make changes this document without notice. Document Revision Page
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Disable cleared, ability detect fact that either NLPs burst FLPs inverted automatically reverse receiver's polarity. polarity state stored Reverse Polarity bit. Auto Polarity Disable set, then Reverse Polarity written force polarity reversal receiver. through hardware configuration. There support Auto-Negotiation interface. above combinations possible limitations environment 802.3 standards. Legitimate operating states are: 10Base-T Half Duplex 10Base-T Full Duplex 100Base-TX Half Duplex 100Base-TX Full Duplex 100Base-FX Half Duplex (Port only) 100Base-FX Full Duplex (Port only)
INITIALIZATION SETUP
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins pulled either high reset time. combination high values determines power state device. Many these pins multi-function pins which change their meaning when reset ends.
Only port supports 100Base-FX. hardware configured force above-mentioned modes. forcing mode, will only that mode, hence limiting locations where product will operate. able negotiate mode operation twisted pair environment using AutoNegotiation mechanism defined clause IEEE 802.3u specification. ANeg enabled disabled hardware (ANEGA pin) software (Reg. 0.12) control. When ANeg enabled, chooses mode operation advertising abilities comparing them with ability received from link partner. configured advertise 100Base-TX 10Base-T operating either full half duplex. Register contains current capabilities, speed duplex, Phy, determined through hardware selects chip defaults. contents Reg. sent link partner during ANeg process using Fast Link Pulses (FLPs). string each which particular meaning, total which called Link Code Word. After reset, software change these bits from back from Therefore, hardware priority over software. When ANeg enabled, sends FLPs during following conditions: power link loss restart ANeg command software
SOFTWARE CONFIGURATION
Several different states operation chosen through software configuration. Please refer section well Register Descriptions. LEDs Each ports individual outputs available indicate Speed, Duplex/Collision, Link/Activity. These multi-function pins inputs during reset output pins thereafter. level these pins during reset determines their active output states. multi-function pulled during reset select particular function, then that output would become active low, circuit must designed accordingly, vice versa. (See Configuration.)
AUTO-NEGOTIATION
definition 10/100 Transceiver able either 10Mbps over Twisted Pair Copper (10Base-T), 100Mpbs over Twisted Pair Copper (100Base-TX) 100Mpbs over Fiber Optics (100Base-FX). addition able either half duplex (repeater mode) full duplex. determine operational state, hardware selects software selects while also supporting AutoNegotiation Parallel Detection. 100Base-FX mode, selection must done
During this period, continually sends FLPs while monitoring incoming FLPs from link partner determine their optimal mode operation. FLPs detected during this phase operation, Parallel Detection mode entered (see below).
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
When receives identical link code words (ignoring acknowledge bit) from link partner, stores these code words Reg. sets acknowledge generated FLPs, waits receive identical code word with acknowledge from link partner. Once this occurs configures itself highest technology that common both ends. technology priorities are: 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T half-duplex. presented bits symbol format. This loopback used check operation 5-bit symbol decoder phase locked loop circuitry. Local Loopback, output forced logic TXOP/N outputs tri-stated. Remote Loopback, incoming data passed through equalizer clock recovery, then looped back NRZI/MLT3 converter then transmit driver. This loopback used ensure device's connection media side. also checks operation device's internal adaptive equalizer, phase locked loop circuit, wave-shaper synthesizer. During Remote Loopback, signal detect (SD) output forced logic zero. Cable Length Indicator detect approximate length cable it's attached display result Reg. 20.[7:4]. reading [0000] translates cable used, [0001] translates meter cable, [1111] translates meter cable. cable length value used network manage determine proper connectivity cable manage cable plant distribution
Once ANeg complete, Reg. set, Reg. 1.[14:11] reflects negotiated speed duplex mode, enters negotiated transmission reception state. This state will change until link lost reset through either hardware software, restart negotiation (Reg. 0.9) set.
PARALLEL DETECTION
Because there many devices field that support ANeg process, must still communicated with, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect: Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle
RESET POWER
reset three ways: During initial power Hardware Reset: logic signal pulse width applied RST* pin. Software Reset: Write Reg. 0.15.
mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems, while maintaining flexibility Auto-Negotiation.
power consumption device significantly reduced built-in power management features. Separate power supply lines used power 10BaseT circuitry 100BaseTX circuitry. Therefore, circuits turnedon turned-off independently. When operate 100Base-TX mode, 10Base-T circuitry powered down, vice versa. following power management features supported: Power down mode: This achieved writing Reg. 0.11 pulling PWRDN high. During power down mode, device still able interface through MDC/MDIO management interface. Energy detect power saving mode: Energy detect mode turns power select internal circuitry when there live network
DIAGNOSTICS
Loopback Operation Local Loopback Remote Loopback provided testing purpose. They enabled write either Reg. 0.14 (LPBK) Reg. 21.3 (EN_RPBK). Local Loopback routes transmitted data through transmit path back receiving path's clock data recovery module. loopback data
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
connected. Energy Detect (ED) circuit always turned monitor there signal energy present media. circuitry also powered ready respond management transaction. transmit circuit still send link pulses with minimum power consumption. valid signal received from media, device will power resume normal transmit/receive operation. (Patent Pending) Reduced Transmit Drive Strength mode: Additional power saving gained level designing with 1.25:1 turns ration magnetic asserting TP125 reset.
CLOCK
clock input must clock oscillator measured MHz-100PPM.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver REGISTER DESCRIPTIONS
first seven registers register defined specification. addition these required registers several Altima Communications Inc. specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format): NOTE: When writing registers recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits.
REGISTERS
Register Description Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Default 3000 7849 0022 5541 01E1 0001 0004 2001
REGISTERS 8-31
Register 8-15 25-31 Description Reserved Polarity Interrupt Level Register Interrupt Control/Status Register Diagnostic Register Power/Loopback Register Cable Measurement Register Receive Error Counter Register Reserved Reserved Mode Control Register Reserved Default XXXX 03C0 0000 5020 8060 XXXX 0304 XXXX 0000 0000 XXXX
LEGEND: Read Write Access Self Clearing Latch until cleared reading Read Only Cleared Read Latch High until Cleared reading
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Control Register Reg.bit 0.15 0.14 Name Reset Loopback Description reset. This self-clearing. Enable loopback mode. This will loopback ignore activity cable media. Normal operation. 100Mbps 10Mbps. Enable Auto-Negotiate process (overrides 0.13 0.8) Disable Auto-Negotiate process. Mode selection controlled 0.8, 0.13 through mode pin. Power down. blocks except will turned off. Setting PWRDN high will achieve same result. Normal operation. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test. Refer Mode Table Mode RW/SC Default
0.13 0.12
Speed Select ANeg Enable
Note Note
0.11
Power Down
0.10
Isolate Restart ANeg Duplex Mode
RW/SC
Note
Collision Test
0.[6:0]
Reserved
0000000
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Status Register Reg.bit 1.15 1.14 1.13 1.12 1.11 1.[10:7] Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANeg Complete Description Permanently tied zero indicates 100BaseT4 capability. 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half-duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-Negotiate process completed. Reg. valid after this set. Auto-negotiate process completed. Remote fault condition detected. remote fault. This will remain until cleared reading register Able perform Auto-Negotiation function, default value determined ANEGA pin. Unable perform Auto-Negotiation function. Link established. link fails, this will cleared remain until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. Refer Mode Table Mode Default Note Note Note Note 0000
Remote Fault
RO/LH
ANeg Ability
ANEGA
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
Register Identifier Register Reg.bit 2.[15:0] Name OUI* Description Composed through 18th bits Organizationally Unique Identifier (OUI), respectively. Based 0010A9 (Hex) Mode Default 0022(H)
Register Identifier Register Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name Model Number Revision Number Description Assigned 19th through 24th bits OUI. manufacturer's model number. encoded 010001. Four-bit manufacturer's revision number. 0001 stands Rev. etc. Based 0010A9 (Hex) Mode Default 010101 010100 0001
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Auto-Negotiation Advertisement Register Reg.bit 4.15 4.14 4.13 4.[12:11] 4.10 Name Next Page Acknowledge Remote Fault Reserved FDFC Description Next Page enabled. Next Page disabled. This will internally after receiving consecutive consistent bursts. Advertises that this device detected Remote Fault. remote fault detected. future technology. Full Duplex Flow Control Advertise that DTE(MAC) implemented both optional control sublayer pause function specified clause annex 802.3u. does support flow control Technology supported. This always 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. Protocol Selection [00001] IEEE 802.3. refer Mode Table Mode Default
4.[4:0]
100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field
Note Note Note Note 00001
Register Auto-Negotiation Link Partner Ability Register/Link Partner Next Page Message Reg.bit 5.15 5.14 5.13 5.[12:10] 5.[4:0] Name Next Page Acknowledg Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Description Link partner desires Next Page transfer. Link partner does desire Next Page transfer. Link Partner acknowledges reception words. acknowledged Link Partner. Remote Fault indicated Link Partner. remote fault indicated Link Partner. future technology. 100BaseT4 supported Link Partner. 100BaseT4 supported Link Partner. 100BaseTX full duplex supported Link Partner. 100BaseTX full duplex supported Link Partner. 100BaseTX half duplex supported Link Partner. 100BaseTX half duplex supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps half duplex supported Link Partner. 10Mbps half duplex supported Link Partner. Protocol Selection [00001] IEEE 802.3. Mode Default 00001
Selector Field *When this register used Next Page Message, definition same Register
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Auto-Negotiation Expansion Register Reg.bit 6.[15:5] Name Reserved Parallel Detection Fault Description Fault detected parallel detection logic, this fault more than technology detecting concurrent link condition. This only cleared reading Register using management interface. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner Auto-Negotiation capable. Link partner Auto-Negotiation capable. Mode RO/LH Default
Link Partner Next Page Able Next Page Able Page Received
Link Partner ANeg-Able
Register Auto-Negotiation Next Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 17.[10:0] Name Reserved ACK2 TOG_TX CODE Description Another Next Page desired. other Next Page Transfer desired. Message page. Un-formatted page. Will comply with message. Cannot comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Un -formatted Code Field. Mode Default
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Interrupt Level Control Register Reg.bit 16.15 16.14 16.13 16.12 16.11 Name Reserved INTR_LEVL TXJAM Reserved Test Inhibit Description 1=INTR will active high. 0=INTR will active low. Force send pattern Normal operation Disable 10BaseT testing. Enable 10BaseT testing, which will generate pulse following completion packet transmission. Disable Auto Polarity detection/correction. Enable Auto Polarity detection/correction. Reverse Polarity when Reg. 16.5 Normal Polarity when Reg. 16.5 Reg. 16.5 writing this will reverse polarity transmitter. Mode Default
16.[10:6] 16.5 16.4
Reserved Auto Polarity Disable Reverse Polarity
16.[3:0]
Reserved
Register Interrupt Control/Status Register Reg.bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Not_OK_IE R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK R_Fault_Int ANeg _Comp Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Interrupt Enable. Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received during ANeg. This when parallel detect fault detected. This when with acknowledge received. This when link status switches from status Non-OK status (Fail Ready). This when remote fault detected. This when ANeg complete. Mode Default
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Diagnostic Register Reg.bit 18.[15:12] 18.11 18.10 18.9 Name Reserved DPLX Speed RX_PASS Description result Auto-negotiation: Full-duplex Half-duplex result Auto-neg. speed: 100base-TX 10Base-T 10BT mode, this indicates that Manchester data been detected. 100BT mode, indicates valid signal been received necessarily locked Indicates receive locked onto received signal selected speed operation (10Base-T 100Base-TX). This whenever cycle-slip occurs, will remain until read. Mode Default
18.8
RX_LOCK
RO/RC
18.[7:0]
Reserved
Register Power/Loopback Register Reg.bit 19.[14:7] 19.6 Name Reserved TP125 Description Reserved Transmit transformer ratio selection. 1.25:1 default value this controlled TP125 pin. Enable advanced power saving mode. Disable advanced power saving mode. Reserved ANeg test mode, send instead order test receive integrity. Sending ANeg test mode. Reserved Mode Default
19.5 19.[4:2] 19.1
Power Mode Reserved Link Integrity Test Reserved
19.0
Register Cable measurement capability Register Reg.bit 20.[15:8] 20.[7:4] Name Reserved Cable measurement capability Description These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Mode Default
20.[3:0]
Reserved
Register Receive Error Counter Reg.bit 21.[15:0] Name RX_ER Counter Description Count Receive Error Events Mode Default
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Register Mode Control Register Reg.bit 24.15 Name SDCM_Sel Description Select Common Mode Voltage Signal Detect. Select internal common mode setting. Select external common mode setting. Force 10B-T link without checking NLP. Normal Operation. Ignore link 100Base-TX transmit data. ANeg must disabled this time (ANEGA tied low). Normal Operation. Disable Jabber function PHY. Enable Jabber function PHY. Activity only responds receive operation. Activity responds receive transmit. This should ignored when Reg. one. Disable Fault Insertion. Enable Fault Insertion detection function. This valid when mode enabled. Force transmission Fault Insertion pattern. Normal operation. Receive Error Counter full. Receive Error Counter full. Disable Receive Error Counter. Enable Receive Error Counter. Disable watchdog timer decipher. Enable watchdog timer. Enable remote loopback. Disable remote loopback. Enable 100M data scrambling. Disable 100M data scrambling. When mode selected, this will forced zero. mode selected. Disable mode. Mode Default
24.14 24.13
Disable Force_link_up
24.12 24.11 24.10
Jabber Disable Reserved Conf_ALED
24.9 24.8
Reserved FEF_Disable
FORCE
24.7
Force Transmit Rx_Er_Cnt Full Disable Rx_Er_Cnt Dis_WDT En_RPBK Dis_Scrm
24.6 24.5 24.4 24.3 24.2
SCRAM_EN
24.1 24.0
Reserved FX_SEL
!FX_DIS
Mode Table FX_Dis Force Scram_En ANEGA Condition Port 100Base-FX Port Auto Negotiate 10Base-T 100Base-TX Port Auto Negotiate 10Base-T 100Base-TX Port Forced 100Base-TX Port Forced 10Base-T Port Forced 100Base-TX (unscrambled)
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver 4B/5B CODE-GROUP TABLE
Code Group[4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 SYMBOL Name (TXD/RXD [3:0]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle Control Code 0000 0101 0101 Undefined Undefined Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Transmit Error; used send HALT codegroup Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver READ/WRITE SEQUENCE
Read/Write Sequence Pream bits) Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
Read Write
CONFIGURATIONS
Mode Link Transmit Receive Collision Transmit Receive 100M Link 100M Transmit 100M Receive Collision 100M Transmit 100M Receive LEDDPX during collision during collision LEDACT TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE TOGGLE LEDSPD
Multi Function pulled high reset. Multi Function pulled reset.
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver ELECTRICAL CHARACTERISTICS
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55o +150o Supply Referenced GND. -0.5V +5.0V Digital Input Voltage. -0.5V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature(Ta) -40o +85o Supply Voltage Range(Vc 2.97V 3.63V
Total Power Consumption Parameter Supply Current (per port) Symbol Conditions Base-T, Idle Base-T, Normal activity Base-TX Base-FX 10/100 Base-TX, power without cable Power down Units
Characteristics Parameter Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance Output Transition Time Tristate Leakage Current REFCLK XTAL Pins Parameter Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Conditions Units Symbol 3.15V 3.45V |Ioz| Conditions VCC-0.4 Units
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
Characteristics LED/CFG Pins Parameter Output Voltage Output High Voltage Input Current Output Current Symbol Conditions Units
BASE-TX Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance Symbol Trfs Conditions Note Note Note Note 1.02 ±250 Note resistor each output BASE-T Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance Symbol Conditions Note Transformer 1.25:1 Transformer Units Units
Scrambled Idle Transformer 1.25:1 Transformer
Note resistor each output
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
BASE-FX Transceiver Characteristics Parameter Differential Output Voltage High Differential Output Voltage Signal Rise/Fall Time Output Jitter Differential Output Voltage High Differential Output Voltage Common-Mode Input Voltage Input Differential Output Current Sink Symbol Conditions Note Note Note 3.3V ground BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receiver Link Pulse Link Receive Timer Link Receive Timer Link Transmit Period Link Pulse Width Symbol Conditions Units Link Pulses Units
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
DIGITAL TIMING CHARACTERISTICS
Power Reset Parameter RST* Period Configuration tRST tCONF Conditions Units
tRST
RST* Configuration Pins Power Reset Timing
tCONF
Management Data Interface Parameter CLOCK CLOCK MDIO Setup MDIO Hold tMDCL tMDCH Conditions Units
Setup Read/Write Cycle Hold Read/Write Cycle
tMDCL
tMDCH
MDIO
Management Data Interface Timing
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
100Base -TX/FX 10Base RMII Transmit System Timing Parameter REFCLK period REFCLK High period REFCLK period TX_EN (SOP) !TX_EN (EOP) Propagation Delay TXD[1:0], TX_EN Setup TXD[1:0], TX_EN Hold !TX_EN TX_EN tCKH tCKL tTXS tTXH tTX_TX Conditions 19.999 9.000 9.000 Packet 20.000 10.000 10.000 20.001 11.000 11.000 Units
From TXD[1:0] TXOP/N(_FX) From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
tTXS
TX_EN
tTX_TX tTXH
TXD[1:0]
TXOP/N
FXTP/N
TXOP/N 100Base-TX/FX 10Base RMII Transmit Timing
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
100Base -TX/FX 10Base RMII Receive System Timing Parameter REFCLK period REFCLK High period REFCLK period /J/K (SOP) CRS_DV /T/R (EOP) !CRS_DV Propagation Delay RXD[1:0], CRS_DV, RX_ER Setup RXD[1:0], CRS_DV, RX_ER Hold tCKH tCKL tRCSA tRCSD tRDVA tRXS tRXH Conditions 19.999 9.000 9.000 20.000 10.000 10.000 20.001 11.000 11.000 Units
From RXIP/N(_FX) RXD[1:0] From rising edge REFCLK From rising edge REFCLK
tCKH
REFCLK
Start Packet tCKL
Packet
tRDVA
CRS_DV
tRDVD tRXS tRXH
RXD[1:0] RX_ER /J/K RXIP/N /T/R
FXRP/N RXIP/N 100Base-TX/FX 10Base-T RMII Receive Timing
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation
3.3V
49.9
49.9
AC104QF Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
RJ45 Unused Unused Unused Unused
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
IBREF
RXIP
RXIN
1000
Chassis
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AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation enable mode, FX_DIS must pulled resistor.
3.3V 69.8 69.8
AC104-QF
HFBR-5903 RXVee RXVcc TXVcc TXVee
FXRN
FXRP FXTP
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FX_DIS
FXTN
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
POWER GROUND FILTERING AC104QF
Please contact Altima Communications Inc. latest component value recommendation. Ground Power .1uf Components placed from
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AC104QF
AC104QF Ultra Power 10/100 Quad RMII Ethernet Transceiver
PACKAGE DIMENSIONS AC104QF (100 PQFP)
Quad Flat Pack Outline
3.40
0.25
2.70
23.20 0.25
20.00 0.10
17.20 0.25
14.00 0.10
0.65
0.88
1.60 0.12
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AC104QF highly integrated, 3.3V, power, four port, 10Base-T/100Base-TX

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