AC101QF/TF highly integrated, 3.3V, power, 10Base-T/100Base-TX/FX, Eth

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AC101QF/TF highly integrated, 3.3V, power, 10Base-T/100Base-TX/FX, Eth

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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver GENERAL DESCRIPTION
AC101QF/TF highly integrated, 3.3V, power, 10Base-T/100Base-TX/FX, Ethernet transceiver implemented 0.35µm CMOS technology. Multiple modes operation, including normal operation, test mode power saving mode, available through either hardware software control. Features include interfaces, ENDECs, Scrambler/Descrambler, Auto-Negotiation (ANeg) with support parallel detection. transmitter includes dual-speed clock synthesizer that only needs external clock source (crystal clock oscillator). chip built-in wave shaping driver circuit both 10Mbps 100Mbps, eliminating need external hybrid filter. receiver adaptive equalizer restoration circuit accurate clock data recovery 100Base-TX signal. also provides on-chip pass filer Squelch circuit 10Base-T signal. interfaces support 10/100 MII, 100M only Symbol Mode, only Symbol Mode only wire interface included. AC101TF AC101QF same product different packages.
connection 5Volt tolerant 2.5Volt capable 10/100 TX/FX Full Duplex Half Duplex FEFI 100FX packages 80TQFP 100PQFP Industrial Temp (-40°C +85°C) Very power 280mW (Total) Cable Detect mode 40mW (Total) Power Down mode 3.3mW (Total) Selectable drivers 1.25:1 transformers additional power reduction 3.3Volt .35micron CMOS Fully compliant with IEEE 802.3 802.3u test labs (pending) Baseline Wander Compensation Multi-Function outputs Legacy 10Base-T wire interface 100M Symbol Mode Symbol Mode Cable length indicator Reverse polarity detection correction with Register indication Automatic Forced programmable interrupts Diagnostic registers
BLOCK DIAGRAM
.Framer .Carrier Detect .4B/5B .Clock Recov. .Link Monitor .Signal Detect TP_PMD .MLT-3 .BLW .Stream Cipher TXOP/N
100TX
RXIP/N
100RX
Data Interface
10TX
TXOP/N FXTP/N RXIP/N FXRP/N
Serial Management Interface
Interface
10BASE
10RX
Control/Statu
Serial Management Interface Registers
Gen. Test/LED Control
AutoNegotiation
PHYAD[4:0]
XTLP/N CKIN
TEST[3:0] Drivers
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
REVISION HISTORY REVISION# DATE June 1998 June 2000 Sept 2000 CHANGE Helene CHANGE DESCRIPTION Preliminary Release Final Release Change default value register 561B page Change default value register [15:0] 0101011000011011 page Enhance descriptions DPLX SPEED (register 18.11 18.10) page 2000 Helene Remove Common mode input voltage input differential 100FX transceiver characteristic
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
General Description Features Block Diagram.1 Diagram AC101QF Diagram AC101TF.7 Descriptions Address Pins. (Media Dependent Interface) Pins. (Media Independent Interface) Bypass (Outputs tri-state during isolation.) 10Mbps Bypass. 10Mbps Wire Interface Special Test Pins. Control Status Pins. Indicators Pins Power Ground Pins Connect Pins. Tech Selections.13 Advanced Selections.14 Functional Description.15 Interface.15 MII.15 Interrupt. Carrier Sense RX_DV 7-Wire Bypass.16 100Mbps. 10Mpbs. Media Interface 10Base-T Transmit Function. Receive Function Link Monitor. 100Base-TX Transmit Function. Parallel Serial, NRZI, MLT3 Conversion. Receive Function Baseline Wander Compensation. Clock/Data Recovery Decoder/De-scrambler Link Monitor. 100Base-FX.19 Transmit Function. Receive Function Link Monitor. Far-End-Fault-Insertion (FEFI) 10Base-T/100Base-TX/FX Multi-Mode Transmit Driver. Adaptive Equalizer Clock Synthesizer Jabber (Heartbeat). Reverse Polarity Detection Correction Hardware Configuration.20 Software Configuration 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications, Inc. reserves right make changes this document without notice. Document Revision Page
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
LEDs Auto-Negotiation.20 Parallel Detection.21 Diagnostics.21 Loopback Operation. Cable Length Indicator. Reset Power.22 Clock.22 Register Descriptions Registers 1-7.23 Registers 8-31.23 Register Control Register. Register Status Register. Register Identifier Register. Register Identifier Register. Register Auto-Negotiation Advertisement Register. Register Auto-Negotiation Link Partner Ability Register. Register Auto-Negotiation Expansion Register. Register Auto-Negotiation Next Page Transmit Register. Register Polarity Interrupt Level Register Register Interrupt Control/Status Register. Register Diagnostic Register. Register Power/Loopback Register. Register Cable Measurement Register. Register Mode Control Register. Register Receive Error Counter Register. 4B/5B Code-Group table 4B/5B Code-Group table Read/Write Sequence ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings.33 Operating Range.33 Total Power Consumption. Characteristics REFCLK XTAL Pins Characteristics LED/CFG Pins BASE-TX Transceiver Characteristics BASE-T Transceiver Characteristics. BASE-FX Transceiver Characteristics. BASE-T Link Integrity Timing Characteristics. Digital Timing Characteristics Management Data Interface 100Base-TX/FX Transmit System Timing 100Base-TX/FX Receive System Timing 10Base-T Transmit System Timing. 10Base-T Receive System Timing. 10Base-T 7-Wire Transmit System Timing 10Base-T 7-Wire Receive System Timing. 10Base-T 7-Wire Receive System Timing. 10Base-T 7-Wire Collision Timing Application Termination Application Termination.44 Power ground filtering AC101QF.45 Power ground filtering AC101TF.46 Package dimensions AC101QF (100 PQFP) 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications, Inc. reserves right make changes this document without notice. Document Revision Page
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Package dimensions AC101QF (100 PQFP) Package dimensions AC101TF(80 TQFP).47 Package dimensions AC101TF(80 TQFP).48
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver DIAGRAM AC101QF
RPTR TEST3/SDP RXIN RXIP GNDEQ NC/TEST0/ FXRN NC/TEST1/ FXRP TEST2 NC/FXTP NC/FXTN GNDREF RIBB VAAREF XTLN XTLP GNDT TXOP TXON VAAT VAAT
VAAEQ VAAEQ LEDFDX*/LEDTXB LEDBT*/LEDTXA/CLK25EN* ANEGA/ACTIVITY TECH0/ LINK_BT TECH1/ SPDSEL TECH2/ DUPLEX VAACRV GNDCRV OGND OVDD LEDL*/SD LEDTX*/LEDBTB LEDRX*/LEDSEL LEDCOL*/SCRAM_EN LEDBTX*/LEDBTA/FX_DIS INTR CRS/ 10CRS COL/10COL
AC101QF
TXD[3] TXD[2] TXD[1] TXD[0]/10TD CVDD CGND TX_EN/10TXEN TX_CLK/10TCLK/CLK20 TXER/TXD[4] RXER/RXD[4] RX_CLK/SYM_RCLK/10RCLK RX_DV CGND CVDD RXD[0]/10RD RXD[1] RXD[2] RXD[3] MDIO
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PCSBP ISODEF GNDT CKIN NC/CLK25 BURN_IN RST* PWRDN VAAPLL GNDPLL OGND OVDD PHYAD[4]/TP_RDPHYAD[3]/TP_RD+ PHYAD[2]/TP_TD++ PHYAD[1]/TP_TD+ GPIO[1]/TP125
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver DIAGRAM AC101TF
VAAEQ VAAEQ LEDFDX*/LEDTXB LEDBT*/LEDTXA/CLK25EN* ANEGA/ACTIVITY TECH0/ LINK_BT TECH1/ SPDSEL TECH2/ DUPLEX VAACRV GNDCRV OGND OVDD LEDL*/SD LEDTX*/LEDBTB LEDRX*/LEDSEL LEDCOL*/SCRAM_EN LEDBTX*/LEDBTA/FX_DIS INTR CRS/ 10CRS COL/10COL
RPTR TEST3/SDP RXIN RXIP GNDEQ NC/TEST0/ FXRN NC/TEST1/ FXRP TEST2 NC/FXTP NC/FXTN GNDREF RIBB VAAREF XTLN XTLP GNDT TXOP TXON VAAT VAAT
AC101TF
TXD[3] TXD[2] TXD[1] TXD[0]/10TD CVDD CGND TX_EN/10TXEN TX_CLK/10TCLK/CLK20 TXER/TXD[4] RXER/RXD[4] RX_CLK/SYM_RCLK/10RCLK RX_DV CGND CVDD RXD[0]/10RD RXD[1] RXD[2] RXD[3] MDIO
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PHYAD[3]/TP_RD+ PHYAD[2]/TP_TD++ PHYAD[1]/TP_TD+ GPIO[1]/TP125
PCSBP ISODEF GNDT CKIN NC/CLK25 BURN_IN RST* PWRDN VAAPLL GNDPLL OGND OVDD PHYAD[4]/TP_RD-
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
DESCRIPTIONS
Many pins these devices have multiple functions. multi-function pins will designated bolding number. separate descriptions these pins will listed proper sections. Designers must assure that they have identified modes operation prior final design. SIGNALS TYPES inputs outputs high impedance pull pull down analog signal Active Signal Connect Power Ground Address Pins Name PHYAD PHYAD PHYAD PHYAD PHYAD 101TF 101QF Type I/O, I/O, Description Address. Allows configurable addresses. PHYAD will also determine scramble seed; this will help reduce emission when there multiple ports switching same time (repeater/switch applications).
(Media Dependent Interface) Pins Name RXIN RXIP TXOP TXON FXRN FXRP FXTP FXTN 101TF 101QF Type AO/AI AO/AI AO/AI Description Receiver input positive negative both 10Base-T 100Base-TX. Transmitter output positive negative both 10Base-T 100Base-TX. Receive input positive negative 100Base-FX when FX_DESEL pulled low. Transmit output positive negative 100Base-FX when FX_DESEL pulled low. Signal Detect input from Fiber-optic transceiver when FX_DESEL pulled
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
(Media Independent Interface) Bypass (Outputs tri-state during isolation.) Name MDIO RX_DV 101TF 101QF Type I/O, Description Management Data Input/Output. Bi-directional data interface. 1.5K pull resistor required specified IEEE-802.3). Management Data Clock. clock sourced transfer MDIO data. received data. data synchronous with RX_CLK when RX_DV active. Bypass RXD[3:0] Receive Data Valid. Asserted high when valid data present RX[3:0]. 100Base mode, asserted with first nibble preamble de-asserted when last data nibble been received. 10Base mode, asserted when (Start-of-Frame) delimiter detected de-asserted data. Receive Clock. continuous clock which provides timing reference RX_DV, RX_ER RXD[3:0] signals. 100Base 10Base. reduce system power consumption RX_CLK held inactive (low) when data received Reg. 16.0 enabled. Receive Error. Active high indicate error been detected during frame reception during 100Base mode. Bypass RXD[4] Transmit Error. When TX_ER asserted, will cause 4B/5B encoding process substitute transmit error code-group encoded data word during 100Base mode. Bypass TXD[4] Transmit Clock. continuous clock which provides timing reference TX_EN, TX_ER TXD[3:0] signals. 100Base 10Base. Transmit Enable. TX_EN asserted indicate that valid data present TXD[3:0]. Transmit Data. will source TXD[3:0] synchronous with TX_CLK when TX_EN asserted. Bypass TXD[3:0] Collision. asserted high when collision detected media. Carrier Sense. asserted high when twisted pair media non-idle. Interrupt. Registers polarity sources. INTR high impedance output, pull-up pull-down resistor needed.
RX_CLK
RX_ER RXD[4] TX_ER
TXD[4] TX_CLK
TX_EN INTR
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
10Mbps Bypass Name TP_RDTP_RD+ TP_TD++ TP_TD-TP_TD+ TP_TD101TF 101QF Type I/O, I/O, Description 10Base-T serial input output. ANeg function disabled, therefore, responsible generating performing media arbitration.
10Mbps Wire Interface Name 10RD 10RCLK 10TCLK 10TXEN 10TD 10COL 10CRS 101TF 101QF Type Description Receive Data. serial data output. receive clock. transmit clock. (10TCLK goes idle seconds after link drop.) Transmit enable. Transmit Data. serial data input. Collision. asserted high when collision detected media Carrier Sense. asserted high when twisted pair media active.
Special Test Pins Name CLK25 TEST /BURN-IN TEST0 TEST1 TEST2 TEST3 RST* 101TF 101QF Type AO/AI AO/AI AO/AI Description CLK25 provides continuous clock CLK25EN asserted during reset. Test Enable. When asserted, will force test mode manufacturing test Burn-in mode reliability assurance control. TEST [3:0] pins used test-mode output monitor pin. Internal pulldown normal 100Base-TX 10Base-T mode.
PWRDN
IBREF CKIN XTLN XTLP
Reset. active input will force known initialization state. reset puls duration must Setting Reg. 0.15 will assert software reset, which same functionality hardware reset. Power Down. Driving this high will power down device's analog modules reset device's digital circuits. device still responds management MDC/MDIO data. Power-down mode also achieved setting Reg. 0.11. Reference Bias Resistor. tied analog ground through external 10.0 (1%) resistor. Clock Input. Connects clock source. When crystal input used, this should tied ground Crystal inputs. connected crystal. CKIN should tied when crystal used clock source.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Control Status Pins Name ISODEF 101TF 101QF Type Description Isolate Default. pulled high during reset, interface will tri-stated with multiple PHYs single MAC. status this will latched Register 0.10. Isolate. output pins assume high impedance state when asserted high. However, input pins still respond data. This allows multiple PHYs attached same interface. same isolate condition also achieved setting Reg. 0.10. repeater mode, will tristate pin. Technology Select. When ANEGA high, TECH[2:0] will then negotiable capabilities. (See Tech Selections table) When ANEGA low, TECH[2:0] will then forced capabilities. (See Tech Selections table) When bypass mode, TECH[2:0] follows: TECH[0] 10BaseT Link input (High Active). responsible ANeg, creates 10BaseT Link signal. TECH[1] SPDSEL SYMBOL interface. When de-asserted, only 10BaseT driver used transmit 10Base-T signals, FLP. TECH[2] DUPLEX. responsible indicating duplex operation mode. input values TECH[2] TECH[0] this mode used display only. Auto-Negotiation Ability. ANeg enabled when this pulled high. When this pulled low, mode operation depended TECH[2:0]. This also controls ANEGA Reg.1.3. Activity. bypass mode (PCSBP pull high), provides activity signal generate activity signal. Repeater Mode. When this asserted high repeater mode will enabled. repeater mode, becomes receive activity. test function disabled 10Base-T mode. Repeater also enabled Reg. 16.15. Requires pull down resistor when used applications. Bypass. 100Base-TX 10Base-T enter bypass PCSBP asserted high reset. General Purpose I/O. These pins configured either input output management Reg. 16.[6]. GPIO[0] pull during reset, Base-T 7-wire interface enabled. General Purpose I/O. These pins configured either input output management Reg. 16.[8]. mode, GPIO[1] used select 10Base-T operation mode. With internal pull down, device defaults standard interface 10Base-T after reset. TP125 GPIO[1] pulled high resistor during Reset, 1.25:1 transformer ratio transmitter enabled. type transformer selected default.
TECH /DUPLEX
TECH[1] /SPDSEL
TECH[0] /LINK_BT
ANEGA
ACTIVITY RPTR
PCSBP GPIO[0]
I/O,
GPIO[1] I/O,
TP125
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Indicators Pins Name LEDBTX* 101TF 101QF Type I/O, Description LEDBTX 100Base-X LED. Active indicates 100Base-TX, active high indicates 10BaseT. LEDBTA This used conjunction with LEDBTB that drives 10Base-T status LED. LEDBTA/B pins enabled LEDSEL pulled during reset. (See Advanced connection.) FX_DIS mode De-select. 100Base-FX mode selected this pulled resistor. This internal pull defaulted have mode selected after reset. LEDCOL Collision LED. This will toggle between high when there collision half-duplex mode. inactive full-duplex mode. SCRAM_EN When this pulled during reset scrambler/de-scrambler function will disabled. LEDRX Receive LED. This will toggle between high when data received. LEDSEL When this pulled down during reset LEDBTA, LEDBTB, LEDTXA, LEDTXB used drive dual-color LEDs. (See Advance connections.) LEDTX Transmit LED. This will toggle between high when data transmitted. LEDBTB This used conjunction with LEDBTA that drives 10B-T status LED. LEDBTA/B pins enabled LEDSEL pulled during reset. (See Advanced connection.) LEDL Link LED. Active when link established. 10LSTA When operating 10Base-T 7-wire serial mode, this indicates Link Status (Active High). When bypass mode, this used indicate Signal Detect (Active High) symbol interface. This also active high when link established PCSBP 100B-TX operation. LEDBT 100Base-X output. Active indicates 10BaseT, high indicates 100Base-TX. LEDTXA This used conjunction with LEDTXB that drives 100B-T status LED. LEDTXA/B enabled LEDSEL pulled during reset. (See Advanced connection.) CLK25EN* enable CLK25 output, pull this with LEDFDX Full Duplex LED. Active indicates full duplex, high indicates half duplex. LEDTXB This used conjunction with LEDTXA that drives 100B-T status LED. LEDTXA/B enabled LEDSEL pulled during reset. (See Advanced connection.)
LEDBTA
FX_DIS
LEDCOL
I/O,
SCRAM_EN* LEDRX* I/O,
LEDSEL
LEDTX*
LEDBTB
LEDL* 10LSTA
LEDBT*
I/O,
LEDTXA
CLK25EN* LEDFDX*
LEDTXB
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Power Ground Pins Power Pins VAAPLL OVDD CVDD VAACRV VAAEQ VAAREF VAAT Ground Pins GNDPLL OGND CGND GNDCRV GNDEQ GNDREF GNDT Connect Pins Name 101TF 101QF Type Connect Description 101TF 101TF 101QF 101QF Type Type Ground VAAPLL. Ground OVDD. Ground CVDD. Ground VAACRV. Ground VAAEQ. Ground VCCREF. Ground VCCT. Description power supply PLL. power supply I/O. power supply digital logic. power supply clock recovery. power supply Equalizer. power supply Bandgap reference. power supply transmit driver. Description
TECH SELECTIONS
ANEGEN TECH[2:0] Reg1[14:11] 1111 0001 0100 0010 1000 0000 0001 0100 0101 0011 1100 1111 Reg4[8:5] 1111 0001 0100 0010 1000 0000 0001 0100 0101 0011 1100 1111 Reg0.13 Decide input (Write-able) (Not Write-able) (Not Write-able) (Not Write-able) 1(Not Write-able) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) Reg0.8 Decide input (Writeable) (Not Write-able) (Not Write-able) (Not Write-able) (Not Write-able) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored) (writable, ignored)
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
ADVANCED SELECTIONS
Condition Link 10B-T Link LEDBTA 10Base-T LEDBTB color Yellow LEDTXA 100Base-TX LEDTXB Flashing color Yellow Yellow Green Green
10B-T Flashing Yellow 10B-T Link Green 10B-T Flashing Green 100B-TX Link 100B-TX RX/TX Flashing 100B-TX Link 100B-TX Note: mode, `A'LED blink occur simultaneously. Multi Function pulled high reset. Multi Function pulled reset.
suggested connection diagram shown below that could simplify board design:
LEDBTA
Yellow Green
LEDTXA
Yellow Green
LEDBTB 10Base-T
LEDTXB 100Base-TX
Dual-color indicator Link, Duplex Activity status.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver FUNCTIONAL DESCRIPTION
AC101TF/QF physical layer device (Phy) integrates 100Base-X 10Base-T functions single chip that used Fast Ethernet 10/100 Mbps applications. 100Base-X section consists PCS, PMA, functions 10Base-T section consists Manchester ENDEC transceiver functions. device performs following functions: 4B/5B MLT3 NRZI Manchester Encoding Decoding Clock Data Recovery Stream Cipher Scrambling De-Scrambling Adaptive Equalization Line Transmission Carrier Sense Link Integrity Monitor Auto-Negotiation (ANeg) connectivity Management Function receipt valid data from wire interface, RX_DV will active signaling that valid data will presented RXD[3:0] pins speed RX_CLK. transmission data from MAC, TX_EN presented indicating presence valid data TXD[3:0]. TXD[3:0] sampled synchronous TX_CLK during time that TX_EN valid.
Phy's internal registers accessible only through 2-wire Serial Management Interface (SMI). clock input which used latch data instructions Phy. clock speed from MHz. MDIO bi-directional connection used write instructions write data read data from Phy. Each data latched either rising edge MDC. required maintain speed duty cycle, provided half cycle less than 20ns that data presented synchronous MDC. MDC/MDIO common signal pair Phys design. Therefore, each needs have unique Physical Address. Physical Address using pins defined PHYAD[4:0]. These input signals strapped externally sampled reset negated. idle, responsible pull MDIO line high state. Therefore, 1.5K Ohms resistor required connect MDIO line Vcc. PHYAD reprogrammed software. detailed definition Serial Management registers follows. beginning read write cycle, will send continuous bits clock rate indicate preamble. zero will follow indicate start frame. read code zero, while write code zero one. These will followed bits indicate address bits indicate register address. Then bits follow allow turn around time. read operation, first will high impedance. Neither station will assert this bit. During second time, will assert this zero. write operation, station will drive first time, zero second time. bits data field then presented. first that transmitted register content.
also provides IEEE802.3u compatible Media Independent Interface (MII) communicate with Ethernet Media Access Controller (MAC). Selection Mbps operation based settings internal Serial Management Interface registers determined on-chip ANeg logic. device operate Mbps with full duplex half-duplex mode.
INTERFACE
Media Independent Interface (MII) wire MAC/Phy interface described 802.3u. purpose interface allow layer devices attach variety Physical Layer devices through common interface. operates either 100Mbps 10Mbps, dependant speed Physical Layer. With clocks running either MHz, data clocked between Phy, synchronous with Enable Error signals. time lock incoming signal from wire interface, will generate RX_CLK either 10Mbps 100Mpbs.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Interrupt INTR will asserted whenever selectable interrupt events occur. Assertion state programmable either high through INTR_LEVL register bit. Selection made setting appropriate upper half Interrupt Control Status register. When INTR goes active, interface required read Interrupt Control Status register determine which event caused interrupt. Status bits read only clear read. When INTR asserted, held high impedance state. Carrier Sense RX_DV Carrier sense asserted asynchronously pins soon activity detected receive data stream. RX_DV asserted soon valid (Start-of-Stream Delimiter) detected. Carrier sense RX_DV de-asserted synchronously upon detection valid stream delimiter consecutive idle code groups receive data stream. However, carrier sense asserted valid detected immediately, RX_ER asserted instead RX_DV. 10Base-T mode, asserted asynchronously when valid preamble data activity detected RXIP RXIN pins. half duplex mode, activated during transmit receiving data. full duplex mode, activated during data reception only.
BYPASS
100Mbps designs, encoding/decoding functions performed Phy, thereby allowing -bit data exchange. Certain designs, however, require data transfer form 5-bit symbols. selecting Bypass mode operation, will present data accept data from layer -bit symbols. Bypass mode RX_ER TX_ER pins used RXD4 TXD4. 10Mpbs When using Bypass 10Mbps, standard interface longer valid. Differential drivers receivers carry data serially between Phy.
MEDIA INTERFACE
10BASE-T
When configured 10Base-T mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function interface used, Parallel Serial logic used convert 4-bit data into serial stream. 7-Wire interface used, serial data goes directly Manchester encoder where synthesized through output waveshaping driver. waveshaper reduces emission filtering harmonics, therefore eliminating need external filter. Receive Function received signal passes through low-pass filter, which filters noise from cable, board, transformer. This eliminates need 10Base-T external filter. Manchester decoder converts incoming serial stream. 7-wire 10Base-T interface enabled, decoded serial data presented MAC. interface used, Serial Parallel logic used generate 4-bit data.
7-WIRE
allow legacy 10Mbps only designs, 7-wire serial interface, referred General Purpose Serial Interface (GPSI) been included. GPSI industry standard interface which been implemented many microcontrollers micro-processors, well majority 10Mpbs MACs. interface consists 10Mbps transmit receive clocks, 0Mbps serial transmit receive data, transmit enable, receive enable collision. When running GPSI mode, must forced 10Mbps only mode through hardware configuration.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Link Monitor 10-Base-T link-pulse detection circuit will constantly monitor RXIP/RXIN pins presence valid link pulses. absence valid link pules, Link Status will cleared Link will de-assert. X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmitted frequency range, thus eliminating peaks single frequency. repeater applications, where ports transmit same data simultaneously, signal energy spread further using non-repeating sequence each Phy, i.e., scrambled seed unique each different based address. When Dis_Scrm data scramb ling function disabled, 5-bit data stream clocked directly device's sublayer. Parallel Serial, NRZI, MLT3 Conversion 5-bit data clocked into Phy's shift register with clock, clocked with clock convert into serial stream. serial data converted from NRZI format, which produces transition Logic transition Logic further reduce emissions, NRZI data converted MLT-3 signal. conversion offers reduction emissions. This allows system designers meet Class limit. Whenever there transition occurring NRZI data, there corresponding transition occurring MLT-3 data. NRZI data, changes count up/down direction after every single transition. MLT-3 data, changes count up/down direction after every transitions. NRZI MLT-3 data conversion implemented without reference timing clock information. conversion requires detecting transitions incoming NRZI data setting count up/down direction MLT-3 data. Asserting FX_SEL high will disable this encoding. slew rate transmitted MLT-3 signal controlled reduce emissions. MLT-3 signal after magnetic typical rise/fall time approximately which within target range specified ANSI standard. This guaranteed with either 1.25:1 transformer. Receive Function 100Base-TX receive path functions inverse transmit path. receive path includes receiver with adaptive equalization restoration front end. also includes MLT-3 NRZI converter, data clock recovery, NRZI/NRZ conversion, Serial-to-Parallel
100BASE-TX
When configured 100Base-TX mode, either through hardware configuration, software configuration ANeg, will support features parameters industry standards. Transmit Function 100Base-TX mode, transmit function converts synchronous 4-bit data nibbles from pair Mbps differential serial data streams. serial data transmitted over network twisted pair cables isolation transformer. Data conversion includes 4B/5B encoding, scrambling, parallel serial, NRZI, MLT-3 encoding. entire operation synchronous clock. Both clocks generated on-chip clock synthesizer that locked external clock source. transmit data, 4-bit nibbles rate, transmitted from TXD[3:0] signals. 4B/5B encoder replaces first nibbles preamble from frame with /J/K/ code-group pair Start-of-Stream Delimiter (SSD), following onset TX_EN signal. 4B/5B encoder appends /T/R/ codegroup pair End-of-Stream Delimiter (ESD) transmission place first IDLE codegroups that follow negation TX_EN signal. encapsulated data stream converted from 4-bit nibbles 5-bit code-groups. During inter-packet gap, when there data present, continuous stream IDLE code-groups transmitted. When TX_ER asserted while TX_EN active, Transmit Error code-group substituted translated code word. 4B/5B encoding bypassed when Reg. 21.1 "1", PCSBP strapped high. 100Base-TX mode, 5-bit transmit data stream scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function:
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
conversion, de-scrambler, 5B/4B decoder. receiver circuit starts with bias differential RX+/- inputs, followed with low-pass filter filter high frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful powersaving mode. amplification ratio slicer's threshold on-chip bandgap reference. Baseline Wander Compensation 100Base-TX data stream always balanced. transformer blocks components incoming signal, thus offset differential receive inputs drift. shifting signal level, coupled with non-zero rise fall times serial stream cause pulse-width distortion. This creates jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. This implements patent-pending restoration circuit. Unlike traditional implementation, circuit does need feedback information from slicer clock recovery circuit. This design simplifies circuit design eliminates random/systematic offset receive path. 10BaseT 100BaseFX modes, baseline wander correction circuit required, therefore disabled. Clock/Data Recovery equalized MLT-3 signal passes through slicer circuit, gets converted NRZI format. uses proprietary mixed-signal phase locked loop (PLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked clock input while receive clock locked incoming data streams. When initial lock achieved, switches data stream, extracts clock, uses framing recovered data. recovered clock also used generate RX_CLK signal. requires external components operation high noise immunity jitter. provides fast phase alignment locks data transition. data/clock acquisition time after power-on less than transitions. maintain lock runlengths data bits absence signal transitions. When valid data present, i.e. when de-asserted, will switch lock TX_CLK. This provides continuously running RX_CLK. interface, data RXD[4:0] synchronized RX_CLK. Decoder/De-scrambler de-scrambler detects state transmit Linear Feedback Shift Register (LFSR) looking sequence representing consecutive idle codes. de-scrambler acquires lock data stream recognizing IDLE bursts more bits locks frequency de-ciphering LFSR. Once lock acquired, device operate with inter-packet-gap (IPG) However, before lock acquired, de-scrambler needs minimum consecutive idles between packets order acquire lock. de-ciphering logic also tracks number consecutive errors received while RX_DV asserted. Once error counter exceeds limit currently consecutive errors, logic assumes that lock been lost, de-cipher circuit resets itself. process regaining lock will start again. Stream cipher de-scrambler used 100Base-FX 10Base-T modes. Link Monitor Signal level detected through squelch detection circuitry. signal detect (SD) circuit allows equalizer assert high whenever peak detector detects post-equalized signal with peak ground voltage greater than This approximately normal signal voltage level. addition, energy level must sustained longer than order signal detect signal stay gets de-asserted approximately after energy level drops consistently below from peak ground. link signal forced during local loopback operation (Loopback register set) forced high when remote loopback taking place (EN_RPBK set). forced 100Base-TX mode, when cable unplugged valid signal detected receive pair, link monitor enters "link fail" state NLP's transmitted. When valid signal detected minimum period time, link monitor enters Link Pass State transmits MLT-3 signal.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
100BASE-FX
When configured 100Base-FX mode, either through hardware configuration software configuration (100Base-FX does support ANeg) will support features parameters industry standards. Transmit Function serialized data bypasses scrambler 4B/5B encoder mode. output data NRZI PECL signals. PECL level signals used drive Fiber-transmitter. Receive Function 100Base-FX mode, signal received through PECL receiver inputs, directly passed clock recovery circuit data/clock extraction. mode, scrambler/de-scrambler cipher function bypassed. Link Monitor 100Base-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly Phy's pin. Far-End-Fault-Insertion (FEFI) ANeg provides mechanism inform link partner that remote fault occurred. However, ANeg disabled 100Base-FX applications. alternative in-band signaling function (FEFI) used signal remote fault condition. FEFI stream consecutive ones followed logic zero. This pattern repeated times. FEFI will signal under conditions: When activity received from link partner, When clock recovery circuit detects signal error lock error, When management entity sets transmit Far-End-Fault bit. FEFI mechanism enabled default 100Base-FX mode, disabled 100Base-TX 10Base-T modes. register setting changed software after reset. 100Base-FX mode, Manchester coded signal 10Base-T mode. 100Base-FX mode, filtering performed. transmit driver utilizes current drive output which well balanced produces noise PECL signal. PECL voltage levels produced with resistive terminations. (See section 16.) 10BaseT mode, high frequency pre-emphasis performed extend cable-driving distance without external filter. pulses also drive through 10BaseT driver. 10BaseT 100BaseTX transmit signals multiplexed transmit output driver. This arrangement results using same external transformer both 10BaseT 100BaseTX. driver output level builtin bandgap reference external resistor connected RIBB pin. resistor sets output current modes operation. TXOP/N outputs open drain devices with serial source resistance maximum. When transformer used, current rating 2Vp-p MLT-3 signal, 5Vp-p Manchester signal. 1.25:1 transmit transformer output driver power reduction. This will decrease drive current 100Base-TX operation, 10Base-T operation. Adaptive Equalizer designed accommodate maximum meters CAT-5 cable. AT&T 1061 CAT5 cable this length typically attenuation MHz. typical attenuation 100meter cable worst case cable attenuation around 24-26 defined TPPMD specification. amplitude phase distortion from cable cause inter-symbol interference (ISI) which makes clock data recovery difficult. adaptive equalizer designed closely match inverse transfer function twisted-pair cable. equalizer ability changes equalizer frequency response according cable length. equalizer will tune itself automatically cable, compensating amplitude phase distortion introduced cable.
10BASE-T/100BASE-TX/FX
Multi-Mode Transmit Driver lti-mode driver transmits MLT-3 coded signal 100Base-TX mode, NRZI coded signal
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Clock Synthesizer includes on-chip clock synthesizer that generate clocks 100Base-TX circuitry. also generates clocks 10BaseT ANeg circuitry. clock generator uses fully differential cell that introduces very jitter. Zero Dead Zone Phase Detection method implemented design provides excellent phase tracking. charge pump with charge sharing compensation also included further reduce jitter different loop filter voltages. on-chip loop filter eliminates need external components minimizes external noise sensitivity. Only external crystal clock source required reference clock. After power-on reset, clock synthesizer generates clock output until 100Base-X operation mode selected. Jabber (Heartbeat) After transmitter exceeds jabber timer (46mS), transmit loopback functions will disabled signal asserted. After TX_EN goes more than transmitter will reactivate gets de-asserted. Setting Jabber Disable will disable jabber function. When test enabled, pulse with 515BT asserted after each transmitted packet. enabled 10Base-T default, disabled Test Inhibit. Reverse Polarity Detection Correction Certain cable plants have crossed wiring twisted pairs; reversal TXIN TXIP. Under normal circumstances this would cause receive circuitry reject data. When Auto Polarity Disable cleared, ability detect fact that either NLPs burst FLPs inverted automatically reverse receiver's polarity. polarity state stored Reverse Polarity bit. Auto Polarity Disable set, then Reverse Polarity written force polarity reversal receiver.Initialization Setup pulled either high reset time. combination high values determines power state device. Many these pins multi-function pins which change their meaning when reset ends.
SOFTWARE CONFIGURATION
Several different states operation chosen through software configuration. Please refer section well Register Descriptions. LEDs Individual outputs available indicate Speed, Duplex, Collision, Receive, Transmit, Link. These multi-function pins inputs during reset output pins thereafter. level these pins during reset determines their active output states. multi-function pulled during reset select particular function, then that output would become active low, circuit must designed accordingly, vice versa. addition individual configurations, advanced circuit been implemented, illustrated Advanced Selections.
AUTO-NEGOTIATION
definition 10/100 Transceiver able either 10Mbps over Twisted Pair Copper (10Base-T), 100Mpbs over Twisted Pair Copper (100Base-TX) 100Mpbs over Fiber Optics (100Base-FX). addition able either half duplex (repeater mode) full duplex. determine operational state, hardware selects software selects while also supporting AutoNegotiation Parallel Detection. 100Base-FX mode, selection must done through hardware configuration. There support Auto-Negotiation interface. above combinations possible limitations environment 802.3 standards. Legitimate operating states are: 10Base-T Half Duplex 10Base-T Full Duplex 100Base-TX Half Duplex 100Base-TX Full Duplex 100Base-FX Half Duplex 100Base-FX Full Duplex
HARDWARE CONFIGURATION
Several different states operation chosen through hardware configuration. External pins
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
hardware configured force above mentioned modes. forcing mode, will only that mode, hence limiting locations where product will operate. able negotiate mode operation twisted pair environment using AutoNegotiation mechanism defined clause IEEE 802.3u specification. ANeg enabled disabled hardware (ANEGA pin) software (Reg. 0.12) control. When ANeg enabled, chooses mode operation advertising abilities comparing them with ability received from link partner. configured advertise 100Base-TX 10Base-T operating either full half duplex. Register contains current capabilities, speed duplex, Phy, determined through hardware selects (TECH[2:0]) chip defaults. contents Reg. sent link partner during ANeg process using Fast Link Pulses (FLPs). string each which particular meaning, total which called Link Code Word. After reset, software change these bits from back from Therefore, hardware priority over software. When ANeg enabled, sends FLPs during following conditions: power link loss restart command enters negotiated transmission reception state. This state will change until link lost reset through either hardware software, restart negotiation (Reg. 0.9) set.
PARALLEL DETECTION
Because there many devices field that support ANeg process, must still communicated with, necessary detect link through Parallel Detection process. parallel detection circuit enabled absence FLPs. circuit able detect: Normal Link Pulse (NLP) 10Base-T receive data 100Base-TX idle
mode operation gets configured based technology incoming signal. above detected, device automatically configures match detected operating speed half duplex mode. This ability allows device communicate with legacy 10Base-T 100Base-TX systems, while maintaining flexibility Auto-Negotiation.
DIAGNOSTICS
Loopback Operation Local Loopback Remote Loopback provided testing purpose. They enabled write either Reg. 0.14 (LPBK) Reg. 21.3 (EN_RPBK). Local Loopback routes transmitted data through transmit path back receiving path's clock data recovery module. loopback data presented bits symbol format. This loopback used check operation 5-bit symbol decoder phase locked loop circuitry. Local Loopback, output forced logic TXOP/N outputs tri-stated. Remote Loopback, incoming data passed through equalizer clock recovery, then looped back NRZI/MLT3 converter then transmit driver. This loopback used ensure device's connection media side. also checks operation device's internal adaptive equalizer, phase locked loop circuit, wave-shaper synthesizer. During Remote Loopback, signal detect (SD) output forced logic zero.
During this period, continually sends FLPs while monitoring incoming FLPs from link partner determine their optimal mode operation. FLPs detected during this phase operation, Parallel Detection mode entered (see below). When receives identical link code words (ignoring acknowledge bit) from link partner, stores these code words Reg. sets acknowledge generated FLPs, waits receive identical code word with acknowledge from link partner. Once this occurs configures itself highest technology that common both ends. technology priorities are: 100Base-TX, full-duplex 100Base-TX, half-duplex 10Base-T, full-duplex 10Base-T half-duplex.
Once ANeg complete, Reg. set, Reg. 1.[14:11] reflects negotiated speed duplex mode, 2055 Gateway Parkway Suite 700, Jose, 95110 (408) 453-3700 (www.altimacom.com) Altima Communications, Inc. reserves right make changes this document without notice. Document Revision Page
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Cable Length Indicator detect length cable it's attached display result Reg. 20.[7:4]. reading [0000] translates cable used, [0001] translates meter cable, [1111] translates meter cable. cable length value used network manage determine proper connectivity cable manage cable plant distribution Energy detect power saving mode: Energy detect mode turns power select internal circuitry when there live network connected. Energy Detect (ED) circuit always turned monitor there signal energy present media. management circuitry also powered ready respond management transaction. transmit circuit still send link pulses with minimum power consumption. valid signal received from media, device will power resume normal transmit/receive operation. (Patent Pending) Valid data detection mode: This achieved writing Receive Clock Register Control Bit. During this mode, there data other than idles coming receive clock (RX_CLK) will turn off. This could save power attached media access controller. RX_CLK will resume operation clock period prior assertion RX_DV. receive clock will again shut clock cycles after RX_DV gets de-asserted. Reduced Transmit Drive Strength mode: Additional power saving gained level designing with 1.25:1 turns ration magnetic (see register descriptions).
RESET POWER
reset three ways: During initial power Hardware Reset: (See descriptions). Software Reset: (See regis descriptions).
power consumption device significantly reduced built-in power management features. Separate power supply lines used power 10BaseT circuitry 100BaseTX circuitry. Therefore, circuits turnedon turned-off independently. When operate 100Base-TX mode, 10Base-T circuitry powered down, vice versa. following power management features supported: Power down mode: (See register descriptions). During power down mode, device still able interface through management interface.
CLOCK
clock input either clock oscillator crystal measured MHz-100PPM.
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
REGISTER DESCRIPTIONS
first seven registers register defined specification. addition these required registers several Altima Communications Inc. specific registers. There reserved registers and/or bits that Altima internal only. following standard registers supported. (Register numbers Decimal format, values format):
NOTE: When writing registers recommended that read/modify/write operation performed, unintended bits unwanted states. This applies registers, including those with reserved bits. LEGEND: Read Write Access Self Clearing Latch until cleared reading Read Only Cleared Read Latch High until Cleared reading
REGISTERS
Register Description Control Register Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Default 3000 7849 0022 561B 01E1 0001 0004 2001
REGISTERS 8-31
Register 8-15 25-31 Description Reserved Polarity Interrupt Register Interrupt Control/Status Register Diagnostic Register Power Management Loopback Register Cable Measurement Register Mode Control Register Reserved Reserved Receive Error Counter Register Reserved Default XXXX 03C0 0000 5020 8060 XXXX 0304 XXXX 0000 0000 XXXX
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Control Register Reg.bit 0.15 0.14 Name Reset Loopback Description reset. This self-clearing. Enable loopback mode. This will loopback ignore activity cable media. Normal operation. 100Mbps 10Mbps. Tech Selections Enable Auto-Negotiate process (overrides 0.13 0.8) Disable Auto-Negotiate process. Mode selection controlled 0.8, 0.13 through TECH[2:0] pins. Power down. blocks except will turned off. Setting PWRDN high will achieve same result. Normal operation. Electrically isolate from MII. still able response SMI. default value this depends ISODEF pin. Normal operation. Restart Auto-Negotiation process. Normal operation. Full duplex. Half duplex. Tech Selections Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. Disable test. Mode RW/SC Default
0.13 0.12
Speed Select ANeg Enable
TECH[2:0] ANEGA
0.11
Power Down
0.10
Isolate
ISODEF
Restart ANeg Duplex Mode
RW/SC
TECH[2:0]
Collision Test
0.[6:0]
Reserved
0000000
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Status Register Reg.bit 1.15 1.14 1.13 1.12 1.11 1.[10:7] Name 100Base-T4 100Base-TX Full Duplex 100Base-TX Half Duplex 10Base-T Full Duplex 10Base-T Half Duplex Reserved Preamble Suppression ANeg Complete Description Permanently tied zero indicates 100BaseT4 capability. 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half-duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. able perform management transaction without MDIO preamble. management interface needs minimum bits preamble after reset. Auto-Negotiate process completed. Reg. valid after this set. Auto-negotiate process completed. Remote fault condition detected. remote fault. This will remain until cleared reading register Able perform Auto-Negotiation function, default value determined ANEGA pin. Unable perform Auto-Negotiation function. Link established. link fails, this will cleared remain until register read again. Link gone down. Jabber condition detect. Jabber condition detected. Extended register capable. This tied permanently one. Mode Default TECH[2:0] TECH[2:0] TECH[2:0] TECH[2:0] 0000
Remote Fault
RO/LH
Aneg. Ability
ANEGA
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
Register Identifier Register Reg.bit 2.[15:0] OUI* Name Description Composed through 18th bits Organizationally Unique Identifier (OUI), respectively. Based 0010A9 (Hex) Register Identifier Register Reg.bit 3.[15:10] 3.[9:4] 3.[3:0] Name Model Number Revision Number Description Assigned 19th through 24th bits OUI. manufacturer's model number. encoded 100001. Four-bit manufacturer's revision number. 0011 stands Rev. etc. Based 0010A9 (Hex) Mode Default 010101 100001 1011 Mode Default 0022(H)
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Auto-Negotiation Advertisement Register Reg.bit 4.15 4.14 4.13 4.[12:10] 4.[4:0] Name Next Page Acknowledge Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field Description Next Page enabled. Next Page disabled. This will internally after receiving consecutive consistent bursts. Advertises that this device detected Remote Fault. remote fault detected. future technology. Technology supported. This always 100BaseTX full duplex capable. 100BaseTX full duplex capable. 100BaseTX half duplex capable. half duplex capable. 10BaseT full duplex capable. 10BaseT full duplex capable. 10BaseT half duplex capable. 10BaseT half duplex capable. Protocol Selection [00001] IEEE 802.3. Mode Default TECH [2:0] TECH [2:0] TECH [2:0] TECH [2:0] 00001
Register Auto-Negotiation Link Partner Ability Register Reg.bit 5.15 5.14 5.13 5.[12:10] 5.[4:0] Name Next Page Acknowledge Remote Fault Reserved 100Base-T4 100Base-TX Full Duplex 100Base-TX 10Base-T Full Duplex 10Base-T Selector Field Description Link partner desires Next Page transfer. Link partner does desire Next Page transfer. Link Partner acknowledges reception words. acknowledged Link Partner. Remote Fault indicated Link Partner. remote fault indicated Link Partner. future technology. 100BaseT4 supported Link Partner. 100BaseT4 supported Link Partner. 100BaseTX full duplex supported Link Partner. 100BaseTX full duplex supported Link Partner. 100BaseTX half duplex supported Link Partner. 100BaseTX half duplex supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps full duplex supported Link Partner. 10Mbps half duplex supported Link Partner. 10Mbps half duplex supported Link Partner. Protocol Selection [00001] IEEE 802.3. Mode Default 00001
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Auto-Negotiation Expansion Register Reg.bit 6.[15:5] Name Reserved Parallel Detection Fault Description Fault detected parallel detection logic, this fault more than technology detecting concurrent link condition. This only cleared reading Register using management interface. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon read this register. Link partner Auto-Negotiation capable. Link partner Auto-Negotiation capable. Mode RO/LH Default
Link Partner Next Page Able Next Page Able Page Received
Link Partner ANeg-Able
Register Auto-Negotiation Next Page Transmit Register Reg.bit 7.15 7.14 7.13 7.12 7.11 17.[10:0] Reserved ACK2 TOG_TX CODE Name Description Another Next Page desired. other Next Page Transfer desired. Message page. Un-formatted page. Will comply with message. comply with message. Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Un -formatted Code Field. Mode Default
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Polarity Interrupt Level Register Reg.bit 16.15 16.14 16.[13:12] 16.11 Name Repeater INTR_LEVL Reserved Test Inhibit Description Repeater mode, full-duplex will inactive, only responses receive activity. test function abled. 1=INTR will active high. 0=INTR will active low. Disable 10BaseT testing. Enable 10BaseT testing, which will generate pulse following completion packet transmission. Enable normal loopback 10BaseT mode. Disable normal loopback 10BaseT mode. When GPIO[1] (Reg. 16.8) one, this value reflects signal GPIO[1] pin. When GPIO[1] value this will display GPIO[1] pin. then GPIO[1] input. zero then GPIO[1] output. When GPIO[0] (Reg. 16.6) one, this value reflects signal GPIO[0] pin. When GPIO[0] value this will display GPIO[0] pin. then GPIO[0] input. zero then GPIO[0] output. Disable Auto Polarity detection/correction. Enable Auto Polarity detection/correction. Reverse Polarity when Reg. 16.5 Normal Polarity when Reg. 16.5 Reg. 16.5 writing this will reverse polarity transmitter. Writing this will shut RX_CLK when incoming data present. RX_CLK will resume clock cycle prior RX_DV going high, shut clock cycles after RX_DV goes low. action when Loopback Bypassed modes. Mode Default RPTR
16.10 16.9
10BaseT Loopback GPIO[1] Data
16.8 16.7
GPIO[1] GPIO[0] Data
16.6 16.5 16.4
GPIO[0] Auto Polarity Disable Reverse Polarity
16.[3:1] 16.0
Reserved Receive Clock Control
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Interrupt Control/Status Register Reg.bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 17.7 17.6 17.5 17.4 17.3 17.2 17.1 17.0 Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Not_OK_ R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK R_Fault_Int ANeg _Comp Description Jabber Interrupt Enable. Receive Error Interrupt Enable. Page Received Interrupt Enable. Parallel Detection Fault Interrupt Enable. Link Partner Acknowledge Interrupt Enable. Link Status Interrupt Enable. Remote Fault Interrupt Enable. Auto-Negotiation Complete Interrupt Enable. This when jabber event detected. This when RX_ER transitions high. This when page received during ANeg. This when parallel detect fault detected. This when with acknowledge received. This when link status switches from status Non-OK status (Fail Ready). This when remote fault detected. This when ANeg complete. Mode Default
Register Diagnostic Register Reg.bit 18.[15:12] 18.11 18.10 18.9 Name Reserved DPLX Speed RX_PASS Description result Auto-Negotiation Full-duplex Half-duplex result Auto-Neg. 100Base-TX 10Base-T 10BT mode, this indicates that Manchester data been detected. 100BT mode, indicates valid signal been received necessarily locked Indicates receive locked onto received signal selected speed operation (10Base-T 100Base-TX). This whenever cycle-slip occurs, will remain until read. Mode Default 0000
18.8
RX_LOCK
RO/RC
18.[7:0]
Reserved
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Power/Loopback Register Reg.bit 19.[14:7] 19.6 Name Reserved TP125 Description Reserved Transmit transformer ratio selection. 1.25:1 default value this controlled TP125 pin. Enable advanced power saving mode. Disable advanced power saving mode. Enable test loopback. (MII through clock recovery MII) Normal operation. Enable loopback. Normal operation. Enable link pulse loopback. Normal operation. ANeg test mode, send instead order test receive integrity. Sending ANeg test mode. Reduce time constant ANeg timer. Normal operation. Mode Default
19.5 19.4 19.3 19.2 19.1
Power Mode Test Loopback Digital loopback LP_LPBK Link Integrity Test Reduce Timer
19.0
Register Cable Measurement Register Reg.bit 20.[15:8] 20.[7:4] Name Reserved Cable measurement capability Description These bits used cable length indicator. bits incremented from 0000 1111, with increment approximately meters. equivalent with increment MHz. value read back from equalizer, measured value absolute. Mode Default
20.[3:0]
Reserved
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Register Mode Control Register Reg.bit 21.15 21.14 21.13 Name Reserved Disable Force_link_up Description Force 10B-T link without checking NLP. Normal Operation. Ignore link 100Base-TX transmit data. ANeg must disabled this time (ANEGA tied low). Normal Operation. Disable Jabber function PHY. Enable Jabber function PHY. Enable 7-wire interface 10Base-T operation. Normal operation. (Not valid Bypass mode.) Activity only responds receive operation. Activity responds receive transmit. This should ignored when Reg. repeater mode. configuration which compatible with TSC78Q2120. Select Advanced Selections. Disable Fault Insertion. Enable Fault Insertion detection function. This valid when mode enabled. Force transmission Fault Insertion pattern. Normal operation. Receive Error Counter full. Receive Error Counter full. Disable Receive Error Counter. Enable Receive Error Counter. Disable watchdog timer decipher. Enable watchdog timer. Enable remote loopback. Disable remote loopback. Enable 100M data scrambling. Disable 100M data scrambling. When mode selected, this will forced zero. Bypass PCS. Disable 4b/5b scrambler 100B-TX mode. Enable PCS. Enable 4b/5b scrambler 100B-TX mode. mode selected. Disable mode. Mode Default
21.12 21.11 21.10
Jabber Disable 10BT_Sel Conf_ALED
21.9
LED_Sel
21.8
FEF_Disable
LED_RX/ LEDSEL TECH,
FX_DESEL,
21.7 21.6 21.5 21.4 21.3 21.2
Force Transmit Rx_Er_Cnt Full Disable Rx_Er_Cnt Dis_WDT En_RPBK Dis_Scrm
ANEGA
LED_COL/ SCRAM_EN
21.1 21.0
PCSBP FX_SEL
PCSBP
FX_DESEL
Register Receive Error Counter Register Reg.bit 24.[15:0] Name RX_ER counter Count receive error events. Description Mode Default 0000
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver 4B/5B CODE-GROUP TABLE
Code Group[4 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 SYMBOL Name (TXD/RXD [3:0])[3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Idle Control Code 0000 0101 0101 Undefined Undefined Invalid Code 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Transmit Error; used send HALT code-group Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Invalid code Inter-Packet Idle; used inter-stream fill code. Start stream delimiter, part always pair with symbol. Start stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. stream delimiter, part always pair with symbol. Description Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data
READ/WRITE SEQUENCE
Read/Write Sequence Pream bits) Start bits) OpCode bits) PHYAD bits) AAAAA AAAAA REGAD bits) RRRRR RRRRR TurnAround bits) Data bits) Idle
Read Write
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver ELECTRICAL CHARACTERISTICS
NOTE: following electrical characteristics design goals rather than characterized numbers.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. -55o +150o Supply Referenced GND. -0.5V +5.0V Digital Input Voltage. -0.5V Output Voltage. -0.5V
OPERATING RANGE
Operating Temperature(Ta) -40o +85o Supply Voltage Range(Vcc) 2.97V 3.63V
Total Power Consumption Parameter Supply Current Symbol Conditions Base-T, Idle Base-T, Normal activity Base-TX Base-FX 10/100 Base-TX, power without cable Power down Units
Characteristics Parameter Input Voltage High Input Voltage Input Current Output Voltage High Output Voltage Output Current High Output Current Input Capacitance Output Transition Time Tristate Leakage Current REFCLK XTAL Pins Parameter Input Voltage Input Voltage High Input Clock Frequency Tolerance Input Clock Duty Cycle Input Capacitance Symbol Conditions Units Symbol 3.15V 3.45V |Ioz| Conditions VCC-0.4 Units
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
Characteristics LED/CFG Pins Parameter Output Voltage Output High Voltage Input Current Output Current Symbol Conditions Units
BASE-TX Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Output Voltage Symmetry Signal Rise/Fall Time Rise/Fall Time Symmetry Duty Cycle Distortion Overshoot/Undershoot Output Jitter Receive Jitter Tolerance Output Current High Output Current High Common Mode Input Voltage Common Mode Input Current Differential Input Resistance Symbol Trfs Conditions Note Note Note Note 1.02 +250 Note resistor each output BASE-T Transceiver Characteristics Parameter Peak Peak Differential Output Voltage Signal Rise/Fall Time Output Current Sink Output Current High Output Current High Start Idle Pulse Width Output Jitter Receive Jitter Tolerance Receive Input Impedance Differential Squelch Threshold Common Mode Rejection Differential Input Resistance Symbol Conditions Note Transformer 1.25:1 Transformer Units Units
Scrambled Idle Transformer 1.25:1 Transformer
Note resistor each output
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
BASE-FX Transceiver Characteristics Parameter Differential Output Voltage High Differential Output Voltage Signal Rise/Fall Time Output Jitter Differential Output Voltage High Differential Output Voltage Output Current Sink Symbol Conditions Note Note Note 3.3V ground BASE-T Link Integrity Timing Characteristics Parameter Time Link Loss Receiver Link Pulse Link Receive Timer Link Receive Timer Link Transmit Period Link Pulse Width Symbol Conditions Units Link Pulses Units
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
DIGITAL TIMING CHARACTERISTICS
Power Reset
Parameter RST* Period Configuration tRST tCONF tRST
RST* Configuration Pins Power Reset Timing
Conditions
Units
tCONF
Management Data Interface Parameter CLOCK CLOCK MDIO Setup MDIO Hold tMDCL tMDCH Conditions Units
Setup Read/Write Cycle Hold Read/Write Cycle
tMDCL
tMDCH
MDIO
Management Data Interface Timing
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
100Base -TX/FX Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TX_EN TX_EN sampled TX_EN sampled !TX_EN !TX_EN sampled !CRS !TX_EN sampled !COL Propagation Delay TXD[3:0], TX_EN, TX_ER Setup TXD[3:0], TX_EN, TX_ER Hold !TX_EN TX_EN tCKH tCKL tCSA tCLA tCSD tCLD tTXS tTXH tTX_TX Start Packet tCKL tTX_TX tTXH
TXD[3:0] TX_ER
Conditions
39.998 18.000 18.000 Packet
40.000 20.000 20.000
40.002 22.000 22.000
Units
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N(FXTP/N) From rising edge TX_CLK From rising edge TX_CLK
tCKH
TX_CLK
tTXS
TX_EN
TXOP/N
FXTP/N
tTCSA
tTCSD
tTCLA
100Base-TX/FX Transmit Timing
tTCLD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
100Base -TX/FX Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period /J/K RX_DV assert /J/K assert /J/K assert /T/R !RX_DV /T/R !CRS /T/R !COL Propagation Delay RXD[3:0], RX_DV, RX_ER Setup RXD[3:0], RX_DV, RX_ER Hold tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions 39.998 18.000 18.000 40.000 20.000 20.000 40.002 22.000 22.000 Units
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N(FXRP/N) RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
tCKH
RX_CLK
Start Packet tCKL
Packet
tRDVA
RX_DV
tRDVD tRXS tRXH
RXD[3:0] RX_ER RX_DV /J/K RXIP/N /T/R
FXRP/N
tRCSA
tRCSD
tRCLA
100Base-TX/FX Receive Timing
tRCLD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
10Base Transmit System Timing Parameter TX_CLK period TX_CLK High period TX_CLK period TX_EN TX_EN sampled TX_EN sampled !TX_EN !TX_EN sampled !CRS !TX_EN sampled !COL Propagation Delay TXD[3:0], TX_EN, TX_ER Setup TXD[3:0], TX_EN, TX_ER Hold !TX_EN TX_EN tCKH tCKL tTCSA tTCLA tTCSD tTCLD tTXS tTXH tTX_TX Start Packet tCKL Conditions 399.98 180.00 180.00 Packet 400.00 200.00 200.00 400.02 220.00 220.00 Units
RPTR logic RPTR logic RPTR logic RPTR logic From TXD[3:0] TXOP/N From rising edge TX_CLK From rising edge TX_CLK
tCKH
TX_CLK
tTXS
TX_EN
tTX_TX tTXH
TXD[3:0] TX_ER
TXOP/N
tTCSA
tTCSD
tTCLA
10Base-T Transmit Timing
tTCLD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
10Base Receive System Timing Parameter RX_CLK period RX_CLK High period RX_CLK period RX_DV !RX_DV !CRS !COL Propagation Delay RXD[3:0], RX_DV, RX_ER Setup RXD[3:0], RX_DV, RX_ER Hold tCKH tCKL tRDVA tRCSA tRCLA tRDVD tRCSD tRCLD tRDVA tRXS tRXH Conditions 399.98 180.00 180.00 400.00 200.00 200.00 400.02 220.00 220.00 Units
RPTR logic RPTR logic RPTR logic RPTR logic From RXIP/N RXD[3:0] From rising edge RX_CLK From rising edge RX_CLK
tCKH
RX_CLK
Start Packet tCKL
Packet
tRDVA
RX_DV
tRDVD tRXS tRXH
RXD[3:0] RX_ER RX_DV RXIP/N
tRCSA
tRCSD
tRCLA
10Base-T Receive Timing
tRCLD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
10Base 7-Wire Transmit System Timing Parameter 10TCLK period 10TCLK High period 10TCLK period 10TXEN 10TXEN sampled 10CRS !10TXEN !10TXEN sampled !10CRS Propagation Delay 10TD Setup 10TD Hold 10TXEN 10TXEN tCKH tCKL tTCSA tTCSD tTXS tTXH tTX_TX Conditions 99.995 45.00 45.00 Packet 100.00 50.00 50.00 100.005 55.00 55.00 Units
RPTR logic RPTR logic From TXD[3:0] TXOP/N From rising edge 10TCLK From rising edge 10TCLK
tCKH
10TCLK
Start Packet tCKL
tTXS
10TXEN
tTX_TX tTXH
10TD
TXOP/N
tTCSA
10CRS 10Base-T 7-WireTransmit Timing
tTCSD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
10Base 7-Wire Receive System Timing Parameter 10RCLK period 10RCLK High period 10RCLK period 10CRS 10CRS 10RD !10CRS Propagation Delay 10RD Setup 10RD Hold tCKH tCKL tRCSA tRDVA tRCSD tRDVD tRXS tRXH Conditions 99.995 45.00 45.00 1500 100.00 50.00 50.00 100.005 55.00 55.00 1700 Units
From RXOP/N 10RD From rising edge 10RCLK From rising edge 10RCLK
tCKH
10RCLK
Start Packet tCKL
Packet
tRDVA tRXS
10RD
tRDVD tRXH
RXIP/N
tRCSA
10Base-T 7-Wire Receive Timing
tRCSD
10Base 7-Wire Collision Timing Parameter Collision 10COL !Collision !10COL tCCA tCCD Conditions Units
RXIP/N
tCCA
10COL 10Base-T 7-Wire Collision Timing
tCCD
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation
3.3V
49.9
49.9
AC101-TF/QF
Transformer TXON TXOP TXC_P TX+_P TX-_P RX+_P RX-_P RXC_P
RJ45 Unused Unused Unused Unused
TXC_S TX+_S TX-_S RX+_S RX-_S RXC_S
RIBB
RXIP
1000
RXIN
Chassis
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
APPLICATION TERMINATION
Please contact Altima Communications Inc. latest component value recommendation enable mode, FX_DIS must pulled resistor.
3.3V 69.8 69.8
HFBR-5903 RXVee RXVcc TXVcc TXVee
AC101-TF/QF
FXRP FXTP
FXTN
FX_DIS
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FXRN
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
POWER GROUND FILTERING AC101QF
Please contact Altima Communications Inc. latest component value recommendation Ground Power .1uf Components placed from
VAAT VAAT
GNDT
GNDREF
GNDEQ
VAAREF
VAAEQ VAAADP
GNDT
AC101QF
VAAPLL GNDPLL OGND OVDD
VAACRV GNDCRV/ADP OGND OVDD
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CGND CVDD
CVDD OGND
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
POWER GROUND FILTERING AC101TF
Please contact Altima Communications Inc. latest component value recommendations.
Components placed from
GNDT
VAAT VAAT GNDT
GNDREF
GNDEQ
AC101TF
VAAPLL OGND VAACRV GNDCRV/ADP OGND OVDD
VAAREF
VAAEQ VAAADP
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CGND CVDD
CVDD OGND
AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
PACKAGE DIMENSIONS AC101QF (100 PQFP)
Quad Flat Pack Outline
3.40
0.25
2.70
23.20 0.25
20.00 0.10
17.20 0.25
14.00 0.10
0.65
0.88
1.60 0.12
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AC101QF/TF Ultra Power 10/100 Ethernet Transceiver
PACKAGE DIMENSIONS AC101TF(80 TQFP)
Quad Flat Pack Outline
1.20
0.05 0.15
1.00 0.05
0.22 0.05
14.20 0.25
12.00 0.10
14.20 0.25
12.00 0.10
0.50
0.60 0.15
1.00 0.12
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AC101QF/TF highly integrated, 3.3V, power, 10Base-T/100Base-TX/FX, Eth

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