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CD1865
Intelligent Eight-Channel Communications Controller
Eight full-duplex asynchronous channels supporting data rates 115.2 kbps Note: support this data rate, specified system clock frequency required. Register-based interrupt acknowledges eliminate need separate interrupt acknowledge signals Automatic prioritizing scheme allows device respond interrupt acknowledge with highest internal interrupt pending (host-programmable) Sophisticated interrupt schemes Vectored interrupts Fair Share interrupts Good Data interrupts improved throughput Simultaneous interrupt requests three classes interrupts: modem state changes Independent baud-rate generators each channel/direction
Software compatibility with CD180 CD1864 devices Generation detection special characters Automatic flow control In-band (Xon, Xoff generation, detection) Out-of-band (DTR/DSR RTS/CTS) On-chip FIFO bytes each Status Line break detection generation Multiple-chip daisy-chain cascading feature Odd, even, forced, parity modem/general-purpose signals channel System clock (x2), 33MHz (x1) CMOS technology 100-pin MQFP
2001, this document replaces Basis Communications Corp. document CL-CD1865 Intelligent 8-Channel Communications Controller. 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. CD1865 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
Intelligent Eight-Channel Communications Controller CD1865
Contents
Overview
Theory Operation Abbreviations.13 Acronyms
Conventions
Device Selection Considerations Information
Diagram.16 Assignments.17 Introduction.18 Internal Operation.20 Service Request Interrupt Operation.26 5.3.1 Theory Operation 5.3.2 Internal Implementation Service Request Logic.28 5.3.3 Priorities Fair Share.31 Types Service Requests 5.4.1 Receive Service Requests 5.4.2 Transmit Service Requests 5.4.3 Modem Signal Change Service Requests.35 Implementing Service Requests.35 5.5.1 Method Full Interrupt Type Three-Level Interrupt with Three-Level Acknowledge 5.5.2 Method Full Interrupt Type Three-Level Interrupt with Single-Level Acknowledge 5.5.3 Method Interrupt Interface, Single-Level Interrupt with Single-Level Acknowledge 5.5.4 Method Polled Interface.40 5.5.5 Comparison Interrupt Polled Code Sequences 5.5.6 Cascading Service Requests with Multiple CD1865s 5.5.7 Multiple CD1865s without Cascading.44 5.5.8 Acknowledging Service Requests System Interface Considerations System Clock Rate Options 6.2.1 System Clock 6.2.2 External Clock 6.2.3 Clock Option.48 6.2.4 Rate Options 6.2.5 Maximum Throughput Limits CD1865 Basic Interface Addressing 6.3.1 Intel, Versus Motorola, Interface Signals Addressing
Functional Description.18
System Interface System Clock
CD1865 Intelligent Eight-Channel Communications Controller
6.3.2 Unclocked Versus Clocked Interface Interface Examples 6.4.1 Interfacing 80X86-Family Processors 6.4.2 Interfacing 680X0-Family Processors 6.4.3 Interfacing Receiver Operation 7.1.1 Basic Operation. 7.1.2 Receive FIFO Operation 7.1.3 FIFO Timer Operations 7.1.4 Receive Service Requests 7.1.5 Receive Good Data Service Request 7.1.6 Receive Exception Service Request 7.1.7 Types Errors. 7.1.8 Types Exceptions 7.1.9 Flow-Control Characters 7.1.10 Programming Notes Transmitter Operation 7.2.1 Basic Operation. 7.2.2 FIFO Operation 7.2.3 Transmit Service Requests 7.2.4 Special Transmitter Commands 7.2.5 Special Character Transmission Send Special Character Command 7.2.6 Embedded Transmit Commands. 7.2.7 Sending Breaks 7.2.8 Sending Inter-Character Delays 7.2.9 Summary Special Transmitter Commands. Flow Control 7.3.1 Receiver Flow Control 7.3.2 Receiver Hardware (Out-of-Band) Flow Control 7.3.3 Receiver Software (In-Band) Flow Control. 7.3.4 Transmitter Flow Control 7.3.5 Transmitter Hardware (Out-of-Band) Flow Control 7.3.6 Transmitter Software (In-Band) Flow Control. Modem Signals General-Purpose 7.4.1 Generating Service Requests with Modem Pins 7.4.2 Using Modem Pins General-Purpose Testing CD1865 Loopback Tests Types Registers Access Duty Cycle Accessing FIFOs Versus Other Registers Initialization Global Register Initialization. Service Request Initialization Prescaler Channel Initialization Changes.
Serial Interfaces
Programming
Intelligent Eight-Channel Communications Controller CD1865
8.10 8.11
Transmitting Data Receiving Data Programming Examples 8.11.1 Programming Service Match Registers 8.11.2 CD1865 Initialization 8.11.3 Basic Operations 8.11.4 Interrupt Response Operations 8.11.5 Polled Mode Operation.93 Register Quick Reference Global Registers.97 9.2.1 Miscellaneous Registers 9.2.2 Configuration Registers.98 9.2.3 Service Request/Interrupt Control Registers .103 Indexed Indirect Registers.108 9.3.1 Receive Data Count Register.108 9.3.2 Receive Data Register .109 9.3.3 Receive Character Status Register .110 9.3.4 Transmit Data Register .111 9.3.5 End-of-Service Request Register.111 Channel Registers.111 9.4.1 Enable Register.112 9.4.2 Channel Command Register .112 9.4.3 Channel Option Register .116 9.4.4 Channel Option Register .116 9.4.5 Channel Option Register .117 9.4.6 Channel Control Status Register.118 9.4.7 Receiver Register.119 9.4.8 Receive Time-Out Period Register.120 9.4.9 Receive Rate Period Registers (High/Low).120 9.4.10 Transmit Rate Period Registers (High/Low).121 9.4.11 Special Character Register .121 9.4.12 Special Character Register .122 9.4.13 Special Character Register .122 9.4.14 Special Character Register .123 9.4.15 Modem Change Register .123 9.4.16 Modem Change Option Register 1.124 9.4.17 Modem Change Option Register 2.125 9.4.18 Modem Signal Value Register.125 9.4.19 Modem Signal Value Request-to-Send Register.126 9.4.20 Modem Signal Value Data-Terminal-Ready Register .126 Absolute Maximum Ratings.127 Recommended Operating Conditions .127 Electrical Characteristics.127 Index Timing Information.128 Electrical Characteristics .128 10.5.1 Clocked Interface .128
Detailed Register Descriptions
10.0
Electrical Specifications .127
10.1 10.2 10.3 10.4 10.5
CD1865 Intelligent Eight-Channel Communications Controller
10.5.2 Unclocked Interface
11.0 12.0 Index
Package Specifications Ordering Information
Figures
Functional Block Diagram Internal Block Diagram. Foreground/Background Internal Structure. Internal Operation Flow Chart Internal Service Acknowledge Decision Tree. Internal Fair-Share Operation Receive Timer Operation Three-Level Interrupt with Three-Level Acknowledge Example. Three-Level Interrupt with Single-Level Acknowledge Example Single-Level Interrupt with Single-Level Acknowledge Example Simple Software Polled Interface Example Polled Code Sequence Interrupt Code Sequence Internal Block Diagram. Clock Option. Typical Unclocked Interface. Typical Clocked Interface. Incorrect Interface Correct Interface. Synchronization CD1865 Receive Operation Data Timer Logic Transmitter Operation Receiver Flow-Control Logic Transmitter Flow-Control Logic Local Remote Loopback Logic. Initialization Clocked Interface Reset. Clocked Interface Clocks Clocked Interface Read Cycle, Motorola,-Style Handshake Clocked Interface Service Acknowledgment Cycle, Motorola,-Style Handshake Clocked Interface Write Cycle, Motorola,-Style Handshake Clocked Interface Read Cycle, Intel,-Style Handshake Clocked Interface Service Acknowledgment Cycle, Intel,-Style Handshake Clocked Interface Write Cycle, Intel,-Style Handshake.
Intelligent Eight-Channel Communications Controller CD1865
Unclocked Interface Read Cycle, Motorola,-Style Handshake.139 Unclocked Interface Service Acknowledgment Cycle, Motorola,-Style Handshake .140 Unclocked Interface Write Cycle, Motorola,-Style Handshake .141 Unclocked Interface Read Cycle, Intel,-Style Handshake.142 Unclocked Interface Service Acknowledgment Cycle, Intel,-Style Handshake .143 Unclocked Interface Write Cycle, Intel,-Style Handshake144
Tables
CD18XX Product Family Differences Between CD1865 CD1864.15 State Machine Logic.29 Service Request Methods Rate Constants, Rate Constants, Rate Constants, Rate Constants, Register Summary.96 Clocked Timings.129 Unclocked Timings .137
CD1865 Intelligent Eight-Channel Communications Controller
Revision History
Revision Date 2001 Initial release. Description
Intelligent Eight-Channel Communications Controller CD1865
Figure Functional Block Diagram
SERIAL INTERFACE RESET* CLK* R/W* A[0:6] INTEL/MOT* RREQ* TREQ* MREQ* DTACKDLY DTACK* DB[0:7] ACKIN* ACKOUT* OSC1 OSC2 DBLCLK CKOUT SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE HOST INTERFACE LOGIC RISC PROCESSOR FIRMWARE SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE
MODEM MODEM MODEM MODEM MODEM MODEM MODEM MODEM
CD1865 Intelligent Eight-Channel Communications Controller
Overview
CD1865 cost-effective controller capable controlling eight full-duplex channels transferring data rates 115.2 kbps. advantage CD1865 lies ability efficiently move data from serial channels host. This results order-of-magnitude improvement system-level throughput reduction overhead host CPU. increase overall data throughput system, device relies combination features. Most important buffers transmit receive data. Each serial channel three 8-byte FIFOs each transmit, receive, receive exception status. receive FIFOs have programmable thresholds minimize interrupt latency requirements. CD1865 based high-performance proprietary RISC processor architecture developed Intel specifically data communication applications. This processor executes instructions clock cycle, uses register-window architecture ensure zero-overhead context switch each type internal interrupt. CD1865 fabricated advanced CMOS process. device's high throughput, lowpower consumption, high-level integration permit system designs with minimum parts count, maximum performance, maximum reliability.
Theory Operation
CD1865 custom RISC processor assisted specialized peripheral logic. Serial data transmission reception handled `bit engines'. Each channel engine transmit another receive. While each engine handles bit-level timing, bit-to-character assembly done firmware. Bits passed processor internal interrupts, over special dedicated this purpose. reduce internal interrupts zero, special interrupt context hardware points correct register window every possible context. unique Global Index register eliminates address calculations always pointing current channel. processor assembles bits into characters, checks parity other formatting parameters, stores data FIFOs required. FIFOs maintained RAM-based structures. Both local processor host access them Pointer registers, effect Indexed Addressing mode. CD1865 communicates with host service requests service acknowledgments. Service requests detected interrupt lines on-device registers. Regardless method used, CD1865 features minimize both number requests serviced time required service them. FIFOs help reduce number service requests every eight characters. reduce time required request, CD1865 supplies separate vectors four different types service requests. This reduces time required processor effect proper operation. instance, there unique vector `good data', that host wastes time checking status bits error conditions. there error condition, CD1865 supplies unique vector pointing error-handling routine. Other vectors report transmit status modem signal change. Interrupts acknowledged either Interrupt Acknowledge pin, reading ondevice register. This allows host software maximum flexibility speed handling service requests.
Intelligent Eight-Channel Communications Controller CD1865
ADDRESS DATA
ADDRESS DECODE CONTROL LOGIC
DTACK* ACKIN*
DTR* DSR* RTS* CTS*
INTERRUPT CONTROLLER
Channel
RREQ* TREQ* MREQ*
RREQ* TREQ* MREQ*
RREQ* TREQ* MREQ*
CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL
CD1865
INTERRUPT CONTROLLER RREQ* TREQ* MREQ*
ACKIN* ACKOUT*
ACKIN* ACKOUT*
ACKIN* ACKOUT*
CD1865
CD1865
CD1865
Typical CD1865 Host Interface
CD1865 Daisy-Chain Scheme
Because CD1865 RISC processor processing every character sent received, features such automatic flow control special character recognition easily implemented. This further reduces processing burden host system. Both In-Band (Xon, Xoff) Out-of-Band (RTS/CTS, DTR) Flow-Control modes supported. in-band flow control, CD1865 automatically starts stops transmitter when remote unit sends flow-control characters. CD1865 also makes easy local host flow-control remote, `send special character' commands. out-of-band flow control, transmitter optionally asserts monitor permission send; assert/negate when Receive FIFO reaches user- definable threshold. Together, in-band out-of-band features only allow data flow controlled real time with minimum host intervention, also prevents loss data. shown previous page, CD1865 interface virtually CPU, with minimum glue logic. Refer CD1865 Data Sheet detailed information interface various microprocessors. Systems with multiple CD1865s easily implemented, with external glue, device daisy-chain scheme. `fair share' feature ensures equal access service requests, both within CD1865 across multiple devices. FIFO bytes FIFO dedicated each channel partitioned bytes transmitter, bytes receiver, bytes status. receive FIFO user-programmable threshold optimize system response latency. receive FIFO threshold programming range from characters. Vectored Interrupt Structure Three interrupt signals ([R, M]REQ*) used. These signals also read on-device register. Each REQ* signal represents three interrupt groups: receive, transmit, modem signal state changes. Upon servicing host, interrupt vector generated CD1865 define interrupt group serviced which CD1865 generated interrupt. This allows host software enter directly into proper interrupt service routine, reducing amount interaction between host controller, determining nature interrupt. Good Data Interrupt data received good, host advised number good data bytes FIFO, allowing host read data without further status queries until good data been transferred. Fair-Share Interrupt Scheme ensure equal service channels, fair share scheme used each interrupt group. channel interrupt same condition until others have chance serviced same interrupt condition.
CD1865 Intelligent Eight-Channel Communications Controller
Note:
support 115.2 kbps, system clock required. System design simplified CD1865 providing choice crystal external clock operation, frequency.
Intelligent Eight-Channel Communications Controller CD1865
Conventions
Abbreviations
Symbol Units measure degree Celsius microfarad microsecond (1,000 nanoseconds) hertz (cycle second) kilobit (1,024 bits) kilobit (1,000 bits) second kilobyte (1,024 bytes) kilobyte (1,000 bytes) second kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) milliampere millisecond (1,000 microseconds) nanosecond picovolt volt watt
Kbit kbps kbits/second Kbyte kbytes/second Mbyte
`tbd' indicates values that determined', `n/a' designates `not available', `n/c' indicates that connect'.
Acronyms
Acronym CMOS DRAM FIFO alternating current complementary metal-oxide semiconductor direct current direct-memory access dynamic random-access memory first in/first Definition
CD1865 Intelligent Eight-Channel Communications Controller
Acronym HDLC MQFP SDLC
Definition (Continued) high-level data link control industry standard architecture least-significant most-significant point-to-point protocol metric quad flat pack random-access memory read/write synchronous data link control transistor-transistor logic
Intelligent Eight-Channel Communications Controller CD1865
Device Selection Considerations
CD1865 device enhanced version same product family CD180 CD1864. CD1865 software compatible with both CD180 CD1864. this CD1865 design, please skip this page. CD1865 recommended designs. Please note that achieve high data rates, 66-MHz system clock required. support data rates 115.2 kbps, specified system clock frequency required. Please refer differences pins between CD1864 CD1865. recommended that 66-MHz, option (oscillator crystal) used wherever possible.
Table
CD18XX Product Family
Features Package System clock Maximum rates Pins CD180 84-pin PLCC 12.5 kbps DTRSEL modem/IO signals channel CD1864 100-pin PQFP 12.5 kbps modem/IO signals channel CD1865 100-pin MQFP 115.2 kbps modem/IO signals channel
Note:
This input (DTRSEL) CD180 sets mode DTR*/CD* pins. When DTRSEL high, DTR*/CD* pins implement DTR* output; when low, DTR*/CD* pins become inputs. CD1864 CD1865 have separate pins DTRSEL eliminated.
Table
Differences Between CD1865 CD1864
Number CD1865 Name CD1864 Name Comments Note Note Note
NOTES: truly no-connects CD1864 device. CD1864 true no-connect, cause problems connected VCC. make single board design compatible with either CD1864 CD1865, configuration jumper must used allow no-connect connection.
Note:
January 1995, Intel changed 100-pin PQFP package types from EIAJ JEDEC. CD1865 available JEDEC package. Before beginning design converting from CD1864 CD1865, please contact Intel package details. CD1865 device have potential latch problems used socket. recommended that this device surface mounted.
Warning:
CD1865 Intelligent Eight-Channel Communications Controller
Information
CD1865 available 100-pin MQFP (metric quad flat pack device) configuration shown below.
Diagram
RESET*
DB[7]
DB[3]
DB[2]
DB[1]
DB[6]
DB[5]
DB[4]
DB[0]
CKOUT
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
DS*(RD*) R/W*(WR*) DTACK* RTS[0]* CTS[0]* CD[0]* DTR[0]* DSR[0]* RTS[1]* CTS[1]* CD[1]* DTR[1]* DSR[1]* RTS[2]* CTS[2]* CD[2]* DTR[2]* DSR[2]* RTS[3]* CTS[3]* CD[3]* DTR[3]* DSR[3]* RTS[4]* CTS[4]* CD[4]*
TEST ACKIN* DBLCLK OSC2 OSC1 NO_OSC RREQ* TREQ* MREQ* TXD[7] TXD[6] TXD[5] TXD[4] TXD[3] TXD[2] TXD[1] TXD[0] RXD[7] RXD[6] RXD[5] RXD[4] RXD[3] RXD[2] RXD[1] RXD[0] DSR[7]* DTR[7]* CD[7]* CTS[7]*
CD1865
100-Pin MQFP
CD[5]*
DSR[5]*
CTS[5]*
RTS[6]*
CTS[6]*
CD[6]*
DSR[6]*
DSR[4]*
RTS[5]*
DTR[5]*
DTR[4]*
INTEL/MOT*
NOTE: Denotes active-low (negative-true) signal.
DTACKDLY
ACKOUT*
DTR[6]*
RTS[7]*
Intelligent Eight-Channel Communications Controller CD1865
Assignments
following conventions used table below: denotes active-low signal; input; input/output; output; open drain; indicates decending numbers; indicates ascending numbers.
CD1865 Intelligent Eight-Channel Communications Controller
Functional Description
Introduction
CD1865 coprocessor controls eight full-duplex channels that transfer data rates 115.2 kbps. CD1865 efficiently moves data between serial channels host, resulting great improvement system-level throughput reduction overhead host CPU. This improvement obtained reducing number service requests (interrupts) host must respond reducing complexity time required handle each service request. CD1865 relies combination features reduce number complexity service requests. Most important buffers transmit receive data. Each serial channel three 8-byte FIFOs each transmit, receive, receive-exception status. Receive FIFOs have programmable thresholds minimize interrupt latency requirements. vectored service requests Good Data interrupt allow host system immediately transfer data upon beginning processing service request, without tedious checking flags error conditions. CD1865 based high-performance, proprietary RISC processor architecture developed Intel specifically data communications applications. CD1865 processor executes instructions one-clock cycle, uses register window architecture ensure zero-overhead context switch each type internal interrupt. instruction this processor optimized bit-oriented tasks that combined with instantaneous response sending receiving bit, allow highly efficient processing characters. firmware CD1865 processor contained on-device ROM, requires user programming. CD1865 processor assisted task specialized peripheral logic. Serial data transmission reception handled `bit engines'. Each channel engine transmitting another receiving. While each engine handles bit-level timing, bit-tocharacter assembly done firmware. Bits passed CD1865 processor internal interrupts over special dedicated this purpose. Special internal-interrupt context hardware reduces overhead internal interrupts zero pointing correct register window every possible context, unique Global Index register eliminates address calculations always pointing current channel. External service requests host system also hardware assisted. There queue each three classes external service requests, request/ acknowledgment mechanism entirely hardware minimize response time. CD1865 processor assembles bits into characters, checks parity formatting parameters, stores data FIFOs required. FIFOs maintained RAM-based structures, both local CD1865 processor host access them Pointer registers Indexed Addressing mode. CD1865 communicates with host service requests service acknowledgments. Service requests handled either interrupts polling. Regardless method used, CD1865 features minimize both number requests serviced time required service them. number service requests reduced FIFOs since service request required only every eight characters. reduce time required request, CD1865 supplies separate vectors four different types service requests. This reduces time required host determine what action take. example, there unique vector Good Data that host wastes time checking status bits error conditions. there error condition, CD1865 supplies unique vector pointing error-handling routine. Other vectors report transmit status modem signal change.
Intelligent Eight-Channel Communications Controller CD1865
Service requests host system implemented CD1865 three hardware service request state machines. Each machine ability `queue-up' multiple requests. state machines designed offer fastest response possible. Whenever CD1865 processor determines that condition needs service request, queues request with appropriate state machine. state machine posts external request, monitors acknowledgment cycles from host, informs CD1865 processor when valid service acknowledgment been completely serviced. This allows CD1865 correctly maintain internal context processing channel being serviced. Because CD1865 processor processes every character sent received, features such Automatic Flow Control Special Character Recognition easily implemented. This reduces processing burden host system. Both In-Band (Xon, Xoff) Out-of-Band (RTS/CTS, DTR/DSR) Flow Control modes supported. In-Band Flow Control, CD1865 automatically starts stops transmitter when remote unit sends flow-control characters. CD1865 makes easy local host flow-control remote `Send Special Character' commands. Out-of-Band Flow Control, transmitter optionally asserts monitors permission send, assert/negate when Receive FIFO reaches user-definable threshold. used gate receiver off. Together, In-Band Out-of-Band features allow data flow controlled realtime with minimum host intervention, this also prevents loss data. Systems with multiple CD1865s easily implemented, with external glue, daisy-chain scheme. fair-share feature ensures equal access service requests, both within CD1865 across multiple devices. Alternately, multiple CD1865s operated parallel independent devices. Serial channels CD1865 entirely independent another. channel programmed combination features regardless state other channels. Bit-rate generators programmed loading divisor value, transmitters receivers each operate standard non-standard data rate. CD1865 detect received line-break condition, send break characters length, transmit delays. This done transmit commands embedded Transmit Data Stream. CD1865 also programmed detect user-defined special characters generate special service request host. Parity checking performed automatically, overridden host force parity errors test purposes. Character length Stop length also programmable per-channel. Modem pins CD1865 general-purpose, that they hard-wired into UART functions. modem pins needed interface actual modems, they used general-purpose pins. either case they readable writable directly host system. addition, CD1865 programmed monitor levels modem input pins generate service requests host upon detecting specified change. CD1865 fabricated advanced CMOS process. high throughput, low-power consumption, high level integration permits system designs with minimum parts count, maximum performance, greater reliability. There significant difference between CD1865 conventional dumb UARTs; CD1865 more efficient intelligent, even when operating polled environment. Systems built with CD1865 interface between host device higher level than systems built with conventional UARTs. example, with dumb UART, host must test each channel presence data, process that time-consuming. With CD1865, host queries entire
CD1865 Intelligent Eight-Channel Communications Controller
serial subsystem presence data. data present, CD1865 determines which channel whether good erroneous. Thus, using CD1865, host-peripheral interface easier implement, faster, more efficient.
Internal Operation
internal architecture CD1865 shown Figure foundation design custom-designed that Intel developed especially this application. This optimized bit-oriented tasks associated with UART functions, registers each channel, arranged register window architecture. These registers eight bits wide. CD1865 processor 16-bit instruction word that retrieves from on-device ROM. Every instruction one-word long executed one-clock cycle. Whenever internal interrupt occurs (from engine), CD1865 processor automatically switches context that channel's block registers. time lost saving machine state. CD1865 processor executes instructions necessary handle that (typically three instructions) then returns context prior internal interrupt. internal interrupts same priority level; interrupt handler block ensures fair-share access across channels. Each channel's serial interface logic consists receive-bit engine, transmit-bit engine, receive-baud-rate generator, transmit-baud-rate generator, timer. receive-bit engine samples state time indicated receive-baud-rate generator, reports this value CD1865 processor interrupt. transmit-bit engine works similar manner. baud rate tick, outputs next generates interrupt CD1865 processor requesting following bit. baud-rate generators 16-bit dividers that operate from master clock, which system clock divided baud-rate generators independent, channel send receive speed. addition baud-rate generators, there channel timers each channel. 8-bit divider, operating master prescaler timer tick. This timer used time-out partially full FIFOs avoid `stale' data. other used time embedded delays transmit data stream. eight channels continuously scanned internal logic that generates interrupts CD1865 processor `fair' manner. This fair-share interrupt feature same mechanism used share service requests across multiple devices. Whenever more channels contending interrupt service, channel that serviced first does assert again until other currently pending channels serviced. This prevents fast, 64-kbps channel from demanding service from slow 1200-bps channel, allows faster channel additional service needs support higher speed. This allows more overall throughput than `roundrobin' `equal-access' method would provide. Service requests host handled fast, dedicated logic each three levels provided. Whenever CD1865 processor detects condition requiring external-host service, queues request with service-request machine that level. This machine asserts External Request pin, monitors service acknowledgment same level. When service acknowledgment sensed, machine automatically provides vector host sets internal context CD1865 service. Upon completion service, machine restores normal context. queue service requests deep, busy system there another request immediately pending when first completed. This method avoids delay between requests, improves overall efficiency.
Intelligent Eight-Channel Communications Controller CD1865
Modem signals implemented `conventional' input-output circuits, readable, writable either on-device host CPU. This allows maximum flexibility using these signals either conventional way, other function required. When CD1865 processor using these pins implement flow-control functions, reads them under software control implements function that way. There direct hardware association between modem pins serial hardware.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Internal Block Diagram
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE RREQ* TREQ* MREQ* ACKOUT* ACKIN* SERVICE TRANSMIT REQUEST SERVICE LOGIC REQUEST QUEUE RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA RECEIVE SERVICE REQUEST QUEUE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA RXDATA TXDATA
MODEM SERVICE REQUEST QUEUE
RECEIVE ENGINE TRANSMIT ENGINE INTERRUPT HANDLER DUAL-BAUD RATE GENERATORS RECEIVE ENGINE
RXDATA TXDATA
ADR[0-6] DATA[1-7]
RXDATA TXDATA
DTACK* INTEL/MOT* RESET* DBLCLK NO_OSC OSC1 OSC2
INTERFACE
TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
CHANNEL TIMER
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
PINS (MODEM CONTROL)
RTS* CTS* DTR* DSR* LINES LINES LINES LINES LINES LINES LINES
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
Intelligent Eight-Channel Communications Controller CD1865
CD1865 workload divided into categories:
Bit-to-character conversion (and vice versa) `traditional' UART function Character-level processing such flow control, FIFO management, host interface
functions CD1865 internal processor handles these tasks firmware. foreground/background scheme used: foreground internal bit-engine interrupts background everything else. This internal structure represented Figure page shows foreground communicates with background. Foreground code handles bit-to-character assembly receive, character-to-bit disassembly transmit. either case Holding register, together with Full/Empty bit, acts `gateway' between interrupt-driven foreground polling-loop background code. background code executes polling loop shown Figure After power-on reset, software runs continuously inner outer loop. Lower-priority tasks handled outer loop, higher-priority tasks handled inner loop. highest-priority tasks events that handled foreground (that interrupt-driven) code. inner loop executes eight times often outer loop. checks each channel's Full/Empty bits sense another character needs moved. first checks receive, there character moved, moved execution moves next channel. receive data does need processing, then transmit checked. This mechanism gives slightly higher priority receive than transmit, favorable because missing receive character fatal error being late transmitting error. (The effect this observed programming CD1865 higher-than-rated serial baud rates providing source receive traffic with virtually 100-percent loading. CD1865 heavily loaded, leaves short gaps between transmit characters because firmware following `receive' path through code. Refer Section 6.2.5 details maximum performance maximum line speed). After eight passes through inner loop (for example, checking eight channels data), pass made through outer loop. This pass checks channel host commands (such `Send Special Character'), timer functions, condition that requires posting external service request (for example, Receive FIFO full, Transmit FIFO empty, modem signal change, on). required, firmware posts service request within queue appropriate servicerequest logic. then continues normal operation, until host responds service request. After single pass through outer loop, eight passes through inner loop again made. most cases CD1865 checks appropriate determine which options enabled then modifies processing accordingly. Some control bits must interpreted moved CD1865 firmware from their location Option registers other locations device. Therefore, host must notify CD1865 when these bits modified. Then, CD1865 alters channel commanded. details channel command functions, refer Section 7.2.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Foreground/Background Internal Structure
RECEIVE DATA COUNT REGISTER
RECEIVER FIFO
RECEIVE STATUS FIFO
BACKGROUND CODE: H.R.-TO-FIFO TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) FULL/ EMPTY FOREGROUND CODE: ASSEMBLY, S.R.-TO-H.R. TRANSFER (INTERRUPT-DRIVEN) RECEIVER SHIFT REGISTER
RECEIVER HOLDING REGISTER
RECEIVER
TRANSMITTER FIFO
BACKGROUND CODE: FIFO-TO-H.R. TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) TRANSMITTER HOLDING REGISTER FULL EMPTY
FOREGROUND CODE: DISASSEMBLY, H.R.-TO-S.R. TRANSFER (INTERRUPT-DRIVEN)
TRANMSITTER SHIFT REGISTER
TRANSMITTER
Intelligent Eight-Channel Communications Controller CD1865
Figure Internal Operation Flow Chart
POWER-ON RESET INITIALIZATION
OUTER_LOOP HOST COMMAND PROCESSING
GLOBAL (SOFTWARE) RESET
TIMER FUNCTIONS
INNER_LOOP
RCV_HLD_REG FULL
PROCESS RECEIVE CHAR.; CHECK SPECIAL FEATURES; PLACE FIFO
XMT_HLD_REG EMPTY PROCESS RECEIVE INTERRUPT
PROCESS TRANSMIT CHAR.; CHECK SPECIAL FEATURES; FETCH FROM FIFO
RECEIVE SERVICE REQUEST SCANNING
TRANSMIT SERVICE REQUEST SCANNING
MODEM SERVICE REQUEST SCANNING
CD1865 Intelligent Eight-Channel Communications Controller
Service Request Interrupt Operation
CD1865 enhances design efficiency, because intelligent device that more closely resembles add-in controller board than mere collection TTL. Conventional UARTs basically passive, `dumb' logic. example, when polling device channels requiring service, each channel individually tested. Because this, certain restrictions placed when FIFOs accessed. CD1865 processor must determine what host doing, when manage queue events correctly efficiently.
Interrupt-Driven Versus Polled
Choosing software interface, interrupt-driven versus polled, critical overall system performance. This choice also affects software written. hardware implementation, programmer choice Mixed mode, that when poll versus when interrupt-driven. Mixed-mode operation allows programmer optimize efficiency system according changing needs. advantages each method discussed Section 5.5.
5.3.1
Theory Operation
CD1865 three independent service request levels, each three categories Receive, Transmit, Modem signal change. priority these lines fixed, determined following three ways:
within CD1865 AutoPriority Option bits. system designer assign priorities manner which three service request lines
connected host interrupt controller.
Under software control, host system define redefine order service requests.
Service Request interface host implemented with five signals ACKIN*, ACKOUT*. asserted when service request pending; ACKIN* asserted during service-acknowledgment cycles; ACKOUT* used multiple CD1865 designs share service requests daisy-chain acknowledgments. Whenever CD1865 processor determines that more channels need service from host, loads appropriate service-request state machine with information about type request. service-request state machine that level then asserts request signal. Note that three request signals active same time. this point, CD1865 determined which request should handled first simply asserts lines, required status various channels. (This true even AutoPri Option enabled; AutoPri takes effect when service request acknowledged, that time CD1865 determines which most important request.) host, after noticing that more three service request pins active either because host interrupted polled external internal CD1865 status register decides which requests more than active) services first. host begins service operation issuing Service Acknowledge cycle. purpose this cycle cause CD1865 internal state that type request. (Note that AutoPri set, necessary host determine which level service request acknowledge; simply acknowledges CD1865 request CD1865 returns vector highest-priority active request.)
Intelligent Eight-Channel Communications Controller CD1865
AutoPri being used, CD1865 needs informed which three possible pending requests host wants acknowledge. There different ways CD1865 informed this hardware software. hardware method based value address bus. CD1865 determines type request being acknowledged value placed address during acknowledge cycle. This method used Motorola-family processors. host places level interrupt being serviced low-order address bits during interrupt acknowledgment cycle. When host performs Service Acknowledge cycle, CD1865 compares value address with three unique values stored three internal registers These values user system initialization. match occurs only these registers, this informs CD1865 type request being acknowledged. most circumstances address should have value that does match three values during acknowledgment cycle. This causes CD1865 recognize that cycle occurring, does assert DTACK*, terminate cycle, take other action. Doing this does affect CD1865, system must have some other provision terminate cycle. example, CD1865 shares interrupt level with another device, different values address should used control responses acknowledgment, cycle should terminate usable way. Service acknowledgments also performed software. host simply reads three Request Acknowledge registers, CD1865 performs hardware service acknowledge cycle executed. Regardless method acknowledgment used, within CD1865, each service request state machine makes following determination: internal service request pending, there service acknowledge same type, asserts internal-acknowledge-accepted signal back Service Request Controller logic, negates Service Request Output pin, holds acknowledge-out daisy chain negated state. also drives value Global Vector register (GVR) onto data bus, host read part Service Acknowledge cycle. value placed during Service Acknowledge cycle serves purposes. least-significant three bits indicate which four types service requests occurring. upper-five bits user-defined serve identify, daisy-chained CD1865 systems, which multiple CD1865s active. service request state machine does have service request pending, there software acknowledgment address match, passes service acknowledgment down chain asserting ACKOUT*. there match, state machine remains idle. service request pending Receive Service Request handled, CD1865 notified because three have different values them; therefore, only match (receive service, this case) occurred. internal grant from service request state machine causes receive service type code active channel number (previously stored time request posted CD1865 processor) pushed onto service request stack. This automatically causes FIFO pointers active channel, with host intervention. host, this point, information needed handle service request. determines exact type service being requested (Transmit, Receive Good Data, Receive Exception, Modem signal change) which multiple CD1865s requesting service. gets channel number reading Global Channel register (GCR) then proceeds service request. completion service, host performs dummy write CD1865 register that causes CD1865 exit internal service request state popping service
CD1865 Intelligent Eight-Channel Communications Controller
request stack. this time CD1865 ready serviced another outstanding requests. another request same level pending, clock periods after write required CD1865 reassert request line. Because CD1865 service request stack, support nested-service requests. example, host middle Transmit Service Request, detect that Receive Service Request asserted, process Receive Service Request, after exiting receive service routine, resume Transmit Service Request. CD1865 stack three deep, three types (one each) nested required. current service request context (for example, stack) readable Service Request Status register. Global Channel registers (GCR) actually three registers that provide number channel requesting service. Reading these registers causes CD1865 mask three bits, specifying channel number currently active channel. Normally these registers read host when handling service request. this case, three bits number channel requesting service. three registers read when CD1865 service-request context, three bits current value CAR. current channel number masked into contents bits this register CD1865 when read host. actual contents register modified. These three registers provided convenience user. most applications, user only uses these locations, register some arbitrary value. However, useful record information about state CD1865 software driving that associated with each three service-request types. this case, user store whatever information required unused bits. Then, when entering service routine, software check these bits find what state they were left this could used `sub-vector'.
5.3.2
Internal Implementation Service Request Logic
discussed above, heart each service request level asynchronous state machine. This state machine three inputs:
MATCH from Priority Interrupt Level register comparator, ACKIN* from host system, INTERNAL_REQUEST from CD1865.
Note: Software acknowledgments (reads from Service Request Acknowledge registers), effect, force MATCH value true their respective level. also three outputs:
Svc_Req host system, INTERNAL_GRANT CD1865, ACKOUT*, which combined with other ACKOUT* signals provide ACKOUT*
next CD1865 daisy chain. Figure page shows logic implemented state machine, which described Table
Intelligent Eight-Channel Communications Controller CD1865
Table
State Machine Logic
State Name Output Condition outputs inactive GoTo REQ_ACTIVE GoTo PASS_ACK Stay IDLE GoTo KEEP_ACK Stay REQ_ACTIVE Stay REQ_ACTIVE GoTo IDLE Stay PASS_ACK GoTo IDLE Stay KEEP_ACK normal `resting' state pass this acknowledge wait here request asserted keep this acknowledge wait here, some other level wait here ACKOUT* asserted return when ACKIN* gone wait here while ACKIN* active INTERNAL_GRANT asserted return when ACKIN* gone wait here while ACKIN* active Comments
IDLE (INTERNAL_REQUEST ELSE (ACKIN* MATCH ELSE REQ_ACTIVE (ACKIN* MATCH (ACKIN* MATCH ELSE PASS_ACK (ACKIN* ELSE KEEP_ACK (ACKIN* ELSE
NOTE: denotes point which, there match, CD1865 determines pass down daisy chain. does this reasons: first, unacceptable have ACKOUT* `glitch' low; second, state machine should fast possible. When state machine senses ACKIN* match valid, cannot conclude that should assert ACKOUT*; ACKIN* other service requests levels. could wait results other MATCH comparators; however, this complicates, therefore slows down, response state machine. reason this complication causes delay implement logical function `assert ACKOUT* match') must determine long wait before declaring no-match condition. implement this delay function, synchronous state machine required, which 15-MHz clock, means delay several hundred nanoseconds from ACKIN* ACKOUT*, instead currently specified.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Internal Service Acknowledge Decision Tree
IDLE STATE OUTPUTS INACTIVE
INTERNAL_REQUEST ACTIVE
TRUE
REQUEST_ACTIVE STATE ASSERT REQUEST
FALSE
IACKIN* ACTIVE MATCH
TRUE
KEEP_ACK STATE ASSERT INTERNAL_GRANT
FALSE IACKIN* INACTIVE IACKIN* ACTIVE MATCH TRUE FALSE
TRUE FALSE
(This block redundant. placed here emphasize that there match, nothing happens.)
IACKIN* ACTIVE MATCH TRUE PASS_ACK STATE ASSERT IACKOUT*
FALSE IACKIN* INACTIVE FALSE
TRUE
Intelligent Eight-Channel Communications Controller CD1865
5.3.3
Priorities Fair Share
CD1865 implements fair-share mechanism ensure that channels receive equal service, without `data starvation'. Fair share works automatically among channels device across multiple devices. Figure page shows fair-share operational block diagram. each three service request lines, CD1865 monitors both internal external value line. (The external value differ because, multiple CD1865 applications, driven other CD1865s.) service acknowledgment cycle, CD1865 checks state both request values. they different, CD1865 determines that there another part also driving request line, does reassert request line until external request gone inactive. This inactive level means every other CD1865 with pending request serviced; therefore, okay reassert requests without controlling host bandwidth.
Figure Internal Fair-Share Operation
INTERNAL REQUEST CD1865 INTERNAL REQUEST LOGIC
EXTERNAL REQUEST (I/O PIN)
ASSERT
LATCH
Types Service Requests
categories service requests that CD1865 generate explained below. Each channel's transmitter, receiver, modem pins require service from host occasionally; however, each category service request conditions tolerate different latencies being serviced. Conditions service requests fall into three basic categories:
Data received from remote device needs transferred host.
CD1865 Intelligent Eight-Channel Communications Controller
Data from host given Transmitter FIFO, which empty. modem signal changes state.
Three separate service request levels provided support following three categories:
Source Receive data Transmit data Modem signal change Name Request Match Register Name
5.4.1
Receive Service Requests
Receive Service Request unique because subtypes; that capable returning different vectors during service request acknowledge cycle. sub-types `Receive Good Data' `Receive Exception'. reason there types within category service request that, while Good Data Exceptions require different handling, they both equal priority, need serviced order they received. example, suppose good characters received, then exception character, then another good character received. There must service request first bytes Good Data, then Exception, then more Good Data. Exception Service Request different level, exception character processed either before after Good Data, sequence should This method also allows Receive Good Data-handling routine host very fast efficient, since only move bytes buffer. special-case conditions separate handler, where they slow down normal data transfers. Exception characters characters with errors that match defined special characters, line breaks, certain time-out conditions. Data must read from Receive FIFO Receive Status FIFO except when CD1865 within context Receive Data Service Request.
5.4.1.1
Receive Good Data
Receive Good Data Service Request asserted following three conditions: RxFIFO threshold reached, FIFO contains Good Data. RxFIFO threshold reached, FIFO contains Good Data, Receive Data Timer times-out. RxFIFO threshold reached, FIFO contains Good Data, newly arrived data contains exception condition. When these conditions occur, modified service request vector indicates host that service request Good Data. CD1865 continues bytes FIFO, increments Count register each good byte added, this allows optimally efficient FIFO. necessary accept Good Data that available when Good Data Interrupt received. host buffer full accept bytes, smaller number (even read, service request context left, host buffer handled first. CD1865 again generates another Good Data Service Request when three conditions listed above met.
Intelligent Eight-Channel Communications Controller CD1865
condition that caused request first place remains true, CD1865 quickly generates another service request. data read, this always case. some, all, available data read, Conditions true, Condition true exception condition cause Good Data Interrupt. this becomes problem, solution temporarily disable receiving interrupts that channel. avoid FIFO overflow, disable channel very long.
5.4.1.2
Receive Exception
Unusual exception conditions reported host character time through Receive Exception Service Request. with normal receive processing, host determines requesting channel reading GCR. then determine specific exception(s) reading Receive Character Status register. Exception conditions generated parity errors, framing errors, FIFO overrun, special character recognition, break detect, special feature called Data Timer' (NNDT). NNDT receive timer option generate service request first receive data time-out following transfer data from FIFO host. often useful, when managing relatively large buffers, processor determine that data arrived lately'. This event used transfer contents local buffer that been storing data from CD1865 FIFO host-system processing. This service request receive exception sub-type, used signal that time transfer buffer. This feature enabled disabled controlling NNDT Service Request Enable register. shown Figure every time received character loaded into FIFO, timer restarted. timer times-out, CD1865 checks there data FIFO. there Good Data Service Request posted avoid `stale data'. there data FIFO, CD1865 checks that NNDT enabled `armed'. Arming occurs when last character transferred FIFO host. NNDT armed, Receive Exception Service Request posted inform host this event. Note that NNDT armed last character removed from FIFO exception character. Every Receive Exception unique, one-character event. Receive Data Count register meaning, unlike Receive Good Data case, Status byte receive exception handling routine must read. Receive Data Count register associated data character discarded CD1865 service routine. Status byte must read before reading Data byte. Once Data register read, Status byte longer available.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Receive Timer Operation
.FROM OTHER BACKGROUND PROCESSING.
BACKGROUND SCANNING DETECTS CHARACTER ARRIVED
CHARACTER FIFO; RELOAD TIMER
TIMER
RESUME BACKGROUND SCANNING LOOP.
FIFO EMPTY
POST RECEIVE GOOD DATA SERVICE REQUEST
DATA TIMEOUT FEATURE ENABLED
NNDT INTERNAL FLAG 'ARMED' CLEAR NNDT INTERNAL FLAG
POST RECEIVE EXCEPTION SERVICE REQUEST
RESUME BACKGROUND SCANNING LOOP.
Intelligent Eight-Channel Communications Controller CD1865
5.4.2
Transmit Service Requests
Each transmitter contains bytes Transmit FIFO addition Transmit Holding register Transmit Shift register. data being transmitted, FIFO status being monitored CD1865. service request invoked following conditions:
Transmit FIFO Empty When Transmit FIFO empty, there still character
Transmit Holding register character Transmit Shift register. host character times respond this request without causing Transmit Data Stream.
Transmitter Empty Transmit FIFO, Transmit Holding register, Transmit Shift
registers empty. This signifies that characters written FIFO completely transmitted. host select which these causes Transmit Service Request, used programming options Service Request Enable register (SRER). Data must into Transmit FIFO time other than when CD1865 Transmit Service Request context that channel. During transmit service, characters eight) placed into FIFO Transmit Data register (TDR).
5.4.3
Modem Signal Change Service Requests
CD1865 programmed assert service request when channel's modem input signals changed states. change-detect options programmed Modem Change Option registers. Individual modem service requests enabled setting corresponding bits Service Request Enable register. host must read Modem Change register during modem change service determine which modem signal changes were detected. This indicated appropriate location. Modem Change register must reset host before exiting service request because CD1865 does this. Refer Section more details.
5.4.3.1
Using Modem Pins Input/Output
pins labelled modem pins general-purpose pins that controlled either CD1865 processor host system. There direct, hardwired connection from modem directly transmitter receiver. This means that these pins used generalpurpose they needed modem-control purposes. Section more details.
Implementing Service Requests
CD1865 designed easily interface with processor, efficient flexible enough provide maximum throughput. CD1865 generates service requests waits acknowledgments these from host. However, service requests implemented either hardware software; likewise, acknowledgments affected either offer maximum advantages system designer programmer. This interfacing grouped various steps. Service requests must `noticed' host system before they acted this done following three ways:
CD1865 Intelligent Eight-Channel Communications Controller
Provide three levels interrupt support, with three separate levels three separate vectors. This well-suited Motorola 680X0 processors. Provide single level interrupt support; this effective method when using 8-bit processors such Z-80 many Intel microprocessors. Poll device directly software. Once host `noticed' service request, following choices acknowledging request beginning service
Acknowledge request hardware-based service acknowledgment, typically done
interrupt-driven systems.
Acknowledge request software reading from register CD1865.
Table Service Request Methods
host detects Service Request Three-level Hardware Interrupt Hardware-based service acknowledge Software-based service acknowledge Full Interrupt Type Full Interrupt Type Single-level Hardware Interrupt recommended (Inefficient) Single Interrupt Software Polling recommended (Inefficient) Software Polled
host acknowledges Interrupt
Thus, there theoretically possible options interfacing CD1865 host system. methods practical implement without external hardware, offer performance advantage. Each other four methods advantages drawbacks depending type host being used whether that host supports more than CD1865. four methods used listed Table
This method called `Full Interrupt Type system fully interrupt driven with
acknowledgments hardware. requires host with least three interrupt priority levels available ability acknowledge multiple levels. This technique used Motorola 680X0 processors. most efficient method when host relatively fast interrupt context switch time when host duties other than driving CD1865s.
This method called `Full Interrupt Type still three levels interrupt,
provides single acknowledgment level. commonly used Intel-type processor systems where there 8259A interrupt controller. 8259A receives three levels interrupt, provides vector host rather than that CD1865s. Then host acknowledges CD1865s Service Request reading Vector register.
This method called `Single Interrupt', best-suited systems having only single
interrupt input, such most 8-bit microprocessors. After host receives interrupt entering interrupt service routine, reads CD1865 evaluate which three types service requests responsible interrupt.Then acknowledges interrupt reading appropriate Request Acknowledge register. Note that single interrupt signal must generated logical three request outputs with external output gates, `wire-OR'ing' them.
Intelligent Eight-Channel Communications Controller CD1865
This method called `Software Polled'. Polling often used situations where host
system primarily dedicated servicing serial channels other tasks perform. usually better when host long interrupt context switch time. this method, host periodically checks CD1865s determine service requests pending. they are, host acknowledges them software proceeds with service. advantages CD1865 that allows above techniques, combination. Such combination referred `Mixed-mode operation'. typical mixedmode design, normal interrupts used signal host that service required. After host enters interrupt service routine, services CD1865 that generated service request. Then host polls CD1865s determine more channels require service. host finds channel requiring service, handles usual manner, then proceeds poll more service requests. This process continues until CD1865s handled. Because host exiting re-entering interrupt context each time, much host time saved, resulting even faster overall performance. Advantage mixed-mode design that software complete control whether fully interrupt driven poll certain circumstances. mixed-mode design recommended tune system optimum performance. CD1865 evaluation board employed analyze CD1865 performance evaluate different software implementations. Intel testing AT-compatible '386 machine) found that mixed-mode system provided highest overall throughput with minimum host loading. This generally found case with host processors that have relatively long interrupt response times, such Intel '386.
5.5.1
Method Full Interrupt Type Three-Level Interrupt with Three-Level Acknowledge
This method illustrated Figure best-suited 680X0-family processors. three CD1865 service request lines connected Interrupt Priority Encoder. When host performs interrupt acknowledgment cycle, CD1865 responds with vector. host uses this vector jump directly appropriate service routine. Other methods also used with 680X0-based system.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Three-Level Interrupt with Three-Level Acknowledge Example
RREQ* TREQ* MREQ* EIGHT-LEVEL PRIORITY ENCODER ACKOUT* ACKIN*
CD1865
D0-D7 A3-A6 A0-A2 RREQ* TREQ* MREQ* ACKIN* ACKOUT*
IPL1 IPL2 IPL3
M68000 MICROPROCESSOR
A8-A23 A4-A7 A1-A3 D0-D7
ADDRESS DECODE LOGIC
CD1865
D0-D7 A3-A6 A0-A2
5.5.2
Method Full Interrupt Type Three-Level Interrupt with Single-Level Acknowledge
This method illustrated Figure useful with 80X86 systems that 8259A Interrupt Controller. Since 8259A supplies vector host when INTA cycle occurs, host simply read CD1865's vector method described polled interface example separate device select decode provided drive ACKIN* input. After 8259A supplies vector 80X86 host CPU, host performs software acknowledgment CD1865, transfers CD1865 vector host. This allows service request processed.
Intelligent Eight-Channel Communications Controller CD1865
Figure Three-Level Interrupt with Single-Level Acknowledge Example
INTERRUPT CONTROLLER (8259A EQUIVALENT)
RREQ* TREQ* MREQ* ACKOUT* D0-D7 A3-A6 A0-A2 ACKIN*
CD1865
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* A8-A23 A4-A7 A1-A3 D0-D7 ADDRESS DECODE LOGIC D0-D7 A3-A6 A0-A2 ACKOUT*
CD1865
5.5.3
Method Interrupt Interface, Single-Level Interrupt with Single-Level Acknowledge
This method illustrated Figure best-suited host systems having single interrupt input. three service request lines from CD1865 through `OR' gate host's interrupt input. When interrupt occurs, host system polls CD1865s, determines which three levels interrupted, acknowledges accordingly.
CD1865 Intelligent Eight-Channel Communications Controller
Figure Single-Level Interrupt with Single-Level Acknowledge Example
RREQ* TREQ* MREQ* ACKOUT* ACKIN*
CD1865
D0-D7 A3-A6 A0-A2
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* ADDRESS DECODE LOGIC ACKOUT*
CD1865
D0-D7 A3-A6 A0-A2
A8-A23 A4-A7 A1-A3 D0-D7
5.5.4
Method Polled Interface
This method illustrated Figure Polled operation used with type host CPU, used combination with interrupts provide mixed-mode system optimized particular application. polled system, host reads Service Request Status register (SRSR) within CD1865 determine whether there channels that need service. (Note that unlike traditional UARTs, only register needs read determine there channels device that need attention, this saves time). host finds channels needing service, acknowledges required type reading three Request Acknowledge registers. These provide vector that used jump directly correct service routine. Processing from this point proceeds case interrupt-driven operation. Note that difference between this method Method lies host system becomes aware need service CD1865. Method single interrupt starts process. Method host polls periodically. methods combined interrupt triggers first service, host continues poll until other pending requests serviced.
Intelligent Eight-Channel Communications Controller CD1865
There difference between CD1865 conventional dumb UARTs that makes CD1865 more efficient even when operating polled environment. With dumb UART, host polls each channel turn determine whether data. With CD1865, host polls CD1865s group whether data. does, CD1865s indicates channel, rather than host testing each channel turn. fact, possible host dictate which channel serviced; CD1865 determines this order. This minimizes both number polling steps required amount time each needs. This also ensures fair, balanced service channels. There several ways that host system poll CD1865. Each method certain advantages. most direct method read Service Request Status register (SRSR). This register contains three bits that indicate whether there request pending receive, transmit, modem signal change, CD1865 being read. There three more bits that provide same information CD1865s system these three bits reflect state wire-OR'ed external request lines. Thus single read operation determine there activity. Figure Simple Software Polled Interface Example
RREQ* TREQ* MREQ* ACKOUT* ACKIN*
CD1865
D0-D7
A3-A6 A0-A2
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* ACKOUT*
CD1865
D0-D7
A4-A7 A1-A3 D0-D7
A3-A6 A0-A2
CD1865 Intelligent Eight-Channel Communications Controller
5.5.5
Comparison Interrupt Polled Code Sequences
Figure Figure show code sequences polled interrupt service request methods.
Figure Polled Code Sequence
READ SERVICE REQUEST STATUS FROM SRSR
RECEIVE REQUEST PENDING?
GOOD DATA HANDLE `BAD' DATA
TRANSMIT REQUEST PENDING?
TRANSMIT ROUTINE
READ REQUESTING CHANNEL NUMBER
READ NUMBER BYTES FROM RDCR
MODEM SIGNAL CHANGE REQUEST PENDING?
MODEM ROUTINE
HOST'S BUFFER POINTERS
LOOP COUNTER RDCR
READ
READ RRAR ACKNOWLEDGE, STATUS VECTOR
WRITE DATA POINTER LOCATION
INCREMENT POINTER
DECREMENT LOOP COUNTER
LOOP COUNTER
SAVE POINTER
EXIT
Intelligent Eight-Channel Communications Controller CD1865
Figure Interrupt Code Sequence
INTERRUPT OCCURS ENTRY POINT GOOD DATA INTERRUPT SERVICE ROUTINE READ REQUESTING CHANNEL NUMBER READ NUMBER BYTES FROM RDCR HOST'S BUFFER POINTERS LOOP COUNTER RDCR
READ WRITE DATA POINTER LOCATION INCREMENT POINTER DECREMENT LOOP COUNTER
LOOP COUNTER
SAVE POINTER EXIT
5.5.6
Cascading Service Requests with Multiple CD1865s
Regardless method used support service requests, multiple CD1865s cascaded tying together lines, lines, lines. These lines open-drain they wireOR'ed. CD1865s then daisy chained simply connecting ACKOUT* device ACKIN* next. host knows which CD1865 requesting service value returned through Global Interrupt Vector register. CD1865s cascaded daisy chain this manner. Since multiple daisy chains possible, maximum number CD1865s large. 32per-daisy-chain limit five bits GVR. These bits used identify which CD1865 responded service request acknowledge cycle. user must program different values into upper-five bits each CD1865s GVR.
CD1865 Intelligent Eight-Channel Communications Controller
Note that thirty-two CD1865s logical limit daisy chain. Since takes over 1000 acknowledgment ripple down devices, efficient have long chain heavy-traffic applications. Note: some systems that daisy chain many CD1865 devices, potential timing hazard exists host processor does allow sufficient time removal ACKIN*/ACKOUT* daisy-chain signal propagate through devices. event that host processor begins operations with another section logic applies (RD* Intel environment) while active ACKIN* being applied CD1865 propagation delay time, unpredictable results occur. This constitutes illegal acknowledge cycle. failure mode most often cessation service requests from device, especially type that being serviced when illegal access occurs. Take care ensure that 35-ns propagation delay device included wait-state generation.
5.5.7
Multiple CD1865s without Cascading
possible interface several CD1865s without using cascade feature. There advantage this because there less delay incurred while waiting service acknowledgment ripple down chain devices. There possible disadvantages. each CD1865's three service request lines separate input interrupt controller, interrupt controller more complex, fair-share feature does work. service request lines wireOR'ed, fair share works, host test each CD1865 turn which generated service request. implement this method, simply connect CD1865 address data lines usual manner.
5.5.8
Acknowledging Service Requests
mentioned Section page different methods used acknowledge service request. method hardware-based, other software-based. hardware-based mechanism specific type cycle that uses ACKIN* ACKOUT* signals CD1865. acknowledge cycle defined where ACKIN* active inactive. This method used processors that perform interrupt acknowledge cycles, such 680X0. software-based mechanism uses three registers Receive Request Acknowledge register, Transmit Request Acknowledge register, Modem Request Acknowledge register. Reading these registers effect acknowledging service request, data read appropriate vector, that contents Global Interrupt Request Vector register. lowthree bits this register modified indicate specific type interrupt being acknowledged. host reads these registers when service request pending, either things happen. daisy chaining acknowledgments enabled, ACKOUT* CD1865 asserts. daisy chaining enabled, part supplies vector with low-three bits `0'. Thus, possible `fish' service requests, that acknowledge each CD1865 turn until non-zero vector received. `Fishing' usually efficient software technique, useful some circumstances. example, systems that normally interrupt-driven, where interrupts available diagnostics other reasons, host determine service request pending reading appropriate Request Acknowledge register. CD1865 must configured daisy chain; this case returns vector request pending, `00' request pending. host three levels request turn. This method works either single CD1865s multiple
Intelligent Eight-Channel Communications Controller CD1865
devices. multiple-device systems, either disable daisy chaining devices `fish' each individually, disable daisy chaining last device only `fish' device beginning chain. Both methods acknowledging service requests used interchangeably. usually advantageous Mixed mode. example, after receiving interrupt servicing normal manner, host should read Service Request Status register (SRSR) other requests pending. host acknowledge reading appropriate Request Acknowledge register (RRAR, TRAR, MRAR) proceed service request. This avoids time required host exit interrupt routine, only re-enter immediately next request.
CD1865 Intelligent Eight-Channel Communications Controller
System Interface System Clock
Figure Internal Block Diagram
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE RREQ* TREQ* MREQ* ACKOUT* ACKIN* SERVICE TRANSMIT REQUEST SERVICE LOGIC REQUEST QUEUE RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA RECEIVE SERVICE REQUEST QUEUE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA
RXDATA TXDATA
MODEM SERVICE REQUEST QUEUE ADR[0-6] DATA[1-7]
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE
RXDATA TXDATA
INTERRUPT HANDLER
RXDATA TXDATA
DTACK* INTEL/MOT* RESET* DBLCLK NO_OSC OSC1 OSC2
INTERFACE
TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
CHANNEL TIMER
RXDATA TXDATA
PINS (MODEM CONTROL)
RTS* CTS* DTR* DSR* LINES LINES LINES LINES LINES LINES LINES
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
RXDATA TXDATA
Intelligent Eight-Channel Communications Controller CD1865
System Interface Considerations
When using CD1865, areas where system architects, designers, programmers should consider options system clock speed, unclocked versus clocked-host interface.
6.2.1
System Clock Rate Options
System Clock
System clock high-frequency clock (supplied user) used CD1865 receive necessary timing. CD1865 capable handling system clock levels TTL-compatible voltage swings; however, specifications identical families logic. Specifically, clock signal (and reset signal) have lower higher than worst-case specifications some families. general, family adequate heavily loaded. Refer Specifications Section 10.3 details.
CD1865 operated from main system clock clock. Operation from main system clock reduce number clocks required, allows interface between system CD1865 clocked, general, typical system clock speeds exact baud-rate multiples. rates received from clock, important consider this when selecting clock value. exact baud rates needed, system clock convenient value, CD1865 must supplied with clock crystal.
6.2.2
External Clock
recommended that option (oscillator crystal) used wherever possible. Figure shows possible design configuration clock circuitry crystal being used. Please refer CD1865 Evaluation documentation details design configurations used. crystal used evaluation board 66-MHz third overtone part.
Figure Clock Option
200K-500K
CD1865 Intelligent Eight-Channel Communications Controller
Figure
NO_OSC OSC1 CKOUT
OSC2 DBLCLK FROM RESET LOGIC
6.2.3
Clock Option
recommended that option used where ever possible. using options, refer Table page clock duty cycle requirements.
6.2.4
Rate Options
CD1865 supports independent transmitter receiver rates each eight channels. rate determined 16-bit period value (divisor) stored Transmitter Rate Period registers (TBPRH TBPRL), Receiver Rate Period registers (RBPRH RBPRL). These registers establish period corresponding Transmitter Receiver Rate counters. given rate, value loaded determined following equation:
frequency Hertz} Rate Divisor -(16 desired Rate bits second})
This equation yield non-integer result. nearest integer value optimum choice that rate system clock combination. value loaded Rate Period registers must that integer expressed 16-bit binary value. rounding necessary, percentage rate error calculated
Rate Divisor Integer Rate Divisor
popular rates their corresponding divisors various system clock rates shown Table
Intelligent Eight-Channel Communications Controller CD1865
Table
Rate Constants,
Rate 1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Divisor 493e 35b6 1adb
Error 0.000% 0.000% 0.000% 0.015% 0.015% 0.044% 0.073% 0.073% 0.393% 0.538% 0.461% 0.538% 0.703% 0.509% 0.538%
divisor values hex.
Table
Rate Constants,
Rate 1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
divisor values hex.
Divisor 377d 28b1 1458
Error 0.003% 0.003% 0.006% 0.006% 0.006% 0.006% 0.147% 0.147% 0.467% 0.762% 0.352% 0.467% 1.696% 2.144% 3.219%
CD1865 Intelligent Eight-Channel Communications Controller
Table
Rate Constants,
Rate 1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Divisor 2c64 208d 1047
Error 0.003% 0.004% 0.008% 0.016% 0.032% 0.032% 0.160% 0.160% 0.160% 1.376% 1.440% 1.376% 2.400% 2.720% 1.376%
divisor values hex.
Table
Rate Constants,
Rate 1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Divisor 214b 186a
Error 0.003% 0.000% 0.000% 0.032% 0.032% 0.096% 0.160% 0.352% 0.352% 1.696% 1.547% 1.696% 2.400% 2.720% 1.696%
divisor values hex.
Intelligent Eight-Channel Communications Controller CD1865
6.2.5
Maximum Throughput Limits
CD1865 internally fully static, synchronous design. Consequently, maximum data rate handled CD1865 determined clock speed which operating. There fixed number CD1865 processor cycles required process each character; slower CD1865 processor rate equates slower rate. minimum clock frequency required determined data rate needed support. general, CD1865 maintain 100% full-duplex throughput when divisors greater used. given master clock frequency, this limitation used determine maximum rate which system sustain 100% throughput both receive transmit. Divisors small used, however degradation throughput observed. This degradation seen gaps between transmit characters are, effect, extra long stop bits. This fail-safe condition. Divisors smaller than work application less than eight channels enabled.
CD1865 Basic Interface Addressing
CD1865 addressed through active-low Chip Select (CS*) conjunction with seven Address Inputs A[0:6] that mapped CD1865 internal addresses addressing modes global channel. Channel Addressing mode, bits defining channel accessed provided from Channel Access register (CAR) within CD1865. most-significant Address Input (A6) performs selection between global- channelspecific addresses. this `1', address global, associated with specific channel. this `0', address channel-related. With exception FIFOs, channel-specific registers accessed first setting required channel number low-three bits Channel Access register. FIFOs only accessed within context service routine. Attempting force access particular FIFO setting causes unpredictable incorrect results. Within context service request, effective channel access value automatically controlled CD1865, thus should modified host system during service-request processing. advantage this method that host never performs address computation access CD1865 during service requests. Because only registers specific active channel (that being serviced) accessible host within service request routine. automatic indexing feature handles this, thus avoiding burden host. Refer Section Indexed Indirect registers details.
6.3.1
Intel Versus Motorola Interface Signals Addressing
CD1865 supports handshake methods. patterned after Motorola 680X0family processors, other after Intel 80X86-bus interfaces. interface selection achieved INTEL/MOT* signal. When this signal `high', Intel interface selected, when this signal `low', Motorola interface selected. This selection affects logical meaning pins, effect timing. signals having dual meaning versus DS*, versus R/W*. When Intel interface selected, these pins function WR*. These pins connected either IOR* IOW*, MEMRD* MEMWR* depending whether CD1865
CD1865 Intelligent Eight-Channel Communications Controller
mapped into memory space. These pins then serve select CD1865, when either active (along with ACKIN*) CD1865 considers itself selected. ACKIN* must never active same time. When Motorola interface selected, these signals function R/W*. must asserted (along with ACKIN*) types cycles, R/W* should when writing device. either case, choice interface entirely user. This feature user convenience, accommodate address bus-control logic that used. CD1865 8-bit data bus, common practice (when connecting 8-bit peripherals 32-bit systems) connect them only lane, 1-byte position. Thus, CD1865 registers only appear host's address space every other byte address. most common practice connect CD1865 portion data labelled D0-D7. little-endian processors, such Intel's, CD1865 appears even addresses big-endian processors, such Motorola's, CD1865 appears addresses.
6.3.2
Unclocked Versus Clocked Interface
Depending type speed host processor, another important choice determining whether system interface will clocked unclocked with host clock. Because there single clock both interface bit-rate generation, decision either Clocked Unclocked interface affected whether exact rates required. Most applications require exact rates, operate with rates varying percent exact rates required, clock speed must baud-rate multiple. method interfacing preferable another certain applications. Although easiest interface CD1865 using unclocked handshake supplied DTACK*, some cases better design clocked interface. latter true host system running same clock speed multiple) CD1865 speed.
Unclocked Interface
Unclocked interface easiest interface implement. Simply connect address, data, control lines customary manner, DTACK* control number wait states either connecting processor's DTACK* one), feeding into wait-state generator. Figure page shows typical Unclocked interface. maximum cycle time clock periods plus though typically less because this specification based worst-case internal synchronization delays. Using DTACK* saves time; however, permissible hard-wire wait-state generator maximum time.
Clocked Interface
CD1865 interface controlled state machine that samples falling edge clock. External strobes (CS*, DS*, R/W*; CS*, WR*) that meet setup time requirement cause cycle begin. external interface designed meet these setup time requirements, have shorter CD1865 access cycles. Figure page shows typical Clocked interface.
Intelligent Eight-Channel Communications Controller CD1865
cycle consists half-clock periods. During clock-low period, transaction internally, local arbitration occurs. During clock-high period, read write transaction occurs. write cycles, data from host latched internally lowto-high clock transition. read cycles, data available shortly after clock-high period. Read write cycles differ slightly timing; during write, permissible remove relatively early during high-clock period, however, this cannot done during read cycles. Strobe used output enable, must remain data appear external data bus. Service request acknowledgment cycles follow different timing than ordinary read cycles. First, necessary have address stable before asserting ACKIN*. Second, setup time from ACKIN* RD*) going falling clock edge longer additional internal logic involved service request acknowledge cycles. Figure Typical Unclocked Interface
A[0:6]
R/W*
CS*,
DB[0:7]
DTACK*
CD1865 Intelligent Eight-Channel Communications Controller
Figure Typical Clocked Interface
CD1864 CLOCK
CYCLE BEGIN
R/W*
DON'T CARE
ADDRESS
DON'T CARE
VALID
DON'T CARE
DATA-READ
UNDEFINED
VALID
DTACK*
Interface Examples
There some general design considerations when interfacing CD1865 host environment. three Service Request pins change time, this introduce metastability problems interrupt controller requires clocked signals. When designing, take care that signals stable when needed. Service Request type being acknowledged negated service acknowledgment cycle. Often, during course servicing channel, another channel reaches state where request would assert, example, while servicing receive channel one, channel two's FIFO fills. Service Request bits Service Request Status register (SRSR) does reassert until approximately clock periods after host completes write register polled mixed-mode systems, determine whether another service request same level pending, make sure that host does re-read SRSR quickly, insert No-Operation similar) instruction. Performing `invalid' service acknowledgment cycle CD1865 permissible, cause problems certain circumstances. Invalid Service Acknowledgment acknowledgment which there request pending. service request acknowledgment cycle performed host when service request pending, either things occur. value address matches three values three Service Match registers daisy chaining enabled, CD1865 assumes that another device down daisy chain should receive request, asserts ACKOUT* pin. This propagates down CD1865 chain until eventually last CD1865 asserts ACKOUT*.
Intelligent Eight-Channel Communications Controller CD1865
this point, system waits endlessly unless cycle terminates. best method connect ACKOUT* last CD1865 chain bus-error input host. there multiple CD1865s that cascaded, ACKOUT* signals should OR'ed together through gate PAL. acknowledgment occurs value address does match Match registers, first CD1865 chain does pass along assert DTACK* system waits endlessly unless there time-out other mechanism detect this condition. either these circumstances, `value' data likely because floating (this system dependent). make robust design, valid Global Service Vector register (GSVR) value. daisy chaining enabled, then CD1865 returns vector `00' invalid acknowledgments.
6.4.1
Interfacing 80X86-Family Processors
Intel 80X86 family processors often 8259A interrupt controller, which supplies vector during INTA cycle. easiest interface CD1865 Intel processor Mixed mode, described Section 5.5. There `bug' 8259A aware 8259A change prioritizing eight inputs, which result acknowledge outputs going briefly (~30 input changes certain time. This typically occurs higher-priority input 8259A asserts when 8259A about issue acknowledge lower-priority device. this occurs beginning cycle, this brief pulse cause CD1865 (and other devices) malfunction. sure that this does occur. Intel 8259A Data Sheet details.
6.4.2
Interfacing 680X0-Family Processors
68000-family interface quite straightforward. three service request lines through priority encoder 680X0 inputs. CD1865s ACKIN* driven decoder. When 680X0 performs Interrupt Acknowledge cycle, drives address lines with three-bit value indicating level being serviced. other address lines level being serviced corresponds level assigned CD1865, external decoding logic should assert CD1865 ACKIN* pin. value address lines programmed into CD1865 recognizes acknowledgment proceeds described Service Request Section 5.3.1. CD1865 service requests also routed single interrupt level using Mixed-mode interface, described Section 5.5.
6.4.3
Interfacing
CD1865 directly interfaced bus, only requires small amount logic complete interface. This necessary because service request acknowledgment works differently than CD1865. defines seven levels interrupts; each level shared among multiple cards. During Interrupt Acknowledge cycle, provides three bits address bus, indicating level being acknowledged (A1-A3). Each card must pass along interrupt levels using CD1865 does automatically pass interrupt acknowledgment.
CD1865 Intelligent Eight-Channel Communications Controller
recognize this difference cause problem, suppose that three Service Request lines from CD1865 connected levels (see Figure page 56). Also, attach 74XX244 that during Interrupt Acknowledgment cycle provides 8-bit code consisting three address bits plus five more hard-wired bits CD1865. Now, whenever acknowledgment level interrupt occurs, CD1865 either responds passes acknowledgment properly. acknowledgment occurs levels 1-4, daisy chain `breaks' because CD1865 does recognize match. Figure Incorrect Interface
ACKOUT* IRQ7* IRQ6* IRQ5* ACKIN* A1-A7 IACK* 74XX244 (BUFFERS SHOWN) A1-A3 ARBITRARY VALUE CD1865
RREQ* TREQ* MREQ* ACKOUT* ACKIN* A0-A6
This condition easily rectified, shown Figure page used assert ACKOUT* whenever ACKIN* occurs level being used CD1865. programmed fixed levels. example, current Interrupt level 1-4, asserts ACKOUT* whenever ACKIN* active. current level 5-7, asserts ACKOUT* when ACKOUT* from CD1865 active. required, assignment Interrupt levels CD1865 field-programmable supplying additional inputs PAL, indicating levels being used CD1865.
Intelligent Eight-Channel Communications Controller CD1865
Figure Correct Interface
ACKOUT* IRQ7* IRQ6* IRQ5* IRQ4* IRQ3* CD1865 IRQ2* IRQ1* ACKIN* A1-A7 A0-A6 RREQ* TREQ* MREQ* ACKOUT* ACKIN*
74XX244 (BUFFERS SHOWN) A1-A3 ARBITRARY VALUE
CD1865 Intelligent Eight-Channel Communications Controller
7.1.1
Serial Interfaces
Receiver Operation
Basic Operation
receivers disabled upon master reset. prepare receiver, first initialize then enable Once initialized enabled, receiver monitors Line waits high-to-low transition, which indicates Start bit. This sampling performed one-eighth Systemclock rate regardless Programmed rate, provides accuracy synchronization with incoming data. Figure below CD1865 synchronization. Once transition detected, receiver checks Input state again half-bit time later) validate that Start bit. valid Start defined `space' logic `0'. Input longer `space', then false Start assumed receiver resumes search high-to-low transition. valid Start detected, Input sampled one-bit time intervals middle ensure stable data. Characters assembled according programmed content Channel Option register (COR1). Valid character framing (presence Stop bit), Optional Parity bits checked. After character assembled, placed temporary Holding register. Then CD1865 processor checks error conditions, FIFO overrun, special character match before placing character corresponding status into Receive Status FIFOs.
7.1.2
Receive FIFO Operation
Eight bytes FIFO assigned each receiver data storage, addition Receive Holding register Receive Shift register. Once number data bytes received stored FIFO reaches programmed threshold, CD1865 programmed generate service request. Figure page Receive Operation. Receive FIFO Service Request threshold selected programming RxTH bits Channel Option register service request threshold one-to-eight characters selected. Once this threshold defined, service request automatically triggered when condition met. possible that time host responds service request, there more data FIFO than threshold level.
Figure Synchronization CD1865
SAMPLES 1/8-SYSTEM CLOCK
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
Start Detect
1/2-bit time
Intelligent Eight-Channel Communications Controller CD1865
overrun condition occurs when data arrives, Receive FIFO Receive Holding register both full. data lost overrun indication flagged character Holding register. That character status including overrun indication eventually transferred host Receive Exception Service Request. Note that this character good, last character received before overrun occurred. Receiver Service Requests enabled disabled Receive Data Enable register Receive Data bit, when `1', enables service requests asserted above causes. Prescaler Period Counter 16-bit counter clocked system clock. system clock 33-MHz clock, maximum count establishes clock tick every 1.9859 Prescaler Period should generate minimum tick period Receive Time-out Counter 8-bit counter decremental every tick Prescaler Period Counter. maximum count tick, maximum time-out period 0.506 seconds. Receive Time-out always enabled transfer data when Receive Data Service Request enabled. From system applications view-point, this time-out function important asynchronous data transmission. This especially true when FIFO service request threshold FIFO greater than character. Timer Service Request eliminates long response times when excessive delay between characters occurs caused either remote operator line being disabled. Data' Timer Service request, which occurs after data transferred host, used manage transfers from host's receive data buffers. Figure Receive Operation
RECEIVE DATA COUNT REGISTER
RECEIVER FIFO
RECEIVE STATUS FIFO
BACKGROUND CODE: H.R.-TO-FIFO TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) FULL/ EMPTY
RECEIVER HOLDING REGISTER
FOREGROUND CODE: ASSEMBLY, S.R.-TO-H.R. TRANSFER (INTERRUPT-DRIVEN)
RECEIVER SHIFT REGISTER
RECEIVER
CD1865 Intelligent Eight-Channel Communications Controller
7.1.3
FIFO Timer Operations
CD1865 uses Receive FIFO Timer purposes. first avoid `stuck' `stale') data FIFO caused receiving enough characters trip threshold, which causes service request issued. second signal host that there been relatively long pause received data. useful host know that data arrived lately' when managing relatively large buffers. This event flushes buffer host processing. avoid `stuck' data, each time CD1865 moves character into channel's Receive FIFO, sets channel's Receive FIFO Timer value contained channel's Receive Time-out Period register (RTPR). timer expires before data arrives, Receive Good Data sub-type service request asserted channel Receive Data Enable set. other receive timer option generate service request first Receive Data Time-out following transfer data from channel host. This called Data Time-out (NNDT). This service request Receive Exception sub-type with status type `Time-out Exception'. There data character associated with Time-out Exception status. This option enabled disabled controlling NNDT enough data arrives fill Receive FIFO level RxTh bits COR3, special character arrives Receive FIFO RxSC set, channel asserts Receive Data Service Request without waiting timer expire. timer times-out FIFO empty, `stale data' condition occurred, device posts Receive Good Data Interrupt. timer times-out there data, conditions checked. First, test made feature enabled, true, then another flag tested make sure this first time condition occurred. this true, Receive Exception Service Request posted. (The NNDT internal flag armed when FIFO emptied).
7.1.4
Receive Service Requests
Receive Service Request unique sub-types; that capable returning different vectors during service request acknowledge cycle. sub-types Receive Good Data Receive Exception. reason there types within category service request because while Good Data Exceptions require different handling, they both equal priority need serviced order they were received. Suppose, example, good characters received, then erroneous character, then another good character, then there must service request first bytes Good Data, then Exception, then more Good Data. Exception Service Requests were different level, erroneous character would processed either before after Good Data, normal sequence. Receiver Service Requests invoked under several conditions. Conditions that cause Receive Good Data Service Request are:
Receive FIFO threshold reached exceeded Receive FIFO time-out interval between character receptions exceeds time-out value
Conditions that cause Receive Exception Service Request are:
Receive erroneous data (parity error) Framing error Stop bit) data received time-out (optional)
Intelligent Eight-Channel Communications Controller CD1865
Special character detection Break detect
Note: Data cannot read from Receive FIFO Receive Status FIFO except when CD1865 within context Receive Data Service Request specific channel.
7.1.5
Receive Good Data Service Request
Receive Good Data Service Request asserted following three conditions: Receive FIFO threshold reached, FIFO contains Good Data. Receive FIFO threshold reached, FIFO contains Good Data Receive Data Timer times-out. Receive FIFO threshold reached, FIFO contains Good Data newly arrived data contains exception condition. When these conditions occur, modified service request vector indicates host that service request Good Data. necessary take available Good Data when Good Data Service Request received. host buffer full accept bytes, smaller number (even `0') read. Service request context then left, host buffer dealt with first. CD1865 generates another Good Data Service Request when three conditions listed above met. CD1865 immediately generates another service request condition that caused first place remains true. data read, this always case. some, available data read, Conditions true; Condition true exception condition caused Good Data Service Request. this problem, solution temporarily disable Receive Service Requests that channel. avoid FIFO overflow, delay handling channel long.
7.1.6
Receive Exception Service Request
Unusual exception conditions reported host character time through Receive Exception Service Request. with normal receive processing, host determines requesting channel reading GCR. then determine specific exception(s) reading Receive Character Status register before performing appropriate action. Receive Exceptions always 1-byte deep; multiple bytes exception conditions causes multiple Receive Exception Service Requests. many exceptions, necessary read Receive Data register after Receive Status register read. example, special character detection enabled, service request recognition special character, character known definition because exception code indicates detected character character sequence. However, every exception byte placed Data FIFO, even though contents that byte suspect data, byte discarded exception service routine regardless whether read host not. This done keep Status Data FIFOs lock-step with each other. This different case Receive Good Data Service Request where user free read many bytes required.
CD1865 Intelligent Eight-Channel Communications Controller
Regardless number type exceptions occurring, they reported host character time; that number-of-bytes value Receive Data Count register meaningful. Since every error reported individually, there Receive Time-out Exception generated only characters FIFOs error exception characters.
7.1.7
Types Errors
There four types errors recognized CD1865: parity, framing, line break, overrun. parity checking enabled, parity errors logged Status FIFO suspect data placed Receive Data FIFO. error also logged framing, that absence Stop bit. these cases, suspect character Receive Data FIFO appropriate status byte placed Status FIFO. When line-break condition recognized (zero data with zero parity, Stop bit), NULL (00) character loaded into Receive FIFO, break status recorded Status FIFO. Note that parity bits received zeroes, marked both break character parity error. Generally when break character received, pre-set parity error ignored. further FIFO entries made until normal-character reception resumed, example, Start found. line must high then back this occur. Multiple errors byte possible because CD1865 evaluates characters bit-by-bit receives them. example, parity error detected flagged before CD1865 recognizes that framing error occurred. Parity plus framing parity plus break error occur, framing plus break error cannot occur because, character received with every equal `0', marked break character. some bits `1', Stop missing, example, `0', marked framing error. Thus, character cannot have both framing break errors. length Stop checked CD1865. Stop long enough sampled mid-bit time interpreted valid Stop bit. addition other errors, overrun occurs, Overrun Error along with other error bits.
7.1.8
7.1.8.1
Types Exceptions
Special Character Recognition
`Special Character Recognition' feature found only CD1865 other Intel data communications controllers. on-chip processor compares every good character received with user-defined special characters stored registers device. Both single-character twocharacter sequence recognition possible. This capability several applications, including InBand Flow Control. Special-character matches reported host Receive Exception Service Request. Four Special Character registers provided channel, allowing received characters compared many four special characters. However, these four registers shared between Receive Special Character Detection Send Special Character Command, some planning required using these characters. full features options available part Special Character Recognition allows Xon/Xoff flow-control implemented transparently host, same time, detect either other special characters data stream alert host their arrival.
Intelligent Eight-Channel Communications Controller CD1865
user individually enable CD1865 channel recognize special characters. There bits used control various recognition flow-control modes. following four registers used control character recognition:
Name SCDE RxSC XonCH XoffCH COR3 COR3 Register COR3 Function Enables detection special characters. Must In-Band Flow Control work. Enables generation service requests. Cannot overridden other bits. Does need In-Band Flow Control work. Controls single- versus double-character matching. Controls single- versus double-character matching.
following table shows effects XonCH XoffCH:
XonCH XoffCH Characters matched Match SCHR1-4 Match SCHR1 SCHR3 (SCHR2 SCHR4) Match (SCHR1 SCHR3) SCHR2 SCHR4 Match (SCHR1 SCHR3) (SCHR2 SCHR4)
Note:
two-character pairs share common first character; however, same character must programmed both SCHR1 SCHR2. Single- versus double-character recognition controlled XonCH XoffCH. singlecharacter compare enabled, CD1865 compares data data stream against four special characters stored Special Character registers (SCHR1-4). fewer than four special characters required, unused Special Character register(s) should disabled duplicating pattern matched unneeded register. When reporting special character, CD1865 always reports lowest-number Special Character register that matches. Special Character Recognition, first characters matched registers SCHR14, then XonCH XoffCH according length match wanted. SCDE bit, lastly enable service requests setting RxSC. Special characters reported host placing appropriate status word Status FIFO recognized special character Receive Data FIFO. case two-character sequence, only second character stored Receive FIFO. This because there room only character preserving both needed these characters user-defined.
7.1.9
Flow-Control Characters
Automatic In-Band Flow Control CD1865 transmitter subset Special Character Recognition capability, understand both these features important. Refer Section page transmitter operation. Flow-control characters operation programmable per-channel basis. This important operating systems that allow users configure their terminal settings independently.
CD1865 Intelligent Eight-Channel Communications Controller
Because CD1865 performs flow-control functions before data passed host, response time required host avoid data overrun greatly reduced. Additionally, flowcontrol characters stripped from data stream, relieving host from processing them. automatic flow-control, Special Character Detection (SCDE) must enabled Channel Option register (COR3). This causes error-free received data compared match with Special Character registers (SCHR1-4). addition, flow-control must enabled Transmit In-Band Enable (TxIBE, COR2. This causes special characters interpreted flow-control characters. single-character flow-control sequences, SCHR1 used SCHR2 Xoff. SCHR3-4 available normal special-detect characters. two-character sequences enabled XoffCH XonCH (bits COR3, SCHR1 SCHR3 form sequence, SCHR2 SCHR4 form Xoff sequence. flow-control characters passed host, they marked special characters Receive Channel Status register (RCSR). two-character sequence detected, compressed second character status indicating match first character set. valid twocharacter sequence requires that both characters received without error; error occurs second character first character treated normal character, this does affect nonflow control special character detection.
Intelligent Eight-Channel Communications Controller CD1865
Bits affecting flow control summarized below.
Name SCDE TxIBE Register COR3 COR2 COR3 Function Enables Special Character Recognition. Enables Automatic Transmitter Flow-Control. Sets Transparency mode flow-control. XonCH XoffCH SCHR1 SCHR1 (SCHR1 SCHR3) (SCHR1 SCHR3) Xoff SCHR2 (SCHR2 SCHR4) SCHR2 (SCHR3 SCHR4)
controls whether flow-control characters passed host. meaning only when In-Band flow control enabled, that TxIBE set. When CD1865 receives flowcontrol character character sequence `0', starts stops transmitter, required, passes character onto host Receive Exception. Since there one-to-one correspondence between Status Receive FIFO, flow-control character detected stored Receive FIFO, status byte indicating special-character detect stored Status FIFO. `0', RxSC must enable service requests issued host. Otherwise, flow-control characters cannot passed Receive Exceptions instead passed Good Data. `1', CD1865 still starts stops transmitter, required, character(s) discarded, exception posted. either case, flow-control status transmitter off) maintained CD1865 Channel Control Status register (CCSR). makes possible support `escaping' flow-control characters. Some systems follow convention where identical flow-control characters indicates that flow control performed, rather flow-control character kept normal received-data stream, other `escape' character discarded. CD1865 such system, `0', allowing flow-control characters pass onto host. When host detects flow-control characters row, simply restores proper flow-control state channel discards characters. However, most systems `1', reducing loading host.
7.1.9.1
Data Received Time-Out
sometimes useful host sense that data arrived lately', when managing relatively large buffers. This event used flush buffer host processing. receive timer options, Data Time-out (NNDT), generates service request first Receive Data Time-out following transfer data from channel host. This service request Receive Exception sub-type, enabled disabled controlling NNDT Refer Figure page timer logic. timer started only data arrival. CD1865 processor determines that Receive FIFO empty, timer expired, there previous receipt Good Data (and timer feature enabled), Receive Exception occurs with status indicating that time-out occurred. last Receive Exception Service Request triggered time-out avoid `stale' data) Data Time-out Service Request occurs immediately after Data Transfer Service Request completes. last service request triggered reaching threshold, timer
CD1865 Intelligent Eight-Channel Communications Controller
still expire that some time passes before Data Service Request occurs. Likewise, last service request triggered some other error, such parity, timer still expire that some time passes before Data Service Request occurs. Data function should confused with time-out that occurs when there Good Data FIFO threshold been reached timer expires. This event Receive Good Data Service Request, Receive Exception event. Timing-out transfer Good Data before becomes `stale' standard, cannot turned user.
Intelligent Eight-Channel Communications Controller CD1865
Figure Data Timer Logic
.FROM OTHER BACKGROUND PROCESSING.
BACKGROUND SCANNING DETECTS CHARACTER ARRIVED
CHARACTER FIFO; RELOAD TIMER
TIMER
RESUME BACKGROUND SCANNING LOOP.
FIFO EMPTY
POST RECEIVE GOOD DATA SERVICE REQUEST
DATA TIMEOUT FEATURE ENABLED
NNDT INTERNAL FLAG 'ARMED' CLEAR NNDT INTERNAL FLAG
POST RECEIVE EXCEPTION SERVICE REQUEST
RESUME BACKGROUND SCANNING LOOP.
CD1865 Intelligent Eight-Channel Communications Controller
7.1.10
Programming Notes
special condition (for example, framing parity error) occurred special character, CD1865 does interpret this character matched. Flow-control characters that processed discarded because never cause overrun. Special Character Recognition only occurs characters that have other problems errors. There case where CD1865 does find special character even though character been correctly received. good character arrives ninth character (for example, FIFO full), stays Holding register. another character arrives, good character Holding register status marked `overflow', indicating that last good character received; however, recognized special character. There cases where CD1865 might detect two-character sequence. first character been found, other character been received long period time Receive Time-out event occurs, match found because first character flushed host. special-character detection disabled clearing SCDE just when CD1865 received first two-character special-character sequence, received second character yet, first character lost.
7.2.1
Transmitter Operation
Basic Operation
Refer Figure page diagram transmitter operation. Upon power-on reset, transmitters disabled with their Transmit Output held `Mark' logic condition. Other channel parameters undefined. minimum configuration channel transmission consists specifying rate, parity, number Stop bits. In-band Out-of-Band Flow Control should also required. Next, either both) service request enable bits. Then issue Transmit Enable Command either service request enable bits. normal operation, TxRDY bit. This causes service request issued when FIFO empty. Since power-up FIFO empty, service request received (less than ms.), that time data transferred FIFO. Data transferred FIFO part channel initialization; instead service-request routine this. Refer Section details. Once channel initialized serviced, character written into Transmit FIFO, transmitter starts transmit first sending Start (space logic `0') followed data character according predefined character length, least significant first. optional parity (none, odd, even, forced) appended followed final Stop logic `Mark'). length Stop one, one-and-a-half, two, two-and-a-half bit-times long. transmitter continues sending characters after other until Transmit FIFO empty. When Transmit FIFO empty last character sent, transmitter stops transmission holds Output `Mark' condition. Transmission resumes another character FIFO. some cases must determined channel completely done transmitting last last character instance, before changing rate. such case, service request issued only when last character sent, rather than when FIFO empty. this case, instead setting TxRDY bit, TxMpty bit. This causes service request issued only when transmitter completely empty.
Intelligent Eight-Channel Communications Controller CD1865
details transmitter flow-control operation, refer Section page Figure Transmitter Operation
TRANSMITTER FIFO
BACKGROUND CODE: FIFO-TO-H.R. TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) TRANSMITTER HOLDING REGISTER FULL EMPTY
FOREGROUND CODE: DISASSEMBLY, H.R.-TO-S.R. TRANSFER (INTERRUPT-DRIVEN)
TRANMSITTER SHIFT REGISTER
7.2.2
FIFO Operation
8-byte FIFO provided each transmit channel. addition 8-byte FIFO, CD1865 also contains Transmit Holding register Transmit Shift register each channel. However, when servicing Transmit Service Request, only eight characters written into Transmit Data register (TDR) consecutively.
7.2.3
Transmit Service Requests
Generating Transmit Service Request depends control bits Enable register Setting TxRdy specifies that Transmit Service Request generated when FIFO empty. When this condition occurs, there still character Transmit Holding register another character Transmit Shift register. host CPU, therefore, two-character times respond before transmitter output goes into idle (Mark) condition. Setting TxMpty instead TxRdy specifies that Transmit Service Request generated only when FIFO, Transmit Holding register, Transm
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