IEEE 1284-Compatible Parallel Interface Parallel Port (Peripheral
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CD1283
IEEE 1284-Compatible Parallel Interface
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (Standard) 1284 specification (including automatic negotiation) Centronics-compatible mode Reverse Byte mode Reverse Nibble mode (extended capabilities port) mode with run-length encoding/decoding (enhanced parallel port) mode 2-Mbytes/sec. transfer rate modes 64-byte parallel FIFO with interface 64-byte FIFO accommodate Kbytes compressed data with (run-length encoded) compression enabled
Supports peripheral-side operation Data control input/output pads support IEEE STD1284 level-2 interface specification interface High-speed slave handshake interface Three clocks word transfers On-the-fly data compression using (run-length encoded) encoding decoding 8/16-bit data interface BYTESWAP input provides easy interface both Big- Little-Endian systems Vectored interrupts simplify interrupt service routines System clock CMOS technology enables high speed power Available 100-pin MQFP package
General
2001, this document replaces Basis Communications Corp. document CL-CD1283 IEEE 1284-Compatible Parallel Interface.
2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. CD1283 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
IEEE 1284-Compatible Parallel Interface CD1283
Contents
Overview
Advantages
Conventions Information
Diagram.13 List.14 Descriptions Register Summary Tables.19 Device Architecture Interface.22 5.2.1 Read Cycles 5.2.2 Write Cycles 5.2.3 Service-Acknowledge Cycles 5.2.4 Cycles.24 5.2.5 Interrupts 5.2.6 DMAREQ* Interrupt Source.25 5.2.7 Daisy-Chain Configurations.26 Parallel Port Service Requests.27 5.3.1 Hardware-Activated Acknowledge 5.3.2 Software-Activated Acknowledge.32 Parallel Port FIFO Data Pipeline 5.4.1 IEEE Standard 1284 Protocols.33 5.4.2 Interface 5.4.3 Parallel Port FIFO.34 5.4.4 Receive Direction 5.4.5 Receiving Compressed Data.35 5.4.6 Stale Data (Stale, OneChar, Timeout Status Bits) 5.4.7 Transmit Direction Parallel Port Overview.36 5.5.1 Terminology.36 5.5.2 Signal Names 5.5.3 State Machine 5.5.4 Configuration 5.5.5 Interrupts 5.5.6 Manual Mode.38 5.5.7 Control Signals 5.5.8 Parallel Port Interface FIFO.39 5.5.9 IEEE 1284-Protocol Negotiations.39 5.5.10 Data Transfers.40 5.5.11 Compatibility Mode Status.40 IEEE 1284 Parallel Protocol Support
Register Summary
Functional Description.22
CD1283 IEEE 1284-Compatible Parallel Interface
5.10
5.6.1 Compatibility Mode. 5.6.2 Reverse-Nibble Reverse-Byte Modes 5.6.3 Request 5.6.4 Mode. 5.6.5 Mode Protocol Timing General-Purpose Port Parallel Port Interface. Hardware Configurations 5.10.1 Interfacing Intel, Microprocessor-Based System 5.10.2 Interfacing Motorola, Microprocessor-Based System. Overview Initialization 6.2.1 Device Reset. 6.2.2 Service Acknowledge Handling. ASCII Code Tables Global Registers. 7.1.1 Access Enable Register 7.1.2 Global Firmware Revision Code Register 7.1.3 General-Purpose Direction Register. 7.1.4 General-Purpose Register. 7.1.5 Parallel Interrupt Register 7.1.6 Prescaler Period Register 7.1.7 Service Request Register Virtual Registers. 7.2.1 End-of-Service Request Register. 7.2.2 Parallel Interrupt Vector Register Parallel Pipeline Registers 7.3.1 Data Error Register 7.3.2 Buffer Data Register. 7.3.3 Holding Register Status Register 7.3.4 Host Timeout Value Register 7.3.5 Local Interrupt Vector Register 7.3.6 Parallel Auxiliary Control Register. 7.3.7 Parallel Channel Reset Register 7.3.8 Parallel FIFO Control Register 7.3.9 Parallel FIFO Empty Pointer Register 7.3.10 Parallel FIFO Fill Pointer Register. 7.3.11 Parallel FIFO Holding Registers. 7.3.12 Parallel FIFO Quantity Register 7.3.13 Parallel FIFO Status Register. 7.3.14 Parallel FIFO Threshold Register. 7.3.15 Run-Length Count Register 7.3.16 Stale Data Timer Count Register 7.3.17 Stale Data Timer Period Register. Parallel Port Registers
Programming
Detailed Register Descriptions.
IEEE 1284-Compatible Parallel Interface CD1283
7.4.1 Address Register.67 7.4.2 Input Value Register.67 7.4.3 Manual Data Register.68 7.4.4 Negotiation Enable Register.68 7.4.5 Negotiation Status Register.69 7.4.6 Ones Detect Register 7.4.7 Output Value Register 7.4.8 Parallel Channel Interrupt Enable Register 7.4.9 Parallel Channel Interrupt Status Register 7.4.10 Parallel Configuration Register.71 7.4.11 Special Command Register.72 7.4.12 Short Pulse Register 7.4.13 Signal Status Register 7.4.14 Zeros Detect Register Special Register 7.5.1 Reset Command Register Absolute Maximum Ratings.76 Recommended Operating Conditions Characteristics.78 8.3.1 Asynchronous Timing.78 8.3.2 Synchronous Timing.84
Electrical Specifications
10.0 Index
Package Dimensions Ordering Information
CD1283 IEEE 1284-Compatible Parallel Interface
Figures
Functional Block Diagram Functional Block Diagram Internal Address Generation CD1283 Daisy-Chain Configuration Interrupt Generation Logic Control Signal Generation. FIFO Data Path Functional Diagram Receive. FIFO Data Path Functional Diagram: Transmit. Supported Compatibility Mode Timing Cable Connection. External Buffer Control. Sample System Block Diagram. Intel, 80x86 Family Interface Motorola, 68020 Interface Flow Diagram CD1283 Master Initialization Sequence. Polling Flow Chart Reset Timing Clock Timing Asynchronous Read Cycle Timing Asynchronous Write Cycle Timing Asynchronous Service Acknowledge Cycle Timing Asynchronous Read Cycle Timing Asynchronous Read Cycle Timing (Two Back-to-Back Reads) Asynchronous Write Cycle Timing Asynchronous Write Cycle Timing Synchronous Read Cycle Timing. Synchronous Write Cycle Timing Synchronous Service Acknowledge Cycle Timing Synchronous Write Cycle Timing (Two Back-to-Back 3-Cycle Writes) Synchronous Read Cycle Timing (Two Back-to-Back 3-Cycle Reads)
Tables
Global Registers. Virtual Registers. Parallel Pipeline Registers Parallel Port Registers Special Register LIVR[2:0] Encoding System Clock Setup. Hexadecimal Character Decimal Character. PIVR[2:0] Encoding. Binary Values 500-ns Pulse Widths Asynchronous Timing Reference Parameters Synchronous Timing Reference Parameters
IEEE 1284-Compatible Parallel Interface CD1283
Revision History
Revision Date 4/01 Initial release. Description
IEEE 1284-Compatible Parallel Interface CD1283
Overview
CD1283 multi-function interface controller printers, scanners, tape-drives, set-top boxes, data acquisition, other applications that require high-speed, bidirectional, parallel communication with host computer. modes IEEE 1284 Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers specification supported, including ECP, EPP, Reverse Byte, Reverse Nibble, Compatible. With full support this standard, CD1283 provides compatibility with types host parallel ports, including older Centronics, PS/2 bidirectional, latest IEEE 1284-compliant ports. dedicated state-machine design provides fastest possible response times host signal changes, with 100% guaranteed compliance IEEE 1284 timing, protocol, signaling requirements. CD1283 device, operating MHz, signal response times support Mbytes/sec. transfers, provided that comparably fast host parallel port used. This performance headroom guarantees that faster data rates future host parallel port implementations will supported peripheral applications using CD1283. addition dedicated state machine, CD1283 provides slave support, 64-byte FIFO allow maximum total throughput performance. Interrupts generated based status changes parallel port. Note, however that interrupts generated FIFO threshold, FIFO full/empty conditions. request signal used generate interrupts long hardware software implementation handled correctly. maximum performance requirement, device monitored controlled polling detailed status registers. Another unique feature CD128X series devices dedicated hardware compression/decompression mode. Special logic used perform ECP-RLE compression/decompression `on-the-fly' while data moved from FIFO. these capabilities above beyond requirements IEEE 1284 specification permit less expensive microprocessor reducing required bandwidth needed parallel port. development hardware software, evaluation complete with application notes programmer's guide provided along with software examples evaluation board schematics. add-in card designed demonstrate capabilities CD128X family devices, enables software developers begin testing code while system hardware still development.
Advantages
Unique Features
Supports IEEE 1284 specification Hardware support IEEE 1284 timings 64-byte FIFO Parallel port signals provide level-2 drive characteristics channel compression/decompression hardware
CD1283 IEEE 1284-Compatible Parallel Interface
Benefits
Multi-protocol bidirectional port wide range applications.
Mbytes/sec. transfer rate Provides future connectivity with host systems
Reduces software complexity guarantees specification compliance. High throughput with reduced load host CPU. Direct connection printer cable; reduces chip count. Reduces host interface overhead. High-speed data movement between memory parallel port.
Reduces software complexity increases throughput compressed-data tranfers.
Figure Functional Block Diagram
GENERAL-PURPOSE PORT
LOGIC INTERRUPT LOGIC
COMPRESSION/ DECOMPRESSION BYTES DATA MOVER LOGIC DATA PIPELINE FIFO
CONTROL STATE MACHINE
LEVEL-2 ELECTRICAL INTERFACE
HOST INTERFACE
IEEE 1284 PERIPHERAL PARALLEL PORT
IEEE 1284-Compatible Parallel Interface CD1283
Conventions
Abbreviations
Symbol
Units Measure degree Celsius hertz (cycles second) kilobyte (1,024 bytes) kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) microfarad microsecond (1,000 nanoseconds) milliampere millisecond (1,000 microseconds) nanosecond picovolt
Kbyte Mbyte
`tbd' indicates values that determined', `n/a' designates `not available', `N/C' indicates that connect'.
Acronyms
Acronym BIOS CISC CMOS DRAM FIFO GPIO HCMOS HDLC alternating current
Definition
basic input/output system complex instruction computer complementary metal-oxide semiconductor direct current direct-memory access dynamic random-access memory extended capibilities port enhanced parallel port first in/first general-purpose high-performance complementary metal-oxide semiconductor high-level data link control
CD1283 IEEE 1284-Compatible Parallel Interface
Acronym MQFP SDLC SRAM VRAM
Definition (Continued) integrated circuit instruction data cache industry standard architecture least-significant microprocessing unit most-significant programmed point-to-point protocol metric quad-flat pack random-access memory run-length encoded read/write synchronous data link control static random-access memory software interrupt instruction translation look-aside buffer translation table base transitor-transitor logic video random-access memory write buffer
IEEE 1284-Compatible Parallel Interface CD1283
Information
Diagram
DB[10]
DB[11]
DB[12]
DB[13]
DB[8]
DB[9]
BYTESWAP
DB[14] DB[15]
OUTEN
A[2]
A[3]
A[4]
A[0]
A[1]
A[5]
A[6]
DB[7] DB[6] DB[5] DB[4] DB[3] DB[2] DB[1] DB[0] DMAACK* DMAREQ*
CLK/2 RESET* R/W* DTACK* DPASS* DGRANT* SVCACKP* SVCREQP* PULLUP6 PULLUP5 PULLUP4 PULLUP3 PULLUP2 PULLUP1 GP[0] GP[1] GP[2] GP[3] GP[4] GP[5] GP[6] GP[7] PDBEN
CD1283
100-Pin MQFP
PerBsy
PerClk
PD[6]
PD[1]
EBDIR
A_1284
HstBsy
Xflag
PD[5]
PD[4]
AkDaRq
nDatAv
HstClk
PD[3]
following table
NOTE: Denotes negative-true signal. `N/C' indicates connection; make connection these pins.
PD[0]
PD[7]
PD[2]
nInit
CD1283 IEEE 1284-Compatible Parallel Interface
Names
Compatibility
Reverse Nibble Mode
Reverse Byte Mode
Mode
Mode
Inputs A_1284 HstBsy HstClk nInit SLCTIN* AUTOFD* STROBE* INIT* A_1284 HstBsy HstClk nInit A_1284 HstBsy HstClk nInit A_1284 HstAck HstClk nRevReq nAStrb nDStrb nWrite nInit
Outputs AkDaR PerBsy PerClk nDatAv XFlag PError BUSY ACK* FAULT* SELECT AkDaRq PerBsy PerClk nDatAv XFlag AkDaRq PerBsy PerClk nDatAv XFlag nAkRev PerAck PerClk nPerReq XFlag USER1 nWait Intr USER2 USER3
List
following naming conventions used pin-assignment tables:
after name indicates that signal active-low indicates input-only indicates output-only `I/O' indicates bidirectional `OD' indicates open-drain output that user must through pull-up resistor (usually about
`TS' indicates tristate `PU' indicates pull-up, which must also tied through resistor (note that
pins wire-OR'ed through same pull-up resistor)
`AR' indicates active release (pin drives high releases indicates ascending numbers indicates descending numbers
Name A[6:0] BYTESWAP CLK/2 Type Number Pins Numbers 84-90 Reset State
IEEE 1284-Compatible Parallel Interface CD1283
Name DB[15:0] DTACK* OUTEN RESET* R/W* DMAREQ* DMAACK* SVCREQP* SVCACKP* DGRANT* DPASS* PD[7:0] GP[7:0] A_1284 nInit HstBsy HstClk PerBsy PerClk AkDaRq Xflag nDatAv EBDIR PDBEN PULLUP1 PULLUP2 PULLUP3 PULLUP4 PULLUP5 PULLUP6
Type
Number Pins
Numbers 92-99, 41-48 53-60
Reset State
High
High
High
High High High
CD1283 IEEE 1284-Compatible Parallel Interface
Symbol A[6:0]
Descriptions
84-90 Type Description (Sheet ADDRESS BUS: Together with SVCACK* inputs DS*, this input selects on-chip register read write operation acknowledgment service request. BYTESWAP: This input determines byte order 2-byte transfers writes DMABUF register.
BYTESWAP
BYTESWAP `1', Data bits 15:8 driven with byte transferred first parallel port bus. Data bits driven with byte transferred second parallel port bus. BYTESWAP `0', data order reversed, bits driven with first byte transferred, bits 15:8 driven with second byte transferred. SYSTEM CLOCK: This input maximum; recommended minimum satisfactory device performance. SYSTEM CLOCK DIVIDED OUTPUT: This signal equivalent internal operating clock device. ACTIVE-LOW CHIP SELECT: When active, input conjunction with DS*, initiates cycle with CD1283. must during read/write operations. BIDIRECTIONAL DATA [15:0]: Only transfers writes Buffer register true 16-bit operations. During register writes other than Buffer register, only bits written addressed register. Register reads duplicate register contents both lower byte, bits 7:0, upper byte, bits 15:8. ACTIVE-LOW DATA STROBE: During active cycle, input strobes data into on-chip registers write cycles enables data onto data during read cycles. ignored during operations. ACTIVE-LOW DATA TRANSFER ACKNOWLEDGE: This output indicates: when device completed requested operation, when cycle finish. This signal used implement wait-state insertion local CPU. Active Release output, driving logic then releasing DTACK* must tied external with pull-up resistor. DTACK* activated cycles. OUTPUT ENABLE: This must enable output functions. When OUTEN `0', forces pins that outputs remain tristate condition. OUTEN used test input normally used application. User designs should this through pull-up resistor.
CLK/2
DB[15:0]
92-99,
DTACK*
OUTEN
RESET*
ACTIVE-LOW RESET INPUT: Initializes device default condition. internal registers their reset condition transfer operations default state. READ/WRITE*: This must register read operation register write operation. This input ignored operations. ACTIVE-LOW REQUEST: When internal control DMAen set, output DMAREQ* asserted whenever internal FIFO conditions warrant transfer. DMAREQ* deasserted falling edge DMAACK* when transfers must continue past current transfer. ACTIVE-LOW ACKNOWLEDGE: This signal must never asserted unless response DMAREQ* from device. DMAACK* only handshake signal recognized during transfer. (CS* must high whenever DMAACK* asserted.) direction transfer determined internal control DMAdir.
R/W*
DMAREQ*
DMAACK*
IEEE 1284-Compatible Parallel Interface CD1283
Symbol
Type
Description (Sheet ACTIVE-LOW SERVICE REQUEST PARALLEL: This open-drain output must tied external through pull-up resistor. Note that this output only activated certain conditions parallel port (such negotiation changes, direction changes, etc.). SVCREQP* activated FIFO threshold, FIFO full/empty conditions (refer Chapter information DMAREQ* implement fully interrupt-driven system). ACTIVE-LOW SERVICE ACKNOWLEDGE PARALLEL: This input must driven active except response parallel service request presented device. ACTIVE-LOW DAISY GRANT: This input driven active during service acknowledge cycles enable daisy-chain function. This input, when qualified with valid service acknowledge (SVCACKP*), activates service acknowledge cycle. ACTIVE-LOW DAISY PASS: This output driven active during service acknowledge cycles enable next device daisy-chain. driven active when valid service request exists service acknowledge input active. multiple CD1283 designs, this signal normally connected DGRANT* input next device chain. PARALLEL PORT DATA LINES [7:0]: Bidirectional, depending protocol being used, these signals used transfer data over interface between master slave. GENERAL-PURPOSE [7:0]: General-purpose input/output port data lines. These signals individually direction-programmable, acting inputs outputs. direction each signal controlled corresponding GPDIR register. Control/status actual signals provided through GPIO register. ACTIVE-HIGH 1284 ACTIVE INPUT: (SLCTIN* Compatibility mode). ACTIVE-LOW INIT SIGNAL: (INIT* Compatibility mode). ACTIVE-HIGH HOST BUSY SIGNAL: (AUTOFD* Compatibility mode). ACTIVE-LOW HOST CLOCK SIGNAL: (STROBE* Compatibility mode).
SVCREQP*
SVCACKP*
DGRANT*
DPASS*
PD[7:0]
41-48
GP[7:0]
53-60
A_1284 nInit HstBsy HstClk
NOTE: above four parallel handshake signals driven master IEEE 1284 interface, such inputs CD1283. Their functions depend transfer protocol selected. Refer IEEE 1284-1994 document protocol functions. (See Chapter 10.0 ordering information.) PerClk PerBsy AkDaRq Xflag nDatAv ACTIVE-LOW PERIPHERAL CLOCK: (ACK* Compatibility mode) ACTIVE-HIGH PERIPHERAL BUSY: (BUSY Compatibility mode) ACKNOWLEDGE DATA REQUEST: (PERROR* Compatibility mode) EXTENSIBILITY FLAG: (SELECT Compatibility mode) ACTIVE-LOW DATA AVAILABLE SIGNAL: (FAULT* Compatibility mode)
CD1283 IEEE 1284-Compatible Parallel Interface
Symbol
Type
Description (Sheet
NOTE: above five parallel handshake signals driven slave IEEE 1284 interface, such outputs from CD1283. Their functions depend transfer protocol selected. Refer IEEE 1284-1994 document protocol functions. (See Section 5.4.1 page ordering information.) EXTERNAL BUFFER DIRECTION: This signal controlled internal parallel port control state machine used control direction external buffer connected Parallel Port data bus. external buffer might desirable applications that require higher drive capacity than that provided CD1283. EBDIR used conjunction with PDBEN control this buffer. EBDIR logic when parallel data output mode, logic when input mode. connected directly direction control input 74245-type device. PARALLEL DATA ENABLE: This signal control buffer Parallel Port data lines applications requiring more signal-drive capability than provided CD1283. PDBEN controlled internal Parallel Port control state machine. When low, parallel port data driving; when high, port output mode actively driving. PDBEN will toggle between states during output modes only active (high) while data pins active driving state. PDBEN logically connected enable control 74245 equivalent) bidirectional buffers (see Section Figure 11).
EBDIR
PDBEN
IEEE 1284-Compatible Parallel Interface CD1283
Register Summary
Local communication with CD1283 occurs through register set. Within this register set, there four types registers:
Global, common functions device Parallel pipeline Parallel port Service-acknowledge accessible
Global registers always available their addresses affected contents (this register provided maintain compatibility with CD1284). Note: must `00h' must changed (except access RCR), access many registers will work properly! following tables define register names, read write access modes, internal address offsets, definitions. detailed description each register, contents functions found Chapter address offset defined binary value that should applied address inputs (A[6:0]) during cycles. Note that addresses shown relative CD1283 definition address lines. 32bit systems, common practice connect 8-bit peripherals only byte lane. Thus, 16bit systems, CD1283 appears every other address (for example, CD1283 A[0] input connected A[1]). 32-bit systems, CD1283 appears every fourth address (CD1283 A[0] connected A[2]). either these cases, address used programmer will different than what shown tables. instance, 16-bit Motorola 68000-based system, CD1283 placed data lines D[7:0], which addresses Motorola scheme addressing. CD1283 A[0] input connected with A[1] 68000, A[1] with A[2], Thus, CD1283 address 0x40 becomes 0x81 programmer. leftshifted A[0] must low-byte (D[7:0]) accesses.
Table
Name GFRCR GPDIR GPIO SVRR
Register Summary Tables
Global Registers
Poll Poll Poll Poll Poll Page Data Data Data
Firmware Revision Code Data PPIreq Data PPort Data Pipeline Data Data
Binary Value DMAREQ
CD1283 IEEE 1284-Compatible Parallel Interface
Table
Name EOSRR PIVR
Virtual Registers
Page
indicates `don't care'.
Table
Name DMABUF (High byte) DMABUF (Low byte) HRSR HTVR LIVR PACR PCRR PFCR PFEP PFFP PFHR1 PFHR2 PFQR PFSR PFTR RLCR SDTCR SDTPR
Parallel Pipeline Registers
DMAwrerr DMArderr Bufwrerr Bufrderr HR1wrerr HR1rderr HR2wrerr HR2rderr Page
HR1full HTVR[7]
HR1tag HTVR[6]
HR2full HTVR[5]
HR2tag HTVR[4]
DMAfull HTVR[3]
DMAempty HTVR[2]
DMAact HTVR[1] AsyncDM ErrEn
Ctnot0 HTVR[0] PChReset DMAbufWe
User-Defined Bits ShrtTen FIFOres ShrtStal DMAen StaleOff DMAdir FIFOlock IntEn ClearTO RLEen
setTAG
6-Bit Binary FIFO Pointer Value 6-Bit Binary FIFO Pointer Value 8-Bit Character Data 8-Bit Character Data Data Space Available FIFO 0x40
FFfull
FFempty
Timeout
HRtag
HRdata
Stale
OneChar
DataErr
Transfer Threshold 7-Bit Unsigned Binary Count 8-Bit Stale Data Timer Count 8-Bit Stale Data Timeout Value
Table
Name
Parallel Port Registers (Sheet
Page nInit HstBsy HstClk
8-Bit Binary Value A1284 8-Bit Binary Data NegOK NegFl HostTO Invalid
4-Bit Negotiation Result Code
IEEE 1284-Compatible Parallel Interface CD1283
Table
Name PCIER PCISR
Parallel Port Registers (Sheet
PerBsy ManMd PerClk E1284 AkDaRq NegCh NegCh ETxfr xFlag SigCh SigCh Ig_SEL A1284 nDatAv EPPAW EPPAW HTmrTst[1] ClrPs nInit DirCh DirCh HTmrTst[0] SetPs HstBsy IDReq IDReq MMDir EPIrq HstClk nINIT nINIT ManOE RevRq Page nInit nInit HstBsy HstBsy HstClk HstClk
8-Bit Binary Value A1284 A1284
Table
Name
Special Register
Page
CD1283 IEEE 1284-Compatible Parallel Interface
Functional Description
Device Architecture
CD1283 consists dedicated logic tailored function sending receiving parallel data. device implements IEEE 1284-compliant parallel port with specialized data pipeline designed high-speed transfers. maintain binary compatibility with CD1284, much architectural layout been duplicated. Therefore, access register parallel channel only possible after loading with CD1284 occupied parallel port address namely channel channelspecific accesses, first loads with pointer channel Thereafter, read write operations occur through parallel channel. parallel channel comprised FIFO data interface, well high-speed state machine manage modes defined IEEE 1284-1994 specification, Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers. parallel port performs slave peripheral function IEEE 1284 interface, accept negotiations into IEEE defined modes.
Interface
interface comprised 7-bit address bus, 8-bit bidirectional data bus, 16-bit port, control inputs identify type cycle occurring. signaling basic timing match that Motorola 68000 family. With addition minimal glue logic, interface will work with nearly CPU. special input provided swap bytes data reduce necessary logic needed with Intel-style CPUs. interface completely compatible with CD1284. Therefore, CD1283 inserted into system instead CD1284 parallel port operates without modifications interface, parallel port hardware software. most cases, when reads writes internal CD1283 location, accesses location array serve bank registers. However, some locations mapped actual hardware resources. example, when hard output signal required (such service-request output SVRR) read actual state input necessary (such parallel port handshake signal IVR).
IEEE 1284-Compatible Parallel Interface CD1283
Figure Functional Block Diagram
PARALLEL PORT FIFO PARALLEL PORT LOGIC
PIPELINE
PIPELINE CONTROL CONTROL STATE MACHINE INTERFACE LOGIC INTERRUPT LOGIC
REGISTERS
Figure Internal Address Generation
REGISTER ARRAY ADDRESS
ADDRESS GENERATION
PARALLEL PORT REGISTERS
CD1283 synchronous device. internal operations occur edges levels (phases) internal clock. internal clock generated dividing external (system) clock two. When performs cycle with CD1283, strobes; address data sampled rising edges internal clock. illustrated Chapter 8.0, external control signals must meet setup times with respect system clock edges. Once cycle starts, sequence events locked CD1283 clock, with events (address setup, write data setup, read data available) occurring predictable times. necessary design synchronous interface CD1283. asynchronous design, DTACK* (Data Transfer Acknowledge) signal indicates that CD1283 completed requested data transfer cycles except DMA. DTACK* input wait-state generation logic that pauses until operation complete. strobes (Chip Select Data Strobe) meet minimum setup time with respect system clock edge, CD1283 does detect request, cycle delays full-system clock cycles, meeting setup time. cycle commences follows predictable timing with DTACK* signaling end.
CD1283 IEEE 1284-Compatible Parallel Interface
5.2.1
Read Cycles
Read cycles initiated when both inputs activated R/W* (read/ write) input high. strobes address inputs must meet setup times specified Chapter 8.0. Both signals must valid cycle start. Cycle times measured from whichever signals goes active last. CD1283 signals completion read cycle (placing data from addressed register data pins) activating DTACK*. read cycle terminates when removes DS*.
5.2.2
Write Cycles
Write cycle timing strobe activity nearly identical read cycles except that R/W* signal must held low. Write data, strobes, address inputs must meet setup hold times specified Chapter 8.0. DTACK* indicates that cycle complete CD1283 accepted data. Removing both terminates cycle.
5.2.3
Service-Acknowledge Cycles
Service-acknowledge cycles special-case read cycle. Timing basically same normal read cycle, SVCACKP* input activated instead input slightly longer setup time required SVCACKP* input than input). data that CD1283 provides during read cycle contents PIVR. with read write cycles, DTACK* indicates cycle removing SVCACK* terminates cycle. Note: With regard timing service-acknowledge cycles, when completes service routine writes EOSRR, subsequent cycle, started immediately, delayed approximately delaying DTACK*. This time required internal processor complete activities associated with service-acknowledge cycle. These activities primarily interrupt-logic updates restoration environment prior procedure. These must completed before internal registers modified CPU. attempts access before internal procedures complete, CD1283 will hold cycle until ready. system designs that monitor DTACK*, this problem; cycle extended until DTACK* becomes active, delay automatically met. system design does monitor DTACK*, mechanism must provided introduce required delay.
Warning:
Failure observe above delay requirement cause device malfunction.
5.2.4
Cycles
CD1283 provides bidirectional, 16-bit interface parallel port. This only direct-data interface port; other 8-bit register accesses make normal interface, previously described. handshake between CD1283 circuitry uses signals: DMAREQ* DMAACK*. address ignored during transfers. When internal conditions warrant transfer when FIFO falls below programmed threshold forward direction rises above threshold reverse direction) transfers enabled through PFCR, device requests service driving DMAREQ* low. DMAREQ* remains active until FIFO less than empty byte locations remaining (forward direction) until
IEEE 1284-Compatible Parallel Interface CD1283
FIFO less than bytes remaining (reverse direction). forward direction, controller logic responds placing data 16-bit data driving DMAACK* input low. This cycle repeated until FIFO less than empty byte locations remaining there more data send. reverse direction, CD1283 responds active DMAACK* signal driving contents DMABUF register onto data bus. Odd-byte transfers reverse direction handled interrupt basis. When number bytes FIFO odd, bytes except last transferred through number 16-bit cycles (two bytes cycle). byte remaining held PFHR1 interrupt generated when stale data timer expires. Status indicating that PFHR1 contains data indicated PFSR. interrupt service routine must manually remove remaining byte from interface. forward direction, remaining byte directly written PFHR1 once last cycle complete. additional input signal determines endian format (whether least-significant byte data bits 15:8) 16-bit buffer. BYTESWAP selects whether lower upper byte buffer moves into FIFO data pipeline first forward direction, from FIFO data pipeline buffer first reverse direction. BYTESWAP low, then least-significant byte (DB[7:0]) immediately moves into data pipeline. BYTESWAP high, opposite occurs (DB[15:8] move into pipeline first). effective duration transfer block (burst) determined threshold value PFTR. Regardless where port moving data when this threshold reached (exceeded receive; less than transmit), cycle begins remains active until FIFO less than bytes remaining (receive) less than empty byte locations remaining (transmit). SVRR provides determine cycle being requested. SVRR[7] true cycle currently being requested. This status indication provided general system status. Refer Chapter detailed information cycle options timing values.
5.2.5
Interrupts
term interrupt generalized description method where CD1283 gains attention CPU. Interrupt used interchangeably with `service request' same function. Interrupt often describes unconditional response part CPU. Whether this case, source still same service request from CD1283. hardware signal generated CD1283 (SVCREQP*) connected interrupt input start interrupt service routine. service routine then begin servicing request from CD1283 starting acknowledge sequence.
5.2.6
DMAREQ* Interrupt Source
Interrupts generated FIFO threshold conditions; therefore, system design requires data move through interrupts, connect DMAREQ* directly interrupt input logically into same interrupt input SVCREQP*. DMAREQ* used generate interrupts, following required: 16-bit data interface must implemented support 16-bit reads DMABUF register. threshold value PFTR must initialized. DMAREQ* remains active until FIFO nearly empty (Rx) nearly full (Tx), followed toggling DMAen data moved to/from FIFO through (refer
CD1283 IEEE 1284-Compatible Parallel Interface
Section 5.2.4). However, software easily change this clearing DMAen (PFCR[6]) start interrupt service routine setting again end. SVCREQP* DMAREQ* logically OR'ed together, service routine must start checking SVRR determine which signal active. SVCACKP* must activated response DMAREQ*; likewise, DMAACK* must activated response SVCREQ*. DMAdir (PFCR[5]) determine whether write read to/from DMABUF register. PFQR determine many reads 16-bit DMABUF register necessary empty pipeline. Note however, four must added PFQR value, then that number then must divided truncated nearest integer (this accounts extra four bytes holding registers 16-bit DMABUF register, well 16-bit instead 8-bit reads).
5.2.7
Daisy-Chain Configurations
Multiple CD1283s connected daisy-chain configuration, forming systems with multiple parallel ports. device provides signals necessary this configuration, with only minimal external logic being (Figure When acknowledges request, both CD1283s receive acknowledge through SVCACK*. However, only device receives DGRANT*. active request this type pending, takes acknowledge drives vector register (RIVR, TIVR, MIVR) onto data bus. first device does have request pending, passes DGRANT* second CD1283 through DPASS*. Assuming that second CD1283 active request pending, then takes acknowledge drives vector register onto data bus.
Figure CD1283 Daisy-Chain Configuration
ADDRESS DECODE LOGIC
SVCACKP* SVCACKP*
DPASS* DGRANT*
DGRANT* DPASS*
CYCLE ERROR
SVCREQP*
SVCREQP*
CD1283
CD1283
IEEE 1284-Compatible Parallel Interface CD1283
previously mentioned, upper bits LIVR reflect what loaded into them during initialization CD1283s. These bits used unique chip identification number. determine which CD1283 responded service acknowledge. These five bits could binary LIVRs first CD1283, binary `00001' those second. able test bits determine which device responded. Some examples service-acknowledge software routines that show performing this task provided Chapter 6.0. Caution: CD1283 chain pending request, DGRANT* passed last CD1283 none respond. This causes cycle fail DTACK* generated). only time this happens when error condition outside CD1283s cause respond request that made. Provide mechanism terminate abort cycle this error occurs. This accomplished with timeout circuitry, DPASS* output last CD1283 activate abort condition. Other devices, such CD1400, share daisy-chain mechanism connected DPASS* output last CD1283 chain. actual implementation system-dependent, important provide some determine that cycle complete normally device responds acknowledge cycle.
Parallel Port Service Requests
Service requests derive from internal sources: data pipeline parallel port state machine (Figure page 28). data pipeline internal service request becomes active, Pipeline (PIR[5]) set; likewise, parallel port state machine internal service request becomes active, PPort (PIR[6]) set. Internal service requests from these sources monitored through Pipeline PPort bits microcode running internal MPU. When either both) these bits detected active, microcode sets PPireq (PIR[7]). PPireq also mirrored (SVRR[3]). SVRR useful polled systems because allows detection service requests, well parallel port service requests with single register read operation. Note: specific register definitions default settings, refer Chapter 7.0. Both internal sources service requests within parallel channel have their enable functions. Interrupts from data pipeline enabled through PFCR; interrupts from parallel port state machine enabled through PCIER. PFCR enable bits: normal interrupts (such tagged data being received), data errors (such write holding register that already holds data). first type interrupt enabled through IntEn (PFCR[4]). second type interrupt enabled through ErrEn (PFCR[1]). Note that IntEn must ErrEn generate interrupt; however, need enable error interrupts does require notification these types errors. error interrupt generated DataErr (PFSR[0]) non-zero. this case, indicates cause error interrupt. parallel channel-control state machine generate types interrupts. Each these enable PCIER:
NegCh negotiation changes SigCh signal changes port status inputs (Manual mode only) EPPAW protocol address writes DirCh direction changes parallel channel
CD1283 IEEE 1284-Compatible Parallel Interface
IDReq slave requests from remote master. nINIT initialization pulses from master (Compatibility mode only)
these bits set, based mode operation. NegCh interrupt issued whenever remote master performs protocol change, such moving from Compatibility mode ECP; examines determine state parallel interface. Signal changes identified reading SSR. response EPPAW interrupt, would read retrieve value that written during address write cycle. Figure Interrupt Generation Logic
KEY: Current mode Interface extensibility request value (see IEEE1284 more details) (register name[x]) that PCIER[1] PCIER,
IDReq PCIER[1]
IDReq PCISR[1]
FAILED NEG. (INVALID EXTCODE) [COMPATIBILITY MODE] NSR=0x41
TERMINATION [COMPATIBILITY MODE] NEG-OK NSR=0x82
NEG-OK NSR=0x89[RN REQUEST] {04} NSR=0x8B[RB REQUEST] {05} NSR=0x8D[ECP REQUEST]{14} NSR=0x8F[ECP REQUEST] {34} NegCh PCIER[5] NegCh PCISR[5]
NSR=0x86[EPP MODE] {40} NSR=0x88[RN MODE] {00} NSR=0x8A[RB MODE] {01} NSR=0x8C[ECP RLE]{10} NSR=0x8E[ECP RLE] {30}
NSR=0x46 (EPP) NSR=0x48 (RN) NSR=0x49 (RN-ID) NSR=0x4A (RB) NSR=0x4B (RB-ID) NSR=0x4C (ECP) NSR=0x4D (ECP-ID) NSR=0x4E (ECP-RLE) NSR=0x4F (ECP-RLE-ID) FAILED MODE ENABLED [COMPATIBILITY MODE]
NSR=0x22
NSR=0x16 (EPP) NSR=0x18 (RN) NSR=0x19 (RN-ID) NSR=0x1A (RB) NSR=0x1B (RB-ID) NSR=0x1C (ECP) NSR=0x1D (ECP-ID) NSR=0x1E (ECP-RLE) NSR=0x1F (ECP-RLE-ID)
HOST TIMEOUT HOST RESPONDED OVER SEC.) [COMPATIBILITY MODE]
INVALID HOST VIOLATED HANDSHAKING SEQUENCE [COMPATIBILITY MODE] NOTE: immediate termination from host generates this interrupt
NOTE: requests fail either negotiation type disabled NER. Other negotiations also fail negotiation type disabled.
IEEE 1284-Compatible Parallel Interface CD1283
Figure Interrupt Generation Logic (Continued)
A1284 signal transition from low-to-high, A1284(ODR[3]) nInit signal transition from low-to-high, nInit(ODR[2]) HstBsy signal transition HstClk signal transition from low-to-high, from low-to-high, HstBsy(ODR[1]) HstClk(ODR[0]) NOTE: Interface must Compatibility mode when ManMd (PCR[7]) ManMd affect
ManMd (PCR[7]) SigCh (PCIER[4]) A1284 signal transition from high-to-low, A1284(ZDR[3]) nInit signal transition from high low, nInit(ZDR[2]) HstBsy signal transition from high-to-low, HstBsy(ZDR[1]) HstClk signal transition from high-to-low, HstClk(ZDR[0]) address received parallel port EPPAW (PCIER[3])
SigCh (PCISR[4])
Host reversed direction interface from ECP-forward ECP-reverse driving nReverseRequest (nInit) signal low.
EPPAW (PCISR[3])
DirCh (PCISR[2])
Host changed direction interface from ECP-reverse ECPforward driving nReverseRequest (nInit) signal high.
Compatibility mode, host requested peripheral re-initialize itself (nInit went low). nInit (PCIER[0])
nInit (PCISR[0])
(PCISR[5]) NegCh
(PCISR[4]) SigCh
(PCISR[3]) EPPAW
(PCISR[2]) DirCh
(PCISR[1]) IDReq
(PCISR[0]) nInit INTEN (PFCR[4]) PPort (PIR[6])
CD1283 IEEE 1284-Compatible Parallel Interface
Figure Interrupt Generation Logic (Continued)
DMAwrerr (DER[7]) (DMAACK* DMAREQ*) DMArderr (DER[6]) (DMAACK* DMAREQ*) Bufwrerr (DER[5]) (write non-empty DMABUF) Bufrderr (DER[4]) (Read from empty DMABUF)
ErrEn (PFCR[1])
DataErr (PFSR[0])
HR1wrerr (DER[3]) (write non-empty HR1)
HR1rderr (DER[2]) (Read from empty HR1))
HR2wrerr (DER[1]) (Write non-empty HR2)
HR2rderr (DER[0]) (Read from empty HR2)
Interface forward direction, PFHR2 full, PFHR1 empty, Timeout (PFSR[5]) set.
OneChar (PFSR[1])
Stale (PFSR[3]) and, interface forward direction, FIFO empty.
DataErr (PFSR[0]) OneChar (PFSR[1]) Timeout (PFSR[5])
Timeout (PFSR[5])
IntEn (PFCR[4])
Pipeline (PIR[5])
PPort (PIR[6])
Pipeline (PIR[5])
PPireq (PIR[7]) (SVRR[3])
IEEE 1284-Compatible Parallel Interface CD1283
Figure Control Signal Generation
CD1283 AD[6:0]
ADDRESS
ADDRESS DECODE LOGIC
SVCACKP* DGRANT* DB[7:0] DATA
CONTROL
R/W*
direction change (DirCh) interrupt occurs when remote master reversed interface from forward reverse reverse forward. IDReq interrupt generated when remote master issues Request command during IEEE 1284 negotiations. normal response local send string after reversing direction data pipeline setting DMAdir `1'. vectored interrupts required system, then LIVR must initialized local CPU. upper five bits defined local value appropriate system design. lower three bits should initialized zero during programming LIVR, however they `don't cares' masked PIVR provide vector indicating source, type request from parallel channel. Access parallel channel LIVR made first setting `x'00', making Channel Zero register accessible. Since LIVR read/write register, local read time. When read during normal read cycle, upper bits return original value loaded CPU. three least-significant bits always ready back current service-request status parallel port interrupt progress; otherwise they read back `0'. encoding three least-significant bits LIVR during service acknowledge cycle indicates which functional blocks parallel channel requesting service shown following table. Table LIVR[2:0] Encoding
Requestor Channel control state machine Data pipeline Both
CD1283 IEEE 1284-Compatible Parallel Interface
5.3.1
Hardware-Activated Acknowledge
When conditions within parallel channel require attention, request made through SVCREQP* output. system interrupt driven, this output connected interruptgeneration circuitry. hardware-activated service-acknowledge system, responds request activating SVCACKP* input along with DGRANT* DS*; input used must remain inactive (high). CD1283 responds SVCACKP* cycle driving contents PIVR onto data with IT2-IT0 encoded shown Table SVCACKP* cycle also places device correct context service parallel channel request. vector supplied PIVR indicates which block parallel channel requested service; cause request indicated status request registers each; PCISR channel control state machine block and/or PFSR data pipeline block. cycle that activates SVCACKP* input also removes active SVCREQP* output. request output remains inactive until after terminates acknowledge routine write EOSRR. This dummy operation data written `don't care'. purpose write clear internal logic current request context allow generate another request when required. Until this write occurs, further service requests made from parallel channel. When detects write EOSRR, clears PIVR bits preparation next service-request cycle.
5.3.2
Software-Activated Acknowledge
During normal read cycle, LIVR always reads back with lower bits, indicating current service-request status device. Thus, Poll-mode system, this register used conjunction with SVRR determine service request needs pending and, which possible sources active. (SVRR[3]), least request conditions true subsequent read LIVR indicates source. scan just SVRR allows polling routine perform only read cycle determine parallel request pending. SVRR indicates active parallel channel service request, software initiate appropriate service routine that reads determine source parallel port request. PPort Pipeline bits indicate block requesting service. Once satisfies request needs parallel channel, must toggle IntEn (PFCR[4]) clear PIR. Toggling IntEn clears PPireq, PPort, Pipeline bits (PIR[7:5]). This action also informs clear PIVR remove external request. PPireq cleared time once enters service routine. system design requires that request removed quickly, this procedure performed beginning polled service routine. After interrupt source determined, clear toggle IntEn, then automatically cleared.
Parallel Port FIFO Data Pipeline
parallel port within CD1283 implements modes defined `slave' (peripheral) side IEEE 1284 Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers. This specification defines four methods performing bidirectional data transfers between computer system peripheral device, addition
IEEE 1284-Compatible Parallel Interface CD1283
generally accepted unidirectional Centronics-compatible mode. These modes include Compatibility mode, Reverse-Nibble mode, Reverse-Byte mode, (Extended Capabilities port) with without (run-length encoding, (Enhanced Parallel port). IEEE 1284-compliant parallel port consists major functional blocks:
data pipeline that moves data between parallel port includes FIFO,
holding registers, control, interrupt control logic.
channel control state machine performs control handshake generation
parallel port interface side device.
5.4.1
IEEE Standard 1284 Protocols
following sections discuss data movement within pipeline various IEEE 1284 operating modes. complete description these modes, refer IEEE 1284 specification; beyond scope this data book relate complete information specification. copy IEEE 1284-1994 obtained from: IEEE Standards Department Hoes Lane P.O. 1331 Piscataway, 08855-1331
5.4.2
Interface
transfers preferred means transferring data to/from FIFO. However, also possible transfer data to/from data pipeline reading writing holding registers directly through PIO. request acknowledge handshake signals support transfers to/from 16-bit-wide DMABUF register. direction transfer determined DMAdir (PFCR[5]). transmit direction, with DMAbufWe (PFCR[0]), write bytes time directly DMABUF register. However, most applications concerned with speed parallel port reverse direction require 16-bit writes FIFO. must avoid writing these registers when they already full reading from them they empty. status bits HRSR indicate holding registers buffer full empty. When writing block data CD1283 (with DMAbufWe `1'), determine much data FIFO accommodate reading PFQR. Should data become `trapped' DMABUF register receive direction because failure external controller because external buffer area full, either remain until transfer resumed read data directly from buffer. Note: buffer only read when DMAREQ* active because data moved into DMABUF register until DMAREQ* activated threshold logic timeout condition. Once request initiated CD1283, maintained until last data transfer FIFO accommodate occurs, either clears DMAen clears FIFO datatransfer logic setting FIFOres. transmit direction, request removed CD1283 when determines that FIFO nearly full. RLEen set, pipeline does fully drain into FIFO, logic does factor that into decision conclude transfer.)
CD1283 IEEE 1284-Compatible Parallel Interface
receive direction, request removed when there least more bytes available transfer tagged byte moved into data pipeline. latter case, interrupt generated (IntEn must true) remove tagged data from pipeline. quantity data transferred within single request significantly exceed capacity FIFO RLEen set, parallel port mode, compressed data being transferred. This because FIFO always stores data compressed form. Since other modes support compression, should only RLEen when parallel port interface mode.
5.4.3
Parallel Port FIFO
CD1283 dedicated 64-byte FIFO with counters maintain fill/empty pointer addresses, logic manage data transfers, automatic handshake, status interrupts CPU. simple register interface provides control over setting direction pipeline, initializing/resetting pointers, setting threshold, FIFO management logic responds data-transfer requests from dedicated IEEE 1284 parallel port state machine. Byte-alignment issues transfers to/from FIFO avoided having FIFO byte-oriented with 2-byte word packing/unpacking occurring between DMABUF register PFHR1 PFHR2. order byte transfers to/from buffer controlled BYTESWAP input. BYTESWAP high, upper byte (bits 15:8) transfers first. BYTESWAP low, lower byte (bits 7:0) transfers first. Data transfers to/from initiated request whenever quantity data space FIFO equals exceeds threshold value stored PFTR. request deasserted during cycle determined logic last because filling/emptying FIFO presence tagged data receive pipeline.
5.4.4
Receive Direction
receive direction (DMAdir first bytes data placed into FIFO parallel port immediately moved into data pipeline, PFHR1 PFHR2 (Figure page 37). This done part make tagged status data visible pipeline control logic. RLEen `0', tagged data from FIFO must move through pipeline. However, tagged data cannot transferred transfer from DMABUF register. Therefore, presence tagged data pipeline causes interrupt CPU. must then examine HRSR determine pipeline status. there tagged data holding registers, must read that register empty clear tag. more data available FIFO, data immediately moves forward fill pipeline. FIFO empty, pipeline does move emptied PFHR2 PFHR1 full, data PFHR1 moves forward PFHR2 only FIFO empty. pipeline logic keeps pipeline full receive direction. value threshold register tested against quantity data FIFO. Therefore, number characters equal PFTR-threshold value plus must arrive before request made remove data.
IEEE 1284-Compatible Parallel Interface CD1283
5.4.5
Receiving Compressed Data
compressed data sequences that consist tagged count followed compressed data character, stored FIFO compressed form. data moved from FIFO into data pipeline, inspected. tagged data count (HostAck signal high) RLEen true, count loaded into RLCR instead PFHR1; next data character loaded into PFHR1. Decompression occurs holding compressed character PFHR1 copies character shifted forward into PFHR2. each copy character shifted, RLCR value decrements. When RLCR reached zero, hold PFHR1 released shift forward pipeline ordinary data. Tagged data from FIFO recognized mode address shifts into pipeline where causes interrupt remove tagged data from pipeline. RLEen `0', tagged data from FIFO shifted into pipeline produces interrupts. immediate termination occurs between reception count corresponding data, then count stored RLCR next data byte received mode uncompressed into FIFO (based values RLCR provided RLEen still set). next byte received mode count, then that value overwrites value RLCR.
5.4.6
Stale Data (Stale, OneChar, Timeout Status Bits)
Data transfers also initiated stale data timer. This timer reloaded with value SDTPR restarts each time data placed into FIFO from parallel port. When timer reaches zero, status indication stale (PFSR[2]) true unless StaleOff (PACR[5]) true. StaleOff keeps stale status false, even though SDTCR counter value zero. Should stale status become true with least characters data available, request made transfer data. stale status true there exactly character available, OneChar status (PFSR[1]) interrupt generated transfer single residual character. PFSR indicates Stale, OneChar, FFempty conditions. HRSR shows that PFHR2 contains final character. number bytes cannot transferred DMA. transfer completes with byte data remaining, data held pending arrival additional data expiration stale data timer. OneChar status latched true when FIFO buffer empty, there character pipeline PFHR2. While OneChar status true, further pipeline operations inhibited. additional data arrives FIFO, remains there until CPU: services interrupt caused OneChar status, reads data character from PFHR2. data arrived since OneChar status latched, FFempty will false. When reads single character from PFHR2, newly arrived data FIFO immediately moves forward into pipeline transfer begin conditions warrant. Another latched status condition associated with stale data timer Timeout status (PFSR[5]). Timeout reset FIFOres (PFCR[7]) ClrTO (PACR[3]). Timeout, OneChar, DataErr pipeline interrupt conditions and, enabled, generate interrupt. receive direction, Timeout condition armed when Stale ClrTO FIFOres also
CD1283 IEEE 1284-Compatible Parallel Interface
`0'. When Stale becomes `1', timeout triggered, until transfer complete, FIFO empty, there more than character left pipeline. clear timeout condition, ClrTO bit. reenable timeout function, clear ClrTO. timeout write `01h' directly SDTCR. timer expires before data arrives, interrupt generated timeout condition. data arrives before timer expires, interrupt delays until data becomes stale.
5.4.7
Note:
Transmit Direction
transmit direction, pipeline behaves ways depending state RLEen control bit. RLEen should only after parallel port mode, otherwise compression data occurs, cannot supported data transfers parallel port. RLEen `0,' data written DMABUF register (DMAen true) write (DMAbufWe true) will moved through PFHR1 PFHR2 immediately transferred into FIFO space available). RLEen `1,' run-length encoding enabled comparators among pipeline stages recognize repeated strings characters compress them (Figure page 38). allow comparator-based logic work, pipeline registers, PFHR1 PFHR2, must kept full. comparator determines characters PFHR1 PFHR2 identical. Another comparator determines next character coming from DMABUF register character PFHR1 identical. Compression begins when pipeline full (immediately after write buffer) both comparators show identical characters their pipeline stages. This starts compression process character PFHR1 character buffer shifted forward. (same) character PFHR2 loaded into FIFO, rather RLCR increments `1.' long identical additional characters loaded into buffer, RLCR value continues increment data PFHR2 moved into FIFO. When repeated sequence finally broken RLCR count reaches 127, RLCR value transfers into FIFO, RLCR zeroes, character PFHR2 transfers into FIFO. Compression resumes when both comparators again indicate presence string least three identical characters. During intervals between transfers, last data characters held PFHR1 PFHR2. After entire block transfer complete, must either force RLEen ensure that both DMAen DMAbufWe `0'. When either these conditions true, pipeline released data held PFHR1 PFHR2 transfers into FIFO. timeout interrupt used general timer interrupt transmit direction. Unlike receive scenario, when DMAdir true, Timeout status immediately when timeout triggered `0'-to-`1' transition Stale. timeout interrupt, must load desired time delay directly into SDTCR. When timer expires, Stale becomes true timeout interrupt activated.
5.5.1
Parallel Port Overview
Terminology
This document uses terms `master' `slave' IEEE-1284-specification terms `host' `peripheral', which describe sides parallel port interface.
IEEE 1284-Compatible Parallel Interface CD1283
5.5.2
Signal Names
IEEE-1284 specification uses different names nine control signals, depending current mode operation (Table page 31). CD1283 uses fixed names each pins. names were selected represent most commonly used names amongst various protocols. CD1283 device operates slave only. There four input-control signals driven master-side device, five output-control signals driven slave-side device. Parallel Data (PD[7:0]) bidirectional.
5.5.3
State Machine
parallel port controlled large synchronous state machine. state machine based IEEE 1284-1994 conforms functional modes (except extensibility link options, which currently defined, print date this document).
5.5.4
Configuration
power-up, interface begins Compatibility mode (Centronics mode) ready accept data from master. Only ETxfr (PCR[5]) required allow transfers Compatibility mode. PCR[7:5] enable transfers, negotiations, Manual mode.
Figure FIFO Data Path Functional Diagram Receive
(RECEIVE) PFSR BITS) PARALLEL PORT FIFO BYTES)
DMABUFH
DB[15:8]
STATUS
STATUS
DMABUFL
PFHR2
PFHR1
DB[7:0]
NOTE: Data does move from FIFO PFHR1 OneChar status true (Section 5.4.6 page 35).
5.5.5
Interrupts
Interrupts enabled PCIER interrupt status read PCISR. These registers have same format.
CD1283 IEEE 1284-Compatible Parallel Interface
5.5.6
Manual Mode
Manual mode allows direct control five output control signals bus. intended data transfers, rather advanced diagnostics. Enter Manual mode setting ManMd (PCR[7]) when interface Compatibility mode. MMDir (PCR[1]) sets direction bus: input; output. When MMDir `1', data comes from MDR. ManOE controls tristate buffer bus: floating; driving. When MMDir `0', ManOE ignored, PD[7:0] inputs, data read MDR.
5.5.7
Control Signals
Output signals controlled OVR. degree control depends current mode. Manual mode, five signals under user control. Compatible modes, only three signals available, others state machine. IVR, ZDR, ODR, monitor four input signals. These four registers have common format. always shows values four input pins. allow user force interrupts specific signal transitions. Bits generate interrupt, specified signal changes from `0'. Similarly, bits generate interrupt specified signal changes from `1'. When both bits set, interrupts generated either transition. shows status signal changes according ODR. shows which signal changed. necessary user read determine signal changed.) signal change interrupt enabled with SigCh (PCIER[4]).
Figure FIFO Data Path Functional Diagram: Transmit
(TRANSMIT) PFSR
BITS) PARALLEL PORT FIFO BYTES)
DMABUFH
DB[15:8]
STATUS
STATUS
DB[7:0]
DMABUFL
PFHR2
PFHR1
IEEE 1284-Compatible Parallel Interface CD1283
5.5.8
Parallel Port Interface FIFO
DMAdir indicates current direction out) transfers between FIFO logic. recent negotiation, this differ from current parallel-port interface direction. must change direction after receives interrupt showing direction change. FIFOlock (PACR[4]) stops pipeline. This useful diagnostics. FIFOlock also used modes stop data transfers forward direction.
5.5.9
IEEE 1284-Protocol Negotiations
IEEE 1284 protocol negotiations initiated master side. role CD1283 accept reject attempted negotiation. contains bits individually enable specific IEEE 1284 modes. various IEEE 1284 modes require negotiations parallel interface before they entered. Until successful negotiation sequence complete, interface remains Compatibility mode. These negotiations occur stages; both stages occur automatically after device commanded begin negotiation procedure particular mode. first stage determines slave IEEE 1284-compatible. Once determined, interface continues process determine mode requested supported. result requested negotiation appears NSR. negotiations occur, slave must enable E1284 (PCR[6]). Data transfers require that ETxfr (PCR[5]) set; negotiations occur without data transfer enabled.
Negotiation Status Register
After IEEE-1284 negotiation termination, current protocol status read NSR. NegOK NegFl (bits 7:6) indicate successful failed attempts. Invalid (bit indicates that mode terminated from invalid state. Termination from valid states reported successful with NegOK. 4-bit code displayed lower portion indicate results successful negotiation. 4-bit code also indicates mode that interface when invalid termination detected, well failed negotiation. Interrupts indicating successful negotiation into reverse mode should prompt load reverse data into FIFO.
Special Command Register
bits cause actions parallel port. SetPs ClrPs (bits 3:2) control data movement into CD1283 from remote master. Compatibility mode, this function posts error status remote. Errors only presented master slave during active BUSY period. SetPs causes CD1283 stop transfers asynchronously asserting BUSY signal. protect against possibility data loss, more byte strobed into CD1283 after BUSY goes active setting SetPs. When error status delivered, ClrPs restores parallel interface normal running state. EPIrq sends interrupt pulse mode. RevRq indicates that data available reverse transfer either Compatibility mode. These operations further described relevant protocol sections.
CD1283 IEEE 1284-Compatible Parallel Interface
5.5.10
Data Transfers
Compatibility mode, incoming HstClk (STROBE*) pulses activate PerBsy (BUSY), data PD[7:0] held latches. PerBsy protects data latches signalling master ready more transfers. After HstClk pulse ends, pulse sent PerClk (ACK*) acknowledge receipt data into holding latches. After data moves from latches FIFO, PerBsy goes signal readiness next character. other data transfer modes require IEEE-1284 negotiations.
5.5.11
Compatibility Mode Status
IEEE 1284 specification requires that three Compatibility mode status lines (SELECT, FAULT*, PError) must asserted unless PerBsy (BUSY) high. PerBsy only activated response received character, must remain high until status condition (for example, paper out) changes. send these status signals master device, SetPs (SCR[2]) appropriate each status signals. SetPs activates PerBsy, which remains active until ClrPs (SCR[3]) set. data lost this operation.
5.6.1
IEEE 1284 Parallel Protocol Support
Compatibility Mode
Compatibility mode provides backward compatibility with Centronics PC-compatible printer interfaces. When host parallel port Compatibility mode (with data transfer progress), host initiate data transfers Compatibility mode initiate negotiations operating mode. Only Busy-while-Strobe Ack-in-Busy timing supported Compatibility mode. Busy-afterStrobe, Ack-after-Busy, Ack-while-Busy timings supported.
Figure Supported Compatibility Mode Timing
nStrobe nAck BUSY
5.6.2
Reverse-Nibble Reverse-Byte Modes
These modes support reverse transfers only, from slave master. Reverse-Nibble mode enabled with NER[0]; Reverse-Byte mode enabled with NER[1]. Reverse-Nibble mode sends bits time over four peripheral status lines. With software drivers advantage this scheme that unidirectional parallel port used bidirectional data transfers. Reverse-Byte mode requires bidirectional buffers hardware, allows substantially faster transfers because moves byte time.
IEEE 1284-Compatible Parallel Interface CD1283
There mechanism Compatibility mode slave indicate that data available reverse transfers. master must poll slave negotiating into reverse mode examining nDatAv signal. RevRq (SCR[0]) instructs CD1283 post availability data master through nDatAv signal.
5.6.3
Request
request enabled with combination NER[6] four other transfer mode bits. requests made conjunction with ECP, ECP/RLE, Reverse-Byte, Reverse-Nibble modes; there request function defined mode. CD1283 accept request mode enabled manage transfers. IDReq when request received enabled mode.
5.6.4
Mode
mode allows bidirectional transfers supports RLE-compression scheme. ability expand data required IEEE-1284, ECP-compliant devices, ability compress data optional. CD1283 handles both expansion compression data path section. parallel port simply passes inverse command signal to/from FIFO ninth FIFO. mode enabled NER[2]. mode enabling requires both bits handshake identical both modes. control signals, HstBsy PerBsy forward reverse directions, respectively), indicate command address options. HstBsy/PerBsy low, upper byte examined: indicates interpret lower bits address; indicates lower bits repeat count. This count shows number times consecutively repeat that next data character datastream. master device responsible determining direction transfer. slave request direction change, master actually changes direction. mode always begins forward direction, from master slave. sets RevRq (SCR[0]) request reverse transfers. Once master changes direction, RevRq automatically cleared DirCh interrupt status appears PCISR enabled PCIER). master device switches direction interface forward transfers when slave indicates more data available.
5.6.5
Mode
Data transfers pipeline FIFO. Address transfers handled out-of-band, FIFO stream. When slave receives address write command, deposits address into asserts EPPAW interrupt request. When slave receives read address command, contents returned.
Protocol Timing
IEEE-1284 specification timing parameter, specifies minimum pulse width minimum setup time must loaded with number system clock ticks equivalent shown Table
CD1283 IEEE 1284-Compatible Parallel Interface
Table
System Clock Setup
Freq. (MHz) Time/Tic (ns) 62.5 Value Width
General-Purpose Port
CD1283 provides 8-bit general-purpose port (GP[7:0]) used control give status external functions. Each eight signals individually programmable direction, port comprised number inputs outputs. Each port signal implemented with standard, bidirectional HCMOS fully compatible. port controlled through internal registers GPDIR GPIO. Each GPDIR sets direction corresponding GPIO; sets signal output, sets input. When writing GPIO, only bits programmed outputs affected contents data bus. When reading GPIO, bits programmed inputs reflect true state condition external pin; bits programmed outputs reflect state last value written register current state output pins. reset, bits GPIO cleared signals programmed inputs. Note: Interrupts generated signal changes within General-Purpose port; must periodically poll GPIO detect changes external conditions. Therefore, necessary detect changes, port with signals that change with low-duty cycles.
Parallel Port Interface
CD1283 parallel port signals implemented with Level-2 characteristics, defined IEEE 1284-1994 specification with exception transient protection. such, port directly connected interface cable with addition external components. components consist passive pull-up resistors, series impedance matching resistors, clipping diodes. Additional noise filtering required system. Figure illustrates typical interface with components listed above. Some system designs require buffers between CD1283 cable. Systems that require drive cables longer than specified maximum those that need protect CD1283 require inexpensive buffers between cable. device provides signal outputs, PDBEN EBDIR, connecting controlling buffers (such 74AS245 equivalent). These signals allow direct control buffer. However, addition XNOR gate provides both enable control signal signal select direction buffer. PDBEN EBDIR outputs from control state machine that indicate current state (see Figure page 44).
IEEE 1284-Compatible Parallel Interface CD1283
Figure Cable Connection
CD1283
BIDIRECTIONAL SIGNAL LINE
OUTPUT SIGNAL LINE
INPUT SIGNAL LINE
TRANSIENT PROTECTION
Caution:
Transient protection implemented inside CD1283 device, therefore transient voltages cause damage. Laboratory testing shown that this type protection necessary under normal conditions. However, damage occur under harsh conditions when subjected unusual abuse. Also note, protection circuit shown here cause powered-up host supply power (Vcc) peripheral powered this concern, then another protection circuit must designed.
CABLE CONNECTOR
CD1283 IEEE 1284-Compatible Parallel Interface
Figure External Buffer Control
CD1283
74AS245
CABLE
PDBEN
EBDIR
Impedance matching protection circuitry (Figure required 74AS245.
5.10
Hardware Configurations
simplicity interface CD1283 allows device designed into systems that employ popular microprocessors such Intel 80x86 family (8086, 80286, 80386, Motorola family (68000, 68010, 68020, on). example CD1283 configuration laser-printer application shown Figure This example provides parallel interface, well general-purpose static control/status.
Figure Sample System Block Diagram
ADDRESS CONTROL PROCESSOR
DATA
GENERAL-PURPOSE I/O: INTERNAL STATUS CONTROL
CD1283
IEEE 1284 PARALLEL CHANNEL
IEEE 1284-Compatible Parallel Interface CD1283
5.10.1
Interfacing Intel Microprocessor-Based System
With very little additional logic, CD1283 interface system based processor Intel 80x86 family. Figure shows generalized view I/O-mapped interface with 80286-based system. provide proper strobes controls, IOR* IOW* control strobes synthesize R/W* signals. DTACK* input wait-state-generation logic that holds processor necessary) until CD1283 completes request.
Figure Intel 80x86 Family Interface
80x86 SYSTEM
CD1283
ADDRESS
A[23:7]
ADDRESS DECODE LOGIC SVCACKP*
A[6:0] A[6:0] DATA IOR* IOW* R/W* DB[15:0]
INPUTS
SVCREQP*
CONTROL
DMAREQ* DMAACK*
READY
WAIT-STATE GENERATION LOGIC
DTACK*
CD1283 IEEE 1284-Compatible Parallel Interface
5.10.2
Interfacing Motorola Microprocessor-Based System
Interfacing Motorola 68000 family device relatively simple. timing interface signal definitions closely match those 68000 microprocessor, which allows direct connection. With later versions (68020, 68030), some additional logic required generate DSACK0* DSACK1* functions that replace DTACK* earlier devices. Figure shows generalized interface 68020 device.
Figure Motorola 68020 Interface
68020 SYSTEM FC[2:0] A[31:9] ADDRESS SVCACKP* ADDRESS DECODE LOGIC CD1283
A[8:2] DATA R/W*
A[6:0] DB[15:0] R/W*
IPL[2:0]
PRIORITY ENCODING
SVCREQP*
CONTROL
DMAREQ* DMAACK*
DSACK1* DSACK0*
TRANSFER CONTROL
DTACK*
IEEE 1284-Compatible Parallel Interface CD1283
Programming
Overview
shown register summary tables Chapter 4.0, CD1283 local interface consists large array registers. These registers control aspects device behavior. Most registers only modified once, during initialization, rarely modified during normal operation. This chapter discusses these aspects, well methods interacting with CD1283 parallelchannel service requirements.
Initialization
properly power-up CD1283, several procedures must completed. These include device initialization, programming global functions, setting port parameters. most cases, initialization routines only executed once during overall system boot-up. Section 6.2.1 details these steps (Figure page flow-chart step outline).
6.2.1
Device Reset
procedures that perform chip reset normally executed after power-up, system-wide reset. hardware reset control signal, RESET* causes CD1284 perform internal initialization. desired, driver software issue full chip reset before chip initialization begins. accomplish this, perform following steps. Wait contain `0x00'. contents must before reset command issued. This required ensure that device ready accept command. Since this probably first command written CD1283 after power-on initialization, likely `0', recommended always check before writing command. `0x02'. This only time during normal operation that value other than `0x00'. Again, this required maintain binary compatibility with CD1284. Write hexadecimal (x'81) RCR. This command causes CD1283 perform global reset. causes internal RISC processor begin execution from power-up reset location. results same RESET* input activated. internal interface registers cleared, FIFO flushed, channel operations disabled. Wait firmware revision code written into GFRCR. Internal firmware uses this operation flag completion reset procedure. After reset issued, GFRCR first registers cleared last before normal runtime code execution begins. initialization routine must wait this register become non-zero before begins other programming CD1284 registers. sufficiently fast, could begin testing GFRCR before clears assumption could made that CD1284 completed internal initialization when, fact, even started. avoid this error, should look GFRCR change `0'. should then look current revision code. Alternatively, clear GFRCR just prior issuing global reset command then poll correct revision code. This
CD1283 IEEE 1284-Compatible Parallel Interface
useful slow systems that cannot guarantee that check register after cleared before loaded with revision code. This procedure also used part diagnostic test suite. device completes internal initialization within µsec. timer (software hardware) detects when operation completed within that time cues device functional. Figure Flow Diagram CD1283 Master Initialization Sequence
CLEAR GFRCR
ISSUE RESET COMMAND
GFRCR
GFRCR
REVISION CODE REVISION DEVICE FUTURE REVISIONS, NECESSARY, WILL INCREMENT THIS ONE; EXAMPLE, REVISION WOULD ETC.
CONTINUE INIT PROCESS
IEEE 1284-Compatible Parallel Interface CD1283
following section programming code shows typical initialization sequence preparing parallel channel Compatibility mode data reception enabling negotiation into modes, except EPP. This procedure also used part diagnostic test suite. device will complete internal initialization within µsec. Therefore, timer (software hardware) used detect that operation does complete within this time that device functional.
Initialization parallel channel consists setting SPR, selecting modes that will supported during negotiation, stale data timeout value, initalizing FIFO, source interrupts that will accepted other operational functions. par_init() First, issue chip reset command outportb(GFRCR, 0x00); Clear GFRCR outportb(AER, 0x02); must equal access RCR*/ while (inportb(RCR) 0x00) Wait clear outportb(RCR, 0x81); while (inportb(GFRCR) 0x00);/* Wait GFRCR cleaared while (inportb(GFRCR) 0x25);/* Wait GFRCR Start initializing parallel channel outportb(AER, 0x00); Access Enable Register outportb(SPR, 0x0d); Assume 25MHz clock, short pulse value outportb(NER, 0x4f); Support modes except outportb(OVR, 0x18); Start Compatibility mode, status signals: PError SELCT nFault outportb(PCIER, 0x37); Enable interrupts except Address Write outportb(PCR, 0x60); Enable 1284 negotiations transfers Next, pipeline control registers outportb(LIVR, 0x00); outportb(PFCR, 0xd8); input, reset*/ FIFO. reset, assumed that starting outportb(PFCR, 0x58); outportb(PFTR, 0x20); outportb(SDTPR, 0x64); outportb(PACR, 0x02); stale data timeout period 10ms asynchronous mode direction will input. Remove Reset threshold receive (burst Initialize interrupt vector Enable pipeline DMA, direction enable interrupts (but error ints)
6.2.2
Service Acknowledge Handling
Service request acknowledge processing, well request acknowledge processing, performed internal MPU. important take behavior into account interrupts used. There different variations where service requests serviced. variation uses SVCACKP*, other does not. SVCACKP* signal activated through input instruction then device will return value LIVR data bus. This used vector service routine used switch instruction jump correct routine.
CD1283 IEEE 1284-Compatible Parallel Interface
When SVCACK* activated, SVCREQP* deactivated. SVCACKP* signal activated, then service request must removed clearing PpIreq (PIR[7]), source interrupt must determined reading LIVR, PIVR, PIR. Regardless variation performed, IntEn (PFCR[4]) must toggled service routine inform device that service routine terminated.
service_par( char
livr_val;
(inportb(SVRR 0x08)) check active service request livr_val inportb(LIVR) 0x07; switch (livr_val) case just parallel channel state-machine request active service_par_chan(); break; case just data path pipeline request active service_pipeline(); break; case both requests active service_par_chan(); service_pipeline(); break; default: break; outportb(PFCR, inportb(PFCR 0xEF);/* terminate service ack. sequence outportb(PFCR, inportb(PFCR 0x10);/* toggling IntEn PFCR return(0);
IEEE 1284-Compatible Parallel Interface CD1283
Figure Polling Flow Chart
NOTE: necessary poll PFSR requests enabled. With requests enabled, DMAREQ (SVRR[7]) polled determine when FIFO threshold exceeded. requests disabled, PFSR register must polled determine when move data from FIFO. requests enabled, data must read through DMABUF register; this requires 16-bit data bus.
HARDWARE RESET
SOFTWARE RESET
INITIALIZE DEVICE POLL DEVICE AGAIN POLL DEVICE AGAIN
SERVICE REQUEST
DMAREQ
TEST SVRR TEST PPort
FULL EMPTY DATA TEST DataErr TEST HRSR TEST PFSR
Pipeline
TEST PFSR
DirCh CHANGE DIRECTION RETURN HOST RESET PRINTER
TEST PCISR
SigCh
NegCh TEST
SERVICE NEGOTIATION CHANGE
SERVICE SIGNAL CHANGE INTERRUPT
SERVICE ERROR INTERRUPT
SERVICE APPROPRIATE HOLDING REGISTER
SVC. FIFO
Table
ASCII Code Tables
Hexadecimal Character (Sheet
CD1283 IEEE 1284-Compatible Parallel Interface
Table
Hexadecimal Character (Sheet
Table
Decimal Character
IEEE 1284-Compatible Parallel Interface CD1283
Detailed Register Descriptions
This section presents detailed description each register. Registers have formats: full eight bits, where entire content defines single function; register collection bits, grouped singly multiples, defining function. second case, descriptions divide register into component parts describe bits individually. registers presented same order outlined Chapter 4.0. Bits defined should modified and, values other than read, program execution should affected software compatibility with future revisions will uncertain.
7.1.1
Global Registers
Access Enable Register
8-Bit Address: Default Value:
Register Name: Register Description: Access Enable Access:
provides binary compatibility with CD1284. Users must program this register with least-significant bits access parallel channel; however, perform device reset through RCR, must 02h. contents upper bits should ignored when read.
7.1.2
Global Firmware Revision Code Register
8-Bit Address: Default Value:
Register Name: GFRCR Register Description: Global Firmware Revision Code Access:
Firmware Revision Code
GFRCR serves purposes CD1283. First, displays revision number firmware device. When revision CD1283 required, revision number firmware increments one. revision code (hex) Revision device, (hex) Revision device. Secondly, this register used system programmer indication when internal processor completed reset procedures, after either power-on reset (through RESET* input) software global reset (through reset command CCR). Immediately after reset operation begins, internal clears register. When complete, CD1283 ready accept host accesses, register loaded with revision code.
CD1283 IEEE 1284-Compatible Parallel Interface
7.1.3
General-Purpose Direction Register
8-Bit Address: Default Value: Dir3 Dir2 Dir1 Dir0
Register Name: GPDIR Register Description: General-Purpose Direction Access: Dir7 Dir6 Dir5 Dir4
7.1.4
General-Purpose Register
8-Bit Address: Default Value: Data4 Data3 Data2 Data1 Data0
Register Name: GPIO Register Description: General-Purpose Access: Data7 Data6 Data5
GPDIR GPIO registers enable access control General-Purpose port. General-Purpose port provides byte-wide general purpose signals that individually direction programmable. GPIO register accesses data port pins 53-60 (G[7:0]) with Data0 accessing GP[0], corresponding GPDIR controls direction associated signal; logic programs signal output, logic programs input. When writing GPIO register, `1's `0's reflected their true states pins that programmed outputs. When reading from GPIO register, bits programmed inputs reflect true state signal condition those bits; bits programmed output will reflect previously state.
7.1.5
Parallel Interrupt Register
8-Bit Address: Default Value:
Register Name: Register Description: Parallel Interrupt Access: PPireq PPort Pipeline
indicates source service requests being presented parallel channel, either from parallel port from pipeline.
IEEE 1284-Compatible Parallel Interface CD1283
Description PPireq: Internal logic sets this generate external service request output. direct reflection inverse state SVCREQP* pin; active-high output latch that drives SVCREQP* pin. This scanned host detect active service request. This cleared internal logic beginning hardware service-acknowledge cycle toggling InTen (PFCR[4]). Clearing automatically deactivates SVCREQP* output clears (SVRR[3]). PPort Pipeline: These bits indicate which functional blocks parallel port requesting service. When PPort set, indicates that parallel channel control state machine cause request; when Pipeline set, indicates that data pipeline requesting service. both bits set, indicates that both blocks requesting service simultaneously. Reserved: remainder bits always return when read host should modified.
7.1.6
Prescaler Period Register
8-Bit Address: Default Value:
Register Name: Register Description: Prescale Period Access:
Binary Value
sets divisor used generate time period CD1283 timer operations. value between (x'FF). clocked system clock prescaled (divided) 512. best device operation, value loaded into should less than x'30.
7.1.7
Service Request Register
8-Bit Address: Default Value:
Register Name: SVRR Register Description: Service Request Access: Read only DMAREQ
SVRR reflects inverse state service request pins (DMAREQ* SVCREQP*). primary polled systems, allows system software determine what, any, service requests pending
Description Request Status: When this `1', indicates that request pending. These bits used don't cares. Service Request Parallel: When this `1', indicates that request pending. These bits used don't cares.
CD1283 IEEE 1284-Compatible Parallel Interface
Virtual Registers
CD1283 operational contexts: normal context that allows host access most registers channel, service-acknowledge context, allowing host access some registers specific channel requesting service. This special registers called `virtual' because they only available host access valid during this service-acknowledge context; other times, their contents will undefined must written host software. Virtual registers context switching allows CD1283 maintain channelspecific information. host need make changes chip registers access registers pertinent parallel channel. service-acknowledge context entered ways: either through activation SVCACKP* input (hardware activated), through host software when contents copied into host software during Poll-mode Acknowledge cycle (softwareactivated). Chapter discussion differences between these modes.
7.2.1
End-of-Service Request Register
8-Bit Address: Default Value:
Register Name: EOSRR Register Description: End-of-Service Request Access: Write only
EOSRR `dummy' location used signal hardware-activated serviceacknowledge procedure, invoked activation SVCACKP*. data pattern written `don't care' value. Writing this location causes CD1283 perform internal switch service-acknowledge context. This register used only during hardware-activated service acknowledge must written during Poll-mode operation.
7.2.2
Parallel Interrupt Vector Register
8-Bit Address: Default Value:
Register Name: PIVR Register Description: Parallel Interrupt Vector Access: Read only
User-Defined Upper Bits LIVR
value this register placed data bus, DB[7:0], when SVCACKP* activated response active SVCREQP*. Section 7.3.5 page more details LIVR. Table PIVR[2:0] Encoding
Description active interrupt.
IEEE 1284-Compatible Parallel Interface CD1283
Table PIVR[2:0] Encoding
parallel channel state machine requests service. parallel channel data pipeline requests service. Both parallel port state machine parallel port data pipeline request service. Invalid. Invalid. Description
7.3.1
Parallel Pipeline Registers
Data Error Register
8-Bit Address: Default Value: Bufwrerr Bufrderr HR1wrerr HR1rderr HR2wrerr HR2rderr
Register Name: Register Description: Data Error Access: Read only DMAwrerr DMArderr
bits this read-only register indicate read/write errors involving Buffer register Data Pipeline registers. DataErr PFSR logical these eight Error Status bits. read this register effect error status. write this register clears bits; they individually writable user. Host software should clear this register (write x'00) after completing error service-acknowledge procedure. This provided primarily driver software development. Under normal circumstances, data errors should never occur. This register cleared during device reset.
Description Write Error: This control logic written buffer when already contains data. indicates that invalid transfer cycle occurred DMAACK* without corresponding DMAREQ*). Read Error: with this indicates that logic performed read from Buffer when there data indicates that invalid transfer cycle occurred. Buffer Write Error: This indicates that system write buffer occurred while still contained data. Buffer Read Error: This indicates that system read from buffer occurred while empty.
Holding Register Write Error: This indicates that system write PFHR1 (Parallel FIFO Holding register occurred while still contained data.
Holding Register Read Error: This indicates that system read from PFHR1 occurred while empty. Holding Register Write Error: This indicates that system write PFHR2 (Parallel FIFO Holding register occurred while still contained data. Holding Register Read Error: This indicates that system read from PFHR2 occurred while empty.
CD1283 IEEE 1284-Compatible Parallel Interface
7.3.2
Buffer Data Register
8-Bit Address: Default Value:
Register Name: DMABUF Register Description: Buffer Data high Access:
Buffer Data High Byte
Register Name: DMABUF Register Description: Buffer Data Access:
8-Bit Address: Default Value:
Buffer Data Byte
This 16-bit data register used buffer data transfers from CD1283. Under normal operating conditions, this register only accessed during data transfer cycle. DMAbufWe (PFCR0) DMAdir (PFCR[5]) `1', 16-bit data transferred from host FIFO directly writing DMABUF. data automatically moves forward into FIFO through Data Pipeline Holding registers. user must ensure that FIFO sufficient free space accept data before writing into DMABUF. BYTESWAP determines order byte transfer from this register into data pipeline. BYTESWAP `1', data transferred DB[15:8] first byte transferred into data pipeline DB[7:0] transferred second. BYTESWAP this sequence reversed. same applies during data read during transfers: BYTESWAP `1', data from data pipeline moves upper byte DMABUF, next byte moves into lower byte. Again, BYTESWAP `0', this sequence reversed. These resisters read through acknowledge cycles. However, DMABUF registers only read when DMAREQ* signal active. DMAREQ* inactive, DMABUF registers will empty. DMAfull (HRSR[3]) indicates DMABUF register empty when DMAREQ* inactive.
7.3.3
Holding Register Status Register
8-Bit Address: Default Value: HR2tag DMAfull DMAmpty DMAact Ctnot0
Register Name: HRSR Register Description: Holding Status Access: Read only HR1full HR1tag HR2full
HRSR read-only indicates current data pipeline status This register directly particular value device reset, reflects current state bits other registers
IEEE 1284-Compatible Parallel Interface CD1283
Description HR1full HR1tag:These bits indicate status PFHR1. indicates that register contains data indicates that data tagged. Both bits simultaneously. HR2full HR2tag:These bits indicate status PFHR2. indicates that register contains data indicates that data tagged. Both bits simultaneously. DMAfull DMAmpty: These bits indicate status transfer buffer (DMA buffer). indicates that register contains data indicates that empty. DMAact: This when set, indicates that handshake active that service requested, complete (DMAREQ* active, waiting DMAACK*). Ctnot0: This indicates that counter zero, thus run-length encoding/decoding progress.
7.3.4
Host Timeout Value Register
8-Bit Address: Default Value:
Register Name: HTVR Register Description: Host Timeout Value Access: Read/Write
Host Timeout Period
HVTR holds 8-bit value used Host Timeout period. HTVR unsigned, binary value. reset state this register `0xFF'. function missing revision earlier devices on-chip timer indicate that remote host responded specified time period. Host timeout defined IEEE 1284 Specification period second. revision device adds user-programmable timer that provides timeout remote host does respond specific parallel port transactions. timer started parallel port state machine each time starts sequence requiring host response. Activation timer automatic interrupt generated local host timer expires before remote host responds. Note: Users familiar with IEEE specification note that events that start timer cause peripheral device move state where waits remote host-generated event. example, during negotiation sequence after event peripheral waits event host-generated event. host does respond moves negotiation sequence event within second, peripheral enters `host Timeout' condition. timer 14-bit counter clocked system clock (CLK) prescaled (divided) 2048. Program 8-bit Host timeout Value register (HTVR, address offset 0x'24), which then compared with most-significant bits 14-bit counter. Each time parallel port executes event requiring host response, 14-bit counter started (from 0x'00). counts until either expected event occurs count matches value HTVR. match occurs, timeout condition exists. HTVR need only loaded once, typically during device initialization. value placed HTVR yields approximate second count time, based value input CLK. example, system clock driving device MHz, HTVR should loaded with 0xC0. following equation provides example.
CD1283 IEEE 1284-Compatible Parallel Interface
25MHz 12207 2FAF16 2048
computed value rounded next largest whole value, this case `0x3000'. Load HTVR with most-significant bits this value, left-shifted places since HTVR 14-bit counter. This results value `0xC0'. MHz, value computed `0x9C' MHz, value `0x7C'; values other clocks easily computed same manner. reset, HTVR defaults value `0xFF'; this prevents extremely short Timeouts that occur register cleared device reset initialized. timeout causes negotiation status change interrupt. This status displayed 0x22 Negotiation Status Register (Host Timeout (bit code return Compatibility mode (0010) result code field). When Compatibility mode reentered, port control state machine waits locked state until signals parallel port return normal Compatibility mode conditions. debug purposes, disable host Timeout timer setting bits (Host Timer Test [1:0]). this case, Timeouts occur link hang indefinitely while waiting hostgenerated event.
7.3.5
Local Interrupt Vector Register
8-Bit Address: Default Value:
Register Name: LIVR Register Description: Local Interrupt Vector Access: User-Defined Bits
This read/write register initialized desired value and, when read normal context (that service acknowledge context), same value returned. upper bits copied into appropriate vector register, PIVR when SVCACKP* signal activated SVCREQP* active. During this hardware-activated service acknowledge read cycle, PIVR driven onto data bus, DB[7:0]. Bits come from LIVR bits supplied CD1283 (Section 7.2.2 page details). This value used vector into appropriate service routine (typical Motorola-type systems) device identifier systems with multiple, daisy-chained CD1283s. Bits ignored. Initialization this register only necessary vectored interrupts used.
Description User-Defined Interrupt Vector: Host software these five bits purpose appropriate application. some cases, these bits might define rest complete interrupt response vector (Motorolatype systems). case daisy-chain systems made multiple CD1283s, these bits used define device number chain. These bits `don't cares'.
IEEE 1284-Compatible Parallel Interface CD1283
7.3.6
Parallel Auxiliary Control Register
8-Bit Address: Default Value: FIFOlock ClearTO AsyncDMA
Register Name: PACR Register Description: Parallel Auxiliary Control Access: ShrtTen ShrtStal StaleOff
PACR provides some special functions parallel data path interrupt-generation circuitry. upper bits used change basic timing timers associated with data pipeline. disable stale data time.
Description ShrtTen: This function shortens Prescaler count cycle that generates internal 10-µs clock (based 25-MHz system clock) stale data counter. This cleared RESET*. set, 10-µs `ticks' counter will generated every CLKs; normal period `tick' every CLKs. ShrtStal: This function shortens period stale data timer. stale data timer includes divide-by-ten prescaler; setting this bypasses prescaler function, causing stale data timer count each 10-µs clock `tick'. both ShrtTen ShrtStal set, stale data timer counts every other CLK. StaleOff: When this set, masks Stale Status bit. inverse this AND'ed with stale state condition parallel channel produce stale status effect disabling OneChar Stale interrupt sources. StaleOff provided primarily test development purposes, when slow movement data into parallel port might cause Stale OneChar always appear true. FIFOlock: This causes FIFO stop accepting data from parallel channel state machine. This action makes FIFO appear full parallel port, thus causing enter `busy' state. This function primarily intended system testing cause timeout 1284 bus. Setting this Forward mode cause stall condition event because event will occur until FIFOlock cleared. mode host transfer recovery handshake sequence (from event stall) supported byte transit discarded required specification. This does provide effective means flow control host. ClearTO: Clear Timeout reset timeout status latch logic. When toggled software, timeout status PFSR cleared; left disable Timeout status function. Note that this left set, OneChar interrupt condition will never become true since there will FIFO timeout activity. Reserved: This read-only always `0'. AsyncDMA: This causes device synchronize DMAACK* signal internal clock (rising clock edge). This capability provides asynchronous interface systems that cannot meet setup times required synchronous logic. Refer Section 8.3.1 page specific timing relationships between DMAACK* when AsyncDMA enabled. Reserved: This read-only always `0'.
7.3.7
Parallel Channel Reset Register
8-Bit Address: Default Value: PChReset
Register Name: PCRR Register Description: Parallel Channel Reset Access:
CD1283 IEEE 1284-Compatible Parallel Interface
This register used issue hardware reset parallel channel
These bits used must always `0'.
Description
PChReset: When this set, asserts equivalent hardware power-on reset parallel channel, Channel host, PChReset must cleared resume normal parallel channel operation. This hardware reset affects only parallel channel effect other functions device.
7.3.8
Parallel FIFO Control Register
8-Bit Address: Default Value: IntEn RLEen setTAG ErrEn DMAbufWe
Register Name: PFCR Register Description: Parallel FIFO Control Access: FIFOres DMAen DMAdir
This register controls overall function parallel FIFO. These include resetting (flushing) FIFO, enabling transfers, enabling host interrupts, run-length encoding, host sets these bits according mode operation desired. After hard reset (either through RESET* input setting PCRR), this register cleared zeroes.
Description (Sheet FIFO Reset: This must together with correct value DMAdir properly initialize data pipeline FIFO registers data transfer when data transfer direction desired. Data remaining FIFO discarded. Enable: This must requests move data to/from FIFO. When DMAen `1', PFQR quantity value compared with PFTR user-programmed threshold value. Receive mode, threshold equalled exceeded, DMAREQ* asserted cause data transfers whole (2-byte) words from FIFO through data pipeline. Transmit mode, amount data FIFO equal less than threshold, DMAREQ* asserted cause data transfers whole (2-byte) words FIFO through data pipeline. Direction: This sets direction transfer between parallel FIFO system memory. DMAdir `1', direction transmit (system memory parallel FIFO); direction receive. desired DMAdir value must together with FIFOres when initializing FIFO logic data transfer. Once DMAdir value FIFOres complete, that DMAdir selection must maintained during other changes control bits PFCR. Interrupt Enable: This master interrupt enable parallel channel. This must interrupts generated data pipeline, parallel port, error status. Poll-mode operation, host software toggle this signal completion service-acknowledge cycle clear current status PIR, SVRR, LIVR. Toggling this updates state SVCREQP* according current state PCISR, DERR PFSR. this reason, PCISR, DERR, PFSR should read cleared beginning service routine. These registers should checked again service routine ensure that requests were skipped because edge-sensitive interrupt controller detect request that already active when program returns from service routine. Enable: This enables run-length encoding/decoding direction defined DMAdir. RLEen affects flow data through data pipeline transmit direction. Data flow into FIFO managed that PFHR1 PFHR2 kept full permit evaluation data sequences possible compression. effect that following data transfer while RLEen set, final bytes written DMABUF register kept PFHR1 PFHR2. allow these bytes moved into FIFO make room PFHR1 tagged data transfer, RLEen must both DMAen DMAbufWe must `0'.
IEEE 1284-Compatible Parallel Interface CD1283
Description (Continued) (Sheet Tag: This specifies that next character written parallel channel through PFHR1 tagged special character. This cleared write PFHR1, thus this must each time tagged character written. Error Interrupt Enable: This enables non-zero DataErr status cause interrupt IntEn also set). Buffer Write Enable: This must enable host writes DMABUF register. also enables FIFO data pipeline empty DMABUF when been written host system. this case, system will write buffer transfers, providing low-performance alternative transfers.
7.3.9
Parallel FIFO Empty Pointer Register
8-Bit Address: Default Value:
Register Name: PFEP Register Description: Parallel FIFO Empty Pointer Access:
6-Bit Binary FIFO Pointer Value
This register contains internal empty location pointer FIFO. identifies location FIFO from which next byte data will transfer from FIFO. PFEP register cleared device FIFO reset.
7.3.10
Parallel FIFO Fill Pointer Register
8-Bit Address: Default Value:
Register Name: PFFP Register Description: Parallel FIFO Fill Pointer Access:
6-Bit Binary FIFO Pointer Value
This register holds internal fill location pointer FIFO. identifies location FIFO receive next data byte from pipeline. PFFP register cleared device FIFO reset.
7.3.11
Parallel FIFO Holding Registers
8-Bit Address: Default Value:
Register Name: PFHR1 Register Description: Parallel FIFO Holding Register Access:
8-Bit Character Data
CD1283 IEEE 1284-Compatible Parallel Interface
Register Name: PFHR2 Register Description: Parallel FIFO Holding Register Access:
8-Bit Address: Default Value:
8-Bit Character Data
These 1-byte registers provide data pipeline between FIFO buffer. Data always flows first into PFHR1, then PFHR2 finally, either FIFO DMABUF register. flow FIFO DMAdir `1', from FIFO DMAdir `0'. pipeline holding registers support `tagged' data complete support Parallel Port mode. Tagged data either address code run-length code. receive direction RLEen PFCR), run-length codes captured RLCR decompression received data. address codes recognized pass into PFHR1- PFHR2 pipeline. presence address will interrupt flow cause interrupt host remove tagged data from pipeline reading either PFHR2 PFHR1. transmit direction, host introduce address (tagged) data run-length codes precompressed data setting setTAG PFCR writing byte tagged PFHR1. setTAG must prior writing PFHR1 each tagged data transfer. perform tagged data transfer, automatic function must disabled prior transfer (set DMAen `0'). This done same time that setTAG `1'. These registers cleared device FIFO reset marked empty HRSR. tagged status also cleared.
7.3.12
Parallel FIFO Quantity Register
8-Bit Address: Default Value:
Register Name: PFQR Register Description: Parallel FIFO Quantity Access:
Data Space Available FIFO x'40
This register maintains quantity count) either data bytes space available parallel FIFO. receive direction (DMAdir `0'), PFQR counts data characters FIFO. transmit direction (DMAdir `1'), PFQR counts space available FIFO additional characters transmit. FIFOres together with value DMAdir initialize PFQR either x'00 (receive) x'40 (transmit). either case, PFQR indicates only quantity data space available FIFO, does include data pipeline registers.
7.3.13
Parallel FIFO Status Register
8-Bit Address: Default Value: HRtag HRdata Stale OneChar DataErr
Register Name: PFSR Register Description: Parallel FIFO Status Access: Read only FFfull FFempty Timeout
IEEE 1284-Compatible Parallel Interface CD1283
PFSR read-only provides current FIFO data pipeline status. Host software should examine these bits response pipeline interrupts polling operations. This register directly cleared reset, individual bits will reflect status other registers. This register cleared device FIFO reset.
Description Parallel FIFO Full: this set, indicates parallel FIFO full. Parallel FIFO Empty: this set, parallel FIFO empty. Timeout: This when Stale goes from false true. receive direction, Timeout delayed until FIFO empty cycles complete. Timeout pipeline-interrupt condition must cleared manually toggling ClearTo PACR FIFO reset PFCR. Holding Register Tag: This indicates that tagged character either PFHR1, PFHR2, both. This being will cause host interrupt generated enabled). host should examine HRSR determine exact cause(s) this being set. Holding Register Data: this set, indicates that either PFHR1, PFHR2, both contain data. Stale: This when stale data timer expires (see description SDTPR). single byte remains data pipeline when this set, host interrupt generated, OneChar set, data entering FIFO will move into PFHR1 until PFHR2 emptied. more bytes remain pipeline when this set, host interrupt generated, however, request will generated enabled. Character: receive direction, when this indicates that FIFO empty stale, character remains PFHR2. This condition occurs number bytes transferred through parallel interface. Since cycles only moves even numbers bytes (words), transfer leaves byte remaining. Host software must remove this character outside transfer cycles. Data Error: When this set, indicates that more bits (Data Error register) set.
7.3.14
Parallel FIFO Threshold Register
8-Bit Address: Default Value: Transfer Threshold
Register Name: PFTR Register Description: Parallel FIFO Threshold Access:
This register sets FIFO threshold initiating requests data transfer. value expressed bytes. Whenever DMAen true, regular comparisons made between PFQR (Parallel FIFO Quantity register) PFTR. value PFQR greater than equal threshold, request logic becomes active remains active until FIFO essentially filled emptied. character space FIFO remain. receive direction, Holding register pipeline (consisting PFHR1 PFHR2) DMABUF enabled) kept filled that tagged data (for example, ECP-mode addresses) detected passed host interrupt. FIFO data pipeline initialized receive and, example, bytes placed into FIFO from parallel port, first those bytes automatically placed Pipeline registers. PFTR were programmed x'40 bytes, x'44 bytes must arrive trigger transfer. PFTR cleared device reset; cleared FIFOres.
CD1283 IEEE 1284-Compatible Parallel Interface
7.3.15
Run-Length Count Register
8-Bit Address: Default Value:
Register Name: RLCR Register Description: Run-Length Count Access:
7-Bit Unsigned Binary Count
This register works with PFHR1 PFHR2 perform run-length encoding/decoding when RLEen (PFCR[3]) (the parallel port must mode; other modes, run-length encoding will occur). transmit direction, strings three more identical characters recognized compressed. running count identical characters kept RLCR. Once sequence broken different character transmit burst transfer, count single copy duplicated character FIFO. receive direction, run-length codes received from remote device. These codes recognized fly' data flows from FIFO through Holding register pipeline. runlength code diverted RLCR. subsequent character from FIFO duplicated (held PFHR1) while RLCR decremented. Once RLCR reaches zero, normal pipeline data movement resumed. run-length codes being received parallel port RLEen set, codes will enter PFHR1 PFHR2 tagged data cause interrupts host. host must directly read tagged Holding register remove character from pipeline clear tag.
7.3.16
Stale Data Timer Count Register
8-Bit Address: Default Value:
Register Name: SDTCR Register Description: Stale Data Timer Count Access:
8-Bit Stale Data Timer Count
This register determines period used signal stale data FIFO. timer used only receive direction. Each time character placed FIFO from parallel port, SDTCR reloaded from SDTPR down-counting begins tick rate. counter reaches zero, Stale (PFSR[2]) set. amount data available greater than equal word, request made move remaining whole words host transfer. Once transfer complete, single remaining character causes interrupt host remove character reading PFHR2. This register cleared device FIFO reset. Clearing manually causes Stale true.
IEEE 1284-Compatible Parallel Interface CD1283
7.3.17
Stale Data Timer Period Register
8-Bit Address: Default Value:
Register Name: SDTPR Register Description: Stale Data Timer Period Access:
8-Bit Stale Data Timeout Value
This register provides user-defined period value timeout value stale data timer (see SDTCR). With 25-MHz input device, resolution this timer maximum value 25.5 25-MHz clock divided produce 10-µs intermediate clock this timer. fixed, divide-by-ten prescaler produces 0.1-ms `ticks' stale data timer. prescaler reset each time stale data timer reloaded ensure accuracy small time-out values. user selection 0.1-ms timeout would result time delay between 0.09 ms.) SDTPR cleared device reset.
7.4.1
Parallel Port Registers
Address Register
8-Bit Address: Default Value:
Register Name: Register Description: Address Access:
8-Bit Binary Value
This register only used during mode. CD1283 deposits value obtained during address write command this register. CD1283 provides this value response address read command.
7.4.2
Input Value Register
8-Bit Address: Default Value: A1284 nInit HstBsy HstClk
Register Name: Register Description: Input Value Access: Read only
This register always shows current state external handshake pins.
CD1283 IEEE 1284-Compatible Parallel Interface
These read-only bits always `0'. A1284 nInit: (active-low Init input) HstBsy: (Host Busy) HstClk: (Host Clock)
Description
7.4.3
Manual Data Register
8-Bit Address: Default Value:
Register Name: Register Description: Manual Data Access:
8-Bit Binary Data
This read/write register read state PD[7:0] signals mode. ManMd (PCR[7])is along with MMDir ManOE bits (PCR[1:0]),
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