28F6408J3 Flash Memory plus SRAM Reduces Memory Board Space Requi

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28F6408J3 Flash Memory plus SRAM Reduces Memory Board Space Requi

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Volt Intel StrataFlash® Memory Stacked-CSP
28F6408J3
Flash Memory plus SRAM Reduces Memory Board Space Required, Simplifying Design Complexity Stacked Chip Scale Package Technology Smallest Memory Subsystem Footprint 64-Mbit Flash 8-Mbit SRAM: Area: Height: Advanced SRAM Technology Access Time Power Operation Voltage Data Retention Mode High-Density Symmetrically-Blocked Architecture 64-Kword Erase Blocks High Performance Interface Asynchronous Page-Mode Reads 120/25 Read Access Time V-3.3 Operation VCCQ 128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable Cells
Enhanced Data Protection Features Absolute Protection withVPEN Flexible Block Locking Block Erase/Program Lockout during Power Transitions Packaging 72-Ball Stacked-CSP Cross-Compatible Command Support Intel Basic Command Common Flash Interface Scalable Command Word Write Buffer Byte Effective Programming Time 6,400,000 Total Erase Cycles 100,000 Erase Cycles Block Automation Suspend Options Block Erase Suspend Read Block Erase Suspend Program Program Suspend Read 0.25 Intel StrataFlash® Memory Technology
Volt Intel StrataFlash® Memory Stacked Chip Scale Package (Stacked-CSP) combines Intel's second-generation.25um StrataFlash memory with high performance, power SRAM deliver most cost effective memory solution today's spaced constrained applications. Currently offered 64Mbit flash plus 8-Mbit SRAM density, this device brings reliable, two-bit-per-cell storage technology wireless market segment. Benefits include: more density less space, high-speed SRAM interface, lowest cost-per-bit technology, support code data storage, easy migration future Stacked-CSP devices. Using same NOR-based ETOXtechnology Intel's one-bit-per-cell products, Intel StrataFlash memory devices take advantage over billion units flash manufacturing experience including tens millions Stacked-CSP units since 1987. result, Intel Stacked-CSP with StrataFlash memory components ideal code data applications where high density, lost cost, small size required. Examples include wireless phones, Personal Digital Assistants (PDAs) Personal Information Devices (PIDs). using industry standard JEDEC approved pinout, Intel Stacked-CSP with StrataFlash memory components allow easy design migrations other Intel Stacked-CSP densities including future product offerings. with Intel Stacked-CSP products, Intel Stacked-CSP with StrataFlash memory offers same quality reliability standards fully compatible with same software features that found Intel's discrete flash memory devices.
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 290709-001 June 2001
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. 28F6408J3 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Other names brands claimed property others.
Preliminary
28F6408J3
Contents
Product Overview. Principles Operation
Flash Data Protection. Flash Read Flash Output Disable. Flash Standby Flash Reset/Power-Down. Flash Read Query Flash Read Identifier Codes. Flash Write Flash Read Array Command. Flash Read Query Mode Command. 4.2.1 Flash Query Structure Output 4.2.2 Flash Query Structure Overview 4.2.3 Flash Block Status Register 4.2.4 Flash Query Identification String 4.2.5 Flash System Interface Information. 4.2.6 Flash Device Geometry Definition. 4.2.7 Flash Primary-Vendor Specific Extended Query Table Flash Read Identifier Codes Command Flash Read Status Register Command. Flash Clear Status Register Command. Flash Block Erase Command. Flash Block Erase Suspend Command. Flash Write Buffer Command Flash Word Program Commands. Flash Program Suspend Command Flash Configuration Command. Flash Block Lock-Bit Commands Flash Clear Block Lock-Bits Command. Flash Protection Register Program Command.24 4.14.1 Reading Protection Register 4.14.2 Flash Programming Protection Register 4.14.3 Flash Locking Protection Register.25 Three-Line Output Control. Block Erase, Program, Lock-Bit Configuration Polling Power Supply Decoupling Input Signal Transitions Reducing Overshoots Undershoots When Using Buffers Transceivers. F-VCC, VPEN, F-RP# Transitions.
Flash Operations
Flash Command Definitions
4.10 4.11 4.12 4.13 4.14
Design Considerations
Preliminary
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Power-Up/Down Protection Power Dissipation Stacked-CSP Absolute Maximum Ratings Stacked-CSP Operating Conditions Stacked-CSP Capacitance. Stacked-CSP Characteristics. Flash Characteristics- Read-Only Operations(1,2) Flash Characteristics- Write Operations(1,2). Flash Block Erase, Program, Lock-Bit Configuration Performance(1,2,3) SRAM Read Operation SRAM Write Operation. SRAM Data Retention Operation
Stacked-CSP Electrical Specifications
SRAM Characteristics
Ordering Information Additional Information
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Revision History
Date Revision 06/06/01 Version -001 Original version Description
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28F6408J3A
Product Overview
0.25 Volt Intel StrataFlash® Stacked-CSP memory family contains high-density memory organized Mbytes Mwords (64-Mbit). These devices accessed 16-bit words. 64-Mbit device organized sixty-four 64-Kword erase blocks. Blocks individually lockable unlockable in-system. 128-bit protection register multiple uses, including unique flash device identification. device's optimized architecture interface dramatically increases read performance supporting page-mode reads. This read mode ideal non-clocked memory systems. Common Flash Interface (CFI) permits software algorithms used entire families devices. This allows device-independent, JEDEC ID-independent, forward- backwardcompatible software support specified flash device families. Flash vendors standardize their existing interfaces long-term compatibility. Scalable Command (SCS) allows single, simple software driver host systems work with SCS-compliant flash memory devices, independent system-level packaging (e.g., memory card, SIMM, direct-to-board placement). Additionally, provides highest system/device data transfer rates minimizes device system-level implementation costs. Command User Interface (CUI) serves interface between system processor internal operation device. valid command sequence written initiates device automation. internal Write State Machine (WSM) automatically executes algorithms timings necessary block erase, program, lock-bit configuration operations. block erase operation erases device's 64-Kword blocks typically within second- independent other blocks. Each block independently erased 100,000 times. Block erase suspend mode allows system software suspend block erase read program data from other block. Similarly, program suspend allows system software suspend programming (word program write-to-buffer operations) read data execute code from other block that being suspended. Each device incorporates Write Buffer words allow optimum programming performance. using Write Buffer, data programmed buffer increments. This feature improve system program performance more than times over non-Write Buffer writes. Individual block locking uses block lock-bits lock unlock blocks. Block lock-bits gate block erase program operations. Lock-bit configuration operations clear lock-bits (Set Block Lock-Bit Clear Block Lock-Bits commands). status register indicates when WSM's block erase, program, lock-bit configuration operation finished. When device disabled F-RP# F-VCC, standby mode enabled. When F-RP# F-Vss, further power-down mode enabled which minimizes power consumption provides write protection during reset. reset time (tPHQV) required from FRP# switching high until outputs valid. Likewise, device wake time (tPHWL) from FRP#-high until writes recognized. With F-RP# F-Vss, reset status register cleared. Volt Intel StrataFlash memory devices available 72-Ball Stacked-CSP Figure show pinouts.
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Table
Symbol
Signal Descriptions
Type Name Function ADDRESS INPUTS: Inputs addresses during read program operations. Addresses internally latched during program cycle. FLASH: 64-Mbit: A0-A21 SRAM: 8-Mbit: A0-A18 DATA INPUTS/OUTPUTS: Inputs array data SRAM write operations second F-CE# F-WE# cycle during flash Program command. Inputs commands flash's Command User Interface when F-CE# F-WE# active. Data internally latched. Outputs array, configuration status register data. data balls float tri-state when chip de-selected outputs disabled. CHIP ENABLE: Activates device control logic, input buffers, decoders, sense amplifiers. When device de-selected, power reduces standby levels. SRAM CHIP SELECT1: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS1# active low. S-CS1# high deselects SRAM memory device reduces power consumption standby levels. SRAM CHIP SELECT2: Activates SRAM internal control logic, input buffers, decoders sense amplifiers. S-CS2 active high. S-CS2 deselects SRAM memory device reduces power consumption standby levels. RESET/ POWER-DOWN: Resets internal automation puts device power-down mode. FRP#-high enables normal operation. Exit from reset sets device read array mode. When driven low, F-RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates device's outputs through data buffers during read cycle. F-OE# active low. SRAM OUTPUT ENABLE: Activates SRAM outputs through data buffers during read operation. S-OE# active low. WRITE ENABLE: Controls writes Command User Interface, Write Buffer, array blocks. F-WE# active low. Addresses data latched rising edge F-WE# pulse. SRAM WRITE ENABLE: Controls writes SRAM memory array. S-WE# active low. SRAM UPPER BYTE ENABLE: Enables upper bytes SRAM (DQ15-8). S-UB# active low. SUB# S-LB# must tied together. SRAM LOWER BYTE ENABLE: Enables lower bytes SRAM (DQ7-0). S-LB# active low. SUB# S-LB# must tied together. ERASE PROGRAM BLOCK LOCK ENABLE: erasing Flash array blocks, programming data, configuring lock-bits. With VPEN VPENLK, memory contents cannot altered. DEVICE POWER SUPPLY: With F-VCC VLKO, write attempts flash memory inhibited. SRAM POWER SUPPLY: [2.7 V-3.3 Supplies power device operations. OUTPUT BUFFER POWER SUPPLY: This voltage controls device's output voltages. obtain output voltages compatible with system data voltages, connect F-VCCQ system supply voltage. GROUND: float ground pins. GROUND: float ground pins. CONNECT: Lead internally connected; driven floated.
A0-A21
INPUT
DQ0- DQ15
INPUT/ OUTPUT
F-CE# S-CS1#
INPUT INPUT
S-CS2
INPUT
F-RP# F-OE# S-OE# F-WE# S-WE# S-UB# S-LB#
INPUT INPUT INPUT INPUT INPUT INPUT INPUT
VPEN F-VCC S-VCC F-VCCQ F-Vss S-Vss
INPUT SUPPLY SUPPLY OUTPUT BUFFER SUPPLY SUPPLY SUPPLY
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Figure Volt Intel StrataFlashStacked-CSP Memory Package Mbit)
F-VSS F-VCCQ
DQ15 S-WE# DQ14 DQ13
F-WE# S-VSS F-RP# S-LB# S-UB# S-OE# F-CE# F-VSS F-OE# S-CS1# VPEN DQ11 DQ12 S-CS2 S-VCC F-VCC DQ10
View, Balls Down
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Principles Operation
Intel StrataFlash Stacked-CSP memory includes on-chip manage block erase, program, lock-bit configuration functions. allows 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, minimal processor overhead with RAM-like interface timings. After initial device power-up return from reset/power-down mode (see Section 3.0, "Flash Operations" page device defaults read array mode. Manipulation external memory control pins allows array read, standby, output disable operations. Read array, status register, query, identifier codes accessed through (Command User Interface) independent VPEN voltage. VPENH VPEN enables successful block erasure, programming, lock-bit configuration. functions associated with altering memory contents-block erase, program, lock-bit configuration-are accessed verified through status register. Commands written using standard microprocessor write timings. contents serve input WSM, which controls block erase, program, lock-bit configuration. internal device algorithms regulated WSM, including pulse repetition, internal verification, margining data. Addresses data internally latched during program cycles. Customer interface software that initiates polls progress block erase, program, lock-bit configuration stored block. This code copied executed from system during flash memory updates. After successful completion, reads again possible Read Array command. Block erase suspend allows system software suspend block erase read program data from/to other block. Program suspend allows system software suspend program read data from other flash memory array location.
Flash Data Protection
Depending application, system designer choose make VPEN switchable (available only when memory block erases, programs, lock-bit configurations required) hardwired VPENH. device accommodates either design practice encourages optimization processor-memory interface. When VPEN VPENLK, memory contents cannot altered. CUI's two-step block erase, word program, lock-bit configuration command sequences provide protection from unwanted operations even when VPENH applied VPEN. program functions disabled when F-VCC below write lockout voltage VLKO when F-RP# VIL. device's block locking capability provides additional protection from inadvertent code data alteration gating erase program operations.
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Flash Operations
local reads writes flash memory in-system. cycles from flash memory conform standard microprocessor cycles.
Figure Flash Array Memory
[21-0]: 64-Mbit
3FFFFF 3F0000
64-Kword Block
1F0000
64-Kword Block
01FFFF 010000 00FFFF 000000
64-Kword Block 64-Kword Block
Preliminary
64-Mbit
1FFFFF
28F6408J3A
Flash Read
Information read from block, query, identifier codes, status register independent VPEN voltage. Upon initial device power-up after exit from reset/power-down mode, device automatically resets read array mode. Otherwise, write appropriate read mode command (Read Array, Read Query, Read Identifier Codes, Read Status Register) CUI. Four control pins dictate data flow component: F-CE#, F-OE#, F-WE#, F-RP#. device must enabled F-OE# must driven active obtain data outputs. F-CE# device selection controls and, when enabled, select memory device. F-OE# data output (DQ0- DQ15) control and, when active, drives selected memory data onto bus. F-WE# must VIH. When reading information read array mode, device defaults asynchronous page mode. This mode provides high data transfer rate memory subsystems. this state, data internally read stored high-speed page buffer. A1:0 addresses data page buffer. page size four words. Asynchronous word mode supported with additional commands required.
Flash Output Disable
With F-OE# logic-high level (VIH), device outputs disabled. Output pins DQ0-DQ15 placed high-impedance state.
Flash Standby
F-CE# disable device place standby mode which substantially reduces device power consumption. DQ0-DQ15 outputs placed high-impedance state independent FOE#. deselected during block erase, program, lock-bit configuration, continues functioning, consuming active power until operation completes.
Flash Reset/Power-Down
F-RP# initiates reset/power-down mode. read modes, F-RP#-low deselects memory, places output drivers high-impedance state, turns numerous internal circuits. F-RP# must held minimum tPLPH. Time tPHQV required after return from reset mode until initial memory access outputs valid. After this wake-up interval, normal operation restored. reset read array mode status register 80H. During block erase, program, lock-bit configuration modes, F-RP#-low will abort operation. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lock-bit configuration. Time tPHWL required after FRP# goes logic-high (VIH) before another command written. with automated device, important assert F-RP# during system reset. When system comes reset, expects read from flash memory. Automated flash memories provide status information when accessed during block erase, program, lock-bit configuration
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modes. reset occurs with flash memory reset, proper initialization occur because flash memory providing status information instead array data. Intel® Flash memories allow proper initialization following system reset through F-RP# input. this application, F-RP# controlled same RESET# signal that resets system CPU.
Flash Read Query
read query operation outputs block status information, (Common Flash Interface) string, system interface information, device geometry information, Intel-specific extended query information.
Flash Read Identifier Codes
read identifier codes operation outputs manufacturer code, device code block lock configuration codes each block (see Table page 18). Using manufacturer device codes, system automatically match device with proper algorithms. block lock configuration codes identify locked unlocked blocks protection register.
Flash Write
does occupy addressable memory location. written when device enabled F-WE# active. address data needed execute command latched rising edge F-WE# first edge F-CE# that disables device. Standard microprocessor write timings used. Writing commands enables reading device data, query, identifier codes, inspection clearing status register, and, when VPEN VPENH, block erasure, program, lock-bit configuration. Block Erase command requires appropriate command data address within block erased. Word Program command requires command address location written. Block Lock-Bit commands require command block within device locked. Clear Block Lock-Bits command requires command address within device.
Flash Command Definitions
When VPEN voltage VPENLK, only read operations from status register, query, identifier codes, blocks enabled. Placing VPENH VPEN additionally enables block erase, program, lock-bit configuration operations. Device operations selected writing specific commands into CUI. Table defines these commands.
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Figure Flash Device Identifier Code Memory
Address 3FFFFF
A[21-0]: Mbit Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation (Blocks through Block Reserved Future Implementation
3F0003 3F0002
3F0000 3EFFFF
1F0003 1F0002
Block Lock Configuration Mbit Reserved Future Implementation (Blocks through Block Reserved Future Implementation Block Lock Configuration Reserved Future Implementation Block Reserved Future Implementation aster Lock Configuration Block Lock Configuration Device Code Manufacturer Code
1F0000 1EFFFF 01FFFF
010003 010002
010000 00FFFF
000004 000003 000002 000001 000000
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Table
Operations
S-UB#,S-LB#(8) F-WE#(1) Address F-OE#(1) S-CS1#
Mode
Read Array Output Disable Standby Reset/ PowerDown Mode Read Identifier Codes Read Query Read Status (WSM off)
2,3,9
DOUT High High
SRAM must High-Z
Valid SRAM Mode High
Figure Table
Note Note DOUT SRAM must High DOUT
Flash
Read Status (WSM
DQ15-8 High DQ6-0 High
Write Read Output Disable SRAM Standby Data Retention Write
VPENH
High-Z
Flash must High-Z
Valid FLASH Mode
High-Z High-Z
Flash must High-Z
NOTES: F-OE# F-WE# should never enabled simultaneously. Refer Characteristics. When VPEN VPENLK, memory contents read, altered. control address pins, VPENLK VPENH VPEN. Characteristics VPENLK VPENH voltages. Table read identifier code data. Section read query data. Command writes involving block erase, program, lock-bit configuration reliably executed when VPEN VPENH F-VCC within specification. Refer Table valid during write operation. S-UB# S-LB# must tied together devices drive memory same time. 10.The SRAM placed into data retention mode lowering S-VCC limit when standby mode.
Preliminary
S-WE#
S-OE#
F-RP#
F-CE#
S-CS2
Notes
VPEN
[15:0]
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Table
Command
Intel StrataFlash® Memory Command Definitions(1)
Scalable Basic Command Set(2) Cycles Req'd. Notes First Cycle Second Cycle
Oper(3) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write Buffer Word Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Block Lock-Bit Clear Block Lock-Bits Protection Program SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS 12,13 11,12 12,14 Write Write Write Write Write Write Write Write Write Write Write Write Write
Addr(4)
Data(5,6)
Oper(3)
Addr(4)
Data(5,6)
Read Read Read
Write Write Write
Write Write Write
NOTES: Commands other than those shown above reserved Intel future device implementations should used. Basic Command (BCS) same 28F008SA Command Intel Standard Command Set. Scalable Command (SCS) also referred Intel Extended Command Set. operations defined Table valid address within device. Address within block. Identifier Code Address: Figure Table Query database Address. Address memory location programmed. Data read from Identifier Codes. Data read from Query database. Data read from status register. Table description status register bits. Data programmed location Data latched rising edge F-WE#. upper byte data (DQ8-DQ15) during command writes "Don't Care". Following Read Identifier Codes command, read operations access manufacturer, device block lock codes. Section read identifier code data. running, only valid; DQ15-DQ8 DQ6-DQ0 float, which places them highimpedance state. After Write Buffer command issued check make sure buffer available writing.
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10.The number words written Write Buffer where word count argument. Count ranges word 0000H 000FH. third consecutive cycles, determined writing data into Write Buffer. Confirm command (D0H) expected after exactly write cycles; other command that point sequence aborts write buffer operation. Please Figure "Flash Write Buffer Flowchart" page additional information. 11.The write buffer erase operation does begin until Confirm command (D0h) issued. 12.Attempts issue block erase program locked block. 13.Either recognized word program setup. 14.Program suspends issued after either Write-to-Buffer Word-Program operation initiated. 15.The clear block lock-bits operation simultaneously clears block lock-bits.
Flash Read Array Command
Upon initial device power-up after exit from reset/power-down mode, device defaults read array mode. device remains enabled reads until another command written. Once internal started block erase, program, lock-bit configuration, device will recognize Read Array command until completes operation unless suspended Erase Program Suspend command. Read Array command functions independently VPEN voltage.
Flash Read Query Mode Command
This section defines data structure "database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component. Query part overall specification multiple command control interface descriptions called Common Flash Interface, CFI.
4.2.1
Flash Query Structure Output
Query "database" allows system software gain information controlling flash component. This section describes device's CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs (DQ0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16), first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte (DQ0-7) high byte (DQ8- 15). Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address. following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h," leading "00" been dropped from table notation only lower byte value shown.
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Table
Flash Summary Query Structure Output Function Device Mode
Query start location maximum device width addresses Query data with maximum device width addressing Offset Code 0051 0052 0059 ASCII Value Query data with byte addressing Offset Code ASCII Value "Null"
Table
Flash Example Query Structure Output
Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0051 0052 0059 P_IDLO P_IDHI A_IDLO A_IDHI Code D15-D0 PrVendor PrVendor TblAdr AltVendor Value
4.2.2
Flash Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database." structure sub-sections address locations summarized below. AP-646 Common Flash Interface (CFI) Command Sets (order number 292204) full description CFI. following sections describe Query structure sub-sections detail.
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Table
Flash Query Structure(1)
Offset (BA+2)h(2) 04-0Fh P(3) Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Manufacturer Code Device Code Block-Specific Information Reserved Vendor-Specific Information Reserved Vendor-Specific Information Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm Description
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
4.2.3
Flash Block Status Register
block status register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations.
Table
Flash Block Status Register
Offset (BA+2)h(1) Length Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked 1-7: Reserved Future Address BA+2: BA+2: BA+2: Value (bit (bit 1-7):
NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode).
4.2.4
Flash Query Identification String
Query Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
Table
Flash Identification
Offset Length Description Query-unique ASCII string "QRY" Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Add. Code Value
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Table
Flash Identification
Offset Length Description Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. Code Value
4.2.5
Flash System Interface Information
following device information optimize system interface software.
Table
Flash System Interface Information
Offset Length Description F-VCC logic supply minimum program/erase voltage bits bits volts F-VCC logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical Add. Code Value
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4.2.6
Flash Device Geometry Definition
This field provides critical details flash device geometry.
Table Flash Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table Below
Flash Device Geometry Definition
Address Mbit
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4.2.7
Flash Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
Table Flash Primary Vendor-Specific Extended Query
Offset(1) (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0." then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant Individual block locking supported Protection bits supported Page-mode read supported Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active F-VCC logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Add. Code Value
(P+5)h (P+6)h (P+7)h (P+8)h
1(1)
Yes(1)
(P+9)h
(P+A)h (P+B)h
(P+C)h
(P+D)h
NOTE: Future devices support described "Legacy Lock/Unlock" function. Thus would have value "0."
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Table Flash Protection Register Information
Offset(1) (P+E)h Length Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) protection register bytes. Some pre-programmed with device-unique serial numbers. Others userprogrammable. Bits 0-15 point protection register lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes Add. Code Value
(P+F)h (P+10)h (P+11)h (P+12)h
NOTE: variable pointer which defined offset 15h.
Table Flash Burst Read Information
Offset(1) Length Description (Optional Flash Features Commands) Page Mode Read capability (P+13)h bits such that value represents number read-page bytes. offset device word width determine page-mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability. Reserved future byte Add. Code Value
(P+14)h (P+15)h
NOTE: variable pointer which defined offset 15h.
Flash Read Identifier Codes Command
identifier code operation initiated writing Read Identifier Codes command. Following command write, read cycles from addresses shown Figure page retrieve manufacturer, device block lock configuration codes (see Table identifier code values). Page-mode reads supported this read mode. terminate operation, write another valid command. Like Read Array command, Read Identifier Codes command functions independently VPEN voltage. This command valid only when device suspended. Following Read Identifier Codes command, following information read:
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Table Flash Identifier Codes
Code Manufacture Code Device Code Block Unlocked Block Locked Reserved Future 64-Mbit Block Lock Configuration Address 00000h 00001h
X00021
Data (00) (00) DQ1-7
NOTES: selects specific block's lock configuration code. Figure device identifier code memory map.
Flash Read Status Register Command
status register read determine when block erase, program, lock-bit configuration complete whether operation completed successfully. read time writing Read Status Register command. After writing this command, subsequent read operations output data from status register until another valid command written. Page-mode reads supported this read mode. status register contents latched falling edge F-OE# first edge F-CE# that enables device. F-OE# must toggle device must disabled before further reads update status register latch. Read Status Register command functions independently VPEN voltage. During program, block erase, lock-bit, clear lock-bit command sequence, only SR.7 valid until Write State Machine completes suspends operation. Device pins DQ0-DQ6 DQ8-DQ15 placed high-impedance state. When operation completes suspends (check status register contents status register valid when read.
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Table Flash Status Register Definitions
WSMS High When Busy? ECLBS PSLBS VPENS bit2 Notes Check SR.7 determine block erase, program, lock-bit configuration completion. SR.6-SR.0 driven while SR.7 "0."
Status Register Bits SR.7 WRITE STATE MACHINE STATUS Ready Busy SR.6 ERASE SUSPEND STATUS Block Erase Suspended Block Erase Progress/Completed SR.5 ERASE CLEAR LOCK-BITS STATUS Error Block Erasure Clear Lock-Bits Successful Block Erase Clear Lock-Bits SR.4 PROGRAM LOCK-BIT STATUS Error Setting Lock-Bit Programming Successful Block Lock Programming SR.3 PROGRAMMING VOLTAGE STATUS (VPENS) Programming Voltage Detected, Operation Aborted Programming Voltage SR.2 PROGRAM SUSPEND STATUS Program suspended Program progress/completed SR.1 DEVICE PROTECT STATUS Block Lock-Bit Detected, Operation Abort Unlock
both SR.5 SR.4 "1"s after block erase lock-bit configuration attempt, improper command sequence entered.
SR.3 does provide continuous programming voltage level indication. interrogates indicates programming voltage level only after Block Erase, Program, Block Lock-Bit, Clear Block Lock-Bits command sequences.
SR.1 does provide continuous indication block lock-bit values. interrogates block lock-bits only after Block Erase, Program, Lock-Bit configuration command sequences. informs system, depending attempted operation, block lock-bit set. Read block lock configuration codes using Read Identifier Codes command determine block lock-bit status. SR.0 reserved future should masked when polling status register.
SR.0 RESERVED FUTURE ENHANCEMENTS
Table eXtended Status Register Definitions
High When Busy? Status Register Bits XSR.7 WRITE BUFFER STATUS Write buffer available Write buffer available XSR.6-XSR.0 RESERVED FUTURE ENHANCEMENTS Reserved bits Notes After Buffer-Write command, XSR.7 indicates that Write Buffer available. SR.6-SR.0 reserved future should masked when polling status register.
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Flash Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, SR.1 "1"s only reset Clear Status Register command. These bits indicate various failure conditions (see Table 15). allowing system software reset these bits, several operations (such cumulatively erasing locking multiple blocks writing several bytes sequence) performed. status register polled determine error occurred during sequence. clear status register, Clear Status Register command (50H) written. functions independently applied VPEN voltage. Clear Status Register command only valid when device suspended.
Flash Block Erase Command
Erase executed block time initiated two-cycle command. block erase setup first written, followed block erase confirm. This command sequence requires appropriate address within block erased (erase changes block data FFH). Block preconditioning, erase, verify handled internally (invisible system). After two-cycle block erase sequence written, device automatically outputs status register data when read (see Figure "Flash Block Erase Flowchart" page 30). detect block erase completion checking status register SR.7. Toggle F-OE#, F-CE# update status register. When block erase complete, status register SR.5 should checked. block erase error detected, status register should cleared before system software attempts corrective actions. remains read status register mode until command issued. This two-step command sequence set-up followed execution ensures that block contents accidentally erased. invalid Block Erase command sequence will result both status register bits SR.4 SR.5 being "1". Also, reliable block erasure only occur when FVCC valid VPEN VPENH. block erase attempted while VPEN VPENLK, SR.3 SR.5 will "1." Successful block erase requires that corresponding block lock-bit cleared. block erase attempted when corresponding block lock-bit set, SR.1 SR.5 will "1".
Flash Block Erase Suspend Command
Block Erase Suspend command allows block-erase interruption read program data another block memory. Once block erase process starts, writing Block Erase Suspend command requests that suspend block erase sequence predetermined point algorithm. device outputs status register data when read after Block Erase Suspend command written. Polling status register SR.7 then SR.6 determine when block erase operation been suspended (both will "1"). Specification tWHRH defines block erase suspend latency. this point, Read Array command written read data from blocks other than that which suspended. program command sequence also issued during erase suspend program data other blocks. During program operation with block erase suspended, status register SR.7 will return "0". However, SR.6 will remain indicate block erase suspend status. Using Program Suspend command, program operation also suspended. Resuming
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suspended programming operation issuing Program Resume command allows continuing suspended programming operation. resume suspended erase, user must wait programming operation complete before issuing Block Erase Resume command. only other valid commands while block erase suspended Read Query, Read Status Register, Clear Status Register, Configure, Block Erase Resume. After Block Erase Resume command written flash memory, will continue block erase process. Status register bits SR.6 SR.7 will automatically clear. After Erase Resume command written, device automatically outputs status register data when read (see Figure "Flash Block Erase Suspend/Resume Flowchart" page 31). VPEN must remain VPENH (the same VPEN level used block erase) while block erase suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
Flash Write Buffer Command
program flash device, Write Buffer command sequence initiated. variable number words, buffer size, loaded into buffer written flash device. First, Write Buffer Setup command issued along with Block Address (see Figure "Flash Write Buffer Flowchart" page 27). this point, eXtended Status Register (XSR, Table information loaded XSR.7 reverts "buffer available" status. XSR.7 write buffer available. retry, continue monitoring XSR.7 issuing Write Buffer setup command with Block Address until XSR.7 When XSR.7 transitions "1", buffer ready loading. word count given part with Block Address. next write, device start address given along with write buffer data. Subsequent writes provide additional device addresses data, depending count. subsequent addresses must within start address plus count. Internally, this device programs many flash cells parallel. Because this parallel programming, maximum programming performance lower power obtained aligning start address beginning write buffer boundary (i.e., A3-A0 start address After final buffer data given, Write Confirm command issued. This initiates (Write State Machine) begin copying buffer data flash array. command other than Write Confirm written device, "Invalid Command/Sequence" error will generated Status Register bits SR.5 SR.4 will "1". additional buffer writes, issue another Write Buffer Setup command check XSR.7. error occurs while writing, device will stop writing, status register SR.4 will indicate program failure. internal verify only detects errors "1"s that successfully program "0"s. program error detected, status register should cleared. time SR.4 and/or SR.5 (e.g., media failure occurs during program erase), device will accept more Write Buffer commands. Additionally, user attempts program past erase block boundary with Write Buffer command, device will abort write buffer operation. This will generate "Invalid Command/Sequence" error status register bits SR.5 SR.4 will "1". Reliable buffered writes only occur when VPEN VPENH. buffered write attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1". Buffered write attempts with invalid F-VCC VPEN voltages produce spurious results should attempted.
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Finally, successful programming requires that corresponding block lock-bit reset. buffered write attempted when corresponding block lock-bit set, SR.1 SR.4 will "1".
Flash Word Program Commands
Word program executed two-cycle command sequence. Word program setup (standard alternate 10H) written followed second write that specifies address data (latched rising edge F-WE#). then takes over, controlling program program verify algorithms internally. After program sequence written, device automatically outputs status register data when read (see Figure "Flash Program Flowchart" page 28). detect completion program event checking status register SR.7. When program complete, status register SR.4 should checked. program error detected, status register should cleared. internal verify only detects errors "1"s that successfully program "0"s. remains read status register mode until receives another command. Reliable word programs only occur when F-VCC VPEN valid. word program attempted while VPEN VPENLK, status register bits SR.4 SR.3 will "1". Successful word programs require that corresponding block lock-bit cleared. word program attempted when corresponding block lock-bit set, SR.1 SR.4 will "1".
4.10
Flash Program Suspend Command
Program Suspend command allows program interruption read data other flash memory locations. Once programming process starts (either initiating write buffer word program operation), writing Program Suspend command requests that suspend program sequence predetermined point algorithm. device continues output status register data when read after Program Suspend command written. Polling status register bits SR.7 determine when programming operation been suspended. When SR.7 SR.2 should also "1", indicating that device program suspend mode. Specification tWHRH1 defines program suspend latency. this point, Read Array command written read data from locations other than that which suspended. only other valid commands while programming suspended Read Query, Read Status Register, Clear Status Register, Configure, Program Resume. After Program Resume command written, will continue programming process. Status register bits SR.2 SR.7 will automatically clear. After Program Resume command written, device automatically outputs status register data when read. VPEN must remain VPENH F-VCC must remain valid F-VCC levels (the same VPEN F-VCC levels used programming) while program suspend mode. Refer Figure "Flash Program Suspend/ Resume Flowchart" page
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4.11
Flash Configuration Command
Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result both status register bits SR.4 SR.5 being "1".
Table Flash Configuration Coding Definitions
Pulse Program Complete(1) DQ7-DQ2 reserved future use. DQ7-DQ2 Reserved default pulse Erase complete pulse Program complete pulse Erase Program Complete Configuration Codes 01b, 10b, pulse mode. Configuration (masking bits DQ7-DQ2 00h) follows: Default B8h, (Erase Interrupt): B8h, Pulse-on-Erase Complete (Program Interrupt): B8h, Pulse-on-Program Complete ER/PR (Erase Program Interrupt): B8h, Pulse-on-Erase Program Complete default (DQ1-DQ0 00), level mode used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. configuration INT, pulse mode used generate system interrupt pulse when flash device array completed Block Erase. Helpful reformatting blocks after file system free space reclamation "cleanup" configuration INT, pulse mode used generate system interrupt pulse when flash device array complete Program operation. Provides highest performance servicing continuous buffer write operations. configuration ER/PR INT, pulse mode used generate system interrupts trigger servicing flash arrays when either erase program operations completed when common interrupt service routine desired. Pulse Erase Compete(1)
Reserved bits
4.12
Flash Block Lock-Bit Commands
flexible block locking unlocking scheme enabled block lock-bits. block lock-bits gate program erase operations. Individual block lock-bits using Block LockBit command. This command invalid while running device suspended. block lock-bit commands executed two-cycle sequence. block setup along with appropriate block address followed either block lock-bit confirm (and address within block locked). then controls lock-bit algorithm. After sequence written, device automatically outputs status register data when read (see Figure page 32). detect completion lock-bit event checking status register SR.7. When lock-bit operation complete, status register SR.4 should checked. error detected, status register should cleared. will remain read status register mode until command issued.
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This two-step sequence set-up followed execution ensures that lock-bits accidentally set. invalid Block Lock-Bit command will result status register bits SR.4 SR.5 being "1." Also, reliable operations occur only when F-VCC VPEN valid. With VPEN VPENLK, lock-bit contents protected against alteration.
4.13
Flash Clear Block Lock-Bits Command
block lock-bits cleared parallel Clear Block Lock-Bits command. Block lockbits cleared using only Clear Block Lock-Bits command. This command invalid while running device suspended. Clear block lock-bits command executed two-cycle sequence. clear block lock-bits setup first written. device automatically outputs status register data when read (see Figure page 33). detect completion clear block lock-bits event checking status register SR.7. When operation complete, status register SR.5 should checked. clear block lock-bit error detected, status register should cleared. will remain read status register mode until another command issued. This two-step sequence set-up followed execution ensures that block lock-bits accidentally cleared. invalid Clear Block Lock-Bits command sequence will result status register bits SR.4 SR.5 being "1." Also, reliable clear block lock-bits operation only occur when F-VCC VPEN valid. clear block lock-bits operation attempted while VPEN VPENLK, SR.3 SR.5 will "1." clear block lock-bits operation aborted VPEN F-VCC transitioning valid range, block lock-bit values left undetermined state. repeat clear block lock-bits required initialize block lock-bit contents known values.
4.14
Flash Protection Register Program Command
Volt Intel StrataFlash Stacked-CSP memory includes 128-bit protection register that used increase security system design. example, number contained protection register used "mate" flash component with other system components such ASIC, preventing device substitution. 128-bits protection register divided into 64-bit segments. segments programmed Intel factory with unique 64-bit number, which unchangeable. other segment left blank customer designers program desired. Once customer segment programmed, locked prevent further programming.
4.14.1
Reading Protection Register
protection register read identification read mode. device switched this mode writing Read Identifier command (90H). Once this mode, read cycles from addresses shown Table retrieve specified information. return read array mode, write Read Array command (FFH).
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4.14.2
Flash Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time. First write Protection Program Setup command, C0H. next write device will latch address data program specified location. allowable addresses shown Table Figure "Flash Protection Register Programming Flowchart" page attempt address Protection Program commands outside defined protection register address space will result status register error (program error SR.4 will Attempting program locked protection register segment will result status register error (program error SR.4 lock error SR.1 will
4.14.3
Flash Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error (program error SR.4 Lock Error SR.1 will Protection register lockout state reversible.Flash Locking Protection Register user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error (program error SR.4 Lock Error SR.1 will Protection register lockout state reversible.
Figure Flash Protection Register Memory
Word Adress
A[21:0]:64 Mbit
Words bits) User Programmed Words bits) Intel Factory Programmed
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Table Flash Protection Register Addressing
Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A21-A8
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Figure Flash Write Buffer Flowchart
Start e-Out Issue rite Buffer E8H, Block Address Read Extended Status Register Operation rite Read rite Buffer ents Data Block Address XSR. Valid Addr Block Address Check XSR. rite Buffer Available rite Buffer Available Data Count Corresponds Count Addr Block Address Data rite Buffer Data Addr Device Start Address Data rite Buffer Data Addr Device Address Program Buffer Flash Confirm Data Addr Block Address Status Register Data with Device Enabled, Updates Addr Block Address Check SR.7 Ready Busy
Standby
XSR.7 rite Count, Block Address rite Buffer Data, Start Address Check Abort rite Buffer and? rite Next Buffer Data, Device Address X=X+1 Program Buffer Flash Confirm
rite Buffer e-Out?
rite (Note rite (Note rite (Note rite
Read (Note
Standby rite Another Block Address
rite Buffer Aborted
Another rite Buffer? Read Status Register SR.7 Full Status Check Desired Program plete Issue Read Status
count values loaded into count register. Count ranges this device word 0000H 000FH. device outputs status register when read (XSR longer available). rite Buffer contents will program device start address destination flash address. Align start address rite Buffer boundary axim program perform ance (i.e., start address device aborts rite Buffer current address outside original block address. status register indicates proper sequence" rite Buffer aborted. Follow this with Clear Status Register and. Toggling F-OE# (low high low) updates status register. This done place issuing Read Status Register and. Full status check done after erase write sequences plete. rite after last operation reset device read array ode.
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Figure Flash Program Flowchart
Start Write 40H, Address Write Data Address Read Status Register Full Status Check Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.1 SR.4 Program Successful Programming Error Device Protect Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.1 Device Protect Detect VIH, Block Lock-Bit Only required systems implemeting lock-bit configuration. Check SR.4 Programming Error
Operation Write Write Read (Note Standby
Command Setup Program Program
Comments Data Addr Location Programmed Data Data Programmed Addr Location Programmed Status Register Data Check SR.7 Ready Busy
SR.7
Toggling F-OE# (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program operation, after sequence programming operations. Write after last program operation place device read array mode.
Voltage Range Error
Standby
Toggling F-OE# (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3 SR.1 only cleared Clear Status Register command cases where multiple locations programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
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Figure Flash Program Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Program Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.2 Programming Suspended Programming Completed
Read Status Register
Standby
SR.7
Standby
Write SR.2 Write Programming Completed Write Read
Read Array
Data Addr Read array locations other than that being programmed.
Program Resume
Data Addr
Read Data Array
Done Reading Write Write
Programming Resumed
Read Array Data
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Figure Flash Block Erase Flowchart
Start Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note Command Erase Block Erase Confirm Comments Data Addr Block Address Data Addr Status register data With device enabled, updates Addr Check SR.7 Ready Busy
Read
Write Confirm Block Address
Standby
Erase Confirm byte must follow Erase Setup. This device does support erase queuing. Please Application note AP-646 software erase queuing compatibility. Full status check done after erase write sequences complete. Write after last operation reset device read array mode. Suspend Erase Loop
Read Status Register
SR.7
Suspend Erase
Full Status Check Desired
Erase Flash Block(s) Complete
0606_09
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Figure Flash Block Erase Suspend/Resume Flowchart
Operation Write Write Read
Start
Command Erase Suspend
Comments Data Addr Status Register Data Addr Check SR.7 Ready Busy Check SR.6 Block Erase Suspended Block Erase Completed
Read Status Register
Standby
SR.7
Standby
Write SR.6 Read Read Program? Read Array Data Done? Write Write Program Loop Program Block Erase Completed
Erase Resume
Data Addr
Block Erase Resumed
Read Array Data
0606_10
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Figure Flash Block Lock-Bit Flowchart
Start Write 60H, Block Address Write 01H, Block Address Read Status Register Full Status Check Desired Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.4 Lock-Bit Successful Lock-Bit Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.4 Lock-Bit Error
Operation Write
Command Block Lock-Bit Setup Block Lock-Bit Confirm
Comments Data Addr =Block Address Data Addr Block Address Status Register Data Check SR.7 Ready Busy
Write
Read
Standby
Repeat subsequent lock-bit operations. Full status check done after each lock-bit operation after sequence lock-bit operations. Write after last lock-bit operation place device read array mode.
SR.7
Command Sequence Error
Standby
SR.5, SR.4 SR.3 only cleared Clear Status Register command, cases where multiple lock-bits before full status checked. error detected, clear status register before attempting retry other error recovery.
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Figure Flash Clear Lock-Bit Flowchart
Start
Operation Write
Command Clear Block Lock-Bits Setup Clear Block Lock-Bits Confirm
Comments Data Addr Data Addr Status Register Data Check SR.7 Ready Busy
Write
Write
Write
Read
Read Status Register
Standby
SR.7 Full Status Check Desired Clear Block Lock-Bits Complete
Write after clear lock-bits operation place device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 SR.4,5 SR.5 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Command Sequence Error Voltage Range Error
Standby Operation Standby Command Comments Check SR.3 Programming Voltage Error Detect Check SR.4, Both Command Sequence Error Check SR.5 Clear Block Lock-Bits Error
Standby
SR.5, SR.4, SR.3 only cleared Clear Status Register command. error detected, clear status register before attempting retry other error recovery.
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Figure Flash Protection Register Programming Flowchart
Start Write (Protection Reg. Program Setup) Write Protect. Register Address/Data Read Status Register
Operation Write Write
Command Protection Program Setup Protection Program
Comments Data Data Data Program Addr Location Program Status Register Data Toggle Update Status Register Data Check SR.7 Ready Busy
Read
Standby
SR.7 Full Status Check Desired Program Complete
Protection Program operations only addressed within protection register address space. Addresses outside defined space will return error. Repeat subsequent programming operations. Full Status Check done after each program after sequence program operations. Write after last program operation reset device read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3, SR.4 SR.1, SR.4 SR.1, SR.4 VPEN Range Error
Standby Operation Standby Command Comments SR.1 SR.3 SR.4 VPEN Prot. Reg. Prog. Error Register Locked: Aborted
Protection Register Programming Error Attempted Program Locked Register Aborted
Standby
SR.3 MUST cleared, during program attempt, before further attempts allowed Write State Machine. SR.1, SR.3 SR.4 only cleared Clear Staus Register Command, cases multiple protection register program operations before full status checked. error detected, clear status register before attempting retry other error recovery.
Program Successful
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Design Considerations
Three-Line Output Control
device will often used large memory arrays. Intel provides three control inputs (F-CE#, F-OE#, F-RP#) accommodate multiple memory connections. This control provides for:
Lowest possible memory power dissipation. Complete assurance that data contention will occur.
these control inputs efficiently, address decoder should enable device while F-OE# should connected memory devices system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices standby mode. F-RP# should connected system POWERGOOD signal prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
Block Erase, Program, Lock-Bit Configuration Polling
default mode, transitions after block erase, program, lock-bit configuration commands returns High when finished executing internal algorithm.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers interested three supply current issues; standby current levels, active current levels transient peaks produced falling rising edges F-CE# F-OE#. Transient current magnitudes depend device outputs' capacitive inductive loading. Two-line control proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from F-VCC pins (these devices include pin), recommended that systems without separate power ground planes attach ceramic capacitor between each device's three F-VCC pins (this includes F-VCCQ) ground. These high-frequency, low-inductance capacitors should placed close possible package leads each Intel StrataFlash Stacked-CSP memory device. Each device should have ceramic capacitor connected between F-VCC F-VSS. These high-frequency, inductance capacitors should placed close possible package leads. Additionally, every eight devices, electrolytic capacitor should placed between F-VCC F-VSS array's power supply connection. bulk capacitor will overcome voltage slumps caused board trace inductance.
Input Signal Transitions Reducing Overshoots Undershoots When Using Buffers Transceivers
faster, high-drive devices such transceivers buffers drive input signals flash memory devices, overshoots undershoots sometimes cause input signals exceed flash memory specifications. (See "Stacked-CSP Absolute Maximum Ratings" page 37.) Many buffer/
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transceiver vendors carry bus-interface devices with internal output-damping resistors reduced-drive outputs. Internal output-damping resistors diminish nominal output drive currents, while still leaving sufficient drive capability most applications. These internal outputdamping resistors help reduce unnecessary overshoots undershoots. Transceivers buffers with balanced- light-drive outputs also reduce overshoots undershoots diminishing output-drive currents. When considering buffer/transceiver interface design flash, devices with internal output-damping resistors reduced-drive outputs should used minimize overshoots undershoots. additional information, please refer AP-647 Volt Intel StrataFlashMemory Design Guide.
F-VCC, VPEN, F-RP# Transitions
Block erase, program, lock-bit configuration guaranteed VPEN F-VCC falls outside specified operating ranges, F-RP# VIH. F-RP# transitions during block erase, program, lock-bit configuration. Then, operation will abort device will enter reset/power-down mode. aborted operation leave data partially corrupted after programming, partially altered after erase lock-bit configuration. Therefore, block erase lock-bit configuration commands must repeated after normal operation restored. Device power-off F-RP# clears status register. latches commands issued system software altered VPEN, F-CE# transitions, actions. state read array mode upon power-up, after exit from reset/ power-down mode, after F-VCC transitions below VLKO. F-VCC must kept above VPEN during F-VCC transitions. After block erase, program, lock-bit configuration, even after VPEN transitions down VPENLK, must placed read array mode Read Array command subsequent access memory array desired. VPEN must kept below F-VCC during VPEN transitions.
Power-Up/Down Protection
device designed offer protection against accidental block erasure, programming, lockbit configuration during power transitions. Internal circuitry resets read array mode power-up. system designer must guard against spurious writes F-VCC voltages above VLKO when VPEN active. Since F-WE# must device enabled command write, driving FWE# disabling device will inhibit writes. CUI's two-step command sequence architecture provides added protection against data alteration. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock unlock capability protects device against inadvertent programming. device disabled while F-RP# regardless control inputs.
Power Dissipation
When designing portable systems, designers must consider battery power consumption only during device operation, also data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data retained when system power removed.
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Stacked-CSP Electrical Specifications
Stacked-CSP Absolute Maximum Ratings
Parameter Temperature under Bias Expanded Storage Temperature Voltage Output Short Circuit Current Maximum Rating +125 -0.5 +3.80 V(1) mA(2)
NOTES: specified voltages with respect F-Vss. Minimum voltage -0.5 input/output pins -0.2 F-VCC VPEN pins. During transitions, this level undershoot -2.0 periods Maximum voltage input/output pins, F-VCC, VPEN F-VCC +0.5 which, during transitions, overshoot F-VCC +2.0 periods Output shorted more than second. more than output shorted time.
NOTICE: This datasheet contains preliminary information products production. specifications subject change without notice. Verify with your local Intel Sales office that have latest datasheet before finalizing design.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only. Operation beyond "Operating Conditions" recommended extended exposure beyond "Operating Conditions" affect device reliability.
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Stacked-CSP Operating Conditions
Table Stacked-CSP Temperature F-VCC Operating Conditions
Symbol F-VCC F-VCCQ S-Vcc Parameter Operating Temperature F-VCC Supply Voltage (2.7 V-3.3 F-VCCQ Supply Voltage (2.7 V-3.3 Notes 2.70 2.70 3.30 3.30 Unit Test Condition Ambient Temperature
F-VCCQ S-VCC must tied together, except when Data Retention Mode.
Stacked-CSP Capacitance
Symbol COUT CF-CE# Parameter(1) Input Capacitance Output Capacitance F-CE# Input Capacitance Unit Condition VOUT
NOTES: Sampled, 100% tested.
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Symbol
Stacked-CSP Characteristics
Parameter Input VPEN Load Current Device Flash/ SRAM Flash/ SRAM Notes Unit Test Conditions F-VCC F-VCC Max; F-VCCQ F-VCCQ F-VCCQ F-VSS F-VCC F-VCC Max; F-VCCQ F-VCCQ F-VCCQ F-VSS CMOS Inputs, F-VCC F-VCC Max, Device enabled F-RP# F-VCCQ Inputs, F-VCC F-VCC Max, Device enabled, F-RP# S-VCC S-VCCMax 8-Mbit SRAM S-CS1# S-VCC S-CS2 S-VCC S-VSS Inputs S-VCC S-VSS S-CS1# S-SC2 S-WE# Inputs Cycle time 100% duty S-CS1# S-SC2 Inputs
Output Leakage Current
ICCS F-VCC Standby Current Flash 1,2,3 0.71
Operating Power Supply Current (cycle time
8-Mbit SRAM
ICC2
Operating Power Supply Current (min cycle time) F-VCC Power-Down Current
8-Mbit SRAM
ICCD
Flash
F-RP# F-VSS IOUT CMOS Inputs, F-VCC F-VCC Max, FVCCQ F-VCCQ using standard word page mode reads. Device enabled MHz, IOUT CMOS Inputs, F-VCC F-VCC Max, FVCCQ F-VCCQ using standard word page mode reads. Device enabled MHz, IOUT
ICCR F-VCC Page Mode Read Current Flash 1,2,3
ICCW
F-VCC Program Lock-Bit Current F-VCC Block Erase Clear Block Lock-Bits Current F-VCC Program Suspend Block Erase Suspend Current
Flash Flash
1,3,4 1,3,4
CMOS Inputs, VPEN F-VCC Inputs, VPEN F-VCC CMOS Inputs, VPEN F-VCC Inputs, VPEN F-VCC Device disabled
ICCE ICCWS ICCES
Flash 1,3,5
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Stacked-CSP Characteristics, Continued
Symbol Parameter Input Voltage Input High Voltage Device Flash/ SRAM Flash/ SRAM Flash/ SRAM Flash/ SRAM Notes FVCCQ Unit F-VCC F-VCCMin F-VCCQ F-VCCQMin F-VCC F-VCCMin F-VCCQ F-VCCQ -100 Test Conditions
Output Voltage
-0.1
Output High Voltage VPEN Lockout during Program, Erase Lock-Bit Operations VPEN during Block Erase, Program, Lock-Bit Operations F-VCC Lockout Voltage
F-VCCQ0.2
VPENLK
Flash
4,6,7
VPENH VLKO
Flash Flash
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Contact Intel's Application Support Hotline your local sales office information about typical specifications. CMOS inputs either F-VCC F-VSS inputs either VIH. Current values specified over temperature range increase slightly Sampled, 100% tested. ICCWS ICCES specified with device de-selected. device read written while erase suspend mode, device's current draw ICCR ICCW. Block erases, programming, lock-bit configurations inhibited when VPEN VPENLK, guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Typically, VPEN connected F-VCC (2.7 V-3.3 Block erases, programming, lock-bit configurations inhibited when F-VCC VLKO, guaranteed range between VLKO (min) F-VCC (min), above F-VCC (max).
Figure Transient Input/Output Reference Waveform
NOTE: test inputs driven F-VCCQ Logic Logic "0." Input timing begins, output timing ends, F-VCCQ/2 (50% F-VCCQ). Input rise fall times (10% 90%)
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28F6408J3A
Figure Transient Equivalent Testing Load Circuit
Device Under Test
NOTE: Includes Capacitance Test Configuration F-VCCQ F-VCC V-3.3 (pF)
Preliminary
28F6408J3A
Flash Characteristics- Read-Only Operations(1,2)
F-VCC F-VCCQ Notes V-3.3 V-3.3
Versions (All units unless otherwise noted) tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tEHEL tAPA tGLQV Parameter Read/Write Cycle Time Address Output Delay F-CE# Output Delay F-OE# Non-Array Output Delay F-RP# High Output Delay F-CE# Output F-OE# Output F-CE# High Output High F-OE# High Output High Output Hold from Address, F-CE#X, F-OE# Change, Whichever Occurs First F-CE# High F-CE# Page Address Access Time F-OE# Array Output Delay
NOTES: F-CE# defined first edge F-CE# that enables device. F-CE# high defined first edge F-CE# that disables device.See Input/Output Reference Waveforms maximum allowable input slew rate. F-OE# delayed tELQV-tGLQV after first edge F-CE# that enables device without impact tELQV. Figures 13-14, Transient Input/Output Reference Waveform F-VCCQ -3.3 Transient Equivalent Testing Load Circuit testing characteristics. When reading flash array faster tGLQV (R16) applies. Non-array reads refer status register reads, query reads, device identifier reads. Sampled, 100% tested. devices configured standard word read mode, (tAPA) will equal (tAVQV).
Preliminary
28F6408J3A
Figure Flash Waveform Both Page-Mode Standard Read Operations
A21:2
Valid Address
A1-0
Valid Address
Valid Address
Valid Address
Valid Address
Data [D/Q]
High
Valid utput
Valid Output
Valid Output
Valid utput
High
RST#
Generic_Pg_Rd RD_PAGE.WM
NOTE: F-CE# defined first edge this will enable device. F-CE# high defined first edge this will disable device. standard word read operations, (tAPA) will equal (tAVQV). When reading flash array faster tGLQV (R16) applies. Non-array reads refer status register reads, query reads, device identifier reads.
Preliminary
28F6408J3A
Flash Characteristics- Write Operations(1,2)
Valid Speeds Notes
Versions Symbol tPHWL (tPHEL) tELWL (tWLEL) tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tQVVL Parameter F-RP# High Recovery F-WE# (F-CE#) Going F-CE# (F-WE#) F-WE# (F-CE#) Going Write Pulse Width Data Setup F-WE# (F-CE#) Going High Address Setup F-WE# (F-CE#) Going High F-CE# (F-WE#) Hold from F-WE# (F-CE#) High Data Hold from F-WE# (F-CE#) High Address Hold from F-WE# (F-CE#) High Write Pulse Width High VPEN Setup F-WE# (F-CE#) Going High Write Recovery before Read VPEN Hold from Valid
Unit
NOTES: F-CE# defined first edge this enables device. F-CE# high defined first edge this disables device. Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations. write operation initiated terminated with either F-CE# F-WE#. Sampled, 100% tested. Write pulse width (tWP) defined from F-CE# F-WE# going (whichever goes first) F-CE# FWE# going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. F-CE# driven before F-WE# going low, F-WE# pulse width requirement decreases Refer Table valid block erase, program, lock-bit configuration. Write pulse width high (tWPH) defined from F-CE# F-WE# going high (whichever goes high first) FCE# F-WE# going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL. array access, tAVQV required addition tWHGL accesses after write. VPEN should held VPENH until determination block erase, program, lock-bit configuration success (SR.1/3/4/5
Preliminary
28F6408J3A
Flash Block Erase, Program, Lock-Bit Configuration Performance(1,2,3)
tWHQV3 tEHQV3 tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Parameter Write Buffer Program Time (Time Program words) Program Time (Using Word Program Command) Block Program Time (Using Write Buffer Command) Block Erase Time Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time Read Erase Suspend Latency Time Read Notes 4,5,6, 0.70 Unit
NOTES: Typical values measured nominal voltages. Assumes corresponding lock-bits set. Subject change based device characterization. These performance numbers valid speed versions. Sampled 100% tested. Excludes system-level overhead. These values valid when buffer full, start address aligned 16-word boundary. Effective per-word program time (tWHQV2, tEHQV2) 13.6 µs/word (typical)
Note:
values measured worst case temperature F-VCC corner after 100k cycles
Preliminary
28F6408J3A
Figure Flash Waveform Write Operations
ADDRESSES
Disabled (VIH) CE#, (WE#) [E(W)] Enabled (VIL)
Disabled (VIH) WE#, (CE#) [W(E)] Enabled (VIL)
High Valid
DATA [D/Q]
VPENH VPENLK VPEN
NOTES:
F-CE# defined first edge this enables device. F-CE# high defined first edge disables device.
F-VCC power-up standby. Write block erase, write buffer, program setup. Write block erase write buffer confirm, valid address data. Automated erase delay. Read status register query data. Write Read Array command.
Preliminary
28F6408J3A
Figure Flash Waveform Reset Operation
0606_18
Flash Reset Specifications(1)
tPLPH tPHRH Parameter F-RP# Pulse Time F-RP# tied F-VCC, this specification applicable) F-RP# High Reset during Block Erase, Program, Lock-Bit Configuration Notes Unit
NOTES: These specifications valid product versions (packages speeds). F-RP# asserted while block erase, program, lock-bit configuration operation executing then minimum required F-RP# Pulse Time reset time, tPHQV, required from latter F-RP# going high until outputs valid.
Preliminary
28F6408J3A
SRAM Characteristics
SRAM Read Operation
Density 8Mbit 2.7-3.3V Unit
Parameter1
S-VCC Speed Note
tCO1, tCO2 tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tBLZ tBHZ
Read Cycle Time Address Output Delay S-CS1#, S-CS2 Output Delay S-OE# Output Delay S-UB#, S-LB# Output Delay S-CS1#, S-CS2 Output Low-Z S-OE# Output Low-Z S-CS1#, S-CS2 Output High-Z S-OE# Output High-Z Output Hold from Address, S-CS1#, S-CS2, S-OE# Change, Whichever Occurs First S-UB#, S-LB# Output Low-Z S-UB#, S-LB# Output High-Z
NOTE: Figure "SRAM Waveform Read Operation" page Sampled, 100% tested. given temperature voltage condition, (Max) less than (Max) given device from device-to-device interconnection. Timings tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels.
Preliminary
28F6408J3A
Figure SRAM Waveform Read Operation
Standby
ADDRESSES
Device Address Selection Address Stable
Data Valid
CS1# (E1) (E2)
High Valid Output High
DATA (D/Q)
UB#,
Preliminary
28F6408J3A
SRAM Write Operation
Density Parameter1 S-VCC Speed Note Write Cycle Time Address Setup S-WE# (S-CS1#) S-UB#, S-LB# Going S-WE# (S-CS1#) Pulse Width Data Write Time Overlap Address Setup S-WE# (S-CS1#) Going High S-SC1# (S-WE#) Setup S-WE# (S-CS1#) Going High S-SC2 Going Data Hold Time from S-WE# (SCS1#) High Write Recovery S-UB#, S-LB# Setup S-WE# (SCS1#) Going High 8Mbit 2.7-3.3V Unit
NOTES: Figure "SRAM Waveform Read Operation" page write occurs during overlap (tWP) S-CS1# S-WE#. write begins when S-CS1# goes S-WE# goes with asserting S-UB# S-LB#. write ends earliest transition when S-CS1# goes high S-WE# goes high. measured from beginning write write. measured from S-CS1# going write. measured from address valid beginning write. measured from write address change; applied case write ends S-CS1# S-WE# going high.
Preliminary
28F6408J3A
Figure SRAM Waveform Write Operation
Standby Device Address Selection Address Stable
ADDRESSES
CS1# (E1) (E2)
High High
DATA (D/Q)
Data
UB#,
Current tSDR tRDR
SRAM Data Retention Operation
Parameter S-VCC Data Retention Deep Retention Data Retention Setup Time Voltages Recovery Time Device SRAM SRAM SRAM SRAM Note Unit Test Conditions S-CS1# S-VCC S-VCC S-CS1# S-VCC Data Retention Waveform
NOTES: Typical values nominal S-VCC, S-CS1# S-VCC S-CS2 S-VCC (S-CS1# controlled) S-CS2 (S-CS2 controlled).
Preliminary
28F6408J3A
Figure SRAM Data Retention Waveform
tSDR tRDR
S-CS1# controlled
Data Retention Mode
S-VCC
VIHMAX S-CS1# (E1) VIHMIN S-VSS
S-CS1#
S-CS2 controlled
S-VCC VIHMIN S-CS2 (E2) VILMAX S-VSS
S-CS2
tSDR
Data Retention Mode
tRDR
Preliminary
28F6408J3A
Ordering Information
Package Designator Stacked Access Speed (ns) Mbit
Product Line Designator Intel® Flash products
Voltage (VCC/VPEN)
Device Density (64-Mbit)
Product Family Intel® StrataFlashMemory bits-per-cell
NOTE: These speeds either standard asynchronous read access times first access pagemode read sequence.
VALID COMBINATIONS
72-Ball SCSP RD28F6408J3A-120
Preliminary
28F6408J3A
Additional Information
Order Number 298130 290668 292237 290608 290598 297859 292222 292221 292218 292204 298161
Document/Tool Volt Intel StrataFlashMemory 28F128J3A, 28F640J3A, 320J3A Specification Update Intel® Persistent Storage Manager datasheet AP-689 Using Intel® Persistent Storage Manager Volt FlashFileMemory; 28F160S3 28F320S3 datasheet Volt FlashFileMemory; 28F004S3, 28F008S3, 28F016S3 datasheet AP-677 Intel® StrataFlashMemory Technology AP-664 Designing Intel® StrataFlashMemory into Intel® Architecture AP-663 Using Intel® StrataFlashMemory Write Buffer AP-660 Migration Guide Volt Intel® StrataFlashMemory AP-646 Common Flash Interface (CFI) Command Sets Intel® Flash Memory Chip Scale Package User's Guide
NOTE: Please call Intel Literature Center (800) 548-4725 request Intel documentation. International customers should contact their local Intel distribution sales office. Visit Intel's World Wide home page http://www.intel.com technical documentation tools. most current information Intel StrataFlash memory, visit website http://developer.intel.com/ design/flash/isf.
Preliminary

28F6408J3 Flash Memory plus SRAM Reduces Memory Board Space Requi

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