ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB 8-Bit, 40/80/1

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ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB 8-Bit, 40/80/1

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FEATURES Dual 8-Bit, MSPS, MSPS, MSPS Power: MSPS Channel On-Chip Reference Track/Holds Analog Bandwidth Each Channel Analog Input Range Each Channel Single +3.0 Supply Operation (2.7 V-3.6 Standby Mode Single Channel Operation Twos Complement Offset Binary Output Mode Output Data Alignment Mode APPLICATIONS Battery Powered Instruments Hand-Held Scopemeters Cost Digital Oscilloscopes Communications
ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB
8-Bit, 40/80/100 MSPS Dual Converter AD9288
FUNCTIONAL BLOCK DIAGRAM
TIMING
OUTPUT REGISTER
AD9288
D7A-D0A SELECT SELECT
OUTPUT REGISTER
DATA FORMAT SELECT D7B-D0B
TIMING
GENERAL DESCRIPTION
AD9288 dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits optimized cost, power, small size ease use. product operates MSPS conversion rate with outstanding dynamic performance over full operating range. Each channel operated independently. requires only single (2.7 power supply encode clock full-performance operation. external reference driver components required many applications. digital outputs TTL/CMOS compatible separate output power supply supports interfacing with logic.
encode input TTL/CMOS compatible 8-bit digital outputs operated from +3.0 (2.5 supplies. User-selectable options available offer combination standby modes, digital data formats digital data timing schemes. standby mode, digital outputs driven high impedance state. Fabricated advanced CMOS process, AD9288 available 48-lead surface mount plastic package LQFP) specified over industrial temperature range (-40°C +85°C).
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
AD9288-SPECIFICATIONS
Parameter RESOLUTION ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes Gain Error1 Gain Tempco1 Gain Matching Voltage Matching ANALOG INPUT Input Voltage Range (With Respect AIN) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH) Encode Pulsewidth (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance DIGITAL OUTPUTS Logic Voltage Logic Voltage
Differential Input; External reference unless otherwise noted.)
AD9288BST-80 +1.25 +1.50 +1.25 +1.50 0.50 +1.25 +1.50 +1.25 +1.50 AD9288BST-40 0.50 +1.25 +1.50 +1.25 +1.50 Units Bits ppm/°C
Temp
Test Level
AD9288BST-100
+25°C Full +25°C Full Full +25°C Full Full +25°C +25°C
0.50
Guaranteed
Guaranteed
Guaranteed
Full Full +25°C Full Full Full +25°C Full +25°C +25°C Full +25°C +25°C +25°C +25°C +25°C Full Full Full Full Full Full +25°C Full Full Full Full +25°C +25°C +25°C
1.25
1.25
1.25
ppm/°C MSPS MSPS mV/V
2.45 0.05 1000 1000
2.45 0.05 1000 1000
2.45 0.05 1000 1000
POWER SUPPLY Power Dissipation4 Standby Dissipation4, Power Supply Rejection Ratio (PSRR) DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3
+25°C +25°C +25°C
47.5 47.5 47.0
47.5
47.5
REV.
AD9288
Parameter
Temp
Test Level
AD9288BST-100
AD9288BST-80
AD9288BST-40
Units
DYNAMIC PERFORMANCE (Continued) Signal-to-Noise Ratio (SINAD) (With Harmonics) 10.3 +25°C +25°C +25°C Effective Number Bits 10.3 +25°C +25°C +25°C Harmonic Distortion +25°C 10.3 +25°C +25°C Harmonic Distortion +25°C 10.3 +25°C +25°C Two-Tone Intermod Distortion (IMD) 10.3 +25°C
Bits Bits Bits
NOTES Gain error gain temperature coefficient based only (with fixed 1.25 external reference). measured from level ENCODE input 10%/90% levels digital outputs swing. digital output load during test exceed load current Digital supply current based +3.0 output drive with loading under dynamic test conditions. Power dissipation measured under following conditions: MSPS, analog input -0.7 dBFS, both channels operation. Standby dissipation calculated with encode clock operation. SNR/harmonics based analog input voltage -0.7 dBFS referenced 1.024 full-scale input range. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION TEST LEVELS
Analog Inputs -0.5 Digital Inputs -0.5 VREF -0.5 Digital Output Current Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Maximum Junction Temperature +175°C Maximum Case Temperature +150°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions outside those indicated operation sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
Test Level 100% production tested. 100% production tested +25°C sample tested specified temperatures. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested +25°C; guaranteed design characterization testing industrial temperature range; 100% production tested temperature extremes military devices.
Table User Select Options
ORDERING GUIDE
Package Options ST-48* Evaluation Board
User Select Options Standby Both Channels Standby Channel Only. Normal Operation (Data Align Disabled). Data align enabled (data from both channels available rising edge Clock Channel data delayed clock cycle).
Model AD9288BST -40, -80, -100 AD9288/PCB
Temperature Ranges -40°C +85°C +25°C
Thin Plastic Quad Flatpack (1.4 thick, LQFP).
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9288 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9288
CONFIGURATION
(MSB)
Aperture Delay
delay between differential crossing ENCODE ENCODE instant which analog input sampled.
ENCA
Aperture Uncertainty (Jitter)
sample-to-sample variation aperture delay.
AINA AINA REFINA REFOUT REFINB AINB AINB
Differential Nonlinearity
IDENTIFIER
deviation code from ideal step.
Encode Pulsewidth/Duty Cycle
AD9288
VIEW (Not Scale)
Pulsewidth high minimum amount time that ENCODE pulse should left Logic state achieve rated performance; pulsewidth minimum time ENCODE pulse should left state. given clock rate, these specs define acceptable Encode duty cycle.
Integral Nonlinearity
ENCB
(MSB)
CONNECT
deviation transfer function from reference line measured fractions using "best straight line" determined least square curve fit.
Minimum Conversion Rate
FUNCTION DESCRIPTIONS
encode rate which lowest analog signal frequency drops more than below guaranteed limit.
Maximum Conversion Rate
Name
Description Ground. Analog Input Channel Analog Input Channel (Complementary). Data Format Select: (Offset binary output available low. Twos complement output available high). Reference Voltage Input Channel Internal Reference Voltage. Reference Voltage Input Channel User Select (Refer Table Tied with Respect User Select (Refer Table Tied with Respect Analog Input Channel (Complementary). Analog Input Channel Analog Supply Clock Input Channel Digital Supply Digital Output Channel Connect. Digital Output Channel Clock Input Channel
AINA AINA
encode rate which parametric testing performed.
Output Propagation Delay
delay between differential crossing ENCODE ENCODE time when output data bits within valid logic levels.
Power Supply Rejection Ratio
ratio change input offset voltage change power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
17-24 37-44
REFINA REFOUT REFINB AINB AINB ENCB D7B-D0B D0A-D7A ENCA
ratio signal amplitude (set below full scale) value other spectral components, including harmonics excluding
Signal-to-Noise Ratio (SNR)
ratio signal amplitude (set below full scale) value other spectral components, excluding first five harmonics
Spurious-Free Dynamic Range (SFDR)
ratio signal amplitude value peak spurious spectral component. peak spurious component harmonic. reported (i.e., degrades signal levels lowered), dBFS (always related back converter full scale).
Two-Tone Intermodulation Distortion Rejection
ratio value either input tone value worst third order intermodulation product; reported dBc.
Two-Tone SFDR
DEFINITION SPECIFICATIONS Analog Bandwidth (Small Signal)
ratio value either input tone value peak spurious component. peak spurious component product. reported (i.e., degrades signal levels lowered), dBFS (always related back converter full scale).
Worst Harmonic
analog input frequency which spectral power fundamental frequency determined analysis) reduced
ratio signal amplitude value worst harmonic component, reported dBc. REV.
AD9288
SAMPLE SAMPLE SAMPLE
SAMPLE
SAMPLE
SAMPLE
ENCODE
D7A-D0A
DATA
DATA
DATA
DATA
DATA
DATA
D7B-D0B
DATA
DATA
DATA
DATA
DATA
DATA
Figure Normal Operation, Same Clock Channel Timing
SAMPLE
SAMPLE
SAMPLE
AINA, AINB
SAMPLE
SAMPLE
SAMPLE
ENCODE ENCODE
D7A-D0A
DATA
DATA
DATA
DATA
DATA
DATA
D7B-D0B
DATA
DATA
DATA
DATA
DATA
DATA
Figure Normal Operation with Clock Sources Channel Timing
REV.
AD9288
SAMPLE SAMPLE SAMPLE
AINA, AINB
SAMPLE
SAMPLE
SAMPLE
ENCODE ENCODE
D7A-D0A
DATA
DATA
DATA
DATA
DATA
DATA
D7B-D0B
DATA
DATA
DATA
DATA
DATA
DATA
Figure Data Align with Clock Sources Channel Timing
REV.
Typical Performance Characteristics-AD9288
60.00 72.00
ENCODE 100MSPS 10.3MHz 48.52dB SINAD 48.08dB HARMONIC -62.54dBc HARMONIC -63.56dBc
ENCODE RATE 100MSPS 68.00 64.00
56.00 52.00
SAMPLE
48.00 44.00 40.00
Figure Spectrum: MSPS, MHz, Single-Ended Input
Figure Harmonic Distortion Frequency
ENCODE 100MSPS 41MHz 47.87dB SINAD 46.27dB HARMONIC -54.10dBc HARMONIC -55.46dBc
ENCODE 100MSPS AIN1 9.3MHz AIN2 10.3MHz -60.0dBc
SAMPLE
SAMPLE
Figure Spectrum: MSPS, MHz, Single-Ended Input
Figure Two-Tone Intermodulation Distortion
50.00
ENCODE 100MSPS 76MHz 47.1dB SINAD 43.2dB HARMONIC -52.2dBc HARMONIC -51.5dBc
ENCODE RATE 100MSPS 48.00 46.00 SINAD 44.00 42.00
40.00
SAMPLE
38.00 36.00
Figure Spectrum: MSPS, MHz, Single-Ended Input
Figure SINAD/SNR Frequency
REV.
AD9288
49.00 10.3MHz SINAD 48.00
POWER
10.3MHz
47.00
46.00 45.00 MSPS MSPS
Figure SINAD/SNR Encode Rate
Figure Analog Power Dissipation Encode Rate
50.00 10.3MHz
48.0 47.5 ENCODE RATE 100MSPS 10.3MHz
46.00
SINAD
47.0 46.5
SINAD
42.00
46.0
45.5 38.00 45.0 34.00 44.5 44.0 30.00 ENCODE HIGH PULSEWIDTH 43.5
TEMPERATURE
Figure SINAD/SNR Encode Pulsewidth High
Figure SINAD/SNR Temperature
-0.5 -1.0 -1.5
ENCODE RATE 100MSPS
ENCODE RATE 100MSPS 10.3MHz
-2.5 -3.0 -3.5 -4.0 -4.5
GAIN
-2.0
-3dB
-0.2 -0.4 -0.6 -0.8
-5.0 -5.5 BANDWIDTH -1.0 TEMPERATURE
Figure Frequency Response: MSPS
Figure Gain Temperature (with External +1.25 Reference)
REV.
AD9288
-0.5 -1.0 -1.5 -2.0
Figure Equivalent Analog Input Circuit
VBIAS
CODE
REFIN
Figure Integral Nonlinearity Figure Equivalent Reference Input Circuit
1.00 0.75 0.50 0.25
ENCODE
0.00
Figure Equivalent Encode Input Circuit
-0.25 -0.50
-0.75 -1.00 CODE
Figure Differential Nonlinearity Figure Equivalent Digital Output Circuit
ENCODE 100MSPS 3.0V
VREFOUT
Figure Equivalent Reference Output Circuit
0.25
0.75 LOAD
1.25
1.75
Figure Voltage Reference Current Load
REV.
AD9288
APPLICATION NOTES
THEORY OPERATION Timing
AD9288 architecture bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine MSBs drive 3-bit flash. Each stage provides sufficient overlap error correction allowing optimization comparator accuracy. input buffers differential both sets inputs internally biased. This allows most flexible differential single-ended input modes. output staging block aligns data, carries error correction feeds data output buffers. output buffers powered from separate supply, allowing adjustment output voltage swing. There discernible difference performance between channels.
USING AD9288
AD9288 provides latched data outputs, with four pipeline delays. Data outputs available propagation delay (tPD) after rising edge encode command (see Figures length output data lines loads placed them should minimized reduce transients within AD9288. These transients detract from converter's dynamic performance. minimum guaranteed conversion rate AD9288 MSPS. clock rates below MSPS, dynamic performance will degrade. Typical power-up recovery time after standby mode clock cycles.
User Select Options
Good high speed design practices must followed when using AD9288. obtain maximum benefit, decoupling capacitors should physically close chip possible, minimizing trace inductance between chip pins capacitor (0603 surface mount caps used AD9288/PCB evaluation board). recommended place capacitor each power-ground pair high frequency decoupling, include capacitor local frequency decoupling. VREF should also decoupled capacitor. also recommended split power plane contiguous ground plane (see evaluation board section). Data output traces should short inch), minimizing on-chip noise switching.
ENCODE Input
pins available combination operational modes. These options allow user place both channels standby, excluding reference, just channel. Both modes place output buffers clock inputs high impedance states. other option allows user skew channel output data clock cycle. other words, clocks AD9288 180° phase, enabling data align will allow Channel output data available rising edge Clock same encode clock provided both channels data align enabled, then output data from Channel will 180° phase with respect Channel same encode clock provided both channels data align disabled, then both outputs delivered same rising edge clock.
EVALUATION BOARD
high speed converter extremely sensitive quality sampling clock provided user. track/hold circuit essentially mixer. noise, distortion timing jitter clock will combined with desired signal output. that reason, considerable care been taken design ENCODE input AD9288, user advised give commensurate thought clock source. ENCODE input fully TTL/CMOS compatible.
Digital Outputs
AD9288 evaluation board offers easy test AD9288. provides means drive analog inputs singleendedly differentially. encode clocks easily accessible on-board connectors These clocks buffered board provide clocks on-board latches. digital outputs output clocks available standard 37-pin connector, board several different modes operation, shipped following configuration: Single-Ended Analog Input Normal Operation Timing Mode Internal Voltage Reference
Power Connector
digital outputs TTL/CMOS compatible lower power consumption. During standby, output buffers transition high impedance state. data format selection option supports either twos complement (set high) offset binary output (set low) formats.
Analog Input
Power supplied board detachable 6-pin power strip, VREFA VREFB Optional External Reference Input (1.25 Optional External Reference Input (1.25 Supply Support Logic V/215 Supply Outputs V/15 Supply Analog V/30
analog input AD9288 differential buffer. best dynamic performance, impedance should match. Special care taken design analog input stage AD9288 prevent damage corruption data when input overdriven. nominal input range 1.024 centered 0.3.
Voltage Reference
Analog Inputs
stable accurate 1.25 voltage reference built into AD9288 (REFOUT). normal operation, internal reference used strapping Pins (REFINA) (REFINB) (REFOUT). input range adjusted varying reference voltage applied AD9288. appreciable degradation performance occurs when reference adjusted full-scale range tracks reference voltage, which changes linearly.
evaluation board accepts analog input signal centered ground each analog input. These single-ended signals using connectors (channel (Channel this mode jumpers E4-E5 E6-E7. (E1-E2 jumpers should lifted.) Differential analog inputs connectors Input centered ground. single-ended input converted
-10-
REV.
AD9288
differential transformers T2-allowing performance differential inputs measured using singleended source. this mode jumpers E1-E2, E3-E4, E7-E8 E9-E10. (E4-E5 E6-E7 jumpers should lifted.) Each analog input terminated board with ground. Each input ac-coupled board through capacitor on-chip resistor divider that provides bias. Note that inverting analog inputs terminated board with (optimized single-ended operation). When driving board differentially these resistors changed provide balanced inputs.
Encode
(DATA)
(CLOCK)
2.00V
2.00V
10.0ns
40mV
Figure Data Output Clock 37-Pin Connector
Outputs
encode clock channel uses connector Channel encode connector Each clock input terminated board with ground. input clocks directly buffers which drive latches. clock inputs compatible, should limited maximum
Voltage Reference
AD9288 internal 1.25 voltage reference. external reference each channel employed instead. evaluation board configured internal reference (use jumpers E18-E41 E17-E19. external references, connect VREFA VREFB pins power connector jumpers E20-E18 E21-E19.
Normal Operation Mode
Each channel reconstructed on-board dual channel DAC, AD9763. This intended assist debug-it should used measure performance ADC. current output with on-board termination resistors. Figure representative output with fullscale analog input. scope setting bandwidth, termination.
this mode both converters clocked same encode clock; latency four clock cycles (see timing diagram). Signal (Pin held high signal (Pin held low. This jumpers E22-E29 E26-E23.
Data Align Mode
500mV
50.0ns
380mV
this mode channel output delayed additional cycle. Signal (Pin signal (Pin both held high. This jumpers E22-E29 E26-E28.
Data Format Select
Figure AD9763 Reconstruction Output
Troubleshooting
Data Format Select sets output data format that outputs. Setting (Pin E30-E27 sets output format offset binary; setting high E30-E25 sets output twos complement.
Data Outputs
digital outputs latched board 574s, latch outputs available 37-pin connector Pins 22-29 (Channel Pins 30-37 (Channel latch output clock (data ready) available output connector. data ready signal aligned with clock input connecting E31-E32 aligned with clock input connecting E31-E33.
board does seem working correctly, following: Verify power pins. Check that jumpers correct position desired mode operation. Verify VREF 1.25 running encode clock analog inputs speeds MSPS/1 MHz) monitor outputs, outputs, outputs toggling. AD9288 Evaluation Board provided design example customers Analog Devices, Inc. makes warranties, express, statutory, implied, regarding merchantability fitness particular purpose.
REV.
-11-
AD9288
BILL MATERIALS
REFDES C1-C15, C20-C25, C16-C19, E1-E43 J1-J8 R5-R7, R10-R14 R15,
DEVICE Ceramic Tantalum W-HOLE SMBPN 37DRFP Resistor Resistor Resistor Resistor Transformer AD9288 AD9763 74ACQ574 SN74LCX86
PACKAGE 0603 TAJD W-HOLE SMBP C37DRFP R1206 R1206 R1206 R1206 T1-1T LQFP48 LQFP48 DIP20\SOL SO14
VALUE
-12-
REV.
OUTPUT
OUTPUT
MODE AVDD
REFIO
ACOM
FSADJ1
DB9-P1
DB8-P1 DB7-P1 DB6-P1 DB5-P1 DB4-P1
REFIO FSADJ2
SLEEP
DCOM1 DVDD1
WRT1/IQWRT
CLK1/IQCLK CLK2/IQRESET WRT2/IQSEL DCOM2
CLKLATA
DVDD2
DB9-P2 DB8-P2
CLKDACA OUT_EN
CLKDACA CLKDACA
CLKDACB
CLKDACB
AINA SINGLE-ENDED
VDD3
ENCA
AINA AINAB 2COMP REFINA REFOUT REFINB
GND1
ENCA
ENCB
GND3
ENCB
REV.
DB0-P2
DB3-P1
VREFA VREFB
AD9763
DB1-P2 DB2-P2 DB3-P2 DB4-P2 DB5-P2 DB6-P2 DB7-P2
VREFA VREFB
DB2-P1 DB1-P1 DB0-P1
ENCA
ENCODE
74LCX86
74ACQ574
CLKCONA
CLKLATA CLKCONA
CLOCK
Figure Dual Evaluation Board Schematic
GND7 VDD2 GND6
-13-
VREFA
CLKCONB
GND5 VDD1
GND4
VREFB
AINBB
AINA DIFFERENTIAL
T1-1T
AD9288
AINB
74ACQ574 OUT_EN CLKLATB C37DRPF CLOCK
GND2
AINB DIFFERENTIAL
T1-1T
AINB SINGLE-ENDED
ENCB CLKLATB
ENCODE
74LCX86
CLKDACB
CLKLATA
AD9288
CLKCONB
AD9288
Figure Printed Circuit Board Side Copper
Figure Printed Circuit Board Ground Layer
Figure Printed Circuit Board Bottom Side Silkscreen
Figure Printed Circuit Board "Split" Power Layer
-14-
REV.
AD9288
Figure Printed Circuit Board Bottom Side Copper
Figure Printed Circuit Board Side Silkscreen
REV.
-15-
AD9288
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
48-Lead LQFP (ST-48)
0.063 (1.60) 0.030 (0.75) 0.018 (0.45) 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35)
0.354 (9.00) 0.276 (7.0)
SEATING PLANE VIEW
(PINS DOWN)
0.006 (0.15) 0.002 (0.05)
0.007 (0.18) 0.004 (0.09)
0.019 (0.5)
0.011 (0.27) 0.006 (0.17)
0.354 (9.00)
0.276 (7.0)
-16-
REV.
PRINTED U.S.A.
C3546-8-4/99

ENCA AINA AINA REFINA REFOUT REFINB AINB AINB ENCB 8-Bit, 40/80/1

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