Dual 8-Bit, MSPS Converter AD9059 PWRDN AD9059 AINA ADC

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Dual 8-Bit, MSPS Converter AD9059 PWRDN AD9059 AINA ADC

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FEATURES Dual 8-Bit ADCs Single Chip Power: Typical On-Chip +2.5 Reference T/Hs Analog Input Range Single Supply Operation Logic Interface Analog Bandwidth Power-Down Mode: APPLICATIONS Digital Communications (QAM Demodulators) YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation
Dual 8-Bit, MSPS Converter AD9059
PWRDN
AD9059
AINA ADCA D7A-D0A
VREF ENCODE +2.5V AINB ADCB D7B-D0B
PRODUCT DESCRIPTION
AD9059 dual 8-bit monolithic analog-to-digital converter optimized cost, power, small size, ease use. With MSPS encode rate capability full-power analog bandwidth typical, component ideal applications requiring multiple ADCs with excellent dynamic performance. minimize system cost power dissipation, AD9059 includes internal +2.5 reference dual track-and-hold circuits. requires only power supply encode clock. external reference driver components required many applications. AD9059's single encode input TTL/CMOS compatible simultaneously controls both internal channels. parallel 8-bit digital outputs operated from supplies. power-down function exercised bring total consumption when data required lengthy periods time. power-down mode digital outputs driven high impedance state. Fabricated advanced BiCMOS process, AD9059 available space saving 28-lead surface mount plastic package SSOP) specified over industrial (-40°C +85°C) temperature range. Customers desiring single channel digitization consider AD9057, single 8-bit, MSPS monolithic based AD9059 core. AD9057 available 20-lead surface mount plastic package SSOP) specified over industrial temperature range.
CONFIGURATION
AINA VREF PWRDN
AINB ENCODE
AD9059
VIEW (MSB) (Not Scale) (MSB) (LSB) (LSB)
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD9059-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter RESOLUTION ACCURACY Differential Nonlinearity Integral Nonlinearity Missing Codes Gain Error1
Gain Tempco1
external reference; ENCODE MSPS unless otherwise noted)
Temp Test Level AD9059BRS +25°C Full +25°C Full Full +25°C Full
Full
Units Bits
ppm/°C
0.75 GUARANTEED -2.5
0.75
ANALOG INPUT Input Voltage Range (Centered +2.5 Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth CHANNEL MATCHING Gain Delta Input Offset Voltage Delta BANDGAP REFERENCE Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SINAD) (with Harmonics) 10.3 Effective Number Bits 10.3 Signal-to-Noise Ratio (SNR) (Without Harmonics) 10.3 Harmonic Distortion 10.3 Harmonic Distortion 10.3 Two-Tone Intermodulation Distortion (IMD) Channel Crosstalk Rejection Differential Phase Differential Gain
+25°C +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C Full Full Full Full +25°C +25°C Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C
ppm/°C MSPS MSPS Bits Bits Degrees REV.
44.5 43.5
14.2
6.35
AD9059
Parameter DIGITAL INPUTS Logic Voltage Logic Voltage Logic Current Logic Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width (tEL) DIGITAL OUTPUTS Logic Voltage (VDD Logic Voltage (VDD Logic Voltage (VDD Output Coding POWER SUPPLY Supply Current Supply Current (VDD
Power Dissipation5, Power-Down Dissipation Power Supply Rejection Ratio (PSRR)
Temp Full Full Full Full +25°C +25°C +25°C Full Full Full
Test Level
AD9059BRS
Units
2.95 4.95 0.05 Offset Binary Code
Full Full
Full Full +25°C
mV/V
NOTES Gain error gain temperature coefficient based only (with fixed +2.5 external reference). measured from level ENCODE 10%/90% levels digital output swing. digital output load during test exceed load current SNR/harmonics based analog input voltage -0.5 dBFS referenced full-scale input range. Digital supply current based output drive with loading under dynamic test conditions. Power dissipation based MSPS encode 10.3 analog input dynamic test conditions 5%). Typical thermal impedance style (SSOP) 28-pin package: 39°C/W, 70°C/W, 109°C/W. Specifications subject change without notice.
EXPLANATION TEST LEVELS
ABSOLUTE MAXIMUM RATINGS*
Test Level 100% production tested. 100% production tested +25°C sample tested specified temperatures. Sample tested only. Parameter guaranteed design characterization testing. Parameter typical value only. 100% production tested +25°C; guaranteed design characterization testing industrial temperature range.
Analog Inputs -0.5 Digital Inputs -0.5 VREF Input -0.5 Digital Output Current Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum ratings extended periods affect device reliability.
ORDERING GUIDE
Model AD9059BRS AD9059/PCB
Temperature Range 40°C +85°C +25°C
Package Option RS-28 Evaluation Board
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD9059 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD9059
DESCRIPTIONS
Name
Function
AINA, AINB Analog Inputs VREF Internal Voltage Reference (+2.5 Typical); Bypass with Ground Overdrive with External Voltage Reference. Power-Down Function Select; Logic HIGH Power-Down Mode (Digital Outputs HighImpedance State). Analog Power Supply. Ground. Digital Output Power Supply. Nominally Digital Outputs ADCA. Digital Outputs ADCB. Encode Clock ADCs (ADCs Sample Simultaneously Rising Edge ENCODE).
ENCODE
DIGITAL OUTPUTS
PWRDN
APERTURE DELAY PULSE WIDTH HIGH PULSE WIDTH OUTPUT VALID TIME OUTPUT PROP DELAY 6.7ns 6.7ns 4.0ns 6.6ns 9.5ns 14.2ns
2.7ns
166ns 166ns
7-14 22-15
D7A-D0A D7B-D0B ENCODE
Figure Timing Diagram
CONFIGURATION
AINA VREF PWRDN
AINB ENCODE
Table Digital Coding (VREF +2.5
Analog Input 2.502 2.498
Voltage Level Positive Full Scale Midscale Midscale Negative Full Scale
Digital Output 1111 1111 1000 0000 0111 1111 0000 0000
AD9059
VIEW (MSB) (Not Scale) (MSB) (LSB) (LSB)
REV.
AD9059
ENCODE 60MSPS ANALOG 10.3MHz, -0.5dBFS SINAD 43.9dB ENOB BITS 45.1dB
HARMONIC ENCODE 60MSPS -0.5dBFS
HARMONIC
FREQUENCY
ANALOG INPUT FREQUENCY
Figure Spectral Plot MSPS, 10.3
Figure Harmonic Distortion Frequency
ENCODE 60MSPS ANALOG 76MHz, -0.5dBFS SINAD 43.0dB ENOB 6.85 BITS 44.1dB
ENCODE 60MSPS 9.5MHz -7.0dBFS 9.9MHz -7.0dBFS -52.0dBc -53.0dBc
FREQUENCY
FREQUENCY
Figure Spectral Plot MSPS,
Figure Two-Tone
10.3MHz, -0.5dBFS
SINAD
SINAD
ENCODE 60MSPS -0.5dBFS
ENCODE RATE MSPS
ANALOG INPUT FREQUENCY
Figure SINAD/SNR Frequency
Figure SINAD/SNR Encode Rate
REV.
AD9059
10.3MHz, -0.5dBFS
POWER
ENCODE RATE MSPS
TEMPERATURE
Figure Power Dissipation Encode Rate
Figure Temperature/Supply V/+5
45.5 45.0 44.5 SINAD 44.0
45.5 44.5
43.5
43.5 43.0 42.5 42.0 ENCODE 60MSPS 10.3MHz, -0.5dBFS
SINAD
42.5 41.5 ENCODE 60MSPS 10.3MHz, -0.5dBFS
41.5
TEMPERATURE
40.5
8.35 ENCODE HIGH PULSE WIDTH
10.9
Figure SINAD/SNR Temperature
Figure SINAD/SNR Encode Pulse Width
-0.2 -0.4
GAIN ERROR
GAIN
-0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8
ENCODE 60MSPS -0.5dBFS
TEMPERATURE
ANALOG FREQUENCY
Figure Gain Temperature (With External +2.5 Reference)
Figure Frequency Response
REV.
AD9059
THEORY OPERATION
AD9059 combines Analog Devices' proprietary MagAmp gray code conversion circuitry with flash converter technology provide dual high performance 8-bit ADCs single cost monolithic device. design architecture ensures power, high speed, 8-bit accuracy. AD9059 provides linked channels that clocked from single ENCODE input (refer block diagram). channels simultaneously sample analog inputs (AINA AINB) provide non-interleaved parallel digital outputs (D0A-D7A D0B-D7B). voltage reference (VREF) internally connected both ADCs channel gains offsets will track external reference control desired. analog input signal buffered input each channel applied high speed track-and-hold. circuit holds analog input value during conversion process (beginning with rising edge ENCODE command). T/H's output signal passes through gray code flash conversion stages generate coarse fine digital representations held analog input level. Decode logic combines multistage data aligns 8-bit word strobed outputs rising edge ENCODE command. MagAmp/Flash architecture AD9059 results three pipeline delays output data.
USING AD9059 Analog Inputs
applied VREF overdrive internal voltage reference gain adjustment (the VREF internally tied directly circuitry). gain offset will vary simultaneously with external reference adjustment with ratio adjustment +2.5 reference varies gain offset mV). Theoretical input voltage range versus reference input voltage calculated from following equations: VRANGE (p-p) VREF/2.5 VMIDSCALE VREF VTOP-OF-RANGE VREF VRANGE/2 VBOTTOM-OF-RANGE VREF VRANGE/2 external reference should have minimum sink/ source current capability ensure complete overdrive internal voltage reference.
Digital Logic V/+3 Systems)
digital inputs outputs AD9059 easily configured interface directly with logic systems. encode power-down (PWRDN) inputs CMOS stages with thresholds making inputs compatible with TTL, CMOS, CMOS logic families. with high speed data converters, encode signal should clean jitter free prevent degradation dynamic performance. AD9059's digital outputs will also interface directly with CMOS logic systems. voltage supply pins (VDD) these CMOS stages isolated from analog voltage supply. varying voltage these supply pins digital output HIGH levels will change systems. pins internally connected AD9059 die. Care should taken isolate supply voltages from analog supply minimize noise coupling into ADCs. AD9059 provides high impedance digital output operation when driven into power-down mode (PWRDN, logic HIGH). (minimum) power-down time should provided before high impedance characteristic required. power-up period should provided ensure accurate output data after reactivation (valid output data available three clock cycles after delay).
Timing
AD9059 provides independent single-ended high impedance (150 analog inputs dual ADCs. Each input requires bias current (typical) centered near +2.5 10%). bias provided user derived from ADC's internal voltage reference. Figure shows cost bias implementation allowing user capacitively couple signals directly into without additional active circuitry. best dynamic performance VREF should decoupled ground with capacitor minimize modulation reference voltage), bias resistor should approximately Figure shows typical connections high performance biasing using ADC's internal voltage reference. components powered from single supply (example analog input signals referenced ground).
Voltage Reference
stable accurate +2.5 voltage reference built into AD9059 (VREF). reference output used gain/offset provide bias analog input signals. internal reference tied circuitry through internal impedance capable providing external drive current (for biasing analog input other user circuitry). Some applications require greater accuracy, improved temperature performance, gain adjustments which cannot obtained using internal reference. external voltage
AD9059 guaranteed operate with conversion rates from MSPS MSPS. MSPS designed operate with encode duty cycle 50%, performance insensitive moderate variations. Pulse width variations (allowing encode signal meet minimum/ maximum HIGH/LOW specifications) will cause degradation performance (refer Figure Timing Diagram). linked ENCODE architecture ADCs, AD9059 cannot operated two-channel ping-pong mode.
REV.
AD9059
Power Dissipation
power dissipation AD9059 specified reflect typical application setup under following conditions: encode MSPS, analog input -0.5 dBFS 10.3 MHz, digital outputs loaded with typical maximum). actual dissipation will vary these conditions modified user applications. Figure shows typical power consumption AD9059 versus encode frequency supply voltage.
AD8041
0.1µF VREF AINA
AD9059
AD8041
(-0.5V +0.5V) AINB
0.1µF VINA p-p) EXTERNAL VREF (OPTIONAL) VREF 0.1µF VINB p-p) 0.1µF AINB
AINA
AD9059
Figure Coupled AD9059 (VIN Inverted)
AD9059
Figure Capacitively Coupled AD9059
power-down function allows users reduce power dissipation when data required. TTL/CMOS HIGH signal (PWRDN) shuts down portions dual brings total power dissipation less than internal bandgap voltage reference remains active during power-down mode minimize reactivation time. power-down function desired, should tied ground. Both channels controlled simultaneously PWRDN pin; they cannot shut down turned independently.
Applications
Figure Digital Receiver
high sampling rate analog bandwidth AD9059 ideal computer video digitizer applications. With full-power analog bandwidth maximum sampling rate, provides sufficient pixel-to-pixel transient settling time ensure accurate MSPS video digitization. Figure shows typical video digitizer implementation AD9059.
AD9059
wide analog bandwidth AD9059 makes attractive variety high performance receiver encoder applications. Figure shows dual typical cost demodulator implementation cable, satellite, wireless modem receivers. excellent dynamic performance higher analog input frequencies encode rates empowers users employ direct sampling techniques (refer Figure Spectral Plot). sampling eliminates simplifies analog mixer filter stages reduce total system cost power.
GREEN
PIXEL CLOCK
H-SYNC
BLUE
AD9059
Figure Video Encoder
REV.
AD9059
+VDD
VREF ENCODE PWRDN D0-D7
VREF
+2.5V
2.5k
Voltage Reference
Digital Inputs
Digital Outputs
Analog Inputs
Figure Equivalent Circuits
Evaluation Board
AD9059/PCB evaluation board provides easy-to-use analog/digital interface dual 8-bit, MSPS ADC. board includes typical hardware configurations variety high speed digitization evaluations. On-board components include AD9059 28-pin SSOP package), optional analog input buffer amplifiers, digital output latches, board timing drivers, configurable jumpers coupling, coupling, power-down function testing. board configured shipment coupling using AD9059's internal reference. coupled analog input applications, amplifiers configured operate unity gain inverters with adjustable offset analog input signals. full-scale drive each analog input signal should into referenced ground. Each amplifier offsets analog signal +VREF (+2.5 typical) center voltage proper input drive. coupled operation, connect (analog input R11), (amplifier output analog input AD9059), (analog input R10), (amplifier output analog input AD9059) using board jumper connectors. coupled analog input applications, amplifiers removed from analog signal paths. analog signals coupled through capacitors C12, each terminated VREF voltage through separate resistors (providing bias current AD9059 analog inputs, AINA AINB).
Analog input signals board should into full-scale drive. coupled operation, connect (analog input feedthrough capacitor), (C12 termination resistor channel (analog input feedthrough capacitor), (C11 termination resistor channel using board jumper connectors. on-board reference voltage used drive external reference applied. standard configuration employs internal voltage reference without external connection requirements. external voltage reference applied board connector input overdrive limited current output AD9059's internal voltage reference. external voltage reference should +2.5 typical. power-down function AD9059 exercised through board jumper connection. Connect PWRDN) power-down mode operation. normal operation, connect (ground PWRDN). encode signal source should TTL/CMOS compatible capable driving termination. digital outputs AD9059 buffered through latches evaluation board available user connector Pins 30-37 Pins 22-29. Latch timing derived from ENCODE clock digital clocking signal provided board user connector Pins
REV.
AD9059
ANALOG IN-A
AD8041Q
0.1µF 10µF 10µF 0.1µF 0.1µF
AD9059RS
0.1µF
C37DRPF
AINA PWRDN
PWRDN
AINB
74ACQ574
74ACQ574
ANALOG IN-B
AD8041Q
0.1µF
74AC00
J11, 0.1µF 0.1µF
0.1µF 0.1µF
0.1µF 0.1µF
0.1µF 10µF
ENCODE
74AC00
DECOUPLING CAPS J12,
74AC00
Figure AD9059 Dual Evaluation Board Schematic
-10-
REV.
AD9059
Figure Evaluation Board Layout (Top)
Figure Evaluation Board Layout (Bottom)
REV.
-11-
AD9059
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
0.212 (5.38)
0.301 (7.64)
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.205 (5.21)
0.311 (7.9)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
-12-
REV.
PRINTED U.S.A.
C2160-10-7/96

Dual 8-Bit, MSPS Converter AD9059 PWRDN AD9059 AINA ADC

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