FEATURES Four On-Chip Track/Hold Amplifiers Simultaneous Sampling Chan
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LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System AD7874
FEATURES Four On-Chip Track/Hold Amplifiers Simultaneous Sampling Channels Fast 12-Bit with Conversion Time/Channel Sample Rate Four Channels On-Chip Reference Input Range Supplies APPLICATIONS Sonar Motor Controllers Adaptive Filters Digital Signal Processing
CONVST
CONTROL LOGIC VIN1 TRACK/ HOLD TRACK/ HOLD TRACK/ HOLD TRACK/ HOLD
INTERNAL CLOCK
VIN2
COMP DATA REGISTERS REFERENCE BUFFER 12-BIT DB11
VIN4
AD7874
GENERAL DESCRIPTION
AD7874 four-channel simultaneous sampling, 12-bit data acquisition system. part contains high speed 12-bit ADC, on-chip reference, on-chip clock four track/hold amplifiers. This latter feature allows four input channels sampled simultaneously, thus preserving relative phase information four input channels, which possible four channels share single track/hold amplifier. This makes AD7874 ideal applications such phased-array sonar motor controllers where relative phase information important. aperture delay four track/hold amplifiers small specified with minimum maximum limits. This allows several AD7874s sample multiple input channels simultaneously without incurring phase errors between signals connected several devices. reference output/reference input facility also allows several AD7874s driven from same reference source. addition traditional accuracy specifications such linearity, full-scale offset errors, AD7874 also fully specified dynamic performance parameters including distortion signal-to-noise ratio. AD7874 fabricated Analog Devices' Linear Compatible CMOS (LC2MOS) process, mixed technology process that combines precision bipolar circuits with low-power CMOS logic. part available 28-pin, 0.6" wide, plastic hermetic dual-in-line package (DIP), 28-terminal leadless ceramic chip carrier (LCCC) 28-pin SOIC.
REFERENCE AGND DGND
PRODUCT HIGHLIGHTS
Simultaneous Sampling Four Input Channels. Four input channels, each with track/hold amplifier, allow simultaneous sampling input signals. Track/hold acquisition time conversion time channel allowing sample rate four channels. Tight Aperture Delay Matching. aperture delay each channel small aperture delay matching between four channels less than Additionally, aperture delay specification upper lower limits allowing multiple AD7874s sample more than four channels. Fast Microprocessor Interface. high speed digital interface AD7874 allows direct connection modern 16-bit microprocessors digital signal processors.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7874-SPECIFICATIONS external. specifications
Parameter SAMPLE-AND-HOLD Acquisition Time2 0.01% Droop Rate2, Small Signal Bandwidth3 Aperture Delay2 Aperture Jitter2, Aperture Delay Matching2 SAMPLE-AND-HOLD DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Peak Harmonic Spurious Noise Intermodulation Distortion Order Terms Order Terms Channel-to-Channel Isolation2 ACCURACY Resolution Relative Accuracy Differential Nonlinearity Positive Full-Scale Error4 Negative Full-Scale Error4 Full-Scale Error Match Bipolar Zero Error Bipolar Zero Error Match ANALOG INPUTS Input Voltage Range Input Current REFERENCE OUTPUTS Error +25°C TMIN TMAX Temperature Coefficient Reference Load Change REFERENCE INPUT Input Voltage Range Input Current Input Capacitance3 LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, Output Voltage, DB0-DB11 Floating-State Leakage Current Floating-State Output Capacitance Output Coding POWER REQUIREMENTS Power Dissipation Version Version Version Units mV/ms
(VDD AGND DGND fCLK TMAX unless otherwise noted.)
Test Conditions/Comments
0.33
0.33
0.33
Bits Volts ppm/°C
Sine Wave, fSAMPLE Sine Wave, fSAMPLE Sine Wave, fSAMPLE kHz, kHz, fSAMPLE
Missing Codes Guaranteed Channel Channel Between Channels Channel Between Channels
Reference Load Current Change (0-500 Reference Load Should Changed During Conversion
2.85/3.15
2.85/3.15
2.85/3.15
min/V
ISOURCE ISINK
COMPLEMENT
Specified Performance Specified Performance CONVST Typically CONVST Typically CONVST Typically
NOTES Temperature ranges follows: Versions: -40°C +85°C; Version: -55°C +125°C. Terminology. Sample tested +25°C ensure compliance. Measured with respect voltage includes bipolar offset error. capacitive loads greater than series resistor required. Specifications subject change without notice.
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AD7874 TIMING CHARACTERISTICS1 otherwise noted.)
Parameter tCONV Versions 32.5 32.5
(VDD
AGND DGND tCLK external unless
Units Conditions/Comments CONVST Pulse Width Setup Time Pulse Width Hold Time Delay Data Access Time after Relinquish Time after Delay Time between Reads CONVST INT, External Clock CONVST INT, External Clock CONVST INT, Internal Clock CONVST INT, Internal Clock Minimum Input Clock Period
Version
tCLK
NOTES Timing Specifications bold print 100% production tested. other times sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level measured with load circuit Figure defined time required output cross derived from measured time taken data outputs change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that time, quoted timing characteristics true relinquish time part such independent external loading capacitances. Specifications subject change without notice.
1.6mA
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
AGND -0.3 DGND -0.3 AGND +0.3 AGND DGND -0.3 AGND AGND Digital Inputs DGND -0.3 Digital Outputs DGND -0.3 Operating Temperature Range Commercial Versions) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation (Any Package) +75°C 1,000 Derates above +75°C mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
OUTPUT
2.1V 50pF
200µA
Figure Load Circuit Access Time
1.6mA
OUTPUT
2.1V 50pF
200µA
Figure Load Circuit Relinquish Time
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7874 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
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AD7874
TERMINOLOGY
ACQUISITION TIME CONFIGURATIONS SOIC
Acquisition Time time required output track/hold amplifiers reach their final values, within LSB, after falling edge (the point which track/ holds return track mode). This includes switch delay time, slewing time settling time full-scale voltage change.
APERTURE DELAY
VIN1 VIN2 CONVST DB11 (MSB)
VIN4 VIN3 AGND (LSB) VIEW (Not Scale)
Aperture Delay defined time required internal switches disconnect hold capacitors from inputs. This produces effective delay sample timing. measured applying step input adjusting CONVST input position until output code follows step input change.
APERTURE DELAY MATCHING
AD7874
Aperture Delay Matching maximum deviation aperture delays across four on-chip track/hold amplifiers.
APERTURE JITTER
DB10 DGND
Aperture Jitter uncertainty aperture delay caused internal noise variation switching thresholds with signal level.
LCCC
VIN1 VIN4 VIN3 VIN2
DROOP RATE
Droop Rate change held analog voltage resulting from leakage currents.
CONVST
CHANNEL-TO-CHANNEL ISOLATION
Channel-to-Channel Isolation measure level crosstalk between channels. measured applying fullscale signal other three inputs. figure given worst case across four channels.
SNR, THD,
AD7874
VIEW (Not Scale)
AGND (LSB)
DB11 (MSB) DB10
DGND
DYNAMIC SPECIFICATIONS section.
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AD7874
FUNCTION DESCRIPTION
Mnemonic VIN1 VIN2 CONVST
Description Analog Input Channel This first four input channels converted conversion cycle. Analog input voltage range Analog Input Channel Analog input voltage range Positive supply voltage, This should decoupled AGND. Interrupt. Active logic output indicating converter status. Figure Convert Start. Logic Input. high transition this input puts track/hold into hold mode starts conversion. four channels converted sequentially, Channel Channel CONVST input asynchronous independent Read. Active logic input. This input used conjunction with enable data outputs. Four successive reads after conversion will read data from four channels sequence, Channel Chip Select. Active logic input. device selected when this input active. Clock Input. external TTL-compatible clock applied this input pin. Alternatively, tying this enables internal laser trimmed clock oscillator. Positive Supply Voltage, Same both pins must tied together package. This should decoupled DGND. Data (MSB). Three-state output. Output coding complement. Data Data Three-state outputs. Digital Ground. Ground reference digital circuitry. Data Data Three-state outputs. Data (LSB). Three-state output. Analog Ground. Ground reference track/hold, reference DAC. Voltage Reference Input. reference voltage part applied this pin. internally buffered, requiring input current only nominal reference voltage correct operation AD7874 Voltage Reference Output. internal analog reference provided this pin. operate AD7874 with internal reference, connected external load capability reference Negative Supply Voltage, Analog Input Channel Analog input voltage range Analog Input Channel Analog input voltage range
ORDERING GUIDE
11-13 15-21
DB11 DB10-DB8 DGND DB7-DB1 AGND
VIN3 VIN4
Model1 AD7874AN AD7874BN AD7874AR AD7874BR AD7874AQ AD7874BQ AD7874SQ3 AD7874SE3
Relative Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C
(dBs)
Accuracy (LSB)
Package Option2 N-28 N-28 R-28 R-28 Q-28 Q-28 Q-28 E-28A
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet availability. Leaded Ceramic Chip Carrier; Plastic DIP; Cerdip; SOIC. Available /883B processing only.
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AD7874
CONVERTER DETAILS EXTERNAL REFERENCE
AD7874 complete 12-bit, 4-channel data acquisition system. comprised 12-bit successive approximation ADC, four high speed track/hold circuits, four-channel analog multiplexer Zener reference. uses successive approximation technique based fast-settling, voltage switching DAC, high speed comparator, fast CMOS high speed logic. Conversion initiated rising edge CONVST. four input track/holds from track hold this edge. Conversion first performed Channel input voltage, then Channel converted four results stored on-chip registers. When four conversions have been completed, goes indicating that data read from these locations. conversion sequence takes either rising clock edges depending synchronization CONVST with CLK. Internal delays reset times bring total conversion time from CONVST going high going 32.5 maximum external clock. AD7874 uses implicit addressing scheme whereby four successive reads same memory location access four data words sequentially. first read accesses Channel data, second read accesses Channel data Individual data registers cannot accessed independently.
INTERNAL REFERENCE
some applications, user require system reference some other external reference drive AD7874 reference input. Figure shows AD586 reference used provide reference required AD7874
+15V +VIN VOUT
INTERNAL COMPARATOR TRACK/HOLD
AD586
REFERENCE CIRCUITRY AGND 2.1R*
AD7874**
3.6k **ADDITIONAL PINS OMITTED CLARITY
Figure AD586 Driving AD7874
TRACK-AND-HOLD AMPLIFIER
AD7874 on-chip temperature compensated buried Zener reference which factory trimmed (see Figure reference voltage provided pin. This reference used provide both reference voltage bipolar bias circuitry. This achieved connecting
track-and-hold amplifier each analog input AD7874 allows accurately convert input sine wave amplitude 12-bit accuracy. input bandwidth track/hold amplifier greater than Nyquist rate even when operated maximum throughput rate. small signal cutoff frequency occurs typically kHz. four track/hold amplifiers sample their respective input channels simultaneously. aperture delay track/hold circuits small and, more importantly, well matched across four track/holds device also well matched from device device. This allows relative phase information between different input channels accurately preserved. also allows multiple AD7874s sample more than four channels simultaneously.
TEMPERATURE COMPENSATION
AD7874
operation track/hold amplifiers essentially transparent user. Once conversion initiated, four channels automatically converted there need select which channel digitized.
ANALOG INPUT
Figure AD7874 Internal Reference
reference also used reference other components capable providing external load. systems using several AD7874s, using device provide other devices ensures good full-scale tracking between AD7874s. Because AD7874 buffered, each AD7874 presents high impedance reference AD7874 drive several AD7874 INs. maximum recommended capacitance normal operation reference required other system uses, should decoupled AGND with resistor series with parallel combination tantalum capacitor ceramic capacitor.
analog input Channel AD7874 shown Figure analog input range into input resistance typically designed code transitions occur midway between successive integer values (i.e., LSB, LSBs, LSBs, LSBs). output code complement binary with FS/4096 V/4096 4.88 ideal input/output transfer function shown Figure
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AD7874
OUTPUT CODE
011.111 011.110
Gain error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedures both cases follows:
Positive Full-Scale Adjust
000.010 000.001 000.000 111.111 111.110 FS=20V 1LSB 4096 1LSB
Apply voltage +9.9927 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Apply voltage -9.9976 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001. alternative scheme adjusting full-scale error systems which external reference adjust voltage until full-scale error channels adjusted out. good full-scale matching channels will ensure small full-scale errors other channels.
TIMING CONTROL
100.001 100.000
INPUT VOLTAGE
Figure Input/Output Transfer Function
OFFSET FULL-SCALE ADJUSTMENT
most Digital Signal Processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale error effect linear does cause problems long input signal within full dynamic range ADC. Invariably, some applications will require that input signal span full analog input dynamic range. such applications, offset full-scale error will have adjusted zero. Figure shows circuit which used adjust offset full-scale errors AD7874 (Channel shown example purposes only). Where adjustment required, offset error must adjusted before full-scale error. This achieved trimming offset driving analog input AD7874 while input voltage below analog ground. trim procedure follows: apply voltage -2.44 (-1/2 LSB) Figure adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000.
INPUT RANGE ±10V AGND VIN1
Conversion initiated AD7874 asserting CONVST input. This CONVST input asynchronous input which independent clock. This essential applications where precise sampling time important. these applications, signal sampling must occur exactly equal intervals minimize errors sampling uncertainty jitter. these cases, CONVST input driven from timer precise clock source. Once conversion started, CONVST should asserted again until conversion complete four channels. applications where precise time interval sampling critical, CONVST pulse generated from microprocessor WRITE READ line gated with decoded address (different AD7874 address). CONVST should derived from decoded address alone because very short CONVST pulses (which occur some microprocessor systems address changing start instruction cycle) could initiate conversion. four track/hold amplifiers from track hold rising edge CONVST pulse. four track/hold amplifiers remain their hold mode while four channels converted. rising edge CONVST also initiates conversion Channel input voltage (VIN1). When conversion complete Channel result stored Data Register four on-chip registers used store conversion results. When result from first conversion stored, conversion initiated voltage held track/hold When conversion been completed voltage held track/hold result stored Data Register goes indicate that conversion process complete. sequence which channel conversions takes place automatically taken care AD7874. This means that user does have provide address lines AD7874 worry about selecting which channel digitized. Reading data from device consists four read operations same microprocessor address. Addressing four on-chip data registers again automatically taken care AD7874.
AD7874*
*ADDITIONAL PINS OMITTED CLARITY
Figure AD7874 Full-Scale Adjust Circuit
REV.
AD7874
first read operation AD7874 after conversion always accesses data from Data Register (i.e., conversion result from VIN1 input). reset high falling edge during this first read operation. second read always accesses data from Data Register address pointer reset point Data Register rising edge CONVST. read operation AD7874 should attempted during conversion. timing diagram AD7874 conversion sequence shown Figure
TRACK/HOLDS INTO HOLD
CONVST
tCONV
tACQUISITION
DATA HIGH- DATA HIGH- HIGH- DATA DATA
DATA
HIGH-IMPEDANCE
HIGH-Z
TIMES SAME FOUR READ OPERATIONS.
Figure AD7874 Timing Diagram
AD7874 DYNAMIC SPECIFICATIONS
Figure AD7874 Plot
Effective Number Bits
AD7874 specified 100% tested dynamic performance specifications well traditional specifications such Integral Differential Nonlinearity. These specifications required signal processing applications such phased array sonar, adaptive filters spectrum analysis. These applications require information ADC's effect spectral content input signal. Hence, parameters which AD7874 specified include SNR, harmonic distortion, intermodulation distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
formula given Equation relates number bits. Rewriting formula, Equation possible measure performance expressed effective number bits (N).
1.76 6.02
effective number bits device calculated directly from measured SNR. Figure shows typical plot effective number bits versus frequency AD7874BN with sampling frequency kHz. effective number bits typically falls between 11.75 11.87 corresponding figures 72.5 73.2
measured signal noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (fs/2) excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal noise ratio sine wave input given (6.02N 1.76) where number bits. Thus ideal 12-bit converter, output spectrum from evaluated applying sine wave signal very distortion input which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7874BN with input signal sampling frequency kHz. obtained from this graph 73.2 should noted that harmonics taken into account when calculating SNR.
Figure Effective Numbers Bits Frequency
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AD7874
Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise
Total Harmonic Distortion (THD) ratio harmonics value fundamental. AD7874, defined
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion
Harmonic Spurious Noise defined ratio value next largest component output spectrum fs/2 excluding value fundamental. Normally, value this specification will determined largest harmonic spectrum, parts where harmonics buried noise floor peak will noise peak.
Linearity Plot
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs. this case, input consists two, equal amplitude, distortion sine waves. Figure shows typical plot AD7874.
When sine wave specified frequency applied input AD7874 several million samples taken, histogram showing frequency occurrence each 4096 codes generated. From this histogram data possible generate integral linearity plot shown Figure This shows very good integral linearity performance from AD7874 input frequency kHz. absence large spikes plot shows good differential linearity. Simplified versions formulae used outlined below.
(o)) 4096 INL(i
where INL(i) integral linearity code V(fs) V(o) estimated full-scale offset transitions, V(i) estimated transition code. V(i), estimated code transition point derived follows:
cum(i
where peak signal amplitude, number histogram samples
cum(i
(n)occurrences
Figure AD7874 Plot
Figure AD7874 Plot
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AD7874
MICROPROCESSOR INTERFACING
TIMER ADDRESS
AD7874 high speed timing allows direct interfacing processors well modern 16-bit microprocessors. Suitable microprocessor interfaces shown Figures through
AD7874-ADSP-2100 Interface
ADDR DECODE
CONVST
Figure shows interface between AD7874 ADSP-2100. Conversion initiated using timer which allows very accurate control sampling instant four channels. AD7874 line provides interrupt ADSP2100 when conversion completed four channels. four conversion results then read from AD7874 using four successive reads same memory address. following instruction reads four results (this instruction repeated four times read four results sequence): DM(ADC) where ADSP-2100 register AD7874 address.
DMA13 ADDRESS DMA0 CONVST ADDR DECODE TIMER
TMS32010
AD7874*
DB11
DATA *ADDITIONAL PINS OMITTED CLARITY
Figure AD7874-TMS32010 Interface
AD7874-TMS320C25 Interface
ADSP-2100 (ADSP-2101/ ADSP-2102)
IRQn DMRD (RD)
AD7874*
DB11 DMD15 DATA DMD0 ADDITIONAL PINS OMITTED CLARITY
Figure shows interface between AD7874 TMS320C25. with previous interfaces, conversion initiated with timer processor interrupted when conversion sequence completed. TMS320C25 does have separate output drive AD7874 input directly. This generated from processor STRB outputs with addition some logic gates. signal OR-gated with signal provide WAIT state required read cycle correct interface timing. Conversion results read from AD7874 using following instruction: D,ADC where Data Memory address AD7874 address.
TIMER ADDRESS
Figure AD7874-ADSP-2100 Interface
AD7874-ADSP-2101/ADSP-2102 Interface
interface outlined Figure also forms basis interface between AD7874 ADSP-2101/ADSP-2102. READ line ADSP-2101/ADSP-2102 labeled this interface, pulse width processor programmed using Data Memory Wait State Control Register. instruction used read four results outlined ADSP-2100.
AD7874-TMS32010 Interface
ADDR DECODE
CONVST
TMS320C25
INTn STRB READY
AD7874*
interface between AD7874 TMS32010 shown Figure Once again conversion initiated using external timer TMS32010 interrupted when four conversions have been completed. following instruction used read conversion results from AD7874: D,ADC where Data Memory address AD7874 address.
DB11
DATA *ADDITIONAL PINS OMITTED CLARITY
Figure AD7874-TMS320C25 Interface
-10-
REV.
AD7874
Some applications require that conversion initiated microprocessor rather than external timer. option decode AD7874 CONVST from address that write operation starts conversion. Data read conversion sequence before. Figure shows example initiating conversion using this method. Note that interfaces, read operation should attempted during conversion.
AD7874-MC68000 Interface AD7874-8086 Interface
interface between AD7874 MC68000 shown Figure before, conversion initiated using external timer. AD7874 line used interrupt processor alternatively, software delays ensure that conversion been completed before read AD7874 attempted. Because nature interrupts, 68000 requires additional logic (not shown Figure allow interrupted correctly. further information 68000 interrupts, consult 68000 users manual. MC68000 outputs used generate separate input signal AD7874. used drive 68000 DTACK input allow processor execute normal read operation AD7874. conversion results read using following 68000 instruction: MOVE.W ADC,D0 where 68000 register AD7874 address.
ADDRESS ADDR DECODE DTACK TIMER
Figure shows interface between AD7874 8086 microprocessor. Unlike previous interface examples, microprocessor initiates conversion. This achieved gating 8086 signal with decoded address output (different AD7874 address). AD7874 line used interrupt microprocessor when conversion sequence completed. Data read from AD7874 using following instruction: AX,ADC where 8086 accumulator AD7874 address.
ADDRESS
8086
ADDR DECODE
LATCH
AD7874*
CONVST DB11
AD15 ADDRESS/DATA *ADDITIONAL PINS OMITTED CLARITY
CONVST
MC68000
Figure AD7874-8086 Interface
AD7874*
DB11
DATA *ADDITIONAL PINS OMITTED CLARITY
Figure AD7874-MC68000 Interface
REV.
-11-
AD7874
APPLICATIONS Vector Motor Control
current drawn motor split into components: produces torque other produces magnetic flux. optimal performance motor, these components should controlled independently. conventional methods controlling three-phase motor, current voltage) supplied motor frequency drive basic control variables. However, both torque flux functions current voltage) frequency. This coupling effect reduce performance motor because, example, torque increased increasing frequency, flux tends decrease. Vector control motor involves controlling phase addition drive current frequency. Controlling phase motor requires feedback information position rotor relative rotating magnetic field motor. Using this information, vector controller mathematically transforms three phase drive currents into separate torque flux components. AD7874, with four-channel simultaneous sampling capability, ideally suited vector motor control applications.
MICROPROCESSOR TORQUE FLUX CONTROL LOOP CALCULATIONS THREE PHASE INFORMATION
block diagram vector motor control application using AD7874 shown Figure position field derived determining current each phase motor. Only phase currents need measured because third calculated phases known. Channel Channel AD7874 used digitize this information. Simultaneous sampling critical maintain relative phase information between channels. current sensing isolation amplifier, transformer Hall effect sensor used between motor AD7874. Rotor information obtained measuring voltage from inputs motor. Channel Channel AD7874 used obtain this information. Once again relative phase channels important. microprocessor used perform mathematical transformations control loop calculations information back AD7874.
DRIVE CIRCUITRY
PHASE MOTOR
TORQUE SETPOINT FLUX SETPOINT VIN1 TRANSFORMATION TORQUE FLUX CURRENT COMPONENTS VIN2 ISOLATION AMPLIFIERS
AD7874*
VIN3 VIN4 VOLTAGE ATTENUATORS *ADDITIONAL PINS OMITTED CLARITY
Figure Vector Motor Control Using AD7874
-12-
REV.
AD7874
MULTIPLE AD7874s
Figure shows system where number AD7874s configured handle multiple input channels. This type configuration common applications such sonar, radar, etc. AD7874 specified with maximum minimum limits aperture delay. This means that user knows maximum difference sampling instant between channels. This allows user maintain relative phase information between different channels. common read signal from microprocessor drives input AD7874s. Each AD7874 designated unique address selected address decoder. reference output AD7874 number used drive reference input other AD7874s circuit shown Figure drive several AD7874 pins. Alternatively, external system reference used drive inputs. common reference ensures good full-scale tracking between channels.
VCH1 VCH2 VCH3 VCH4
input signal connects buffer amplifier driving analog input ADC. shorting plug omitted, wire link used connect input signal component grid. Microprocessor connections board made 26contact connector, SKT8, pinout which shown Figure This connector contains data, control status signals AD7874 (with exception input CONVST input which provided SKT5 SKT7, respectively). also contains decoded STRB inputs which necessary TMS32020 interfacing (and also 68000 interfacing although labels 68000 different). Note that AD7874 input must decoded prior AD7874 evaluation board. SKT1, SKT2, SKT3 SKT4 provide inputs VIN1, VIN2, VIN3, VIN4 respectively. Assuming place, these input signals four buffer amplifiers, IC1, before being applied AD7874. external clock source optional; there shorting plug (LK5) AD7874 input which must connected either (for ADCs internal clock) SKT5. SKT6 SKT7 provide reference CONVST inputs respectively. Shorting plug provides option using external reference ADCs internal reference.
STRB DB11
AD7874(1)
VCH5 VCH6 VCH7 VCH8
AD7874(2)
ADDRESS DECODE
ADDRESS
DB10
VCHm VCHm+1 VCHm+2 VCHm+3
AD7874(n)
Figure Multiple AD7874s Multichannel System
DATA ACQUISITION BOARD
Figure SKT8, Connector Pinout
POWER SUPPLY CONNECTIONS
Figure shows AD7874 data acquisition circuit. corresponding printed circuit board (PCB) layout silkscreen shown Figures 26-contact connector provides microprocessor connection board. component grid provided near analog inputs which used provide antialiasing filters analog input channels provide signal conditioning circuitry. facilitate this option, four shorting plugs (labeled PCB) provided analog inputs, plug input. shorting plug particular channel used,
requires analog power supplies digital supply. analog supplies labeled range both supplies (see silkscreen Figure 23). Connection digital supply made SKT8. supply supply required AD7874 generated from voltage regulators (IC3 IC4) supplies.
REV.
-13-
AD7874
SKT1 SKT2 SKT3 SKT4 AGND DGND
79L05
78L05 AD713
CONVST SKT6
VIN1
CONVST DB11
SKT8 DATA
AD7874
SKT5
DGND
REFERENCE SKT6
Figure Data Acquisition Circuit Using AD7874
Figure Silkscreen Figure
-14-
REV.
AD7874
Figure Component Side Layout Circuit Figure
Figure Solder Side Layout Circuit Figure
REV.
-15-
AD7874
SHORTING PLUG OPTIONS COMPONENT LIST
There seven shorting plug options which must before using board. These outlined below: LK1-LK4 Connects analog inputs buffer amplifiers. analog inputs also connected component grid signal conditioning. Selects either AD7874 internal clock external clock source. Selects either AD7874 internal reference external reference source. Connects AD7874 input directly input SKT8 decoded STRB input. This shorting plug setting depends microprocessor, e.g., TMS32020 68000 require decoded signal.
LK1, LK2, LK4, LK5, SKT1, SKT2, SKT3, SKT4, SKT5, SKT6, SKT7 SKT8
Sockets
26-Contact (2-Row) Connector
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-28)
SOIC (R-28)
Cerdip (Q-28)
0.100 (2.54) 0.064 (1.63)
LCCC (E-28A)
0.055 (1.40) 0.045 (1.14) 0.075 (1.91)
0.028 (0.71) 0.022 (0.56)
BOTTOM VIEW
0.040 (1.02 45°) PLCS 0.458 (11.63) 0.442 (11.23)
0.020 (0.51 45°)
NOTES THIS DIMENSION CONTROLS OVERALL PACKAGE THICKNESS. APPLIES FOUR SIDES. TERMINALS GOLD PLATED.
-16-
REV.
PRINTED U.S.A.
0.050 0.005 (1.27 0.13)
INDEX
C1388a-5-5/91
AD713 Quad AD7874 Analog-to-Digital Converter MC78L05 Regulator MC79L05 Regulator 74HC00 Quad NAND Gate Capacitors Capacitors Pull-Up Resistors Shorting Plugs
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