16-Bit/20-Bit Multi-Range with 4-Bit Latch Features General Descr

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16-Bit/20-Bit Multi-Range with 4-Bit Latch Features General Descr

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CS5525 CS5526
16-Bit/20-Bit Multi-Range with 4-Bit Latch
Features General Description
16-bit CS5525 20-bit CS5526 highly integrated converters which include instrumentation amplifier, (programmable gain amplifier), eight digital filters, self system calibration circuitry. converters designed provide their negative supply which enables their on-chip instrumentation amplifiers measure bipolar ground-referenced signals ±100 directly supplying with -2.5 with ±2.5 signals (with respect ground) measured. digital filters provide programmable output update rates between 3.76 (XIN 32.768 kHz). Output word rates increased approximately using kHz. Each filter designed settle full accuracy output update rate conversion cycle. filters with word rates less (XIN 32.768 kHz) reject both line interference simultaneously. power, single conversion settling time, programmable output rates, ability handle negative input signals make these single supply products ideal solutions isolated non-isolated applications. ORDERING INFORMATION page
Delta-Sigma Converter Bipolar/Unipolar Input Ranges Chopper Stabilized Instrumentation Amplifier On-Chip Charge Pump Drive Circuitry 4-Bit Output Latch Simple three-wire serial interface Programmable Output Word Rates
SPIand MicrowireCompatible Schmitt Trigger Serial Clock (SCLK) 3.76 202Hz (XIN 32.768 kHz) 11.47 (XIN kHz) Linearity Error: 0.0015%FS Noise Free Resolution: 18-bits
Output Settles Conversion Cycle Simultaneous 50/60 Noise Rejection System Self-Calibration with
Read/Write Registers Single Analog Supply +3.0 Digital Supply Power Mode Consumption:
Input Ranges
AGND VREF+
VREF-
DGND
AIN+ AIN-
Programmable Gain
Differential Order Delta-Sigma Modulator
Digital Filter
Calibration Register
SCLK
Control Register
Latch Calibration Memory Calibration Clock Gen.
Output Register
XOUT
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved)
DS202F1
CS5525 CS5526
VA+, ±5%; VREF+ VREF- AGND, -2.1 FCLK 32.768 kHz, (Output Word Rate) Bipolar Mode, Input Range ±100 Notes CS5525 Parameter CS5526 Unit Bits nV/°C ppm/°C µA/V
ANALOG CHARACTERISTICS
Accuracy Linearity Error Missing Codes Bipolar Offset (Note Unipolar Offset (Note Offset Drift (Notes Bipolar Gain Error Unipolar Gain Error Gain Drift (Note Voltage Reference Input Range (VREF+) (VREF-) Common Mode Rejection Input Capacitance Current (Note
±0.0015 ±0.003
±0.0007 ±0.0015
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. LSB16 CS5525, LSB20 CS5526. Drift over specified temperature range after calibration power-up section data sheet which discusses input models page
NOISE (Notes
Output Rate Filter (Hz) Frequency 3.76 3.27 7.51 6.55 15.0 12.7 30.1 25.4 60.0 50.4 123.2 (Note 103.6 168.9 (Note 141.3 202.3 (Note 169.2 Input Range, (Bipolar/Unipolar Mode) 20.0
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown Peak-to-Peak Noise multiply ranges output rates. input ranges <100 output word rates 32.768 chopping frequency used. Specifications subject change without notice.
DS202F1
CS5525 CS5526
ANALOG CHARACTERISTICS (Continued)
Parameter Unit
Analog Input Common Mode Signal AIN+ AINBipolar/Unipolar Mode -1.8 -2.5 Range Range AGND Range Range Common Mode Rejection Input Capacitance Current AIN+ AIN(Note Range Range System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode (Note Offset Calibration Range Bipolar/Unipolar Mode (Note Power Supplies Power Supply Currents (Normal Mode) INBV
Power Consumption Normal Mode Power Mode Standby Sleep Positive Supplies (Note
-0.150 1.85
0.950 2.65
µA/V
17.5 38.5 0.70 1.75 3.50
32.5 71.5 1.30 3.25 ±12.5 ±27.5 ±0.5 ±1.25 ±2.50
Power Supply Rejection
Notes: minimum Full Scale Calibration Range (FSCR) limited maximum allowed gain register value (with margin). maximum FSCR limited modulator's density range. maximum full scale signal limited saturation circuitry within internal signal path. outputs unloaded. input CMOS levels.
DS202F1
CS5525 CS5526
DIGITAL CHARACTERISTICS VA+, ±5%;
Notes 12.)) Parameter High-Level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+) 0.45 (VA+) (VD+) (VD+) Cout Unit
Low-Level Input Voltage
High-Level Output Voltage Pins Except (Note CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance Notes: measurements performed under static conditions.
Iout -100 unless stated otherwise. (VOH Iout µA.)
DIGITAL CHARACTERISTICS
Notes 12.)) Parameter High-Level Input Voltage
±5%; ±10%; Symbol 0.54 (VD+) 0.45 (VA+) (VD+) (VD+) Cout 0.16 Unit
Pins Except SCLK SCLK Pins Except SCLK SCLK
Low-Level Input Voltage
High-Level Output Voltage Pins Except SDO, Iout -400 CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance
DS202F1
CS5525 CS5526
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/2 1/fout Unit
RECOMMENDED OPERATING CONDITIONS (AGND, DGND Note 14.))
Parameter Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: voltages with respect ground. Positive Digital Positive Analog (VREF+) (VREF-) Symbol VRefdiff 4.75 -1.8 -2.1 5.25 5.25 -2.5 Unit
ABSOLUTE MAXIMUM RATINGS (AGND, DGND Note 14.)
Parameter Power Supplies (Note Positive Digital Positive Analog Negative Potential (Note (Note VREF pins Pins Symbol IOUT VINR VINA VIND Tstg -0.3 -0.3 +0.3 -0.3 -0.3 +6.0 +6.0 -3.0 (VA+) (VA+) (VD+) Unit
Negative Bias Voltage Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: should more negative than Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS202F1
CS5525 CS5526
±5%; ±10% ±5%; Input Levels: Logic Logic VD+; pF.)) Parameter Master Clock Frequency (Note Internal Clock External Clock (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note Symbol trise tfall tost tpor 1003 cycles 32.768 32.768 Unit
SWITCHING CHARACTERISTICS
Master Clock Duty Cycle Rise Times
Fall Times
Start-up Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing Serial Clock Frequency SCLK Falling Falling continuous running SCLK (Note Serial Clock Pulse Width High Pulse Width Write Timing Enable Valid Latch Clock
Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
SCLK
Read Timing Data Valid
SCLK Falling Data Rising Hi-Z
Notes: Device parameters specified with 32.768 clock; however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. Applicable when SCLK continuously running.
DS202F1
CS5525 CS5526
SCLK
Continuous Running SCLK Timing (Not Scale)
MSB-1
SCLK
Write Timing (Not Scale)
MSB-1
SCLK
Read Timing (Not Scale)
DS202F1
CS5525 CS5526
GENERAL DESCRIPTION
CS5525 CS5526 16-bit 20-bit compatible converters which include chopperstabilized instrumentation amplifier input, on-chip programmable gain amplifier. They both optimized measuring low-level unipolar bipolar signals process control medical applications. CS5525/26 also include fourth order deltasigma modulator, calibration microcontroller, eight digital filters, 4-bit analog latch, serial port. digital filters provide eight different output update rates. CS5525/26 include (Charge Pump Drive) output (shown Figure provides negative bias voltage on-chip instrumentation amplifier when used with combination external diodes capacitors. This enables CS5525/26 measure negative voltages with re+5V Analog Supply
spect ground, making converters ideal thermocouple temperature measurements.
Theory Operation
CS5525/26 converters designed operate from single analog supply provide several different input ranges. Analog Characteristics section page details. Figure illustrates CS5525/26 connected generate their negative bias supply using on-chip (Charge Pump Drive). This enables CS5525/26 measure ground referenced signals with magnitudes down (Negative Bias Voltage, approximately -2.1 this example). Figure illustrates charge pump circuit when converters powered from +3.0 digital supply. Alternatively, negative bias supply generated from negative supply voltage resistive divider illustrated Figure
2.5V Input BAV199 Note: Cold-junction measurement performed second multiplexer. Logic Outputs: Switch from AGND. AINAGND VREF+ VREF-
XOUT 32.768 Optional Clock Source
AIN+
CS5525 CS5526 SCLK
Serial Data Interface
DGND
0.015
Optional, Charge Pump Drive section. Charge-pump network only 32.768 kHz.
1N4148
1N4148
Figure CS5525/26 Configured on-chip charge pump supply NBV.
DS202F1
CS5525 CS5526
Figure illustrates CS5525/26 connected measure ground referenced unipolar signals positive polarity using input voltage ranges converter. ranges signal must have common mode near +2.5 (NBV 0V). CS5525/26 optimized measurement thermocouple outputs, they also well suited measurement ratiometric bridge transducer outputs. Figure illustrates CS5525/26 connected measure output ratiometric differential bridge transducer while operating from single supply.
2N5087 similar 10µF
34.8K 30.1K
2.0K
2.1K
Figure Charge Pump Drive Circuit
Figure Alternate Circuits.
Analog Supply
XOUT 32.768 Optional Clock Source
2.5V
VREF+ VREFCS5525 CS5526
Input
AIN+
AIN11 SCLK AGND DGND
Serial Data Interface
Figure CS5525/26 Configured ground-referenced Unipolar Signals.
DS202F1
CS5525 CS5526
Analog Supply
VREF+ VREFAIN+ CS5525 CS5526 XOUT 32.768 100kHz Optional Clock Source
30mV F.S.
AINSCLK AGND DGND
Serial Data Interface
Figure CS5525/26 Configured Single Supply Bridge Measurement.
System Initialization
When power CS5525/26 applied, they held reset condition until their 32.768 oscillators have started their start-up counter-timer elapses. high 32.768 crystal, oscillators take 400-600 start. converter's counter-timer counts more than 1024 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register set. reset initiated time writing logic (Reset System) configuration register. This automatically sets until written logic configuration register read. After reset, on-chip registers initialized following states converters ready perform conversions.
configuration register: offset register: gain register: 000040(H) 000000(H) 800000(H)
Command Operation
CS5525/26 include microcontroller with five registers used control converter. Each register 24-bits length except 8-bit command register (command, configuration, offset, gain, conversion data). After system initialization reset, serial port initialized command mode converter stays this mode until valid 8-bit command received (the first 8-bits into serial port). Table lists valid commands. Once valid 8-bit command read write command word) received interpreted command register, serial port enters data mode. data mode next serial clock pulses shift data either into serial port serial clock pulses needed set-up register selected). Table configuring CS5525/26.
DS202F1
CS5525 CS5526
Reading/Writing On-Chip Registers
CS5525/26's offset, gain, configuration registers read/writable while conversion data register read only. perform read from specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. perform write specific register, command word must logic PS/R bits must logic (MSB) must logic register written selected with RSB2-RSB0 bits command word. Figure illustrates serial sequence necessary write read from serial port. Set-up Registers chosen with RSB2RSB0 bits, registers read written following sequence: Offset, Gain Configuration. This accomplished following 8-bit command word with three 24-bit data words total data bits.
Command Register
D7(MSB) NAME Command Bit, RSB2 VALUE D3-D1 Single Conversion, Continuous Conversions, Read/Write, Register Select Bit, RSB2-RSB0 RSB1 RSB0 PS/R FUNCTION Null command operation). command bits, including must Logic executable commands. Single Conversion active. Perform conversion. Continuous Conversions active. Perform conversions continuously. Write selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Power Save
Power Save/Run, PS/R
Table Command
DS202F1
CS5525 CS5526
Configuration Register
D23(MSB) D23-D20 D15-D13 NAME Latch Outputs, A3-A0 Used, Chop Frequency Select, Used, Power Mode, Word Rate, WR2-0 Note: 32.768kHz VALUE 0000 110/111 Must always logic Amplifier chop frequency 32768 Amplifier chop frequency Must always logic Normal Mode Reduced Power mode 15.0 (2182 cycles) 30.1 (1090 cycles) 60.0 (546 cycles) 123.2 (266 cycles) 168.9 (194 cycles) 202.3 (162 cycles) 3.76 (8722 cycles) 7.51 (4362 cycles) Bipolar Measurement mode Unipolar Measurement mode (assumes VREF 2.5V) Used. Charge Pump Enabled goes Hi-Z output state. Normal Operation Activate Reset cycle. return Normal Operation write zero. reset occurred been cleared (read only). Valid Reset occurred. (Cleared when read.) Port Flag mode inactive Port Flag mode active Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) Done Flag cleared (read only). Calibration Conversion cycle completed (read only). Normal Operation calibration) Offset Self-Calibration Gain Self-Calibration Offset Self-Calibration followed Gain Self-Calibration used. Offset System Calibration Gain System Calibration Used. FUNCTION Latch Output Pins A3-A0 mimic D23-D20 Register bits.
D11-D9
Unipolar/Bipolar, Gain Bits, G2-G0
D2-D0
Pump Disable, Reset System, Reset Valid Port Flag, Power Save Select, Done Flag, Calibration Control Bits, CC2-CC0
indicates value after part reset Table Configuration Register DS202F1
CS5525 CS5526
SCLK
Command Time SCLKs
Data Time SCLKs SCLKs Set-up Registers) Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs SCLKs Set-up Registers) Read Cycle
SCLK
Command Time SCLKs
XIN/OWR Clock Cycles
SCLKs Clear Flag
XIN/OWR clock cycles each conversion except first conversion which will take XIN/OWR clock cycles
Continuous Conversion Read
Data Time SCLKs
Figure Command Data Word Timing.
DS202F1
CS5525 CS5526
Analog Input
Figure illustrates block diagram analog input signal path inside CS5525/26. front consists chopper-stabilized instrumentation amplifier with gain programmable gain section. instrumentation amplifier powered from from (Negative Bias Voltage) allowing CS5525/26 operated either analog input configurations. biased negative voltage between -1.8 -2.5 tied AGND. choice operating mode voltage depends upon input signal common mode voltage. input ranges, input signals AIN+ AIN- amplified instrumentation amplifier. ground referenced signals with magnitudes less then should biased with -1.8 -2.5 tied between -1.8 -2.5 (Common Mode Signal) input AIN+ AIN- must stay between -0.150 0.950 ensure proper operation. Alternatively, tied AGND where input (Common Mode Signal) AIN+ AIN- must stay between 1.85 2.65 ensure that amplifier operates properly. input ranges, instrumentation amplifier bypassed input signals directly connected Programmable Gain block. With tied between -1.8 -2.5 (Common Mode Signal) input AIN+ AIN- must stay between VA+. Alternatively, tied AGND where input (Common Mode Signal) AIN+ AIN- pins span entire range between AGND VA+. CS5525/26 accommodate full scale ranges other than performing system calibration within limits specified. Calibration section more details. Another change full scale range increase decrease voltage reference other than Voltage Reference section more details. Three factors operating limits input span. They include: instrumentation amplifier saturation, modulator density, lower reference voltage. When range selected, input signal (including common mode voltage amplifier offset voltage) must cause amplifier saturate either input stage output stage. prevent saturation absolute voltages AIN+ AINmust stay within limits specified (refer `Analog Input' table page Additionally, differential output voltage amplifier must exceed equation ABS(VIN VOS) defines differential output limit, where (AIN+) (AIN-) differential input voltage absolute maximum offset voltage instrumentation amplifier (VOS will exceed mV).
VREF+ VREF-
AIN+
AINNBV
Programmable Gain
Differential order deltasigma modulator
Digital Filter
Figure Block Diagram Analog Signal Path DS202F1
CS5525 CS5526
Nominal(1) Differential Input -(1) Max. Input 0.75 1.65
Input Range(1)
Max. Differential Output Amplifier
VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Gain Factor 2.272727. 1.25
Note:
converter's actual input range, delta-sigma's nominal full scale input, delta-sigma's maximum full scale input scale directly with value voltage reference. values table assume VREF voltage. Table Relationship between Full Scale Input, Gain Factors, Internal Analog Signal Limitations
differential output voltage from amplifier exceeds amplifier saturate, which will cause measurement error. input voltage into modulator must cause modulator exceed percent high percent density. nominal full scale input span modulator (from percent percent density) determined VREF voltage divided Gain Factor. Table determine CS5525/26 being used properly. example, range determine nominal input voltage modulator, divide VREF (2.5 Gain Factor (2.2727). When smaller voltage reference used, resulting code widths smaller causing converter output codes exhibit more changing codes fixed amount noise. Table based upon VREF other values VREF, values Table must scaled accordingly. Figure's illustrate input models VREF pins. dynamic input current each pins determined from models shown dependent upon setting (Chop Frequency Select) bit. effective input impedance AIN+ AIN- pins remains constant three level measurement ranges mV). input current lowest with cleared logic
DS202F1
Note: Residual noise appears converter's baseband output word rates greater than logic setting logic amplifier's chop frequency chops 32768 eliminating residual noise, increasing current. Note that C=48pF input current modeling only. physical input capacitance `Input Capacitance' specification under `Analog Characteristics' page
25mV, 55mV, 100mV Ranges
25mV fVos
48pF
32.768
Ranges
AIN+ AINC 32pF
[(VAIN+) (VAIN-
32.768 Figure Input models AIN+ AIN- pins
VREF+ VREFC 16pF
[(VREF+) (VREF-)] 32.768
Figure Input model VREF+ VREF- pins.
CS5525 CS5526
Charge Pump Drive
(Charge Pump Drive) converters used with external components (shown Figure develop appropriate negative bias voltage pin. When used generate NBV, voltage regulated with internal regulator loop referenced VA+. Therefore, change results proportional change NBV. With NBV's regulation proportional approximately -2.1 Figure illustrates means supplying voltage from supply. ground based signals with instrumentation amplifier engaged (when 25mV, 55mV, 100mV ranges), voltage should time less negative than -1.8 more negative than -2.5 prevent excessive voltage stress chip voltage should more negative than -3.0 components Figure preferred components filter. However, smaller capacitors used with acceptable results. ensures very ripple NBV. Intrinsic safety requirements prohibit electrolytic capacitors. this case, 0.47 ceramic capacitors parallel used. itself tri-state output enters tri-state whenever converters placed into Sleep Mode, Standby Mode, when charge pump disabled (when Pump Disable bit, configuration register, set). Once tristate, digital current increase this output floats near digital supply. ensure stays near ground minimize digital current, resistor between DGND (see Figure resistor left out, digital supply current increase from
Voltage Reference
CS5525/26 specified operation with reference voltage between VREF+ VREF- pins devices. single-ended reference voltage, such LT1019-2.5, reference's output connected VREF+ CS5525/26. ground reference LT10192.5 connected VREF- pin. differential voltage between VREF+ VREF- voltage from however, VREF- below analog ground.
Calibration
CS5525/26 offer five different calibration functions including self calibration system calibration. However, after CS5525/26 reset, they perform measurements without being calibrated. this case, converters will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words ±100 range. initial offset gain errors internal circuitry chips will remain. gain offset registers, which used both self system calibration, used zero full-scale points converter's transfer function. offset register 2-24 proportion input span (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). converters typically trim percent input span. gain register spans from 2-23). decimal equivalent meaning gain register
where binary numbers have value either zero corresponds MSB). Refer Table details.
DS202F1
CS5525 CS5526
Offset Register
Register
Reset
Sign
2-20 2-21 2-22 2-23 2-24
2-19
represents 2-24 proportion input span (bipolar span times unipolar span) Offset data word bits align (bit MSB-4 offset register changes MSB-4 data)
Gain Register
Register
Reset
2-23
gain register span from (2-2-23). After Reset other bits Table Table Offset Gain Registers
offset gain calibration steps each take conversion cycle complete. calibration step, calibration control bits will back logic (Done Flag) will logic combination self-calibration (CC2-CC0= 011; offset followed gain), calibration will take conversion cycles complete will after gain calibration completed. will cleared time data register, offset register, gain register, setup register read. Reading configuration register alone will clear bit.
modulator connected together then routed VREF- shown Figure self-calibration gain, differential inputs modulator connected VREF+
CLOSED AIN+
Self Calibration
CS5525/26 offer both self offset self gain calibrations. self-calibration offset ranges, converter internally ties inputs instrumentation amplifier together routes them AIN- shown Figure proper self-calibration offset occur ranges, AIN- must proper common-mode-voltage (i.e. AIN- must between -1.8 -2.5 self-calibration offset ranges, inputs
Figure Self Calibration Offset (Low Ranges).
OPEN
AIN+
CLOSED OPEN
CLOSED
AINVREF-
Figure Self Calibration Offset (High Ranges).
DS202F1
CS5525 CS5526
OPEN AIN+ AINVREF+ Reference VREFCLOSED CLOSED OPEN
External Connections AIN+ AINX20
Figure Self Calibration Gain (All Ranges).
Figure System Calibration Offset (Low Ranges).
VREF- shown Figure input range other than range, modulator gain error completely calibrated out. This lack accurate full scale voltage internal chips. range exception because external reference voltage nominal used full scale voltage. addition, when self-calibration gain performed input ranges, instrumentation amplifier's gain calibrated. These factors leave converters with gain error ±20% after self-calibration gain. Therefore, system gain required better accuracy, except range.
External Connections AIN+ AINX20
Figure System Calibration Offset (High Ranges).
External Connections Full cale INX20
System Calibration
system calibration functions, user must supply converters calibration signals which represent ground full scale. When system offset calibration performed, ground reference signal must applied converter. Figures shown Figures user must input signal representing positive full scale point perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications).
Figure System Calibration Gain (Low Ranges)
External Connections AIN+ Full Scale AINX20
Figure System Calibration Gain (High Ranges).
DS202F1
CS5525 CS5526
Assuming system provide known voltages, equations allow user manually compute calibration register's values based uncalibrated conversions. offset gain calibration registers used adjust typical conversion follows: Co>>4) 223. Calibration performed using following equations: (Rc0/G Ru0) where (Rc1 Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that gain offset registers default {gain register 0x800000 (Hex) offset register 0x000000 (Hex)}. bits. equations work correctly results with four zeros right).
Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near devices, user should wait each calibration step completed before reading writing serial port. maximum accuracy, calibrations should performed offset gain each gain setting (selected changing G2-G0 bits configuration register). factory calibration performed using system calibration capabilities CS5525/26, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converters when power first applied system, when gain range changed. final tips include ways determine when calibration complete: wait fall. falls logic (Port Flag) configuration register logic poll (Done Flag) configuration register which completion calibration. Whichever method used, calibration control bits (CC2CC0) will return logic upon completion calibration.
variables defined below.
First calibration voltage Second calibration voltage (greater than Result uncalibrated conversion Result uncalibrated conversion (20-bit integer complement) Result uncalibrated conversion (20-bit integer complement) Result conversion Desired calibration result converting (20-bit integer complement) Desired calibration result converting (20-bit integer complement) Offset calibration register value (24-bit complement) Gain calibration register value (24-bit integer)
shift right operator (e.g. shifted right bits) shift left operator (e.g. x<<2 shifted left bits)
Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. System calibration also limited intrinsic gain errors instrumentation amplifier modulator. gain calibrations
Note: shift operators used here align decimal points words various lengths. Data right decimal point used calculations shown. CS5525 conversion results (Ru, Rc.) bits instead DS202F1
CS5525 CS5526
input signal reduced point which gain register reaches upper limit (decimal) [FFFFFF Hex] (this most likely occur with input signal approximately nominal range). Alternatively, input signal increased point which modulator reaches one's density upper limit (this most likely occur with input signal approximately times nominal range). Also, full scale inputs larger than nominal full scale value range selected, there some voltage which various internal circuits saturate limited amplifier headroom (this most likely occur range setting when
Serial Port Initialization
serial port initialized command mode whenever power-on reset performed inside converter, when port initialization sequence completed, whenever command byte, data word sequence completed. port initialization sequence involves clocking more) bytes 1's, followed byte with following contents (11111110). This sequence places chips command mode where waits valid command.
Performing Conversions (With
Setting (Single Conversion) command word logic with other command bits CS5525/CS5526 will perform conversion. completion conversion (Done Flag) configuration register will logic user read configuration register determine set. been set, command issued read conversion data register obtain conversion data word. configuration register will cleared logic when data register, gain register, offset register, set-up registers read. Reading only configuration register will clear flag bit. command issued converters while they performing conversion, filter will restart convolution cycle perform conversion.
Analog Output Latch Pins
A3-A0 pins converters mimic D23D20 bits configuration register. A3-A0 used control multiplexers other logic functions outside converter. outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA+, hence, their output voltage logic will limited voltage.
Serial Port Interface
CS5525/26 serial interface consist four pins, SCLK, SDO, SDI, must held (logic before SCLK transitions recognized port logic. output will held high impedance time logic tied low, port function three wire interface. SCLK input designed with Schmitt-trigger input allow optoisolator with slower rise fall times directly drive pin. output capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
Performing Conversions (With
Setting configuration register logic enables output behave flag signal whenever conversions completed. This eliminates need user read flag configuration register determine conversion data word available. (Single Conversion) command issued other command bits will completion converDS202F1
CS5525 CS5526
sion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic data conversion word must read before command entered command used with (Continuous Conversion) command issued other command bits will completion conversion. user would then issue SCLKs (with logic clear flag. Upon falling edge SCLK, will present first (MSB) conversion word. SCLKs (high, then low) required read conversion word from port. user must give explicit command read conversion data register when logic When operating continuous conversion mode, user need read every conversion. user does nothing after falls, will rise clock cycle before next conversion word available then fall again signal that another conversion word available. user begins clear flag read conversion data, this action must finished before conversion cycle which occurring background complete user wants able read conversion data. exit continuous conversion mode, issue valid command input when flag falls. command issued converter while performing conversion, filter will restart convolution cycle perform conversion.
Output Word Rate Selection
WR2-WR0 bits configuration register output conversion word rate converters shown Table word rates indicated table assume master clock 32.768 kHz. Upon reset converters operate with output word rate 15.0
Clock Generator
CS5525/26 include gate which connected with external crystal provide master clock chips. They designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected other XOUT. Lead lengths should minimized reduce stray capacitance. converters will operate with external (CMOS compatible) clock with frequencies three times typical crystal frequency 32.768 kHz. Figure details converter's performance increased clock rates.
Figure High Speed Clock Performance
32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. °C). However, applications with CS5525/26 don't generally require such tight tolerances. When 32.768 surface mount crystals used, recommended that protection components, external resistor capacitor shown Figure used.
DS202F1
CS5525 CS5526
XOUT
CS5525 CS5526
32.768
Figure Surface Mount Crystal Connection Diagram
Digital Filter
CS5525/26 have eight different linear phase digital filters which output word rates (OWRs) stated Table These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield better than rejection both with output word rates below 15.0 converter's digital filters scale with XIN. example with output word rate filter's corner frequency typically 12.7 increased 64.536 doubles filter's corner frequency moves 25.4
Figure Filter Response (Normalized Output Word Rate
first followed rest data bits descending order. CS5525 last byte composed bits D7-D4, which always logic D3-D2, which always logic bits D1-D0 which flag bits. CS5526 last byte includes data bits D7-D4, D3-D2 which always logic flag bits. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than zero (unipolar mode), more negative than negative full scale (bipolar mode). cleared back logic whenever conversion word occurs which overranged. (Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input
Output Coding
CS5525/26 output data binary format when operating unipolar mode two's complement when operating bipolar mode. output conversion word bits, three bytes long, shown Table output
Output Conversion Data CS5525 bits flags)
Output Conversion Data CS5526 bits flags)
Table Data Conversion Word
DS202F1
CS5525 CS5526
CS5525 16-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFF VFS-1.5 FFFF -FFFE 8000 -7FFF 0001 -0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000 8000 CS5526 20-Bit Output Coding Unipolar Input Offset Voltage Binary >(VFS-1.5 LSB) FFFFF VFS-1.5 FFFFF -FFFFE 80000 -7FFFF 00001 -00000 00000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement 7FFFF 7FFFF -7FFFE 00000 -FFFFF 80001 -80000 80000
VFS/2-0.5
-0.5
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table 5525/26 Output Coding
converters extremely overranged. set, conversion data bits completely erroneous. flag will cleared logic when modulator becomes stable. Table illustrates output coding CS5525/26.
Power Consumption
CS5525/26 accommodate four power consumption modes: normal, power, standby, sleep. normal mode, default mode, entered after power-on-reset typically consumes power mode alternate mode that reduces consumed power entered setting (the power mode bit) configuration register logic Since converter's noise performance improves with increased power consumption, slightly degraded noise linearity performance should expected power mode. final modes referred power save modes. They power down most analog portion chips stop filter convolutions. power save modes entered whenever PS/R
command word logic particular power save mode entered depends state (the Power Save Select bit) configuration register. logic converters enters standby mode reducing power consumption 1.2mW. standby mode leaves oscillator on-chip bias generator running. This allows converters quickly return normal power mode once PS/R back logic configuration register PS/R command word logic sleep mode entered reducing consumed power less than Since sleep mode disables oscillator, approximately 500ms oscillator start-up delay period required before returning normal power mode.
Layout
CS5525/26 should placed entirely over analog ground plane with both AGND DGND pins device connected analog plane. Place analog-digital plane split immediately adjacent digital portion chip.
DS202F1
CS5525 CS5526
DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT LOGIC OUTPUT CHARGE PUMP DRIVE CRYSTAL CRYSTAL AGND AIN+ AINNBV XOUT
VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT CHIP SELECT SERIAL DATA INPUT LOGIC OUTPUT LOGIC OUTPUT SERIAL DATA OUTPUT POSITIVE DIGITAL POWER
DGND DIGITAL GROUND SCLK SERIAL CLOCK INPUT
Clock Generator
XIN; XOUT Crystal Crystal Out, Pins gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device.
Control Pins Serial Data
Chip Select, When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input, input serial input port. Data will input rate determined SCLK. Serial Data Output, serial data output. will output high impedance state SCLK Serial Clock Input, clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Logic Outputs, logic states A0-A3 mimic states D20-D23 bits configuration register. Logic Output AGND, Logic Output VA+.
DS202F1
CS5525 CS5526
Measurement Reference Inputs
AIN+, AIN- Differential Analog Input, Pins Differential input pins into device. VREF+, VREF- Voltage Reference Input, Pins Fully differential inputs which establish voltage reference on-chip modulator. Negative Bias Voltage, Input supply negative supply voltage gain instrumentation amplifier. tied AGND AIN+ AIN- inputs centered around +2.5 tied negative supply voltage (-2.1 typical) allow amplifier handle level signals more negative than ground. Charge Pump Drive, Square wave output used provide energy charge pump.
Power Supply Connections
Positive Analog Power, Positive analog supply voltage. Nominally Positive Digital Power, Positive digital supply voltage. Nominally +3.0 AGND Analog Ground, Analog Ground. DGND Digital Ground, Digital Ground.
DS202F1
CS5525 CS5526
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin.). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
ORDERING GUIDE
Model Number CS5525-AP CS5525-AS CS5526-BP CS5526-BS Linearity Error (Max) ±0.003% ±0.003% ±0.0015% ±0.0015% Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C Package 20-pin 0.3" Plastic 20-pin 0.2" Plastic SSOP 20-pin 0.3" Plastic 20-pin 0.2" Plastic SSOP
SPIis trademark Motorola Inc., Microwireis trademark National Semiconductor Corp. DS202F1
CS5525 CS5526
PLASTIC (PDIP) PACKAGE DRAWING
SEATING PLANE
VIEW
SIDE VIEW
BOTTOM VIEW
INCHES 0.155 0.020 0.015 0.050 0.008 0.960 0.240 0.095 0.300 0.125 0.180 0.040 0.022 0.065 0.015 1.040 0.260 0.105 0.325 0.150
MILLIMETERS 3.94 4.57 0.51 1.02 0.38 0.56 1.27 1.65 0.20 0.38 24.38 26.42 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81
Notes: Positional tolerance leads shall within 0.25 (0.010 in.) maximum material condition, relation seating plane each other. Dimension center leads when formed parallel. Dimension does include mold flash.
DS202F1
CS5525 CS5526
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS202F1
CDB5525 CDB5526
CDB5525/26 Evaluation Board Software
Features General Description
CDB5525/26 inexpensive tool designed evaluate performance CS5525 CS5526, 16-bit 20-bit Multi-Range Analog-to-Digital Converters (ADC). evaluation board includes LT1019 voltage reference, 80C51 microcontroller, RS232 driver/receiver, firmware. 8051 controls serial communication between evaluation board firmware, thus, enabling quick easy access CS5525/26's registers. CDB5525/26 also includes software Time Domain Analysis, Histogram Analysis, Frequency Domain Analysis.
Direct Thermocouple Interface RS-232 Serial Communication with On-board 80C51 Microcontroller On-board Voltage Reference Windows/CVIEvaluation Software
Register Setup Chip Control Analysis Time Domain Analysis Noise Histogram Analysis
On-board Charge Pump Drive Circuitry Integrated RS-232 Test Mode
ORDERING INFORMATION: CDB5526
ANALOG
ANALOG
AGND
DGND
DIGITAL RS232 CONNECTOR
VOLTAGE REFERENCE
REF+
CS5526
AIN+
80C51 MICROCONTROLLER TEST SWITCHES
AIN+ AINREF-
HDR6 AINCS SCLK
RS232 DRIVER/RECEIVER
DRIVE CIRCUITRY
LEDs
CRYSTAL 32768Hz
XOUT
CRYSTAL 11.0592MHz
RESET CIRCUITRY
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved)
DS202DB5
CDB5525 CDB5526
PART HARDWARE
thermocouple's output reduce interference picked thermocouple leads. evaluation board provides voltage reference options, on-board external. With HDR5's jumpers positions LT1019 provides volts (the LT1019 chosen drift, typically 5ppm/°C). setting HDR5's jumpers position user supply external voltage reference J1's REF+ REF- inputs (Application Note back 1995 Crystal Semiconductor Data Acquisition Databook details various voltage references). serial interface SPIand MICROWIREcompatible. interface control lines (CS, SDI, SDO, SCLK) connected 80C51 microcontroller port one. interface external microcontroller, these control lines also connected HDR6. However accomplish this, evaluation board must modified three ways: interface control traces going microcontroller, remove resistors R1-R8, remove microcontroller. Figure illustrates schematic digital section. contains microcontroller, Motorola MC145407 interface chip, test switches. test switches debugging communication problems between CDB5525/26 microcontroller derives clock from 11.0592 crystal. From this, controller configured communicate RS-232 9600 baud, parity, 8-bit data, stop bit.
Introduction
CDB5525/26 evaluation board provides quick means testing CS5525 CS5526 Analog-to-Digital Converters (ADCs). board interfaces CS5525/26 IBMcompatible RS-232 interface while operating from power supply. accomplish this, board comes equipped with 80C51 microcontroller 9-pin RS-232 cable physically interfaces evaluation board Additionally, analysis software provides easy access internal registers converter, provides means display converter's time domain, frequency domain, noise histogram performance.
Evaluation Board Overview
board partitioned into main sections: analog digital. analog section consists CS5525 CS5526, precision voltage reference, circuitry generate negative voltage. digital section consists 80C51 microcontroller, hardware test switches, reset circuitry, RS-232 interface. CS5525/26 designed digitize level signals while operating from 32.768 crystal. shown Figure thermocouple connected converter's inputs J1's AIN+ AIN- inputs. Note, simple network filters
DS202DB5
CDB5525 CDB5526
Analog 0.1µF Analog 10µF HDR1 AGND AIN+ 4700pF AGND 10µF
0.1µF
CS5526
AIN+ XOUT SCLK DGND
REF-
32768Hz
REF+ AIN+ AINREF-
0.68µF
HDR2 4700pF
0.68µF AIN4 AIN2, AGND HDR5
1,LT1019 2,REF+ 3,REF4,AGND
Figure
REF+
Analog
LT1019 2.5V
0.1µF BAT85 Analog LM337_LZ 0.1µF VOUT
0.1µF
HDR3
TP70
10µF HDR4
TP68
1N4148 0.015µF
1N4148
Note: CS5525 CS5526 interchangeable
Figure Analog Schematic Section
DS202DB5
SCLK
Digital HDR6 10µF Digital P3.0 P3.1 P1.4 P1.5 P1.6 P1.7 P2.0 XTAL1 P2.1 11.0592MHz 33pF Digital 1N4148 Bypass 0.1µF XTAL2 P2.3 Digital 80C51 P2.2 P3.2 P3.3 P3.4 5.11k 5.11k 5.11k LED_555_5003 RESET COMM GAINCAL OFFSETCAL Test Switch Test Switch Test Switch Loopback MC145407 10µF Normal HDR7 From RS-232 47µF 0.1µF 10µF From Figure SCLK 33pF C2C2+ C1C1+ 10µF P1.0 P1.1 P1.2 P1.3 P0.0 TP71 TP72 RS-232
CDB5525 CDB5526
750k 0.1µF
RESET
Figure Digital Schematic Section
DS202DB5
CDB5525 CDB5526
Register Offset Register Gain Register Configuration Register Conversion Data Register
Read Command Byte 0x90 0x92 0x94 0x96 Table Microcontroller Command RS-232
Write Command Byte 0x80 0x82 0x84
Table lists RS-232 commands used communicate between microcontroller. develop additional code communicate evaluation board RS-232, following applies: write internal register, choose appropriate write command byte (See Table transmit first. Then, transmit three data bytes lowest order byte (bits 7-0) first with each byte transmitted first. These three data bytes provide 24-bits information written desired register. read from internal register, choose appropriate read command byte transmit first. Then, microcontroller automatically acquires ADC's register contents returns 24-bits information. returned data transmitted lowest order byte first with each byte transmitted first. Figure illustrates power supply connections evaluation board. Analog supplies analog section evaluation board, LT1019 ADC. Analog supplies negative bias voltage circuitry. Digital supplies separate five volts digital section
evaluation board, 80C51, reset circuitry, RS-232 interface circuitry.
Using Evaluation Board
CS5525/26 highly integrated ADCs. They contain instrumentation amplifier (IA), programmable gain amplifier (PGA), on-chip charge pump drive (CPD), programmable output word rates (OWR). provides gain while sets input levels either (for VREF provides square wave output. This output used supply negative supply enabling measurements ground referenced signals. ADC's digital filter allows user select output word rates (OWR's) from 3.76 output word rates attained when 100kHz clock source used. Since CS5525/26 have such high degree integration flexibility, CS5525/26 data sheet should read thoroughly before consulted during CDB5525/26.
Analog
Analog
Digital
Digital
P6KE6V8P AGND
47µF
0.1µF
P6KE6V8P DGND
47µF
0.1µF
P6KE6V8P
Analog
47µF
0.1µF
Analog
Figure Power Supplies
DS202DB5
CDB5525 CDB5526
Negative Bias Voltage
evaluation board provides three means supplying Negative Bias Voltage (NBV). HDR4 selects between them. When HRD4 position one, LM337 supplies with adjustable voltage. used adjust this voltage between -1.25 When position two, HDR4 grounds NBV. setting HDR4 position three, converter's Charge Pump Drive provides with rectified voltage, nominally -2.1
Note: should exceed voltage more negative than -3.0
Name HDR1 HDR2 HDR3 Function Description Used switch AIN+ between input AGND. Used switch AIN- between input AGND. Used conjunction with HDR4 switch power from LM337, analog ground. Used conjunction with HDR3 switch power from LM337, analog ground. Used switch VREF+ VREFpins from external connection header board LT1019 reference. Used connect external micro-controller. Used conjunction with self test modes test UART communication between microcontroller
Software
evaluation board comes with software RS-232 cable link evaluation board executable software developed with Windows/CVIand meant under Windows3.1 later. After installing software, read readme.txt file last minute changes software. Additionally, Part Software further details install software.
HDR4
HDR5
IBM, PS/2 trademarks International Business Machines Corporation. Windows trademark Microsoft Corporation. Windows trademarks National Instruments. SPIis trademark Motorola. MICROWIREis trademark National Semiconductor.
HDR6 HDR7
DS202DB5
CDB5525 CDB5526
PART SOFTWARE
Using Software
start-up, window START-UP CONFIGURATION appears first. This window contains information concerning software's title, revision number, copyright date, etc. Additionally, screen menu which displays user options. Notice, menu item Menu initially disabled. This eliminates conflicts with mouse concurrent modems. Before proceeding further, user prompted select serial communication port. initialize port, pull down option Setup from menu select either COM1 COM2. After port initialized, good idea test RS-232 link between evaluation board. this, pull down Setup menu from menu select option TESTRS232. user then prompted evaluation board's test switches then reset board. Once this done, proceed with test. test fails, check hardware connection repeat again. Otherwise, test switches (normal mode) reset board. option Menu available performance tests executed. evaluation software provides three types analysis tests Time Domain, Frequency Domain, Histogram. Time Domain analysis processes acquired conversions produce plot Conversion Sample Number versus Magnitude. Frequency Domain analysis processes acquired conversions produce magnitude versus frequency plot using Fast-Fourier transform (results Fs/2 calculated plotted). Also, statistical noise calculations calculated displayed. Histogram analysis test processes acquired conversions produce histogram plot. Statistical noise calculations also calculated displayed (see figures through figure evaluation software developed with Windows/CVITM, software development package from National Instruments. More sophisticated
Installation Procedure
install software: Turn prompt type Launch Windows 3.1or later. Insert Installation Diskette into From within Windows Program Manager, pull down File from menu select option. prompt type: A:\SETUP.EXE <enter>. program will begin installation. After seconds, user will prompted enter directory which install Run-Time EngineTM. Run-Time Enginemanages executable created with Windows/CVIand takes approximately megabytes hard drive space. default directory acceptable, select RunTime Enginewill installed there. After Run-Time Engineis installed, user prompted enter directory which install CDB5525/26 software. Select accept default directory. program takes minutes install. After program installed, double click Eval5526 icon launch After seconds, user should CS5525/26 environment.
Note: software written with (standard Windows 3.1TM) resolution; however, will work with 1024 resolution. user interface seems little small, user might consider setting display settings standard (640x480 chosen accommodate variety computers).
DS202DB5
CDB5525 CDB5526
analysis software developed purchasing development package from National Instruments (512-794-0100). file save format. format part number, throughput sample rate), number conversions, maximum range, data conversions. user prompted enter path file name previously saved data. prevent hardware conflicts, this option deactivated while Input/Output Window. TESTRS232: This test mode tests ability communicate evaluation board. consists subtests: test link between RS-232 interface circuitry; test RS-232 link between microcontroller. HDR7 distinguishes these subtests. HDR7 Normal test complete communication link. HDR7 Loop Back test link between RS-232 Circuitry Then, test switches reset evaluation board. LED's should indicate binary signifying that hardware ready initiate test. complete test, user must initialize First, SETUP menu select communications port then select TESTRS232 option. From there, user prompts navigate user through test. indicates test passes fails. Once either test complete, LED's toggle indicate that test mode complete. PART: Allows user select different converter. QUIT: Allows user exit program.
Menu Bars Overview
menu controls link between windows allows user exit program. also allows user initialize serial port load presaved data conversions from file. five principal windows START CONFIGURATION (also referred Setup Window), Input Output Window, Histogram Window, Power Spectrum Window (also referred window), Time Domain Window. Specifically, menu following control items: Menu: select, click option Menu from menu bar, associated keys. items associated with MENU listed described below. Setup Window Input/Output Window Histogram Window Power Spectrum Window Time Domain Window (F1) (F2) (F3) (F4) (F5)
These five menu items allow user navigate between five windows. They available times menu keys. SETUP: select, click option Setup from menu bar. functions available under Setup are: COM1: When selected, COM1 initialized 9600 baud, parity, data bits, stop bit. COM2: When selected, COM2 initialized 9600 baud, parity, data bits, stop bit. Load From Disk: Used load display previously saved data conversions from file. file must comply with CDBCAPTURE
Input/Output Window Overview
Input/Output Window allows user read write internal register converter either binary hexadecimal, acquire real-time conversions. quick access control icons that quickly reset converter, reset converter's serial port, self-calibrate converter's offset
DS202DB5
CDB5525 CDB5526
gain. following controls indicators associated with this window. Acquire: This control icon. When pressed, transmits collect single conversion command microcontroller. microcontroller turn collects conversion from returns stores conversion collects additional conversions form set. From sample collected, high, low, peak-to-peak, average, standard deviation, computed (the size data Average input) then display icons updated. This process continues until STOP button pressed, until another window selected. Note: quick access control icons disabled once Acquire selected. This eliminates potential hardware conflicts. BINARY: Input icons clear individual bits gain, configuration, offset registers. bits first set, then control icon Write Registers selected update registers converter. CONFIGURATION REGISTER: Text display that displays decoded meaning each configuration register. DECIMAL: Three display icons that display decimal contents gain, configuration, offset registers. DIGITAL OUTPUT: Display icon that displays four states output latch. GAIN REGISTER: Display icon that displays decimal equivalent bits gain register. HEX: Three input/display icons that allow user bits gain, configuration, offset registers hexadecimal nibbles. upper nibbles registers zero's, then leading zero nibbles need entered. Average: Input icon that sets size data conversion referred when Acquire button pressed. Read Registers: This control icon. When pressed gain, offset, configuration registers contents acquired. Then, configuration text register content icons updated. Reinitialize: This control icon. When pressed, logic followed logic sent ADC's serial port reset port. does reset RS-232 link. Reset A/D: This control icon. When pressed, microcontroller sends appropriate commands return converter initial default state. SELF Calibrate: This control icon. When pressed, appropriate commands sent calibrate offset gain. STOP: Stops collection conversion data. Write Registers: This control icon. When pressed, binary input icons settings acquired. This data then transmitted ADC's gain, offset, configuration registers. Then, PC's display updated reflect registers changes.
DS202DB5
CDB5525 CDB5526
Histogram Window Overview
following description controls indicators associated with Histogram Window. Many control icons usable from Histogram Window, Frequency Domain Window, Time Domain Window. brevity, they only described this section. BIN: Displays x-axis value cursor Histogram. CANCEL: Once selected, allows user exit from COLLECT algorithm. data conversion sample sets larger than being collected CANCEL button selected, recommended that user reset evaluation board. board will eventually recover from continuous collection mode, recovery time could long minutes. COLLECT: Initiates data conversion collection process. COLLECT modes operation: collect from file collect from converter. collect from file appropriate file from SETUP-DISK menu option must selected. Once file selected, content displayed graph. user collecting real-time conversions analyze, appropriate port must selected. user then free collect preset number conversions (preset CONFIG pop-up menu discussed below). Notice, there significant acquisition time difference methods. CONFIG: Opens pop-up panel configure much data collected, process data once collected. following controls indicators associated with CONFIG panel. SAMPLES: User selection 256, 512, 1024, 2048, 4096, 8192 conversions. WINDOW: Used Power Spectrum Window calculate FFT. Windowing algorithms include Blackman, Blackman-Harris, Hann, 5-term Hodie, 7-term Hodie. 5-term Hodie 7term Hodie windowing algorithms developed Crystal Semiconductor. information concerning these algorithms needed, call technical support. AVERAGE: Sets number consecutive FFT's perform average. LIMITED NOISE BANDWIDTH: Limits amount noise converters bandwidth. Default Accept change MAGNITUDE: Displays y-axis value cursor Histogram. MAXIMUM: Indicator maximum value collected data set. MEAN: Indicator mean data sample set. MINIMUM: Indicator minimum value collected data set. OUTPUT: Control that calls pop-up menu. This menu controls three options: save current data file with CDBCAPTURE format, print current screen, print current graph. RESTORE: Restores display graph after zoom been entered. STD. DEV.: Indicator Standard Deviation collected data set. TEST: Quick access control icon, similar keys, allow user quickly switch between time domain, frequency domain, histogram display. VARIANCE: Indicates Variance current data set.
DS202DB5
CDB5525 CDB5526
ZOOM: Control icon that allows operator zoom specific portion current graph. zoom, click ZOOM icon, then click graph select first point (the point left corner zoom box). Then click graph again select second point (the point bottom right corner zoom box). Once area been zoomed OUTPUT functions used print hard copy that region. Click RESTORE when done with zoom function. ZOOM: description Histogram Window Overview. AVG: Displays number FFT's averaged current display.
Time Domain Window Overview
following controls indicators associated with Time Domain Window. CANCEL: description Histogram Window Overview. COLLECT: description Histogram Window Overview. CONFIG: description Histogram Window Overview. COUNT: Displays current x-position cursor time domain display. MAGNITUDE: Displays current y-position cursor time domain display. MAXIMUM: Indicator maximum value collected data set. MINIMUM: Indicator minimum value collected data set. OUTPUT: description Histogram Window Overview. TEST: description Histogram Window Overview. ZOOM: description Histogram Window Overview.
Frequency Domain Window (i.e. FFT)
following describe controls indicators associated with Frequency Domain Window. CANCEL: description Histogram Window Overview. COLLECT: description Histogram Window Overview. CONFIG: description Histogram Window Overview. FREQUENCY: Displays x-axis value cursor display. MAGNITUDE: Displays y-axis value cursor display. OUTPUT: description Histogram Window Overview. S/D: Indicator Signal-to-Distortion Ratio, harmonics used calculations (decibels). S/N+D: Indicator Signal-to-Noise Distortion Ratio (decibels). SNR: Indicator Signal-to-Noise Ratio, first harmonics included (decibels). S/PN: Indicator Signal-to-Peak Noise Ratio (decibels). TEST: description Histogram Window Overview.
Trouble Shooting Evaluation Board
This section describes special test modes incorporated microcontroller software diagnose hardware problems with evaluation board.
Note: enter these modes, test switches appropriate position reset evaluation board. reenter normal operation mode, switches back binary zero reset board again.
Test Mode Normal Mode: This default mode operation. enter this mode, test
DS202DB5
CDB5525 CDB5526
switches reset board. evaluation board allows normal read/writes ADC's registers. LED's toggle then after reset, then only when communicating with Test Mode Loop Back Test: This test mode checks microcontroller's on-chip UART. enter this mode, test switches 001, HDR7 loop back, then reset board. communication works, LED's toggle. Otherwise, only LED's toggle indicate communication problem. Test Mode Read/Write ADC: This test mode tests microcontroller's ability read write ADC. enter this mode, switches reset board. this test mode, ADC's configuration, offset, gain registers written then read from. correct data read back, LED's toggle. Otherwise, only half them toggle indicate error. Test Mode Continuously Acquire Single Conversion: This test mode repetitively acquires single conversion. enter this mode, test switches press reset. binary three indicated LED's. probing HDR6 using triggering pin, oscilloscope logic analyzer will display real-time microcontroller reads conversion data. Test Mode Reserved future modifications. Test Mode Continuously Read Gain Register: This test mode repetitively acquires gain registers default contents (0x800000 HEX). enter this mode, test switches press reset. LED's should indicate binary five. probing HDR6 using triggering pin, oscilloscope logic analyzer will display realtime microcontroller acquires conversion. Test Mode Microcontroller RS-232 Communication Link Test: This test mode tests ability communicate evaluation board. consists subtests: test link between RS-232 interface circuitry; test RS-232 link between microcontroller. HDR7 distinguishes these subtests. HDR7 Normal test complete communication link. HDR7 Loop Back test link between RS-232 Circuitry Then, test switches reset evaluation board. LED's should indicate binary signifying that hardware ready initiate test. complete test, user must initialize First, SETUP menu select communications port then select TESTRS232 option. From there, user prompts navigate user through test. indicates test passes fails. Once either test complete, LED's toggle indicate that test mode complete. Test Mode Toggle LED's: This test mode tests evaluation board LED's. enter this mode, test switches reset board. mode passes, LED's toggle.
Note: Remember, return normal operating mode, test switches binary zero, return HDR7 Normal, reset evaluation board.
DS202DB5
CDB5525 CDB5526
Figure Main Menu
Figure Input/Output Window
DS202DB5
CDB5525 CDB5526
Figure Frequency Domain Analysis
Figure Configuration Menu
DS202DB5
CDB5525 CDB5526
Figure Time Domain Analysis
Figure Histogram Analysis
DS202DB5
CDB5525 CDB5526
Figure CDB5525/26 Component Side Silkscreen
DS202DB5
CDB5525 CDB5526
Figure CDB5525/26 Component Side (top)
DS202DB5
CDB5525 CDB5526
Figure CDB5525/26 Solder Side (bottom)
DS202DB5
Notes

16-Bit/20-Bit Multi-Range with 4-Bit Latch Features General Descr

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