8-Channel, 24-Bit Buffered Multi-Range Delta-Sigma General D
|
|
|
Top Searches for this datasheet
CS5522/24/28
8-Channel, 24-Bit Buffered Multi-Range
Delta-Sigma
General Description
Converter
24-bit CS5522/24/28 highly integrated converters which include instrumentation amplifier, (programmable gain amplifier), multi-channel multiplexer, digital filters, self system calibration circuitry. chips designed provide their negative supply which enables their on-chip instrumentation amplifiers measure bipolar ground-referenced signals less-than equal ±100 digital filters provide programmable output update rates 1.88 3.76 7.51 61.6 84.5 101.1 when operating from crystal. CS5522/24/28 capable producing output update rates with 100kHz clock. filters designed settle full accuracy selected output update rate within conversion cycle. When operated word rates less, digital filters reject both line interference simultaneously. power, single conversion settling time, programmable output rates, ability handle negative input signals make these single supply products ideal solutions isolated non-isolated applications.
Linearity Error: 0.0007%FS Noise Free Resolution: 18-bits
Buffered Chopper
Bipolar/Unipolar Input Ranges
Stabilized Instrumentation Amplifier On-Chip Charge Pump Drive Circuitry Multiplexer Conversion Data FIFO Programmable/Auto Channel Sequencer 2-Bit Output Latch Simple three-wire serial interface
SPIand MicrowireCompatible Schmitt Trigger Serial Clock (SCLK)
Output
Settles Conversion Cycle 50/60 Simultaneous Rejection Buffered VREF with Input Capability System Self-Calibration with Registers Channel Single Analog Supply +3.0 Digital Supply Power Mode Consumption:
AGND
ORDERING INFORMATION page
VREF+ VREFX1 DGND
AIN1+ AIN1AIN2+ AIN2AIN3+ AIN3AIN4+ AIN4MUX
CS5524 Shown
Programmable Gain Differential Order Digital Filter Calibration Register Control Register Output Register SCLK
Modulator
Latch
Calibration Memory
Calibration
Clock Gen.
XOUT
Preliminary Product Information
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. 17847, Austin, Texas 78760 (512) 7222 FAX: (512) 7581 http://www.crystal.com
This document contains information product. Cirrus Logic reserves right modify this product without notice.
Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved)
DS265PP3
CS5522/24/28
TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS. NOISE. DIGITAL CHARACTERISTICS DIGITAL CHARACTERISTICS DYNAMIC CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS GENERAL DESCRIPTION Theory Operation System Initialization Serial Port Overview Serial Port Interface Serial Port Initialization Channel-Setup Registers Conversion Protocol Calibration Protocol Pointers Command Byte Analog Input Charge Pump Drive Voltage Reference Calibration Self Calibration System Calibration Calibration Tips Limitations Calibration Range Analog Output Latch Pins Output Word Rate Selection Clock Generator Digital Filter Output Coding Power Consumption Layout DESCRIPTIONS SPECIFICATION DEFINITIONS ORDERING GUIDE
SPIis trademark Motorola Inc., Microwireis trademark National Semiconductor Corp. Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise). Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
DS265PP3
CS5522/24/28
TABLE FIGURES
CS5522/24/28 Configured on-chip charge pump supply NBV. Charge Pump Drive Circuit Alternate Circuits. CS5522/24/28 Configured ground-referenced Unipolar Signals. CS5522/24/28 Configured Single Supply Bridge Measurement. Command Data Word Timing. Multiplexer Configuration Input models AIN+ AIN- pins each range. Input model VREF+ VREF- pins. Self Calibration Offset (Low Ranges). Self Calibration Offset (High Ranges). Self Calibration Gain (All Ranges). System Calibration Offset (Low Ranges). System Calibration Offset (High Ranges). System Calibration Gain (Low Ranges) System Calibration Gain (High Ranges). High Speed Clock Performance Filter Response(Normalized Output Word Rate
DS265PP3
CS5522/24/28
CHARACTERISTICS SPECIFICATIONS
VA+, ±5%; VREF+ VREF- AGND, -2.1 FCLK 32.768 kHz, (Output Word Rate) Bipolar Mode, Input Range ±100 Notes Parameter (Note (Note (Notes (Note
(VREF-)+1
ANALOG CHARACTERISTICS
(VREF+)-1
Unit Bits LSB24 LSB24 nV/°C ppm/°C
Accuracy Resolution Linearity Error Bipolar Offset Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift Voltage Reference Input Range (VREF+) (VREF-) VREF+ VREFCommon Mode Rejection Input Capacitance Current
±0.0007 ±0.0015
(Note
Notes: Applies after system calibration temperature within Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after calibration power-up section data sheet which discusses input models.
NOISE (Notes
Output Rate Filter (Hz) Frequency 1.88 1.64 3.76 3.27 7.51 6.55 15.0 12.7 30.0 25.4 61.6 50.4 84.5 (Note 70.7 101.1 (Note 84.6 Input Range, (Bipolar/Unipolar Mode)
Notes: Wideband noise aliased into baseband. Referred input. Typical values shown Peak-to-Peak Noise multiply ranges output rates. input ranges <100 output rates 16.384 chopping frequency used. DS265PP3
CS5522/24/28
ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode Signal AIN+ AINBipolar/Unipolar Mode -1.8 -2.5 Range Range AGND Range Range Common Mode Rejection Input Capacitance Current AIN+ AIN(Note Range Range System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode Offset Calibration Range Bipolar/Unipolar Mode (Note Power Supplies Power Supply Currents (Normal Mode) (Note 10)ID+ INBV Power Consumption Normal Mode (Note Power Mode Standby Sleep Power Supply Rejection Positive Supplies Unit
-0.150 1.85
0.950 2.65
0.40
32.5 71.5 1.30 3.25 ±12.5 ±27.5 ±0.5 ±1.25 ±2.50
Notes: maximum full scale signal limited saturation circuitry within internal signal path. Measured with Charge Pump Drive off. outputs unloaded. input CMOS levels.
DS265PP3
CS5522/24/28
DIGITAL CHARACTERISTICS VA+, ±5%;
Notes 12.)) Parameter High-Level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+)-0.5 (VD+) 0.45 (VA+) (VD+) (VD+) Cout Unit
Low-Level Input Voltage
High-Level Output Voltage Pins Except (Note CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance Notes: measurements performed under static conditions.
Iout -100 unless stated otherwise. (VOH Iout µA.)
DIGITAL CHARACTERISTICS ±5%; ±10%;
Notes 12.) Parameter High-Level Input Voltage Pins Except SCLK SCLK Pins Except SCLK SCLK Symbol (VD+)-0.5 (VD+) 0.45 (VA+) (VD+) (VD+) Cout 0.16 Unit
Low-Level Input Voltage
High-Level Output Voltage Pins Except SDO, Iout -400 CPD, Iout -4.0 SDO, Iout -5.0 Low-Level Output Voltage Pins Except SDO, Iout CPD, Iout SDO, Iout Input Leakage Current 3-State Leakage Current Digital Output Capacitance
DS265PP3
CS5522/24/28
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time (Full Scale Step) Symbol Ratio XIN/4 1/fout Unit
RECOMMENDED OPERATING CONDITIONS (AGND, DGND Note 14.))
Parameter Power Supplies Analog Reference Voltage Negative Bias Voltage Notes: voltages with respect ground. Positive Digital Positive Analog (VREF+) (VREF-) Symbol VRefdiff 4.75 -1.8 -2.1 5.25 5.25 -2.5 Unit
ABSOLUTE MAXIMUM RATINGS (AGND, DGND Note 14.)
Parameter Power Supplies (Note Positive Digital Positive Analog Negative Potential (Note (Note VREF pins Pins Symbol IOUT VINR VINA VIND Tstg -0.3 -0.3 +0.3 -0.3 -0.3 -0.3 -2.1 +6.0 +6.0 -3.0 (VA+) (VA+) (VD+) Unit
Negative Bias Voltage Input Current, Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: should more negative than Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
DS265PP3
CS5522/24/28
SWITCHING CHARACTERISTICS ±5%; ±10% ±5%;
Levels: Logic Logic VD+; pF.)) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times (Note Digital Input Except SCLK SCLK Digital Output (Note Digital Input Except SCLK SCLK Digital Output XTAL 32.768 (Note trise tfall tost tpor 2006 cycles (Note External Clock Internal Oscillator Symbol 32.768 Unit
Fall Times
Start-up Oscillator Start-up Time Power-on Reset Period Serial Port Timing Serial Clock Frequency
SCLK
SCLK Falling Falling continuous running SCLK (Note Serial Clock Pulse Width High Pulse Width
Write Timing
Enable Valid Latch Clock Data Set-up Time prior SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior Disable
Read Timing
Data Valid SCLK Falling Data Rising Hi-Z
Notes: Device parameters specified with 32.768 clock; however, clocks used increased throughput. Specified using points waveform interest. Output loaded with Oscillator start-up time varies with crystal parameters. This specification does apply when using external clock source. Applicable when SCLK continuously running.
Specifications subject change without notice.
DS265PP3
CS5522/24/28
SCLK
Continuous Running SCLK Timing (Not Scale)
MSB-1
SCLK
Write Timing (Not Scale)
MSB-1
SCLK
Read Timing (Not Scale)
DS265PP3
CS5522/24/28
GENERAL DESCRIPTION
CS5522/24/28 24-bit converters which include chopper-stabilized instrumentation amplifier input, on-chip programmable gain amplifier. They optimized measuring lowlevel unipolar bipolar signals process control medical applications. CS5522/24/28 also include fourth order delta-sigma modulator, calibration microcontroller, eight digital filters used select between eight output update rates, 2-bit analog latch, multiplexer, serial port. CS5522/24/28 include (Charge Pump Drive) output (shown Figure which provides negative bias voltage on-chip instrumentation amplifier when used with combination external diodes capacitors. This makes converters ideal thermocouple temperature measurements because biasing scheme enables
Analog Supply
CS5522/24/28 measure negative voltages with respect ground without need negative supply.
Theory Operation
CS5522/24/28 converters designed operate from single analog supply with several different input ranges. Analog Characteristics section page details. Figure illustrates CS5522/24/28 connected generate their negative bias supply using on-chip (Charge Pump Drive). This enables CS5522/24/28 measure ground referenced signals with magnitudes down -100mV. Figure illustrates charge pump circuit when converters powered from +3.0 digital supply. Alternatively, negative bias supply generated from negative supply voltage resistive divider illustrated Figure
2.5V Input BAV199
XOUT 32.768 Optional Clock Source
VREF+ VREF-
CS5522 AIN1+
AIN11 AGND AIN2+ AIN216
Cold Junction LM334 Absolute Current Reference V301
SCLK
Serial Data Interface
DGND
0.03
Logic Outputs: Switch from AGND.
1N4148 BAT85
1N4148
Charge-pump network only 32.768 kHz.
Figure CS5522/24/28 Configured on-chip charge pump supply NBV.
DS265PP3
CS5522/24/28
Figure illustrates CS5522/24/28 connected measure ground referenced unipolar signals positive polarity using ranges converter. ranges signal must have common mode near +2.5 (NBV 0V). CS5522/24/28 optimized measurement thermocouple outputs, also well suited measurement ratiometric bridge transducer outputs. Figure illustrates CS5522/24/28 connected measure output ratiometric differential bridge transducer while operating from single supply.
2N5087 similar BAT85
10µF
34.8K
2.0K
30.1K BAT85 2.1K
Figure Charge Pump Drive Circuit
Figure Alternate Circuits.
Analog Supply
VREF+ VREF-
XOUT
32.768 Optional Clock Source
CS5522
Input
AIN1+
AIN1SCLK AGND AIN2+ AIN2SDO DGND
Serial Data Interface
Figure CS5522/24/28 Configured ground-referenced Unipolar Signals.
DS265PP3
CS5522/24/28
VREF+ XOUT 32.768 100kHz Optional Clock Source
Analog Supply
VREF+ AIN1+ CS5522 AIN1AGND AIN2+ AIN2A1 DGND
SCLK
Serial Data Interface
Figure CS5522/24/28 Configured Single Supply Bridge Measurement.
System Initialization
When power CS5522/24/28 applied, chips held reset condition until 32.768 oscillator started counter-timer elapses. high 32.768 crystal, oscillator takes 400-600 start. counter-timer counts 2006 oscillator clock cycles make sure oscillator fully stable. During this time-out period serial port logic reset (Reset Valid) configuration register indicate that valid reset occurred. After reset, on-chip registers initialized following states converter placed command mode where waits valid command.
configuration register: offset registers: gain registers: channel setup registers: 000040(H) 000000(H) 400000(H) 000000(H)
Serial Port Overview
CS5522/24/28's serial port includes microcontroller which contains command register, configuration register, gain offset register each input channel. serial port also includes programmable channel sequencer which sequence channels converted. sequencer consists channel-setup registers (CSRs) which contain information about modes used when conversions performed. complement sequencer conversion data FIFO (CDF, read only) included store sixteen data conversions. registers except 8-bit command register 24-bits length. conversion data FIFO just array 24-bit conversion data registers used store conversion words until FIFO read. serial port modes operation: command mode data mode. After system initialization reset, serial port initialized into command mode where waits receive valid command (the first 8-bits into serial port). Tables used decode valid commands. Once valid command received, byte
DS265PP3
Note: system reset initiated time writing logic (Reset System) configuration register. After reset, until configuration register read. user must then write logic take part reset mode.
CS5522/24/28
instructs converter read from write register(s), perform conversion calibration, perform NULL command. command other than start calibration NULL command received, serial port enters data mode. data mode, either internal registers, CSRs, (read only) read from written number bytes transferred depends type register/FIFO being accessed accessed. Once data transferred, serial port either remains data mode returns command mode. mode which entered depends status loop (LP), (multiple conversion), (read convert) bits configuration register. More information concerning provided Conversion/Calibration Protocol section. Note that falls logic anytime calibration conversion completed. with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive optoisolator LED. will have less than loss drive voltage when sinking sourcing
Serial Port Initialization
serial port initialized command mode whenever power-on reset performed inside converter, when user transmits port initialization sequence. port initialization sequence involves clocking bytes 1's, followed byte with following contents `11111110'. This sequence places chip command mode where waits valid command written.
Channel-Setup Registers
Table depicts channel-setup registers (CSRs). CS5522 CSRs. CS5524 four CSRs CS5528 eight CSRs. Each contains logical channels which programmed user contain data conversion information such state output latch pins, output word rate, gain range, polarity, address physical input channel converted. Note that particular physical input channel represented more than logical channel with different output rates, gain ranges, conversion modes. Once programmed CSRs sequencer determine order which conversions performed. program CSRs twelve bits needed configure each logical channel. example, configure CS5522, bits contain information third logical channel bits contain information fourth logical channel. Note that while reading/writing CSRs, only even number logical channels accessed. depth bits configuration register only 0001, 0011, 0101, 0111, 1001, 1011, 1101, 1111 accessing CSRs.
Serial Port Interface
CS5522/24/28's serial interface consists four control lines: SCLK, SDI, SDO. Chip Select, control line which enables access serial port. tied low, port function three wire interface. SCLK, Serial Clock, serial bit-clock which controls shifting data from ADC's serial port. must held (logic before SCLK transitions recognized port logic. SDI, Serial Data data signal used transfer data converters. SDO, Serial Data Out, data signal used transfer output data from converters. output will held high impedance time logic Figure illustrates serial sequence necessary write read from serial port's registers. accommodate optoisolators SCLK designed with Schmitt-trigger input allow optoisolaDS265PP3
CS5522/24/28
Command Register
D7(MSB) D6-D4 CSB2 CSB1 NAME Command Bit, Channel Select Bits, CSB2-CSB0 CSB0 VALUE RSB2 RSB1 RSB0 FUNCTION Must logic these commands. Table CSB2-CSB0 provide address eight physical channels. These bits used access calibration registers associated with respective channels. Note: These bits ignored when reading data register. Write selected register. Read from selected register. Reserved Offset Register Gain Register Configuration Register Conversion Data FIFO (read only) Channel Set-up Registers register 48-bits long CS5522 register 96-bits long CS5524 register 192-bits long CS5528 Reserved Reserved
D2-D0
Read/Write, Register Select Bit, RSB2-RSB0
Table Command-Set with MSB=0
D7(MSB) D6-D3
CPB3
CPB2 NAME
CPB1
CPB0 VALUE 0000 1111
FUNCTION
Command Bit, Channel Pointer Bits, CPB3-CPB0
Table Must logic these commands. These bits used pointers logical channels. Note: bit, must logic these bits take effect. When these bits ignored. bits configuration register ignored during calibration. Normal Conversion Self-Offset Calibration Self-Gain Calibration Reserved Reserved System-Offset Calibration System-Gain Calibration Reserved
D2-D0
Conversion/Calibration Bits, CC2-CC0
Table Command-Set with MSB=1
DS265PP3
CS5522/24/28
SCLK
Command Time SCLKs
Data Time SCLKs
Write Cycle
SCLK
Command Time SCLKs
Data Time SCLKs
Read Cycle
SCLK
Command Time SCLKs
XIN/OWR Clock Cycles SCLKs Clear Flag
XIN/OWR clock cycles each conversion except first conversion which will take XIN/OWR clock cycles
Data Time SCLKs
Figure Command Data Word Timing.
DS265PP3
CS5522/24/28
Channel-Setup Registers
(Channel-Setup Register) (Log. Channel) Bits <47:36> Bits <23:12> Bits <35:24> Bits <11:0> CS5522 Bits <23:12> Bits <11:0> CS5524 Bits <23:12> CS5528 Bits <11:0> Bits <95:84> Bits <83:72> Bits <191:180> Bits <179:168>
D23(MSB)
NAME
FUNCTION
VALUE
D23-D22/ Latch Outputs, A1-A0 D11-D10 D21-D19/ Channel Select, CS2D9-D7
Latch Output Pins A1-A0 mimic D23/D11-D22/D10 register bits. Select physical channel Select physical channel Select physical channel Select physical channel Select physical channel Select physical channel Select physical channel Select physical channel 15.0 (2180 cycles). 30.0 (1092 cycles). 61.6 (532 cycles). 84.5 (388 cycles). 101.1 (324 cycles). 1.88 (17444 cycles). 3.76 (8724 cycles). 7.51 (4364 cycles). (assumes VREF Differential used. used. Bipolar measurement mode. Unipolar measurement mode.
D18-D16/ Word Rate, WR2-WR0 D6-D4
D15-D13/ Gain Bits, G2-G0 D3-D1
D12/D0
Unipolar/Bipolar,
indicates value after part reset Table Channel-Setup Registers
DS265PP3
CS5522/24/28
Configuration Register
D23(MSB) D23-D22 D21-D20 CFS1 PS/R NAME Used, Chop Frequency Select, CFS1-CFS0 CFS0 VALUE Must always logic Amplifier chop frequency. 4,096 Amplifier chop frequency. 16,384 Amplifier chop frequency. 1,024 Amplifier chop frequency. Must always logic Perform single channel conversions. ignored during calibrations. Perform multiple conversions logical channels channel-setup register issuing only command with Don't loop. ignored during calibrations. conversions single channel multiple channels continuously performed. Don't wait user finish reading data before starting conversions. used conjunction with when logic ignored. waits user read data conversion(s) before converting again. ignored during calibrations. Refer Calibration Protocol details. When writing reading CSRs, these bits (DP3-DP0) determine number CSR's accessed. They also used determine many logical channels converted when MC=1 command byte with issued. Note that CS5522 CSRS, CS5524 four CSRs, CS5528 CSRs. Standby Mode (Oscillator active, allows quick power-up). Sleep Mode (Oscillator inactive). Charge Pump Enabled. goes Hi-Z output state. Run. Power Save. Normal Mode. Reduced Power Mode. Normal Operation. Activate Reset cycle. return Normal Operation write zero. reset occurred been cleared (read only). after Valid Reset occurred. (Cleared when read.) clear when oscillation condition occurred (read only). when oscillatory condition detected modulator. clear when overrange condition occurred (read only). when input signal more positive than positive full scale, more negative than zero (unipolar mode), when input more negative than negative full scale (bipolar mode). Must always logic FUNCTION
Used, Multiple Conversion,
Loop,
Read Convert,
D15-D12
Depth Pointer, DP3-DP0
0000 1111
Power Save Select, Pump Disable, Power Save/Run, PS/R Power Mode, Reset System, Reset Valid, Oscillation Detect, Overrange Flag,
D3-D0
Used,
0000
indicates value after part reset Table Configuration Register
DS265PP3
CS5522/24/28
Conversion Protocol
acquire single multiple conversion(s) command byte issued with MSB=1 CC2-CC0 `000'. type conversion(s) performed access resulting data determined (multiple conversion), (loop), (read convert) bits configuration register. MC's, LP's, RC's functional descriptions follow. other bits configuration register detailed Table converter remains this conversion mode continues convert selected channel. While this mode, user choose acquire only conversions required application rises falls indicate availability conversion. exit this conversion mode user must provide `11111111' during first SCLKs. user decides exit, SCLKs required clock last conversion before converter will return command mode. Based information provided CSRs, single conversion performed repeatedly physical channel referenced logical channel. command byte contains pointer address logical channel used during conversion embedded After conversion cycle complete, falls serial port placed data mode where will remain until conversion data read. user doesn't read conversion word converter stops performing conversions will remain until conversion data acquired. acquire conversion data thirty-two SCLKs needed. first SCLKs used clear flag. next needed read conversion result. `00000000' provided during first SCLKs clear flag, conversion cycle will started after conversion data read. exit this conversion mode return command mode, user must provide `11111111' during first SCLKs. final SCLKs required clock last conversion data.
Based information provided channelsetup registers (CSRs), single conversion performed physical channel referenced logical channel. command byte contains pointer address logical channel used during conversion embedded serial port enters data mode soon 8-bit command byte start conversion issued. port remains data mode during conversion. Upon completion conversion, falls logic Thirty-two SCLKs needed acquire conversion. first SCLKs used clear flag. last needed read conversion result. After reading data, serial port returns command mode, where waits command issued.
Based information contained CSRs, single conversion repeatedly performed physical channel referenced logical channel. command byte contains pointer address logical channel used during conversion. Once conversion complete, falls indicate that conversion ready. Thirty-two SCLKs needed acquire conversion (which must acquired within certain window, refer Figure first SCLKs used clear flag. next needed read conversion result. `00000000' provided during first SCLKs when flag cleared,
Based information provided CSRs, multiple conversions performed once physical channels referenced logical channels CSRs. first conversions based information channel-setup register (CSR) (logical channels two); third fourth conversions based information
DS265PP3
CS5522/24/28
(logical channels three four); conversions when CS5528 used. depth (DP3-DP0) information bits configuration register determine many conversions performed hence must initialized before this conversion mode entered. Upon completion conversions, falls indicate that conversion data ready read. read conversions from conversion data FIFO, user must first issue SCLKs clear flag. read conversions, user must then supply 24x(N) SCLKs. defined here number logical channels being converted which decimal equivalent depth example, DP3-DP0 `0010', (2+1) return command mode, user must read conversion data from FIFO because serial port remains data mode during conversions during read data. Whether `00000000' `11111111' provided during SCLKs needed clear flag, serial port returns command mode after conversion data FIFO read. this case, rises falls once conversions complete indicate that data ready acquire; read conversion data FIFO remain this mode; this accomplished providing with `00000000' during first SCLKs then giving 24xN more SCLKs read conversion data; user must finish reading FIFO before first logical channel finishes conversion.
Based information provided CSRs, multiple conversions performed repeatedly logical channel CSR. This mode similar conversion mode when MC=1, LP=1, RC=0. only exception that converter stops waits conversion data FIFO emptied before conversions started. before falls when data complete. Once falls, user options: exit after emptying FIFO; this accomplished providing `11111111' during first SCLKs then giving 24xN more SCLKs read conversion data; empty conversion data FIFO remain this mode; this accomplished providing with `00000000' during first SCLKs then giving 24xN more SCLKs read conversion data. After FIFO emptied, converter returns CSRs (i.e. logical channel CSR#1) repeats.
Based information provided CSRs, multiple conversions repeatedly performed physical channels referenced logical channels CSRs. This conversion mode similar conversion mode when MC=1, LP=0, RC=X. Once conversion data converted conversions stored conversion data FIFO. only exception that converter then returns CSRs (i.e. logical channel repeats. before, falls indicate when data compete. Once falls, user three options: exit after reading conversion data FIFO; this accomplished providing `11111111' during first SCLKS then giving 24xN more SCLKs acquire conversion data; provide SCLKs remain this mode without reading data;
Calibration Protocol
perform calibration user must send command byte with MSB=1, pointer bits (CPB3CPB0) address desired logical channel calibrated, appropriate calibration bits (CC2-CC0) choose type calibration performed. Proper calibration assumes that CSRs have been previously initialized because information concerning physical channel, filter rate, gain range, polarity, comes from channel-setup register being addressed pointer bits command byte.
DS265PP3
CS5522/24/28
Once CSRs initialized future calibrations performed with command byte. Once calibration cycle complete falls results stored either gain offset register physical channel being calibrated. Note that additional calibrations performed same physical channel referenced different logical channel with different filter rates, gain ranges, conversion modes, last calibration results will replace effects from previous calibration only offset gain register available physical channel. final note that only calibration performed with each command byte. calibrate channels additional calibration commands necessary.
(CPB3-CPB0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Address
CSR#4
Logical Channel 10th 11th 12th 13th 14th 15th 16th
Pointers Command Byte
time calibration command issued (CB=1 proper CC2-CC0 bits set) time normal conversion command issued (CB=1, CC2=CC1=CC0=0, MC=0), bits D6-D3 CPB3 CPB0) command byte used pointers address logical channels channel-setup registers (CSRs). Table details pointer bits address. Note that CS5524, D6-D3 only 0000 0111 logical channels). CS5522, D6-D3 CPB3 CPB0) only 0000 0011 logical channels). Five example situations that user might encounter when acquiring conversion calibrating converter follow. These examples assume that user using CS5528 logical channels) that CSRs programmed with following physical channel order:
Table Command Byte Pointer Table
Example configuration register following bits shown: DP3-DP0 `1001', command byte issued `1XXXX000'. These settings instruct converter repeatedly perform multiple single conversions logical channels. order which channels converted falls after physical channel converted. acquire conversions SCLKs with required clear flag. Then more SCLKs required read conversion data from FIFO. order which data provided same order which channels converted. first bytes data correspond first logical channel which this example physical channel next bytes data correspond second logical channel which this example physical channel and, last bytes data corresponds 10th logical channel which here physical channel Since logical channels converted background, while data being read, user must finish reading conversion data FIFO before updated with conversions. exit this conversion mode user
DS265PP3
CS5522/24/28
must provide `11111111' during first SCLKs. byte provided, serial port returns command mode only after conversion data FIFO emptied this case conversions acquired). Note that this example physical channel converted five times. Each conversion could with same different filter rates depending setting logical channels Note that there only offset gain register physical channel. Therefore, physical channel only calibrated gain range selected during calibration. Specifying different gain range logical channel setting than range that calibrated will result gain error. Example configuration register following bits shown: DP3-DP0 `0101', command issued `1XXXX000'. These settings instruct converter perform single conversion logical channels once. order which channels converted falls after physical channel converted. acquire conversions SCLKs required clear flag. Then additional SCLKs required conversion data. Again, order which data provided same order which channels converted. After last bytes conversion data corresponding physical channel read, serial port automatically returns command mode where will remain until next valid command byte received. Example configuration register following bits shown: DP3-DP0 `XXXX', command byte issued `10011000'. These settings instruct converter repeatedly convert fourth logical channel CPB3-CPB0 `0011' (which happens physical channel this example). falls after physical channel converted. acquire conversion SCLKs required. first SCLKs needed clear flag. ExDS265PP3
ample `00000000' provided during first SCLKs, conversion performed again physical channel converter will remain data mode until `11111111' provided during first SCLKs following fall SD0. After `11111111' provided, additional SCLKs required transfer last bytes conversion data before serial port will return command mode. Example configuration register following bits shown: DP3-DP0 `XXXX', command issued `11110000'. These settings instruct converter convert 15th logical channel once, CPB3 CPB0 `1110' (which happens physical channel this example). falls after physical channel converted. read conversion, SCLKs then required. Once acquired, serial port returns command mode. Example configuration register following bits shown: DP3-DP0 `XXXX', command issued `10101101'. These settings instruct converter perform system offset calibration logical channel (which physical channel this example). During calibration serial port remains command mode. Once calibration completed, falls. perform additional calibrations, more commands have issued.
Notes: configuration register must written before channel-setup registers (CSRs) because depth information contained configuration register defines many CSRs use. CSRs need written irrespective single conversion multiple single conversion mode. When single conversions desired, channel address embedded command byte. multiple single conversion mode channels selected preprogrammed order based information contained CSRs depth bits (DP3-DP0) configuration register. Once CSRs programmed, multiple conversions logical channels performed issuing only command byte. single conversion mode also requires only command, whenever another
CS5522/24/28
different single conversion wanted, this command modified version issued again. NULL command used keep serial port command mode, once command mode.
Analog Input
Figure illustrates block diagram analog input signal path inside CS5522/24/28. front consists multiplexer, chopper-stabilized instrumentation amplifier with gain programmable gain section. instrumentation amplifier powered from from (Negative Bias Voltage) allowing CS5522/24 operated either analog input configurations. biased negative voltage between -1.8 -2.5 tied AGND (for CS5528, between -1.8V -2.5V lower input ranges when amplifier engaged). choice operating mode voltage depends upon input signal common mode voltage. input ranges, input signals AIN+ AIN- amplified
instrumentation amplifier. ground referenced signals with magnitudes less then should biased with -1.8 -2.5 tied between -1.8 -2.5 (Common Mode Signal) input AIN+ AIN- must stay between -0.150 0.950 ensure proper operation. Alternatively, tied AGND (except CS5528 where inputs AGND referenced) where input (Common Mode Signal) AIN+ AIN- must stay between 1.85 2.65 ensure that amplifier operates properly. input ranges, instrumentation amplifier bypassed input signals connected Programmable Gain block. Whether tied between -1.8 -2.5 tied AGND, (Common Mode Signal) input AIN+ AIN- must stay between VA+. CS5522/24/28 accommodate full scale ranges other than performing system calibration with-
AIN2+ AIN2AIN1+ AIN1-
CS5522
VREF+ VREF-
AIN4+ AIN4* AIN1+ AIN1-
CS5524
ININ-
Programmable Gain
Differential order delta-sigma modulator
Digital Filter
AIN8+ AIN7+ AIN1+
CS5528
also supplies negative supply voltage coarse/fine change buffers
Figure Multiplexer Configuration
DS265PP3
CS5522/24/28
limits specified. Calibration section more details. Another change full scale range increase decrease voltage reference other than Voltage Reference section more details. Three factors operating limits input span. They include: instrumentation amplifier saturation, modulator density, lower reference voltage. When range selected, input signal (including common mode voltage amplifier offset voltage) must cause amplifier saturate either input stage output stage. prevent saturation absolute voltages AIN+ AINmust stay within limits specified (refer `Analog Input' table page Additionally, differential output voltage amplifier must exceed equation ABS(VIN VOS) defines differential output limit, where (AIN+) (AIN-) differential input voltage absolute maximum offset voltage instrumentation amplifier (VOS will exceed mV). differential output voltage from amplifier exceeds amplifier saturate, which will cause measurement error. input voltage into modulator must cause modulator exceed percent high percent density. nominal full scale input span modulator (from percent percent density) determined VREF voltage divided Gain Factor. Table determine CS5522/24/28 being used properly. example, range, determine nominal input voltage modulator, divide VREF (2.5 Gain Factor (2.2727). When smaller voltage reference used, resulting code widths smaller causing converter output codes exhibit more changing codes fixed amount noise. Table based upon VREF other values VREF, values Table must scaled accordingly. Figure's illustrate input models VREF pins. dynamic input current each pins determined from models shown dependent upon setting CFS1 CFS0 (Chop Frequency Select) bits. effective input impedance AIN+ AINpins remains constant three level measurement ranges mV). input current lowest with bits cleared logic
Note: Residual noise appears converter's baseband output word rates greater than 61.6 bits logic eliminate residual noise word rates 61.6 lower, chopping recommended, 84.5 101.1 filters, 4096 chopping recommended. Note that C=48pF input current modeling only. physical input capacitance `Input Capacitance' specification under `Analog Characteristics' page
Ranges
fVos CFS1/CFS0 CFS1/CFS0 4096 CFS1/CFS0 16.384 CFS1/CFS0 1024 Ranges Fine Coarse
fVos
32.768
Figure Input models AIN+ AIN- pins each range.
DS265PP3
CS5522/24/28
Max. Differential Output Amplifier
Input Range(1)
VREF 2.5V 2.5V 2.5V 2.5V 2.5V 2.5V
Gain Factor 2.272727. 1.25
Nominal(1) Differential Input
-(1) Max. Input 0.75 1.65
Table Relationship between Full Scale Input, Gain Factors, Internal Analog Signal Limitations Note: converter's actual input range, delta-sigma's nominal full scale input, delta-sigma's maximum full scale input scale directly with value voltage reference. values table assume VREF voltage. limit output amplifier differential output voltage.
Fine Coarse 10pF 32.768
2.5V, ranges) voltage should more negative than -2.5 components Figure preferred components filter. However, smaller capacitors used with acceptable results. ensures very ripple NBV. Intrinsic safety requirements prohibit electrolytic capacitors. this case, four 0.47 ceramic capacitors parallel used.
Note: charge pump designed nominally provide 400µA current instrumentation amplifier when 0.03µF pumping capacitor used (XIN 32.768 kHz). When larger pumping capacitor used, charge pump source more current power external loads. Refer Applications Note more details using charge pump with external loads.
VREF 25mV fVos
Figure Input model VREF+ VREF- pins.
Charge Pump Drive
(Charge Pump Drive) converter used with external components (shown Figure develop appropriate negative bias voltage pin. When used generate NBV, voltage regulated with internal regulator loop referenced VA+. Therefore, change results proportional change NBV. With NBV's regulation proportional approximately -2.1 Figure illustrates means supplying voltage from supply. ground based signals with instrumentation amplifier engaged (when 25mV, 55mV, 100mV ranges), voltage should time less negative than -1.8 more negative than -2.5 prevent excessive voltage stress chip when instrumentation amplifier isn't engaged (when
Voltage Reference
CS5522/24/28 specified operation with reference voltage between VREF+ VREF- pins device. single-ended reference voltage, such LT1019-2.5, reference voltage input into VREF+ converter VREF- grounded. differential voltage between VREF+ VREF- voltage from VA+, however, VREF+ cannot above VREF- below NBV.
DS265PP3
CS5522/24/28
Calibration
CS5522/24/28 offer five different calibration functions including self calibration system calibration. However, after CS5522/24/28 reset, converter functional perform measurements without being calibrated. this case, converter will utilize initialized values on-chip registers (Gain 1.0, Offset 0.0) calculate output words ±100 range. initial offset gain errors internal circuitry chip will remain. gain offset registers, which used both self system calibration, used zero full-scale points converter's transfer function. offset register 2-24 proportion input span (bipolar span times unipolar span). offset register determines offset trimmed positive negative positive, negative). converter typically trim percent input span. gain register spans from 2-22). decimal equivalent meaning gain register
where binary numbers have value either zero corresponds MSB-1, N=22). Refer Table details. offset gain calibration steps each take conversion cycle complete. calibration step, falls calibration control bits will back logic
Self Calibration
CS5522/24/28 offer both self offset self gain calibrations. self-calibration offset 25mV, 55mV, 100mv ranges, converters internally inputs instrumentation amplifier together route them AINpin shown Figure CS5528 they routed AGND). proper self-calibration offset occur ranges, AIN- must proper common-mode-voltage specified `Common Mode +Signal AIN+/-' specification under `Analog Input' section page AIN- must between -1.8 -2.5 self-calibration offset ranges, inputs modulator connected together then routed VREF- shown Figure self-calibration gain, differential inputs modulator connected VREF+ VREF- shown Figure input range
Offset Register
Register
Reset
Sign
2-20 2-21 2-22 2-23 2-24
2-19
represents 2-24 proportion input span (bipolar span times unipolar span) Offset data word bits align (bit MSB-4 offset register changes MSB-4 data)
Gain Register
Register
Reset
2-18 2-19 2-20 2-21 2-22
2-17
gain register span from (4-2-22). After Reset (MSB-1) other bits Table Offset Gain Registers DS265PP3
CS5522/24/28
other than range, converter's gain error completely calibrated out. This lack accurate full scale voltage internal chips. range exception because external reference voltage nominal used full scale voltage. addition, when self-calibration gain performed input ranges, instrumentation amplifier's gain calibrated. These factors leave converters with gain error ±20% after self-calibration gain. Therefore, system gain calibration required better accuracy, except range. perform system gain calibration. either case, calibration signals must within specified calibration limits each specific calibration step (refer System Calibration Specifications). system gain calibration performed following conditions must met: Full-scale input must saturate instrumentation amplifiOPEN AIN+ AINVREF+ Reference VREFCLOSED
OPEN
System Calibration
system calibration functions, user must supply converters calibration signals which represent ground full scale. When system offset calibration performed, ground reference signal must applied converters. Figures shown Figures user must input signal representing positive full scale point
OPEN AIN+ CLOSED AIN+
CLOSED
Figure Self Calibration Gain (All Ranges).
External Connections AIN+ AINX20
Figure System Calibration Offset (Low Ranges).
External Connections AIN+ AIN+
Figure Self Calibration Offset (Low Ranges).
OPEN CLOSED AIN+ AINVREFS2 OPEN CLOSED
Figure System Calibration Offset (High Ranges).
External Connections
AIN+ Full Scale AIN-
Figure Self Calibration Offset (High Ranges).
Figure System Calibration Gain (Low Ranges)
DS265PP3
CS5522/24/28
(Rc0/G Ru0)
External Connections AIN+ Full Scale
where (Rc1 Rc0)/(Ru1-Ru0).
Note: Uncalibrated conversions imply that gain offset registers default {gain register 0x400000 (Hex) offset register 0x000000 (Hex)}.
AIN-
Figure System Calibration Gain (High Ranges).
variables defined below.
First calibration voltage Second calibration voltage (greater than Result uncalibrated conversion Result uncalibrated conversion (24-bit integer complement) Result uncalibrated conversion (24-bit integer complement) Result conversion Desired calibrated result converting (24-bit integer complement) Desired calibrated result converting (24-bit integer complement) Offset calibration register value (24-bit complement) Gain calibration register value (24-bit integer)
calibration input range where instrumentation amplifier involved. density modulator must greater than percent (the input modulator must exceed maximum input which Table specifies). input must cause resulting gain register's content, decoded decimal, exceed 3.9999998 (see discussion operating limits input span under Analog Input Limitations Calibration Range sections). above conditions require full scale input voltage modulator least percent nominal value. converter's input ranges were chosen guarantee gain calibration accuracy when gain calibration performed. This useful when user wants manually scale full scale range converter maintain accuracy. example, gain calibration performed with full scale voltage 1.25 input range desired, user read contents gain register, shift bit, then write results back gain register. Assuming system provide known voltages, following equations allow user manually compute calibration register's values based uncalibrated conversions (see note). offset gain calibration registers used adjust typical conversion follows: 222. Calibration performed using following equations:
Calibration Tips
Calibration steps performed output word rate selected WR2-WR0 bits configuration register. Since higher word rates result conversion words with more peak-to-peak noise, calibration should performed lower output word rates. Also, minimize digital noise near device, user should wait each calibration step completed before reading writing serial port. maximum accuracy, calibrations should performed offset gain (selected changing G2-G0 bits configuration register). Note that only gain range calibrated physical channel. factory calibration user's system performed using system calibration
DS265PP3
CS5522/24/28
capabilities CS5522/24/28, offset gain register contents read system microcontroller recorded EEPROM. These same calibration words then uploaded into offset gain registers converter when power first applied system, when gain range changed. converter. outputs sink source least recommended limit drive currents less than reduce self-heating chip. These outputs powered from VA+, hence, their output voltage logic will limited voltage.
Output Word Rate Selection
WR2-WR0 bits channel-setup registers output conversion word rate converter shown Table word rates indicated table assume master clock 32.768 kHz. Upon reset converter operate with output word rate 15.0
Limitations Calibration Range
System calibration limited signal headroom analog signal path inside chip discussed under Analog Input section this data sheet. gain calibration full scale input signal reduced point which gain register reaches upper limit (4-2-22 decimal) FFFFFF (hexadecimal). Under nominal conditions, this occurs with full scale input signal equal about nominal full scale. With converter's intrinsic gain error, this full scale input signal higher lower. defining minimum Full Scale Calibration Range (FSCR) under "Analog Characteristics", margin retained accommodate intrinsic gain error. Alternatively input full scale signal increased point which modulator reaches density limit percent, which under nominal condition occurs when full scale input signal times nominal full scale. With chip's intrinsic gain error, this input full scale input signal maybe higher lower. defining maximum FSCR, margin again incorporated accommodate intrinsic gain error. addition, full scale inputs greater than nominal full scale value range selected, there some voltage which various internal circuits saturate limited amplifier headroom. This most likely occur 100mV range.
Clock Generator
CS5522/24/28 include gate which connected with external crystal provide master clock chip. chips designed operate using low-cost 32.768 "tuning fork" type crystal. lead crystal should connected other XOUT. Lead lengths should minimized reduce stray capacitance. converters will operate with external (CMOS compatible) clock with frequencies 100kHz crystal. Figure details converter's performance increased clock rates.
Figure High Speed Clock Performance
Analog Output Latch Pins
A1-A0 pins converter mimic D23/D11-D22/D10 bits channel setup registers. A1-A0 used control external multiplexers other logic functions outside
32.768 crystal normally specified time-keeping crystal with tight specifications both initial frequency drift over temperature. maintain excellent frequency stability, these crystals specified only over limited operating temperature ranges (i.e. °C).
DS265PP3
CS5522/24/28
However, applications with CS5522/24/28 don't generally require such tight tolerances.
Digital Filter
CS5522/24/28 have eight different linear phase digital filters which output word rates (OWRs) stated Table These rates assume that 32.768 kHz. Each filters magnitude response similar that shown Figure filters optimized settle full accuracy every conversion yield better than rejection both with output word rates below 15.0 converter's digital filters scale with XIN. example with output word rate filter's corner frequency typically 12.7 increased 64.536 doubles filter's corner frequency moves 25.4
Figure Filter Response (Normalized Output Word Rate
Output Coding
CS5522/24/28 output data binary format when operating unipolar mode two's complement when operating bipolar mode.
output conversion word bits, three bytes long, shown Table output first followed rest data bits descending order.
Power Consumption
CS5522/24/28 accommodate four power consumption modes: normal, power, standby,
Output Conversion Data bits)
Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5
Offset Binary FFFFFF FFFFFF -FFFFFE 800000 -7FFFFF 000001 -000000 000000
Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5
Two's Complement 7FFFFF 7FFFFF -7FFFFE 000000 -FFFFFF 800001 -800000 800000
VFS/2-0.5
-0.5
+0.5 <(+0.5 LSB)
-VFS+0.5 <(-VFS+0.5 LSB)
Note: table equals voltage between ground full scale unipolar gain ranges, voltage between full scale bipolar gain ranges. text about error flags under overrange conditions. Table CS5522/24/28 Output Coding Data Conversion Word DS265PP3
CS5522/24/28
sleep. normal mode, default mode, entered after power-on-reset typically consumes power mode alternate mode that reduces consumed power entered setting (the power mode bit) configuration register logic Slightly degraded noise linearity performance should expected power mode. final modes referred power save modes. They power down most analog portion chip stop filter convolutions. power save modes entered whenever PS/R configuration register logic particular power save mode entered depends state (PSS, Power Save Select bit) configuration register. logic converter enters standby mode reducing power consumption standby mode leaves oscillator on-chip bias generator running. This allows converter quickly return normal power mode once PS/R back logic PS/R configuration register logic sleep mode entered reducing consumed power around Since sleep mode disables oscillator, approximately 500ms oscillator start-up delay period required before returning normal power mode.
Layout
CS5522/24/28 should placed entirely over analog ground plane with both AGND DGND pins device connected analog plane. Place analog-digital plane split immediately adjacent digital portion chip. separate digital (VD+) analog (VA+) supplies used, recommended that diode placed between them (the cathode diode should point VA+). digital supply comes before analog supply, start properly.
Note: CDB5522 data sheet suggested layout details Applications Note more detailed layout guidelines. Before layout, please call Free Schematic Review Service.
DS265PP3
CS5522/24/28
DESCRIPTIONS
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT NEGATIVE BIAS VOLTAGE LOGIC OUTPUT
CHARGE PUMP DRIVE
AGND
AIN1+
VREF+
VREFAIN2+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT SERIAL CLOCK INPUT
POSITIVE DIGITAL POWER
CS5522
AIN1NBV
AIN2A1 SCLK DGND XOUT
SERIAL DATA INPUT CHIP SELECT CRYSTAL
DIGITAL GROUND SERIAL DATA CRYSTAL
ANALOG GROUND POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
NEGATIVE BIAS VOLTAGE
AGND
AIN1+
VREF+
VREFAIN2+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT
LOGIC OUTPUT
CS5524
AIN1AIN3+ AIN3NBV
AIN2AIN4+ AIN4A1 SCLK DGND
LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL
SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA CRYSTAL
XOUT
ANALOG GROUND POSITIVE ANALOG POWER SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT
NEGATIVE BIAS VOLTAGE
AGND
AIN1+
VREF+
VREFAIN3+
VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT SINGLE-ENDED ANALOG INPUT
LOGIC OUTPUT
CS5528
AIN2+
AIN5+ AIN6+
AIN4+
AIN7+ AIN8+ SCLK DGND
LOGIC OUTPUT CHARGE PUMP DRIVE SERIAL DATA INPUT CHIP SELECT CRYSTAL
SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA CRYSTAL
XOUT
DS265PP3
CS5522/24/28
Clock Generator
XIN; XOUT Crystal Crystal Out. gate inside chip connected these pins used with crystal provide master clock device. Alternatively, external (CMOS compatible) clock supplied into provide master clock device.
Control Pins Serial Data
Chip Select. When active low, port will recognize SCLK. When high will output high impedance state. should changed when SCLK Serial Data Input. input serial input port. Data will input rate determined SCLK. Serial Data Output. serial data output. will output high impedance state SCLK Serial Clock Input. clock signal this determines input/output rate data SDI/SDO pins respectively. This input Schmitt trigger allow slow rise time signals. SCLK will recognize clocks only when low. Logic Outputs. logic states A0-A1 mimic states D22/D10-D23/D11 bits channel-setup register. Logic Output AGND, Logic Output VA+.
DS265PP3
CS5522/24/28
Measurement Reference Inputs
AIN1+, AIN1-, AIN2+, AIN2- AIN3+, AIN3-, AIN4+, AIN4- Differential Analog Input. Differential input pins into CS5522 CS5524 devices. AIN1+, AIN2+, AIN3+, AIN4+, AIN5+, AIN6+, AIN7+, AIN8+ Single-Ended Analog Input. Single-ended input pins into CS5528. VREF+, VREF- Voltage Reference Input. Fully differential inputs which establish voltage reference on-chip modulator. Negative Bias Voltage. Input supply negative supply voltage gain instrumentation amplifier coarse/fine charge buffers. tied AGND AIN+ AIN- inputs centered around +2.5 tied negative supply voltage (-2.1 typical) allow amplifier handle level signals more negative than ground. When using CS5528 either 25mV, 55mV 100mV range, analog inputs expected ground referenced; therefore, must between -1.8 -2.5 ensure proper operation. Charge Pump Drive. Square wave output used provide energy charge pump.
Power Supply Connections
Positive Analog Power. Positive analog supply voltage. Nominally Positive Digital Power. Positive digital supply voltage. Nominally +3.0 AGND Analog Ground. Analog Ground. DGND Digital Ground. Digital Ground.
DS265PP3
CS5522/24/28
SPECIFICATION DEFINITIONS
Linearity Error deviation code from straight line which connects endpoints Converter transfer function. endpoint located below first code transition other endpoint located beyond code transition ones. Units percent full-scale. Differential Nonlinearity deviation code's width from ideal width. Units LSBs. Full Scale Error deviation last code transition from ideal [{(VREF+) (VREF-)} LSB]. Units LSBs. Unipolar Offset deviation first code transition from ideal (1/2 above voltage AIN- pin.). When unipolar mode (U/B Units LSBs. Bipolar Offset deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). When bipolar mode (U/B Units LSBs.
ORDERING GUIDE
Model Number CS5522-AP CS5522-AS CS5524-AP CS5524-AS CS5528-AP CS5528-AS Linearity Error (Max) ±0.0015% ±0.0015% ±0.0015% ±0.0015% ±0.0015% ±0.0015% Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C Package 20-pin 0.3" Skinny Plastic 20-pin 0.2" Plastic SSOP 24-pin 0.3" Skinny Plastic 24-pin 0.2" Plastic SSOP 24-pin 0.3" Skinny Plastic 24-pin 0.2" Plastic SSOP
DS265PP3
CS5522/24/28
PLASTIC (PDIP) PACKAGE DRAWING
SEATING PLANE
VIEW
SIDE VIEW
BOTTOM VIEW
INCHES 0.155 0.020 0.015 0.050 0.008 0.960 0.240 0.095 0.300 0.125 0.180 0.040 0.022 0.065 0.015 1.040 0.260 0.105 0.325 0.150
MILLIMETERS 3.94 4.57 0.51 1.02 0.38 0.56 1.27 1.65 0.20 0.38 24.38 26.42 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81
Notes: Positional tolerance leads shall within 0.25 (0.010 in.) maximum material condition, relation seating plane each other. Dimension center leads when formed parallel. Dimension does include mold flash.
DS265PP3
CS5522/24/28
SKINNY (PDIP) PACKAGE DRAWING
SEATING PLANE
VIEW
SIDE VIEW
BOTTOM VIEW
INCHES 0.155 0.020 0.014 0.040 0.008 1.235 0.240 0.095 0.300 0.125 0.180 0.040 0.022 0.065 0.015 1.265 0.260 0.105 0.325 0.150
MILLIMETERS 3.94 4.57 0.51 1.02 0.36 0.56 1.02 1.65 0.20 0.38 31.37 32.13 6.10 6.60 2.41 2.67 7.62 8.25 3.18 3.81
Notes: Positional tolerance leads shall within 0.25 (0.010 in.) maximum material condition, relation seating plane each other. Dimension center leads when formed parallel. Dimension does include mold flash.
DS265PP3
CS5522/24/28
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.272 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.295 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 6.90 7.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS265PP3
CS5522/24/28
SSOP PACKAGE DRAWING
SIDE VIEW
VIEW
SEATING PLANE
VIEW
INCHES -0.002 0.064 0.009 0.311 0.291 0.197 0.024 0.025 0.084 0.010 0.074 0.015 0.335 0.323 0.220 0.027 0.040
MILLIMETERS -2.13 0.05 0.25 1.62 1.88 0.22 0.38 7.90 8.50 7.40 8.20 5.00 5.60 0.61 0.69 0.63 1.03
NOTE
Notes: "E1" reference datums included mold flash protrusions, include mold mismatch measured parting line, mold flash protrusions shall exceed 0.20 side. Dimension does include dambar protrusion/intrusion. Allowable dambar protrusion shall 0.13 total excess dimension maximum material condition. Dambar intrusion shall reduce dimension more than 0.07 least material condition. These dimensions apply flat section lead between 0.10 0.25 from lead tips.
DS265PP3
Notes
Preliminary product information describes products which production, which full characterization data available. Advance product information describes products which development subject development changes. Cirrus Logic, Inc. made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Cirrus Logic, Inc. this information, infringements patents other rights third parties. This document property Cirrus Logic, Inc. implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc. Items from Cirrus Logic website disk printed user. However, part printout electronic files copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise) without prior written consent Cirrus Logic, Inc.Furthermore, part this publication used basis manufacture sale items without prior written consent Cirrus Logic, Inc. names products Cirrus Logic, Inc. other vendors suppliers appearing this document trademarks service marks their respective owners which registered some jurisdictions. list Cirrus Logic, Inc. trademarks service marks found http://www.cirrus.com.
Other recent searches
VRPB-10A - VRPB-10A VRPB-10A Datasheet
TSM5ND50 - TSM5ND50 TSM5ND50 Datasheet
TR250-120 - TR250-120 TR250-120 Datasheet
PP1101SB - PP1101SB PP1101SB Datasheet
LL-304BC2G-001 - LL-304BC2G-001 LL-304BC2G-001 Datasheet
HD6433664 - HD6433664 HD6433664 Datasheet
DSP1629 - DSP1629 DSP1629 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
