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CD1283/'1284 Evaluation
2001, this document replaces Basis Communications Corp. document AN-CD6.
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. CD1283/1284 Evaluation contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
CD1283/'1284 Evaluation
Contents
Evaluation Contents
Hardware. Software 1.2.1 References
Introduction Supplemental Information
Interrupts CD1283/'1284 DMAACK Select Ordering Information System Requirements Evaluation Board 4.2.1 Switches Jumpers Running Demonstration Software Functional Blocks Using Parallel Channel.11 6.2.1 Channel Initialization 6.2.2 Data Pipeline Channel Operation 6.3.1 Receiving Data Compatibility Mode.14 6.3.2 Receiving Data Mode.14 6.3.3 Changing Directions 6.3.4 Transmit Data Reverse Nibble Mode.16 6.3.5 Transmit Data Reverse Byte Mode.16 6.3.6 Transmit Data Mode.16 Mode Initialization Code Service Requests 7.2.1 Parallel Port.19 7.2.2 Pipeline.21 7.2.3 Miscellaneous Pipeline Routines.22 Flowcharts
Hardware Installation
Software Installation
CD1283/'1284 Parallel Channel Programming Guide
Programming Examples
Equations Schematic
CD1283/'1284 Evaluation
Figures
Polling Method Interrupt-Driven Method
Tables
Switch Setup Jumpers Eligible Switch Jumper Settings
CD1283/'1284 Evaluation
Evaluation Contents
Hardware
CD1284 Evaluation Board IEEE Std. 1284 type IEEE Std. type cable
Software
Floppy disk contents:
CD1284 programming examples Genoa test suite programming example CD1284 schematics
1.2.1
References CD1283 Datasheet CD1284 Datasheet
Introduction
This document describes CD1283/'1284 evaluation board.This board buscompatible plug-in board. This board used evaluate CD1283 CD1284 devices using provided software documentation, customer-based software used. board also function development tool easy-to-use environment (IBM PC-compatible). Therefore, code implementation begin while hardware design/debug phase. serial ports CD1283/'1284 used, custom cables must built user. Section page describes hook-up procedures, jumper settings, board address assignments. Section page describes installation operation demonstration software.
CD1283/'1284 Evaluation
Supplemental Information
Interrupts
board provides optional interface methods CD1283/'1284. These options interrupt selection optional access device. interrupt generated board CD1283/'1284. This interrupt selected jumper wires jumper block JP8. left column pins jumper block indicate interrupt number that selected; right column pins selection pins with interrupt source. This interrupt wired interrupts appropriate system use.
CD1283/'1284 DMAACK Select
DMAACK input CD1283/'1284 driven from either sources:
DMAACK input from address decode from on-board address
decoder (see users manual address assignment).This option allows evaluation CD1283/'1284 without programming controller
cycles emulated performing 16-bit read write from defined
address decode. selection made through jumper which should 2-3. programmed method emulation should used. Jumper locations reserved future development.
Ordering Information
Number: CDK1284-E-AT02A
Software examples floppy disk evaluation documentation ordered separately from Intel additional charge.
CD1283/'1284 Evaluation
Hardware Installation
System Requirements
system requirements are:
PC/AT compatible with minimum 640K available 16-bit expansion slot version higher
Evaluation Board
evaluation board add-on card with type IEEE, 36-pin parallel port connector, RJ-45 serial connectors, MACH120, CD1283/'1284. Note: Verify that CD1283/'1284 latest version. device should printed with CD128410QC-E. not, please return board Intel replacement.
4.2.1
Switches Jumpers
includes eight switches; each convey certain information jumper consists gold pins that connected plastic connector plug. port address 8-bit pattern 01001000xxx (binary) 240h. card allocates base addresses from 0x240 0x25F. description these valid addresses provided Table Table presents jumper definitions Table provides switch settings.
Table
Switch Setup
Base Address 0x240 0x242 0x244 0x246 0x248 0x24A 0x24C 0x24D 0X250 0X252 Address Description RESERVED RESERVED CD1283/'1284 register address CD1283/'1284 reset CD1283/'1284 SVCACKR SVCACKT SVCACKP SVCACKM Generate DMAACK CD1283/'1284.
CD1283/'1284 Evaluation
Table
Jumpers
Jumper Request (DREQ Acknowledge (DACK
Motorola /Intel format selector CD1283/'1284
Reset switch Quickturn connector Quickturn connector Quickturn connector select through CD1283/'1284 acknowledge selector (JP2 command from
Table
Eligible Switch Jumper Settings
Base Address 0x200 0x220 0x240 0x260 0x280 0x2A0 0x2C0 0x2E0 0x300 0x320 0x340 0x360 0x380 0x3A0 0x3C0 0x3E0
CD1283/'1284 Evaluation
Software Installation
CD1283/'1284 demonstration software provided floppy disk with directories:
1284: genrn.c genrn.exe programs perform Genoa test suite. BOARD: CD1283/'1284 evaluation board schematics, MACH120 schematics, 22V10
schematics OrCad.
DOC: CD1283/'1284 technical documentation (portable document format)
online viewing.
EVAL1284:Two programs that demonstrate CD1283/'1284 programming, operation
device.
MISC1284: Miscellaneous programming examples. INTERRUPT: interrupt-driven code program demonstration.
Running Demonstration Software
There should when running these programs; host other target. Copy host1284.exe from EVAL1284 directory host Copy eval1284.exe from EVAL1284 directory target host1284.exe host simultaneously eval1284.exe target Type target initialize CD1283/'1284 registers. Type `n10' host interface negotiates Forward. Note: other values refer IEEE Std. 1284-1994, page Table Type target view CD1283/'1284 register contents after negotiations. Type host terminate from current protocol. Type target list CD1283/'1284 register contents after protocol termination. Note: eval1284.exe runs CD1284 evaluation board; host1284.exe runs Warp Nine Engineering (previously called Point Communications) parallel port host. Warp Nine parallel card obtained from Warp Nine Engineering directly (phone: (805) 726-4420; fax: (805) 726-4438; www.fapo.com). name parallel card used Intel F/PortPlus parallel card.
CD1283/'1284 Evaluation
CD1283/'1284 Parallel Channel Programming Guide
CD1283/'1284 parallel channel provides unique features straightforward IEEE 1284compatible interface programming. Many functions built into device, such automatic negotiation among various protocols (reverse nibble, reverse byte, ECP, EPP), built-in onthe-fly data compression using length encoding/decoding, simple handshake, programmable FIFO threshold. These functions free from parallel interface interactions helps eliminate some mundane tasks associated with higher-level protocol implementation. parallel channel CD1283/'1284 comprised major functional blocks: local data interface parallel port control state machine. interface further subdivided into three blocks: 64-byte FIFO, data pipeline, buffer register.These major blocks share interrupt logic block that informs conditions that require direct intervention.
Functional Blocks
Although separate entities, interface parallel port state machine tightly coupled through data interface that includes data transfer buffer/latch status/control signals. Depending upon direction data movement within parallel channel, control status indicate current state FIFO state data parallel port. receive direction, FIFO control logic moves data into FIFO space available). response parallel port request space available) `move request' honored. parallel port remains BUSY state, stopping further transfers from remote. transmit direction, status signals from FIFO indicate data available transfer remote. data available remote BUSY state, parallel port transmits byte FIFO. enabled quantity data FIFO equal exceeds programmed threshold (receive direction) equal less than programmed threshold (transmit direction), transfer cycle initiates. data pipeline logic attempts fill FIFO transmit direction; attempts empty when threshold reached receive direction.Two registers used this determination, PFTR (Parallel FIFO Threshold register) PFQR (Parallel FIFO Quantity register). Data always moved into FIFO 16-bit words; bytes must handled directly CPU. byte, once FIFO time-out occurs receive direction, removes remaining byte from PFHR2 (Parallel FIFO Holding register transmit direction, byte block transfer placed FIFO through PFHR1 (Parallel FIFO Holding register Figures CD1284 datasheet graphic presentation FIFO/data pipeline structure. CD1283/'1284 port works conjunction with system controller. handshake signals, DMAREQ* DMAACK*, provided communication with system controller. When device ready transfer, activates DMAREQ*, which remains active until three events occur: FIFO full (transmit) FIFO empty (receive) transfers disabled
CD1283/'1284 Evaluation
duration transfer controlled threshold setting. example, burst words maximum required transmit direction, PFTR value would equal full FIFO (the FIFO byte-organized filled word increments, where bytes words) minus desired burst size.(in this case, 20). When FIFO quantity falls below this point, CD1283/'1284 activates DMAREQ* remains effect until words bytes) moved into FIFO. each word transferred system activates DMAACK* once. This procedure reversed receive direction. receive direction, same 20-word burst desired, threshold should When FIFO quantity reaches this point, logic attempts empty FIFO. Since holding registers included burst count, threshold should actually less than desired burst length, this case, After device initialization, CD1283/'1284 parallel channel enters Compatibility mode where parallel port input-only Centronics -compatible port. port receives data; handshake signals operate defined Compatibility mode IEEE specification. other mode move data bidirectionally, CD1283/'1284 must negotiate with remote master 1284 device. Also, CD1283/'1284 must have negotiations enabled desired mode(s). When remote master attempts negotiations into other modes, enabled mode accepted device. Note: CD1283/'1284 cannot move into bidirectional modes own; remote master required. Modes enabled (Negotiation Enable register). Typically, modes would enabled that peripheral communicates mode requested remote. However, only some modes supported, only bits corresponding those modes set. When successful negotiation completes, CD1283/'1284 posts interrupt notifying change. (Negotiation Status register) indicates negotiation results mode entered. status bits indicate negotiation completed correctly, NegOK, with error, NegFI. invalid negotiation attempted (the extensibility request bits during negotiations were recognized value), then NegFI status along with Invalid status bit. invalid state requested entered, port returns Compatibility mode (default); port failures force return Compatibility mode. Refer IEEE Std. 1284-1994 specification detailed discussion negotiation sequence.
Using Parallel Channel
Several steps must performed before parallel channel used. example, basic channel initialization must performed. Examples include: setting correct count short pulse duration based frequency master device clock, setting FIFO threshold, enabling supported modes, Once initialization operations complete, should system controller receiving transmitting data. Finally, interrupts, DMA, parallel port transfers should enabled CD1283/'1284. Each these initialization operations detailed Section 6.2.1. purposes this document, operating frequency clock (CLK) MHz. Also, serial channels CD1283/'1284 ignored. Manual control channel
through Manual mode Manual Data register discussed; this mode intended primarily testing special cases considered part normal operation. Flowcharts various operations provided Section 7.3.
CD1283/'1284 Evaluation
6.2.1
Channel Initialization
initialization channel performed sequences: First parallel port then data pipeline.
6.2.1.1
Parallel Port
During initialization parallel port, supported modes must first selected setting appropriate enable bits NER. E1284 (Parallel Configuration
register) must higher-level parallel port operations. ETxfr must also transfers port. However, this after controller interface have been initialized. transfers enabled begin before transfers occur, FIFO fills port BUSY state.
Note: This error inconsistent with rest system programming. step that must performed proper operation parallel interface setting minimum pulse width defined IEEE specification. This pulse width
duration allows maximum data transfer performance; however, longer pulse widths allowed.
pulse width value programmed (Short Pulse register). simple counter/divider driven input therefore, value loaded depends upon
operating clock frequency CD1283/'1284. 25-MHz clock, proper value this value produces minimum pulse width close generated with 25-MHz clock).
520ns 25MHz
mode support, load (EPP Address register) with value driven parallel port during address read cycle. control registers used during normal, non-compatible mode 1284 transfers with parallel port. exception during mode. this case, three signals
(Output Value register) user-defined labeled USER1-USER3. these three signals used, then their value before mode entered.
Compatibility mode, delivers port status host. This status might consist paper empty, fault, status pins, host must place port into Manual
mode, desired status OVR, then resume normal operation.
final step initializing parallel port setting interrupt enable bits required PCIER (Parallel Channel Interrupt Enable register). Under normal operating conditions,
interrupts should enabled. However, some modes supported, bits set. example, mode enabled, EPPAW (EPP Address Write) interrupt enable need set.
This completes parallel port configuration. next step configuring data path registers.
CD1283/'1284 Evaluation
6.2.2
Data Pipeline
data pipeline registers FIFO control, circuitry, timer. There also several registers that display current status entire pipeline. FIFO data threshold used triggering transfers PFTR. During operation, CD1283/'1284 compares this value that PFQR (Parallel FIFO Quantity
register) burst requirement. receive direction, PFQR greater than PFTR, device requests transfer empty FIFO. remains active until last full word (16-bits) transferred; remaining byte left PFHR2 remove manually. transmit direction, PFQR less than PFTR, transfers occur remain active until FIFO full.
CD1283/'1284 ensures that data trapped FIFO (`stale') amount data received does reach threshold programmed PFTR. This feature
implemented with stale data timer. timer duration value placed SDTPR (Stale Data Timer Period register). timer driven clock generated dividing master device clock (CLK) 250. This `intermediate' clock then prescaled fixed divide-by-ten algorithm produce basic stale timer period. Thus,
with 25-MHz clock, resolution timer Each time character placed FIFO, SDTCR (Stale Data Timer Count register) loaded from value SDTPR. data does arrive restart timer,
expires after programmed duration SDTPR. This forces `stale' condition become true triggers transfer empty FIFO.
purpose this timer determine when block transmission complete. Data arriving considered block `frame' data, normal protocol moving parallel
data between host peripheral does include concept message therefore, does have defined delimiting message from another. However, once text block transmits commands transmit from high-level page-description language such PostScript), there pause while block prepared. This pause enables timer expire, allowing local assume transmission complete.
There several miscellaneous control bits special pipeline operations. These bits PACR (Parallel Auxiliary Control register). During initialization process, only bits
this register used, Unfair Async DMA. Unfair associated with serial channels. Async provides alternate timing control circuitry. These bits discussed CD1284 Datasheet, relevant this document.
vector driven data during parallel channel service acknowledge cycle (SVCACKP* input) LIVR (Local Interrupt Vector register). most-
significant five bits appropriate value system interrupt service routine. least-significant three bits supplied CD1283/'1284 indicate interrupt source within parallel channel (pipeline, parallel port, both).
PFCR (Parallel FIFO Control register) must enable channel supported special operations. beginning activity within parallel channel, FIFO reset
command desired DMAdir must issued. This initializes channel sets direction pipeline parallel port. This procedure must performed whenever direction parallel channel changed. RLEen must also RunLength data compression supported mode.
CD1283/'1284 Evaluation
Channel Operation
operation descriptions that follow assume that interface Compatibility mode (default state after device reset) that preceding initialization procedures were performed.
Final initialization includes setting IntEn that interrupts generated parallel channel. ErrEn must also interrupt sources Data Error register included interrupts from channel. Finally, DMAen enable transfers.
parallel channel operates many modes moves freely between modes command remote master. CD1283/'1284 never change modes own;
must always wait master complete negotiation sequence. Available modes enabled individually control bits NER. mode operation differs significantly from other modes. does incorporate `receive' `transmit' behaves more like processor address/data bus. such, included with other modes that follow. Section page more details mode.
6.3.1
Receiving Data Compatibility Mode
data arrives parallel port, begins filling FIFO. first bytes will fall through bottom FIFO then into holding registers, PFHR1 PFHR2.
Subsequent data continues filling FIFO. transfers when programmed threshold reached continue until FIFO holding registers empty. Incoming data continue filling holding registers FIFO until threshold once again reached, then transfers commence. request signal (DMAREQ*) remains active until FIFO empty, this programmed threshold sets burst duration transfer.
incoming data ceases period longer than programmed stale data time-out period, situations occur. there data pipeline because even number bytes
received, nothing occurs, except Stale PFSR set.
transfers leave single character holding register because interface only performs 16-bit transfers. such, number bytes received, time-out occurs.
addition time-out indication, OneChar status indicating that must manually remove last byte transfer from holding register.
must then toggle ClrTO PACR remove Time-out interrupt status rearm time-out mechanism next transfer from parallel port.
6.3.2
Receiving Data Mode
remote master opts mode, enter negotiations with CD1283/'1284 this
mode. local must have previously enabled mode NER. Upon completion negotiation sequence, CD1283/'1284 posts interrupt with status indicating that negotiation change occurred. mode indicated four-bit result code. purpose this document, assumed that transfer direction remains receive.
CD1283/'1284 Evaluation
Unless data compression enabled compressed data being received, basic operation parallel channel mode receive same Compatibility mode.
transfers commence when level FIFO reaches programmed threshold continues until FIFO empty time-out occurs single character remaining holding registers more data remains.
compression enabled RLE-compressed data being received, behavior pipeline (the holding registers plus buffer) changes slightly. RLE-compressed
data sent over parallel interface two-byte sequence; command data byte (refer IEEE 1284 Std. specification complete description mode compression.). command byte indicates that this pair compressed includes byte count; second byte data replicated. pipeline stores count, then repeats data while decrementing counter. resultant count repeated characters odd, then last character compressed sequence joined next character FIFO form full 16-bit word transfer. character last character transfer time-out occurs, then OneChar interrupt generated.
other function available mode. addition compression using command/data sequences, address received using address-command/address
byte sequence. When CD1283/'1284 receives address command, stops movement posts interrupt indicating that `tagged' byte been received. must manually remove tagged character from holding register. PFSR HRSR (Holding Register Status register) determine that tagged character been received which holding register After tagged character removed from holding register, normal data movement continues.
Note that compression enabled PFCR, receipt compressed data
sequence causes data movement stop tagged-data interrupt occur.
6.3.3
Changing Directions
send data remote master, link must reversed. Reversal occurs when master negotiates into directions capable reverse transfers (Reverse Nibble, Reverse
Byte, ECP, EPP) local data send. Status indicating availability data provided parallel interface during negotiation sequence differs implementation each mode; however, procedure used local same. special case reverse-data transfer quite different from others. method moving data reverse direction discussed Section 6.4.
important remember that CD1283/'1284 cannot initiate reversal; must wait remote master initiate reversal with negotiation sequence. CD1283/'1284
request direction reversal through RevRq Special Command register.
CD1283/'1284 requests reversal using command SCR, RevRq (bit When local ready send data remote master, sets RevRq waits
remote perform negotiation sequence. Then, CD1283/'1284 activates appropriate signal, nDataAvail, indicate that reverse data available. When negotiations complete, CD1283/'1284 posts interrupt local indicating direction change (the DirChg PCISR). Upon receipt this direction change interrupt, should proceed change direction parallel channel through command PFCR. This done setting FIFOres DMAdir bits. Program PFTR next threshold changed transmit direction.
CD1283/'1284 Evaluation
Finally, after programming system controller, DMAen PFCR initiate actual reverse data transfer. specified IEEE Std. 1284 specification,
this data pipeline direction change allowed take infinite amount time occur. When pipeline FIFO have been reversed, transfers begin filling FIFO. When first data byte available parallel port, begins moving data with defined Strobe/Acknowledge sequence.
With exception mode, transmitting data remote Reverse Nibble, Reverse Byte modes occurs similar ways. long data available, nDataAvail status
remains asserted remote continues data. When there longer data FIFO, nDataAvail deasserts, which time remote master might negotiate back into forward data direction return forward data transfers. However, this unnecessary; link left reverse idle state. this case more data arrives FIFO, data movement start again.
6.3.4
Transmit Data Reverse Nibble Mode
When data (status request responses) must transfer from local memory remote master, local initiates reversal previously stated. Data transmitted four-bit
nibbles using Centronics-defined status lines data lines rather than using actual data signals.
This method used reversed data transmission necessary, data lines bidirectional, could case older host systems. Each byte data transmitted
using nibbles with least-significant four bits being sent first. transmission speed necessarily slow requirement to.break data into four-bit nibbles (transmission speed half that full bytes being transmitted).
Handshake signals, Strobe, Acknowledge, Busy implemented using reverse sense. handshake forward direction. strobe from local remote uses ACK* signal. acknowledge from remote local uses STROBE signal. BUSY
implemented using nAutoFeed BUSY.
6.3.5
Transmit Data Reverse Byte Mode
Reverse Byte mode similar Reverse Nibble mode except that data moved using parallel data signal lines data lines, rather than status lines. Generally, host systems
provide bidirectional data interface full, byte-wide data path exists both directions. Strobe, Acknowledge Busy functions implemented using same signals used Reverse Nibble mode.
6.3.6
Transmit Data Mode
mode transmit similar Reverse Nibble Byte modes, adds capability send
RLE-compressed data. also includes ability send channel address sequence, case during receive data.
compression enabled, data pipeline scans incoming data identical sequences characters. number duplicate sequential characters greater than two, pipeline
begins count characters while maintaining copy character. When nonmatching character arrives count characters reaches 128, pipeline logic generates tagged, two-byte sequence including command data. resultant
CD1283/'1284 Evaluation
two-bytes placed FIFO along with status. When this tagged reaches parallel port, transmits while activating appropriate control signals indicate that RLE-compressed command.
Sending channel address requires that local manually place tagged-byte address PFHR1 after setting SetTag PFCR. When tagged byte reaches
parallel port, transmitted with control signals indicate address byte.
Mode
mode differs significantly from other modes, primarily because behavior more like microprocessor interface than typical peripheral parallel interface. defines both
address data cycles using handshake signals indicate address reads writes, data reads writes. also case that transactions `bus' initiated master, there equivalent receive transmit operation. clear this mode should used peripheral interface (printer, scanner, on), included CD1283/'1284 completely compatible with IEEE 1284 Std. specification.
mode capability high-speed data movement long does address cycle with each data transfer cycle. this `burst' mode used, minimal local
interrupt overhead required. Each time address write performed parallel interface, value written placed (EPP Address register) and, EPPAW PCIER, interrupt generated. However, cycles primarily data writes, then FIFO pipeline perform same manner other receive modes: Data flows into FIFO then into holding registers, when programmed threshold reached, transfers commence continue until FIFO empty.
Reading from parallel port while mode requires that pipeline reversed before first read transaction occurs. This because CD1283/'1284 control data
movement handshake; remote controls movement through data read cycle. Therefore, pipeline must reversed FIFO filled before remote read data. this switch occur, some higher level protocol must implemented software that message contents indicate reversal requested.
CD1283/'1284 Evaluation
Programming Examples
This section provides specific programming examples various operations required
CD1283/'1284. These examples expand upon examples shown CD1284 Datasheet include parallel channel initialization code handle direction reversal, single remaining character left pipeline byte count, These examples Borland C++.
Initialization Code
Initialization parallel channel consists setting SPR, selecting modes supported during negotiation, setting stale data time-out value, initializing FIFO, setting source
acceptable inter-rupts, other operational functions.
par_init() First, issue chip reset command outportb(GFRCR, 0x00); /*Clear GFRCR*/
outportb(CAR, 0x02); channel (could also while (inportb(CCR) 0x00) /*Wait clear outportb(CCR, 0x81); while inportb(GFRCR) 0x00) Wait GFRCR Start initializing parallel channel outportb(CAR, outportb(SPR, outportb(NER, outportb(PCR, outportb(OVR, 0x00); 0x0D); 0x4F); 0x80); 0x58); channel access register Assume 25MHz clock, short pulse value Support modes except manual mode Start Compatible Mode, status signals: PError SELECT nFault nACK
outportb(PClER, 0x37); outportb(PCR, 0x60);
Enable interrupts except address write Enable 1284 negotiations transfers
Next, pipeline control registers
Clear GFRCR outportb(LIVR, 0x00); outportb(PFCR, 0xD8); Clear LIVR, device Enable pipeline DMA, direction input, enable interrupts (but error ints) reset*/ FIFO. reset, assumed that starting direction will input. outportb(PFCR, 0x58); Clear FIFOres complete reset operation outportb(PFTR, 0x20); threshold receive (burst outportb(SDTPR, 0x64); stale data time-out period 10ms outportb(PACR, 0x02); asynchronous mode
CD1283/'1284 Evaluation
Service Requests
When CD1283/'1284 parallel channel requires local intervention, posts interrupt with status PIVR indicating which section channel, parallel port
pipeline, requires service. Each section status register specify which several possible sources cause interrupt. following sections provide detailed descriptions interrupt sources software examples service routines.
7.2.1
Parallel Port
parallel channel post requests service from either pipeline port. This section discusses service requests from port. Section 7.2.2 page discusses pipeline.
Service requests from port occur when more several events happen. These requests individually enabled following bits PCIER:
nlNIT: remote master pulsed nlnit signal parallel interface (Compatibility mode
only).
IDReq: During negotiations, remote master requested device DirCh: remote master reversed direction channel. This generally occurs
response data available state CD1283/'1284.
EPPAW: address write cycle occurred parallel port (EPP mode only). SigCh: programmed signal transitions (ZDR ODR) occurred parallel port
(Manual mode only).
NegCh: remote master performed negotiation state port changed.
Refer CD1284 Datasheet service request handling code. code following segment
example shows service parallel port request might occur. This code segment example might called response `service_par' routine shown CD1284 Datasheet routine called `service_par_chan'.
Many reactions these interrupts system-specific allow useful examples shown documentation. However, some requests have general responses that shown
example code. These responses must make change device operation, example, direction reversal parallel channel. first step responding parallel port service request read parse contents interrupt status register, PCISR. following example this routine. Note final command issued completion routine; required that PCISR cleared local host remove pending requests.
This routine called main parallel channel interrupt handler, service_par*l/ /*(shown data book). service_par_chan() char status; status inportb(PCISR); while (status){ switch (status) interrupt sources from status register interrupt sources*/ case statement used prioritize response
CD1283/'1284 Evaluation
case 0x01: nlnit(); status break; case 0x02: IDReq(); status break; case 0x04: DirCh(); status break; case 0x08: EPPAW(); status break; case 0x10: SigCh(); status break; case 0x20: NegCh(); status break; default: break; This example simply steps through each source 0xFE; Clear this status, recycle
IDReq could also include Mode change 0xFD; Routine should also check NegCh
0xFB;
0xF7;
0xEF;
0xDF;
outportb(PCISR, 0x00); outportb(PFCR, inportb(PFCR) 0xEF); outportb(PFCR, inportb(PFCR) 0x10);
Clear pending requests Toggle IntEn clear pending request
nlnit handling system-dependent, response SigCh interrupt. nlnit interrupt only occurs Compatibility mode; SigCh interrupt only occurs Manual mode. nlnit
might used force printer into reset condition. Signal changes only generate interrupt Manual mode being used signals used status/ control. other modes, output signals under automatic control parallel port input signals used remote host part data transfer protocol.
responses require more clarification because specific changes must made device:
DirCh IDReq interrupts. IDReq interrupt request response could follow somewhat same.procedure DirCh interrupt response, since normally involves direction change transmission string. following routine shows responding DirCh interrupt.
following routine example servicing interrupts from data pipeline directing processing appropriate routine. beyond scope this document attempt
show detail system might respond these interrupt conditions that dependent upon number system architecture parameters. general, response `Time-out with OneChar' remove remaining character place receive buffer; `Time-out without OneChar' buffer might tagged complete. interrupt with HRtag indicates that either tagged address received change virtual device address made. this purpose ECP, device addresses application, command were received, automatic decompression enabled.
This routine responds direction change interrupt issuing required commands flush FIFO reverse direction data path. assumed that data been removed from FIFO before DirCh interrupt generated. Optionally, routine could wait FFmpty become active
CD1283/'1284 Evaluation
PFSR before reversal initiated. general procedure DMAdir transmit, receive then FIFOres bit. Setting FIFOres required this command initialize direction circuits flush FIFO. FIFOres will clear automatically after action complete. extern char direction; Global direction value DirCh() char pfcr_val; Holding location current status pfcr_val inportb(PFCR); switch (direction) case direction Change direction transmit pfcr_val 0xA0; FIFOres DMAdir outportb(PFCR, pfcr_val);/* Issue command break; case direction Change direction receive pfcr_val 0xDF; DMAdir pfcr_val 0x80; FIFOres outportb(PFCR, pfcr_val); Issue command break; default: break;
7.2.2
Pipeline
There three sources interrupts from pipeline Those that occur when stale data timer expires. Those generated arrival tagged data when port operating mode. Those data handling errors part local system. stale data timer causes Time-out condition PFSR when decrements zero there either single characters remaining data pipeline. explained
CD1284 Datasheet, this timer restarts whenever character placed FIFO parallel port. Once regular arrival data stops, timer expires and, FIFO empty, Time-out interrupt posted. there were number bytes transferred block, then OneChar status also because there would character remaining PFHR2. there more characters remaining FIFO, expiration timer causes cycle initiated empty then
Time-out interrupt Time-out with OneChar interrupt posted. `tag' interrupt generated ECP-tagged data received port. tagged data either address RLE-compressed data. RLEen PFCR, data
automatically decompressed interrupt generated. RLEen set, receipt RLE-compressed data causes interrupt, which local host software must decode manually.
Data error interrupts only generated DataErr PFCR. DataErr set, occurrence conditions described Data Error register cause interrupt
posted. These errors induced erroneous read/write operations local system, such reading empty holding register writing DMABUF register when already contains data. data error interrupt primarily intended debug purposes would used during normal system operation.
CD1283/'1284 Evaluation
This routine called main parallel channel interrupt handler, service_par. checks either Time-out interrupt directs service accordingly. Time-out posted, ClearTO PACR must toggled order clear Time-out status PFSR. service_pipeline() char status; status inportb(PFSR); Read status register switch(status 0x30) Just check status bits that cause ints
case 0x10: HR_tag(status); Holding register tagged data break; case 0x20: Time_out(status); Time-out, check OneChar, etc. outportb(PACR, inportb(PACR) 0x08);/* Toggle ClearTO outportb(PACR, inportb(PACR) 0xF7); break; default: Must both Time_out(status); outportb(PACR, inportb(PACR) 0x08);/* Toggle ClearTO outportb(PACR, inportb(PACR) 0xF7);.HR_tag(status); break;
outportb(PFCR, inportb(PFCR) 0xEF); Toggle IntEn clear pending request outportb(PFCR, inportb(PFCR) 0x10);
7.2.3
Miscellaneous Pipeline Routines
diagnostic purposes, possible perform `loopback' test pipeline verify correct movement data FIFO, well testing compression/
decompression. Doing this involves placing data into FIFO through pipeline logic transmit operation then reversing direction removing data after updating quantity value PFQR (Parallel FIFO Quantity register). this done without enabling transfers parallel port that device will attempt actually move data over parallel interface. facilitate this, FIFOlock PACR (Parallel Auxiliary Control register). following example this operation:
This routine tests proper operation parallel FIFO using `pseudo' loopback operation. routine first sets FIFOlock PACR prevent parallel port from trying move data FIFO. Data then moved into FIFO PFHR2 (could also PFHR1 using single bytes instead words, followed reversing direction updating quantity value PFQR `fake' full FIFO
CD1283/'1284 Evaluation
Data read compared with data verify correct operation.
#define fail #define pass loopback() Loopback without compression test pattern[] {0x11, 0x22, 0x44, 0x88, 0x55,0xAA};/* Test pattern, walking one's temp; channel output fill FIFO outportb(PACR, outportb(PFTR, outportb(PFCR, outportb(PFCR, 0x10); 0x20); 0xA0); 0x20); Lock FIFO threshold value (only needed DMA, really) direction FIFO reset Clear FIFO reset
sizeof(pattern); i++) Fill FIFO with first pattern while (!(inportb(HRSR) 0x04)) /*Wait DMAbuffer empty outport(PFHR2, pattern[i]); Stuff word into buffer ((temp inportb(PFQR)) 58){ Read quantity register, should outportb(PACR, 0x00); Unlock FIFO return(fail); Quantity should have been outportb(PFCR, 0x00); Reverse direction outportb(PFQR, temp));/* Load quantity receive direction outDortb(PFTR, 0x01); threshold (only needed DMA, really) (sizeof(pattern)*2); while(linportb(HRSR) 0x20) temp inportb(PFHR2); Read data when PFHR2 full (temp pattern[i]){ Read data outportb(PACR, 0x00); Unlock FIFO return(fail); outportb(PFCR, 0x80); outportb(PFCR, 0x00); Reset FIFO Reverse Direction Reverse Direction
(inportb(HRSR) 0x20){ outportb(PACR, 0x00); Unlock FIFO return(fail); Shouldn't have been chars left outportb(PACR, 0x00); Unlock FIFO return(pass);
This same general loopback method used test compression/decompression. perform this test, pattern placed FIFO should have number repeating values
(greater than RLEen must PFCR. Also, have compression/ decompression function, data must placed into, removed from pipeline through buffer.
CD1283/'1284 Evaluation
After loading FIFO, PFQR should contain value that shows compression occurred. example, repeating pattern characters that length placed FIFO along with additional, non-matching character, PFQR should have count three, used compressed data count/tag plus single character that match pattern.
CD1283/'1284 Evaluation
Flowcharts
This section provides flowchart examples interrupt-driven polling method code CD1284.
Figure Polling Method
Hardware Reset
Software Reset
Initialize Device
Poll Device Again Poll Device Again
Service Request
DMAREQ
Test SVRR
*00H
FIFO Full FIFO Empty Data DataErr
Test
PPort
Pipeline
Test PFSR
Change Direction Return Host Reset Printer
DirCh
Test PCISR
SigCh
Test Test HRSR Test PFSR
IDReq
NegCh
ninit
Test
Note: necessary poll PFSR requests enabled. With requests enabled, DMAREQ BLINT SVRR polled determine when FIFO threshold exceeded. requests disabled, PFSR must polled determine when move data to/from FIFOO.
Service Negotiation Change
Service Signal Change Interrupt
Service Error Interrupt
Service Appropriate Holding Register
Service FIFO
A8706-01
CD1283/'1284 Evaluation
Figure Interrupt-Driven Method
Hardware Reset
Software Reset
Initialize Device
Wait Next Service Request
Interrupts
Note: DMAREQ signal connected interrupt request input processor interrupt controller make system interrupt driven.
Error Glitch ServicingReq Service Request
DMAREQ
Test SVRR
FIFO Full FIFO Empty Data DataErr
Test
PPort
Pipeline
Test PFSR
Change Direction Return Host Reset Printer
DirCh
Test PCISR
SigCh
Test Test HRSR Test PFSR
IDReq
NegCh
nInit
Test
Service Negotiation Change
Service Signal Change Interrupt
Service Signal Change Interrupt
Service Appropriate Holding Register
Service FIFO
A8707-01
CD1283/'1284 Evaluation
Equations Schematic
This section includes equations MACH120, 22v10 device, schematic evaluation board. Equations
;PALASM Design Description Declaration Segment -TITLE ADDRESS DECODER 22V10 PATTERN REVISION AUTHOR NIMA TAIE-NOBARIE DATE 06/09/97 CHIP _1284pal2 PAL22V10 Declarations -PIN SA10 COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMP1 COMBINATORIAL /IOREQ COMBINATORIAL OUTPUT Boolean Equation Segment -EQUATIONS COMP1 (/(SA10 SW1) /(SA9 SW2))*(/(SA8 SW3) /(SA7 SW4)) IOREQ COMP1 /(SA6 SW5) /(SA5 SW6) ;IOREQ COMP1 COMP2 COMP3 Simulation Segment -SIMULATION ;TRACE_ON IOREQ ;SETF /SW2 /SW5 ;TRACE_OFF
CD1283/'1284 Evaluation
;PALASM Design Description Declaration Segment -TITLE MACH120 PATTERN REVISION AUTHOR Nima Taie-Nobarie DATE 06/06/97 CHIP _1284PLD MACH120 Declarations -PIN /BPPCS COMBINATORIAL OUTPUT /SVCACKT COMBINATORIAL OUTPUT /DMAACK COMBINATORIAL OUTPUT /RESET COMBINATORIAL OUTPUT /WW1 COMBINATORIAL OUTPUT /BUSEN COMBINATORIAL OUTPUT DREQOUT COMBINATORIAL OUTPUT /BPPRW COMBINATORIAL OUTPUT /IOREQ COMBINATORIAL INPUT COMBINATORIAL INPUT /IOW COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT COMBINATORIAL INPUT SVCREQT COMBINATORIAL INPUT SVCREQR COMBINATORIAL INPUT SVCREQM COMBINATORIAL INPUT SVCREQP COMBINATORIAL INPUT /BPPDTACK COMBINATORIAL INPUT RPXDREQ COMBINATORIAL INPUT /IOR COMBINATORIAL INPUT INT2 COMBINATORIAL OUTPUT /LOW COMBINATORIAL INPUT /IOCS16 COMBINATORIAL OUTPUT /BPPDS COMBINATORIAL OUTPUT /DGRANT COMBINATORIAL OUTPUT /SVCACKM COMBINATORIAL OUTPUT /SVCACKP COMBINATORIAL OUTPUT /SVCACKR COMBINATORIAL OUTPUT /CHRDY COMBINATORIAL OUTPUT /CHRDYOE COMBINATORIAL OUTPUT Boolean Equation Segment -EQUATIONS /WW1 /AEN IOREQ /SA4 /SA3 /SA1 BUSEN /AEN IOREQ /AEN IOREQ IOCS16.TRST /AEN IOREQ IOCS16
CD1283/'1284 Evaluation
RESET /AEN IOREQ /SA4 /SA3 BPPCS /AEN IOREQ /SA4 /SA2 /SA1 /BPPDTACK /AEN IOREQ /SA4 /SA2 /SA1 /BPPDTACK BPPRW BPPDS /AEN IOREQ /SA4 /SA2 /SA1 /AEN IOREQ /SA4 /SA2 /SA1 SVCACKR SVCACKP SVCACKT SVCACKM INT2 /SVCREQR /SVCREQT /SVCREQP /SVCREQM DGRANT SVCACKR SVCACKT SVCACKP SVCACKM SVCACKR /AEN IOREQ /SA4 /SA2 SVCACKT /AEN IOREQ /SA4 /SA1 SVCACKP /AEN IOREQ /SA4 SVCACKM /AEN IOREQ /SA3 /SA2 /SA1 DREQOUT /RPXDREQ DMAACK /AEN IOREQ /SA3 /SA2 /AEN IOREQ /SA3 /SA2 CHRDYOE /AEN IOREQ /BPPDTACK /SA4 /SA2 /SA1 /AEN IOREQ /BPPDTACK /SA4 /SA2 /SA1 CHRDY CHRDY.TRST CHRDYOE Simulation Segment -SIMULATION ;TRACE_ON INT2 ;SETF SVCREQR SVCREQT SVCREQP /SVCREQM ;SETF /SVCREQR SVCREQT SVCREQP /SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT /SVCREQP SVCREQM ;SETF /SVCREQR /SVCREQT SVCREQP /SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR /SVCREQT SVCREQP SVCREQM ;SETF /SVCREQR /SVCREQT /SVCREQP /SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF /SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;SETF SVCREQR SVCREQT SVCREQP SVCREQM ;TRACE_OFF
CD1283/'1284 Evaluation
;TRACE_ON BPPCS ;SETF /AEN IOREQ /BPPDTACK ;SETF /SA4 /AEN IOREQ /BPPDTACK ;SETF /SA3 /AEN IOREQ /BPPDTACK ;SETF /SA2 /AEN IOREQ /BPPDTACK ;SETF /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA3 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA2 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA3 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA3 /SA2 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA3 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA3 /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA3 /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA2 /SA1 /AEN IOREQ /BPPDTACK ;SETF /SA4 /SA2 /SA1 IOREQ /BPPDTACK ;SETF /SA4 /SA2 /SA1 /AEN /IOREQ /BPPDTACK ;TRACE_OFF ;TRACE_ON IOCS16 ;SETF /AEN /IOREQ /LOW ;SETF /AEN /IOREQ ;SETF /AEN IOREQ /LOW ;SETF /AEN IOREQ ;SETF /IOREQ /LOW ;SETF /IOREQ ;SETF IOREQ /LOW ;SETF IOREQ ;TRACE_OFF ;TRACE_ON CHRDY BPPCS BPPDS ;SETF /AEN /IOREQ /IOW /BPPDTACK /SA4 /SA2 /SA1 ;SETF /AEN /IOREQ /IOW /BPPDTACK /SA4 /SA2 /SA1 ;SETF /AEN IOREQ /BPPDTACK /SA4 /SA2 /SA1 ;SETF /AEN IOREQ /BPPDTACK /SA4 /SA2 /SA1 ;SETF /AEN IOREQ /BPPDTACK /SA4 /SA2 /SA1 ;SETF /AEN IOREQ BPPDTACK /SA4 /SA2 /SA1 ;TRACE_OFF
OUTEN XD10 XD11 XD12 XD13 XD14 XD15 R/W* DTACK* /DMMACK /DMAREQ /SVCREQR /SVCACKR /SVCREQT /SVCACKT /SVCREQM /SVCACKM /SVCREQP /SVCACKP DGRANT* DMAACK* DB10 DB11 DB12 DB13 DB14 DB15 DMAACK DMAREQ SVCREQR SVCACKR REQT SVCACKT SVCREQM SVCACKM CREQP SVCACKP RANT RESET DPASS BYTESWAP CLK/2 BYTESWAP 1284 INT2 Reset_Drv IRQ9 RESDRV IRQ9 -12V -0WS +12V -SMEMW -SMEMR -IOR -DACK3 -DACK1 -REFSH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 -DACK2 14.3MHZ SA10 /IOREQ SA10 I/O8 IOREQ CLK/I0 PAL22V10 DIP-8 -IOCHCK IOCHRDY CHRDY INT2 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 BPPCS I/O2 SVCACKT I/O3 DMAACK I/O5 RESET I/O8 BUSEN DREQOUT BPPRW IOREQ BUSEN* DREQOUT /IOREQ /IOW ADER A_1284 HST_BSY HST_CLK NINIT AK_DA_RQ PER_BSY PER_CLK N_DAT_AV XFLAG EX_B_DIR P_D_B_EN TXD3 RXD3 DTR3 RTS3 CTS3 DSR3 TXD2 RXD2 DTR2 RTS2 CTS2 DSR2 CLK/2 EX_B_DIR P_D_B_EN TXD3 RXD3 DTR3* RTS3* CTS3* DSR3* CD3* TXD2 RXD2 DTR2* RTS2* CTS2* DSR2* CD2* C1AP_1 C1AM_1 C1BP_1 C1BM_1 DTR2* RTS2* CTS2* DSR2* CD2* RXD2 C1A+ C1AC1B+ C1BT MAX562 VC2+ C2T1_O T2_O T3_O R1_I R2_I R3_I R4_I R5_I SHDN* RJ45-10 4.7K RP1A (PBSY) (XFLAG) (PCLK) (NDAV) (ADR) CON36 C3_1 C4_1 C2P_1 C2M_1 TXD2E* DTR2E RTS2E CTS2E DSR2E CD2E RXD2E* CONT0 CONT1 CONT2 CONT3 CONT4 CONT8 CONT6 CONT5 CONT7 C1AP_0 C1AM_0 C1BP_0 C1BM_0 DTR3* RTS3* CTS3* DSR3* CD3* RXD3 C1A+ C1AC1B+ C1BT MAX562 VC2+ C2T1_O T2_O T3_O R1_I R2_I R3_I R4_I R5_I SHDN* RJ45-10 4.7K C3_0 C4_0 C2P_0 C2M_0 TXD3E* DTR3E RTS3E CTS3E DSR3E CD3E RXD3E*
CONT[0.8]
DACK0 DACK5 DACK6 DACK7
pullDACK
/IOCS16 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 DACK0 DREQ0 DACK5 DREQ5 DACK6 DREQ6 DACK7 DREQ7 EMCS16 -DACK0 -DACK5 -DACK6 -DACK7 -SBHE SA23 SA22 SA21 SA20 SA19 SA18 SA17 -MEMR -MEMW SD10 SD11 SD12 SD13 SD14 SD15
-BHE
pull_SW_NO pull_SW_NC pullDACK
XD[0.15]
DREQ0 DREQ5 DREQ6 DREQ7
PD[0.7]
RESET*
PBSY=Busy G=Select Fault =Perror
25MHz CONT8 CONT7 CONT6 CONT5 CONT4
(NINIT) CONT3 (HCLK) CONT2 (A1284) CONT0 (HBSY) CONT1 HOST LOGIC
Reset Switch
Reset_Drv ISA_Reset
SW_NC SW_NO SPDT
SWpullA SWpullB OUTEN
/IOW /IOR
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3
SA10
/IOCS16
SVCREQR RPXDREQ REQM CREQP DTACK mach120
I/O18 BPPDS I/O20 SVCACKR I/O22 SVCACKP
pull_SW_NO
pull_SW_NC
I/O36 I/O37 I/O38 I/O40 REQT
I/O12 I/O13 I/O14 I/O15 DGRANT SVCACKM
1.2K
XD10 XD11 XD12 XD13 XD14 XD15 BYTESWAP R/W* DTACK* DMAACK*
Quickturn Connectors
A[0.6] 74LS373 P_D_B_EN CONT1 CONT3 CLK2 CLK1 EX_B_DIR CONT0 CONT2 CONT4 CONT5 CONT7 OUTEN /SVCACKP CLK2 CLK1 CONT6 CONT8 /SVCREQP XD10 XD12 XD14 CLK2 CLK1 XD11 XD13 XD15 CLK/2 DMAACK* CLK2 CLK1 BYTESWAP
C1AP_0
C1BP_0
C2P_0
C1AM_0 C3_0
0.33uF C1BM_0 C4_0
0.33uF C2M_0
0.33uF
D[0.15]
Connct 20x2
Connct 20x2
1.2K
74LS245
30X2
C1AP_1
C1BP_1
C2P_1
C1AM_1 C3_1
0.33uF C1BM_1 C4_1
33uf
33uf
.1uf
.1uf
0.68uF
0.68uF
0.33uF
Connct 20x2
Connct 20x2 /SVCREQP /SVCACKP
RESET* EX_B_DIR P_D_B_EN CONT0 CONT1 CONT2 CONT3 CONT4 CONT5 CONT6 CONT7 CONT8 OUTEN
PASSIVE, DEV.
INT2 74LS245 XD10 XD11 XD12 XD13 XD14 XD15 RXD2 DTR2* RTS2* CTS2* DSR2* CD2* CLK2 CLK1 TXD3 RXD3 DTR3* RTS3* CTS3* DSR3* CD3*
0.33uF C2M_1
0.33uF
0.33uF
IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15
PASSIVE, DEV.
11X2
Connct 20x2
30X2
30X2
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
.1uf
Title .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf .1uf Size Date:
aluation Board
Document Number
CDK1284-E-AT02A 1997
Sheet

2001, this document replaces Basis Communications Corp. document AN-CD

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