Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monol

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Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monol

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TC90A66F
Preliminary TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC90A66F
PAP/PIP/POP Controller Wide-Screen (PAL/NTSC)
With built-in converters (ADC/DAC), TC90A66F picture-and-picture (PAP)/picture-in-picture (PIP)/picture-out-picture (POP) controller NTSC formats. used combination with field memory, video signal processor ICs. TC90A66F enables variety picture display functions. optimal provide wide-screen with additional functionality.
Features
Two-channel 8-bit ADC, three-channel 8-bit DAC, clamp circuit, multiplexer integrated single chip External field memory Recommended memory: MSM51V8221, MSM51V8222 Oki) Picture display functions display display display Half-picture left right sides 16:9 screen (Motion Picture mode Still mode selectable) 16:9 aspect ratio (Motion Picture mode Still mode selectable) aspect ratio pictures Still mode, picture Motion Picture mode pictures Still mode, Strobe mode selectable) Multi-picture still Channel search Display still pictures screen picture search (Still mode, Strobe mode, picture Motion Picture mode selectable) Variable frame width frame color Built-in horizontal vertical filters micro controller interface 3.3-V single power supply Package: QFP144 Weight: 4.64 (typ.)
2001-06-07
TC90A66F
Assignment
TIMRST PWRST HYOJUN KAYS RHREF RMCKI RMCK ERRST EREN RRST RDAY7 RDAY6 RDAY5 RDAY4 RDAY3 RDAY2 RDAY1 RDAY0 RDAC7 RDAC6 RDAC5 RDAC4 RDAC3 RDAC2 RDAC1 RDAC0 WDAY0 WDAY1
TESO IICNR SADSEL SACN TEST4 TEST3 TEST2 TEST1 TEST0 T107 T106 T105 T104 T103 T102 T101 T100 CNT6 CNT5 CNT4 CNT3 DAVDD YOUT DAVSS IOUT DAVDD QOUT VREF ADBIAS
TC90A66F
WDAY2 WDAY3 WDAY4 WDAY5 WDAY6 WDAY7 WDAC0 WDAC1 WDAC2 WDAC3 WDAC4 WDAC5 WDAC6 WDAC7 WRST WIEN EWRST EWEN EWIEN WMCK EWMCK WHREFS WCKS WHDS WVDS HRST WHREFE WCKE
ADVDD YINS ADVSS IINS ADVDD QINS ADVSS VRTY VRBY VRTC VRBC ADVDD YINE ADVSS IINE AVDD QINE AVSS CNT2 CNT1 CNT0 CLAMP TIN9 TIN8 TIN7 TIN6 TIN5 TIN4 TIN3 TIN2 TIN1 TIN0 WVDE WHDE
2001-06-07
TC90A66F
System Block Diagram
Output signal µ-COM YOUT IOUT QOUT VCD1 TA1270AF picture Image input signal Y1IN I1IN Q1IN Y2IN I2IN Q2IN YOUT IOUT QOUT WVDS WHDS VCD2 TA1270AF picture Image input signal YOUT IOUT QOUT YINE IINE QINE PAP/PIP/POP TC90A66F YINS IINS QINS YOUT IOUT QOUT
circuit RHREF
RDAY RDAC RMCK WDAY WDAC WMCK
MEMORY*2 MSM51V8221
WVDE WHDE
WCKS WHREFS WCKE WHREFE circuit circuit
2001-06-07
TC90A66F
TC90A66F Block Diagram
(not required mode) MAIN µ-COM WDAY Horizontal filter Line memory Vertical filter Y/IQ separator WMCK WRST RMCK RDAY WDAC 1200 WENY 1200 (4M/2M) WENC (4M/2M) RRST RMCKI RDAC memory (MSM51V8221) memory (MSM51V8221)
Vertical filter Odd/Even detector circuit picture WVDS WHDS WCKS WHREF picture WVDE WHDE WCKE WHREFE Main picture RHREF Line memory Generates system clock write 2400 (4M/2M) Generates system clock write 2400 (4M/2M) Generates control signal write
Output processor (frame color select, phase adjustment) Code processor
YOUT IOUT QOUT VREF
Stand processor
Picture display switch signal
Control signals write
PWRST Generates system clock read 2400 (4M/2M) Generates control signal read Control signals read Memory switch signal
2001-06-07
TC90A66F
Functions (144-pin QFP)
Name Number ADVDD YINS ADVSS IINS ADVDD QINS ADVSS VRTY VRBY VRTC VRBC ADVDD YINE ADVSS IINE AVDD QINE AVSS CNT2 CNT1 CNT0 CLAMP TIN9 TIN8 TIN7 TIN6 TIN5 TIN4 TIN3 TIN2 TIN1 TIN0 WVDE WHDE WCKE WHREFE HRST Power supply (3.3 signal system) input signal signal system) input Power supply (3.3 signal signal system) input Reference voltage signal (top) Reference voltage signal (bottom) Reference voltage signal (top) Reference voltage signal (bottom) Power supply (3.3 signal system) input signal signal system) input Power supply analog circuit (3.3 signal signal system) input analog circuit Power supply (3.3 Test output Test output Test output Clamp signal monitor output Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) system) vertical sync signal input inverted using bus) system) horizontal sync signal input inverted using bus) system) system clock input (Note1)
Function
(Note1) (Note1)
system) phase comparison output Power supply (3.3 Unit adjusting Memory switch signal [(YCS TC90A66F (H))
Note1: Supports interface.
2001-06-07
TC90A66F
Name Number WVDS WHDS WCKS WHREFS EWMCK WMCK EWIEN EWEN EWRST WIEN WRST WDAC7 WDAC6 WDAC5 WDAC4 WDAC3 WDAC2 WDAC1 WDAC0 WDAY7 WDAY6 WDAY5 WDAY4 WDAY3 WDAY2 WDAY1 WDAY0 RDAC0 RDAC1 RDAC2 RDAC3 RDAC4 RDAC5 RDAC6 RDAC7 RDAY0 Function system) vertical sync signal input inverted using bus) system) horizontal sync signal input inverted using bus) system) system clock input system) phase comparison output Power supply (3.3 system) write clock output field memory system) write clock output field memory system) field memory input enable system) field memory write enable system) field memory write reset system) field memory input enable system) field memory write enable system) field memory write reset picture system) signal output (field memory write signal/MSB) picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ (Note1)
(Note1) (Note1)
picture system) signal output (field memory write signal/LSB) picture system) signal output (field memory write signal/MSB) picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/ picture system) signal output (field memory write signal/
picture system) signal output (field memory write signal/LSB) picture system) signal input (field memory read signal/LSB) picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/MSB) Power supply (3.3 picture system) signal input (field memory read signal/LSB) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1)
Note1: Supports interface.
2001-06-07
TC90A66F
Name Number RDAY1 RDAY2 RDAY3 RDAY4 RDAY5 RDAY6 RDAY7 RRST EREN ERRST RMCK RMCKI RHREF KAYS HYOJUN PWRST TIMRST TESO IICNR SADSEL SACN TEST4 TEST3 TEST2 TEST1 TEST0 TIO7 TIO6 TIO5 TIO4 TIO3 TIO2 Function picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/ picture system) signal input (field memory read signal/MSB) system) field memory read enable system) field memory read reset system) field memory read enable system) field memory read reset (S/E system) read clock output field memory RMCK input (phase adjustment) phase comparison output main picture System clock input main picture Power supply (3.3 Horizontal sync single input main picture inverted using bus) Vertical sync single input main picture inverted using bus) signal output Wallpaper signal output Standard/non-standard signal output [standard (L)/non-standard (H)] System reset input [reset (L)] Test reset input [reset (H)/normal (L)] Test monitor output noise reduction circuit (H)/off (L)] Main/sub address switch [main (H)/sub (L)] acknowledge output serial clock input
(Note1) (Note1) (Note1) (Note1) (Note1) (Note1) (Note1)
(Note1)
(Note1) (Note1)
(Note1) (Note1)
serial data input (IN)/acknowledge (OUT) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Test input (connect GND) Power supply (3.3
Test input/output (normally, open) Test input/output (normally, open) Test input/output (normally, open) Test input/output (normally, open) Test input/output (normally, open) Test input/output (normally, open)
Note1: Supports interface.
2001-06-07
TC90A66F
Name Number TIO1 TIO0 CNT6 CNT5 CNT4 CNT3 DAVDD YOUT DAVSS IOUT DAVDD QOUT VREF ADBIAS Test input/output (normally, open) Test input/output (normally, open) Test output Test output Test output Test output Power supply (3.3 Signal output signal signal output Power supply (3.3 signal signal output bias bias reference bias (supply bias Function
2001-06-07
TC90A66F
Description
Number Name YINS Y-signal system) analog input Input amplitude Vp-p typical. IINS signal system) analog input Input amplitude Vp-p typical. QINS signal system) analog input Input amplitude Vp-p typical. VRTY High-level reference power supply signal. Sets upper limit dynamic range. Fixed (typ.) internal resistance type potential division. Connect bypass capacitor between GND. Low-level reference power supply voltage signal. Sets lower limit dynamic range. Fixed (typ.) internal resistance type potential division. Connect bypass capacitor between GND. High-level reference power supply signal. Sets upper limit dynamic range. Fixed (typ.) internal resistance type potential division. Connect bypass capacitor between GND. Low-level reference power supply voltage signal. Sets lower limit dynamic range. Fixed (typ.) internal resistance type potential division. Connect bypass capacitor between GND. signal system) analog input Input amplitude Vp-p typical. IINE signal system) analog input Input amplitude Vp-p typical. QINE signal system) analog input Input amplitude Vp-p typical. CLAMP Clamp signal monitor output pin. monitor clamp pulse start/stop position 25h. Outputs signal last data system) transfer. WVDE system) vertical sync signal input pin. inverted using bus) Inputs vertical sync signal from picture composing interface. negative polarity input, address [26H: EVINV] (negative polarity input). system) horizontal sync signal input pin. inverted using bus) Inputs horizontal sync signal from picture composing interface. negative polarity input, address [26H: EHINV] (negative polarity input). system) write clock input pin. Inputs from external circuit. composing interface. Inputs 2400 both memory mode. WHREFE system) phase comparison output. HREF signal obtained divider circuit phase comparison result picture horizontal sync signal. HRST Unit adjustment (WS/WE/R switch able) External field memory signal output pin. Output amplitude Vp-p typical. Setting address [21H: MOH] uses TC90A66F; setting sets memory output pins Hi-Z. WVDS system) vertical sync signal input pin. inverted using bus) Inputs vertical sync signal from picture composing interface. negative polarity input, address [27H: WVINV] (negative polarity input). system) horizontal sync signal input pin. inverted using bus) Inputs horizontal sync signal from picture composing interface. negative polarity input, address [27H: WHINV] (negative polarity input). system) write clock input pin. Inputs from external circuit. composing interface. Inputs 2400 both memory mode. Function
VRBY
VRTC
VRBC
YINE
WHDE
WCKE
WHDS
WCKS
2001-06-07
TC90A66F
Number Name WHREFS system) phase comparison output. HREF signal obtained divider circuit phase comparison result picture horizontal sync signal. This signal used control external voltage. EWMCK Outputs picture write clock external field memory. Output amplitude Vp-p typical. WMCK Outputs picture write clock external field memory. Output amplitude Vp-p typical. EWIEN Control signal output external field memory (sub picture Output amplitude Vp-p typical. EWEN Control signal output external field memory (sub picture Output amplitude Vp-p typical. EWRST Control signal output external field memory (sub picture Output amplitude Vp-p typical. WIEN Control signal output external field memory (sub picture Output amplitude Vp-p typical. Control signal output external field memory (sub picture Output amplitude Vp-p typical. WRST Control signal output external field memory (sub picture Output amplitude Vp-p typical. WDAC7-0 Output signal write external field memory. system). Output amplitude Vp-p typical. Connect only when using memory. MSB: WDAC7, LSB: WDAC0 WDAY7-0 Output signal write external field memory. system). Output amplitude Vp-p typical. MSB: WDAY7, LSB: WDAY0 RDAC0-7 Input signal read from external field memory system). composing interface. Connect only when using memory. MSB: RDAC7, LSB: RDAC0 RDAY0-7 Input signal read from external field memory system). composing interface. MSB: RDAY7, LSB: RDAY0 Control signal output external field memory (sub picture Output amplitude Vp-p typical. RRST Control signal output external field memory (sub picture Output amplitude Vp-p typical. EREN Control signal output external field memory (sub picture Output amplitude Vp-p typical. ERRST Control signal output external field memory (sub picture Output amplitude Vp-p typical. RMCK Outputs read clock external field memory. Output amplitude Vp-p typical. Outputs 1200 both memory. RMCKI RMCK phase adjustment input pin. Inputs RMCK. Function
2001-06-07
TC90A66F
Number Name RHREF Function phase compare output main picture. HREF signal obtained divider circuit phase comparison result signal. This signal used control external voltage. Read clock input pin. composing interface. Inputs from external circuit. Inputs 2400 both memory. Horizontal sync signal input main picture (read). Inputs horizontal sync signal from main picture. composing interface (negative polarity input). negative polarity input, address [28H: RHINV] non-inversion (L). Vertical sync signal input main picture (read). Inputs vertical sync signal from main picture. composing interface (negative polarity input). negative polarity input, address [28H: RVINV] non-inversion (L). Main/sub picture switch timing signal output pin. Output amplitude Vp-p typical. When signal High, displays picture. Wallpaper signal output. Standard/non-standard signal output [standard (L)/non-standard (H)] System reset input pin. When input, carries reset. least required reset duration. IICNR noise reduction circuit setting pin. When (connect VDD), data latched once internal clock, then written register. When (connect GND), data written register directly. address main/sub picture switching pin. [main (H)/sub (L)] Normally, (enables addresses 7Fh). SACN acknowledge output pin. serial clock input pin. composing interface. serial data input/acknowledge output pin. composing interface. signal output pin. Output amplitude Vp-p typical. signal output pin. Output amplitude Vp-p typical. signal output pin. Output amplitude Vp-p typical. Bias DAC. Connect bypass capacitor between pins GND. VREF reference voltage input pin. Reference voltage typical. ADBIAS Bias ADC. Connect bypass capacitor between AGND.
KAYS HYOJUN PWRST
SADSEL
YOUT IOUT QOUT VB2-1
2001-06-07
TC90A66F
Example Typical Converter Input Level Luminance Signal
Dec. (IRE)
0.71 pedestal clamp value
(IRE) 0.27 (IRE) signal amplitude: Vp-p (100% white)
Example Typical Converter Input Level Chrominance Signal
Dec.
reference potential clamp value
signal amplitude: Vp-p
2001-06-07
TC90A66F
Example Typical Converter Output Level Luminance Signal
Dec. (IRE)
0.64
(IRE) 0.25 (IRE) signal amplitude: Vp-p (100% white)
Example Typical Converter Output Level Chrominance Signal
Dec. 3.25
0.45
0.45
2.35 signal amplitude: Vp-p
2001-06-07
TC90A66F
Picture Display Function
picture
Main picture
picture
2-picture (PAP) display aspect ratio (full picture displayed) picture (S), (E): motion still (pictures exchanged)
1-picture display (full picture used)
picture
Multi search pictures picture (S): motion still picture (E): still pictures, strobe display only motion picture others still.
Main picture
picture picture picture
Main picture picture display picture: 16:9 aspect ratio Motion still Main picture: display using TC90A18AF (EDWAC)
3-picture display picture: aspect ratio Still, strobe, only motion picture Main picture: display using TC90A18AF (EDWAC)
Multiple picture search using whole screen still pictures, strobe display, only motion picture others still
2001-06-07
TC90A66F
Address Setting Table
Address FRFI ROEFON ROEALT RGAME RFISW DWSW RFALT RRH11 RHSIZ11
RHYSCE11 RHYSCS11 RHYSBE11 RHYSBS11 RHYSAE11 RHYSAS11
MYPH2 YSBACT MBLKIQ7 MMWIQ7 RCKINV YSBCLR RREPH1 YSACLR MBLKY7 MMWY7 M4M2 SESW
MYQPH0 RRSTINV FRACLR YSCCLR
RVYSAE9 RVYSAS9
RVYSBE9 RVYSBS9
RVYSCE9 RVYSCS9
RVSIZ9 RRV9
Note2: blank columns.
2001-06-07
TC90A66F
Address SCLPST7 ECLPST7 WPLHS WHIHYO RHIHYO
JVLOCHG
RWRN9 RWRA9 RHRFTH RHRFIV RHINV2 RCKCHG PRHP11
RPLLPH11
SCLPED7 ECLPED7
HDWDT7
WOERSTN
EHIHYO
EKHYO
WHST10
DWFIL WHMOD3 WEYINV WECINV WHRFTH PCMAIN
JSWAP WEYDL2 WECDL2 WHRFIV SIQINV WHINV2 EIQINV WCKINV IENINV WEPCM SHRST11 EHRST11 WCKEON PHREF11 EPLHS WKHYO RKHYO JFMINT POEINV VSPD1 BVIE5 STREND EHINV WHINV RHINV EVINV WVINV RVINV NTPAL WS262 RS262
WHED10 KWST10 KWED10
RPLHS HYJ3 HIJ3 VFILOFF RSTDEL WVST8 WVED8 WVMSK7 RVMSK7 KJV7 ATFLD7 STVS7
JVLOINV WKYFRM MAINRST MSKOFF INT3S2 VSKOFF ATSTRV JVSCRL KSKOFF ATSTRH BHRN3 ATMH3 STMH3 AT2CHG RANDM
JWRTON FIELD MWBACK MULT BHIE5 BVRN3 ATMV3 STMV3
HIE9 KJH9 STHS9
BVWE8
Note2: blank columns.
2001-06-07
TC90A66F
Address FRAON
BMASKON
CHMV3 CHMH3 YCMF2 KD15 KD31 YCMF1 YCMN C2HFT Y2HFT W1NSEL THRUY KMODE ATLV3 THRUYC HFSPAIV VFN3 VFYTH VKOS4 YDL2 ATLH3 YLPFCH THRUC CLPFTH
OFSET YLPFTH
SYCINV
PCMAIN
STHRU
CBYS
ABYS
ACYS
Note2: blank columns.
2001-06-07
TC90A66F
Address
RMHTES10 RMHCNT11 RHMBLE11 RHMBLS11
RVMBLE9 RVMBLS9
MFRAY7
MFRAIQ7
RMVCNT9
Note2: blank columns.
2001-06-07
TC90A66F
Address RMWSEL YSCMVON AUTOIN FHWE3 FHWS3 FVWE3 FVWS3
YSAMVON YSBMVON
RMVTES8
RMHMOV6 RMVMOV6
RMHSEL4
RHMDN RVFRE9 RVFRS9
RMHUP
RMVSEL4
RHFRE11 RHFRS11 FHEON FVEON
FHSON FVSON
Note2: blank columns.
2001-06-07
TC90A66F
Outline Control Format
control TC90A31F conforms Philips format.
Data Transfer Format
Slave address 7-bit address 8-bit XXXXXXXX 8-bit XXXXXXXX 8-bit
start condition stop condition acknowledge Start stop conditions
Start condition when clock line defined falling edge data line. Stop condition When clock line defined rising edge data line.
transfer
change SDA.
changed.
Data valid only when clock pulse (including rising/falling edges).
2001-06-07
TC90A66F
Acknowledge
from master High impedance
from slave
High impedance
from master
Slave address
Purchase TOSHIBA components conveys license under Philips Patent Right these components system, provided that system conforms Standard Specification defined Philips.
2001-06-07
TC90A66F
Functions (write)
Address 10-0 15-12 DWFIL JSWAP WHST10-0 WHMOD3-0 Image compression switching image compression Data Signal Name Function
Memory write control inversion Horizontal write start position Horizontal reduction ratio 1/16 (0H) (1H) (6H) (CH) (7H) (2H) (8H)
inversion (used right-and-left picture swapping)
(3H) (9H)
(4H) (AH)
(5H) (BH)
(CH) 15/16 (EH) 16/16 (FH) inversion
10-0 13-12
WCKINV WHED10-0 WEYINV WEYDL1-0
Memory phase inversion Horizontal write stop position
Memory Y-signal polarity inversion Memory Y-signal delay adjustment delay delay delay
polarity inversion
delay-1
10-0 13-12
IENINV KWST10-0 WECINV WECDL2 WECDL1-0
Memory polarity inversion
polarity inversion
Horizontal filter processing start position Memory C-signal polarity inversion normal polarity inversion
when memory mode H3/4 (WHMOD3-0
Memory C-signal delay adjustment delay delay delay delay-1
10-0 11-0 11-0 11-0 15-8 15-8
WEPCM KWED10-0 WHRFTH WHRFIV WHINV2 SHRST11-0 PCMAIN SIQINV EIQINV EHRST11-0 WCKEON PHREF11-0 SCLPST7-0 SCLPED7-0 ECLPST7-0 ECLPED7-0 WPLHS EPLHS EHINV EVINV NTPAL RPLHS HDWDT7-1
Memory 1-picture
1-picture processing
Horizontal filter processing stop position HREF signal through function phase comparison through
Polarity inversion HREF signal
polarity inversion polarity inversion
Polarity inversion signal phase comparison Field memory signal
S-system horizontal phase reference 1-picture processing 1-picture processing inversion
memory system/4M memory-I/Q inversion memory system-I/Q inversion E-system horizontal phase reference E-system operating control
inversion
E-system operation NTSC4M/2M [95D]
divider counter cycle write S-system clamp pulse start position
S-system clamp pulse stop position (start setting value stop setting value) E-system clamp pulse start position E-system clamp pulse stop position (start setting value stop setting value) Through function S-system phase comparison signal Through function E-system phase comparison signal E-system polarity inversion E-system polarity inversion negative polarity input negative polarity input through through polarity inversion polarity inversion
NTSC/PAL switching typical detector circuit
NTSC through
Through function phase comparison signal read
Pulse width adjustment function phase comparison signal read (change units W1CK)
2001-06-07
TC90A66F
Address 10-8 10-8 14-13 14-9 WHIHYO WKHYO WHINV WVINV WS262 HYJ3-1 WVMSK7-3 WOERSTN EHIHYO EKHYO RHIHYO RKHYO RHINV RVINV RS262 HIJ3-1 RVMSK7-0 JVLOCHG JFMINT JVLOINV WKYFRM MAINRST MSKOFF VFILOFF WVST8-0 JWRTON POEINV INT3S2 RSTDEL WVED8-0 FIELD VSPD1-0 JVSCRL VL8-0 MWBACK BVIE5-0 BVWE8-0 S-system forced non-standard S-system forced standard forced non-standard Data Signal Name Function
forced standard negative polarity input negative polarity input polarity inversion polarity inversion
S-system signal polarity inversion S-system signal polarity inversion S/E-system odd/even inversion
Read S/E-system standard inversion slice level S/E-system masking (each lines) Odd/even generator circuit clear stop E-system forced non-standard E-system forced standard forced non-standard
forced standard forced non-standard
Forced non-standard read Forced standard read
forced standard
Horizontal direction (HD) signal polarity inversion read negative polarity input polarity inversion Vertical direction (VD) signal polarity inversion read negative polarity input polarity inversion Odd/even inversion read
S/E-system non-standard decision inversion slice level read masking read (each lines) Change vertical reduction center Field memory initialize initialize normal center gravity change
Change vertical reduction center direction Forced frame write processing
forced frame 1-picture processing
Memory reset switching 1-picture processing masking function during Fixed Vertical write start line Write on/off Fixed Memory initialize width change Fixed Vertical write stop line Only 1-field write 1-field still live
mask
Scroll down speed change Scroll down on/off normal [001H]
Number lines moved vertical reduction center Background on/off
[2CH: MWBACK block vertical interval [2CH: MWBACK number block lines
2001-06-07
TC90A66F
Address MULT STREND VSKOFF Multi-search strobe function on/off Fixed [2DH: MULT write block position change function Data Signal Name Function
When off, only picture (upper left) strobe mode motion picture. (effective ATSTRV, KSKOFF RANDM HIE9-0 [2DH: MULT reference skip function Fixed [2DH: MULT horizontal skip width [2CH: MWBACK number block pixels 15-10 15-12 11-8 15-12 11-8 15-12 11-8 15-12 11-8 BHIE5-0 KJH9-0 BVRN3-0 BHRN3-0 KJV7-0 ATMV3-0 ATMH3-0 ATFLD7-0 STMV3-0 STMH3-0 STVS7-0 ATSTRV ATSTRH AT2CHG STHS9-0 CHMV3-0 CHMH3-0 ATLV3-0 ATLH3-0 RH9-0 [2CH: MWBACK block horizontal interval [2DH: KSKOFF reference skip horizontal position [2CH: MWBACK number vertical blocks (setting value: number vertical blocks [2CH: MWBACK number horizontal blocks (setting value: number horizontal blocks [2DH: KSKOFF reference skip vertical position Number strobe mode vertical blocks (setting value: number vertical blocks Number strobe mode horizontal blocks (setting value: number horizontal blocks [2DH: MULT write field interval (00H 2Fi,
[2DH: MULT vertical block position motion picture (specified block [2DH: MULT horizontal block position motion picture (specified block [2DH: MULT number vertical block lines [2DH: MULT vertical strobe function multi search strobe multi search strobe
[2DH: MULT horizontal strobe function
[2DH: MULT strobe vertical 2-row write function
[2DH: MULT number horizontal block pixels (setting value: number block pixels [32H: AT2CHG strobe [32H: AT2CHG strobe line [32H: AT2CHG strobe [32H: AT2CHG strobe line [2DH: MULT number multi search horizontal pixels (setting value: horizontal pixels 15H: field memory horizontal read size Multi Search, Strobe mode Number pixels (number block pixels) (number horizontal blocks)
YCMF2 YCMF1 YCMN C2HFT Y2HFT W1NSEL THRUY KMODE THRUYC YDL2-0 KTC-A OFSET
YCMIX signal (M/N type) polarity inversion
polarity inversion polarity inversion
YCMIX signal (before multiplier) polarity inversion Compression switching compression
compression
Color signal (I/Q) binary interpolation circuit on/off Luminance signal binary interpolation circuit on/off Reduction processor circuit switching Through output on/off Y-signal only
processing processing
Horizontal filter coefficient mode switching
[35H: YCMN horizontal filter through on/off signal delay adjustment Number filter coefficients Fixed
0Hex 1Hex
7Hex
2001-06-07
TC90A66F
Address 15-0 15-0 11-8 KD15-0 KD31-16 HFSPAIV YLPFCH THRUC CLPFTH YLPFTH VFN3-0 Horizontal filter coefficient 3-0)~coefficient (KD31-28) compression: 10H-setting value (complement) compression: Data Signal Name Function
mode] polarity inversion separation control signal before HFIL stage polarity inversion signal switching Stage stage
C-signal-only through output on/off signal on/off signal on/off
Vertical compression ratio (setting value: denominator (1/2 Select from above reduction ratios.
VFYTH VKOS4-0
Vertical filter through on/off
address specification vertical filter coefficient according specified vertical reduction ratio follows: (00H), (03H), (07H), (09H), (0DH), (13H), (1BH)
SYCINV PCMAIN STHRU AUTOIN
Polarity inversion separation control signal 1-picture processing 1-picture processing
polarity inversion
block through on/off
Vertical filter SRAM data transmission vertical reduction.
Auto Increment mode
2001-06-07
TC90A66F
Functions (read)
Address 15-13 15-12 11-8 15-12 11-8 11-0 11-0 11-0 11-0 11-0 11-0 11-0 11-0 MYPH2-0 MIQPH0 RRSTINV RCKINV RREPH1-0 M4M2 SESW YSBACT FRACLR YSCCLR YSBCLR YSACLR MBLKIQ7-4 MBLKIQ3-0 MBLKY3-0 MMWIQ7-0 MMWIQ3-0 MMWY7-0 signal phase adjustment read signal phase adjustment read Polarity inversion field memory read reset (RRST) signal Polarity inversion field memory read clock (PCK) signal inversion inversion inversion Data Signal Name Function
Phase adjustment field memory read enable (RRE) signal memory/2M memory mode switching system control switching
system system
Frame signal system) (external) system)
Blanking level Blanking level Blanking level Background level Background level Background level
PHYSAE11-0 horizontal stop position system) PHYSAS11-0 horizontal start position system) RVYSAE9-0 RVYSAS9-0 vertical stop position system) vertical start position system)
RHYSBE11-0 horizontal stop position (external) RHYSBS11-0 horizontal start position (external) RVYSBE9-0 RVYSBS9-0 vertical stop position (external) vertical start position (external)
RHYSCE11-0 horizontal stop position system) RHYSCS11-0 horizontal start position system) RVYSCE9-0 RVYSCS9-0 RHSIZ11-0 RVSIZ9-0 ROEFON RGAME DWSW RRH11-0 FRFI ROEALT RFISW RFALT RRV9-0 vertical stop position system) vertical start position system) Field memory horizontal read size (set number horizontal pixels Field memory read size (vertical) Field memory read/write phase control write Game mode display
display (vertical size smaller)
Field memory horizontal read start position Field/frame display switching Odd/even switching Field/frame display switching (field memory read/write phase control on/off) frame field Field memory read/write phase control memory read Field memory vertical read start position normal frame field
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Address RWRN9-0 RWRA9-0 Field memory read/write phase control start standard) Field memory read/write phase control start non-standard) control registers frame display (PIP, DW). when main/sub picture standard signal; when either main/sub picture non-standard signal. calculate setting value: address 15H: field memory horizontal read size address 16H: field memory vertical read size Data Signal Name Function
(calculate decimal)
Input result above calculation hexadecimal (19H have same value). 11-0 11-0 RHRFTH RHRFIV RHINV2 RCKCHG PRHP11-0 Control output mode RHREF signal output control Polarity inversion RHREF signal forced output
polarity inversion polarity inversion
polarity inversion RHREF signal output control Read clock switching normal
Read horizontal reference (PLL counter decoded value)
RPLLPH11-0 counter read setting) FRAON BWASKON Frame signal background image
Background/image switching
(Set background level 03H.) 11-0 11-0 15-12 11-8 11-0 10-0 CBYS ABYS ACYS (YSA: system, YSB: external, YSC: system)
RHMBLE11-0 Blanking horizontal stop position RHMBLS11-0 Blanking horizontal start position RVMBLE9-0 RVMBLS9-0 MFRAIQ7-4 MFRAIQ3-0 MFRAY7-0 Blanking vertical stop position Blanking vertical start position Frame level Frame level Frame level
RMHCNT11-0 Wipe signal horizontal reference (center) RMVCNT9-0 Wipe signal vertical reference (center)
RMHTES10-0 Wipe signal horizontal phase range (width) RMVTES8-0 Wipe signal vertical phase range (width)
RMHMOV6-0 Wipe signal horizontal operating speed RMWSEL Wipe signal system select window cross
RMVMOV6-0 Wipe signal vertical operating speed
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Address 15-12 11-0 15-12 11-0 15-12 15-12 YSCMVON YSAMVON YSBMVON RMHDN RMHUP RMVSEL4 RMVSEL3 RMVSEL2 RMVSEL1 RMHSEL4 RMHSEL3 RMHSEL2 RMHSEL1 FHWE3-0 RHFRE11-0 FHWS3-0 RHFRS11-0 FVWE3-0 FHEON FHSON RVFRE9-0 FVWS3-0 FVEON FVSON RVFRS9-0 E-system wipe S-system wipe External wipe Wipe counter down reset Data Signal Name Function
Wipe counter reset Vertical wipe (top) Vertical wipe Fixed Fixed
(bottom)
Horizontal wipe (right) Horizontal wipe (left) Fixed Fixed
Frame horizontal width (stop position) Frame horizontal stop position Frame horizontal width (start position) Frame horizontal start position Frame vertical width (stop position) Frame horizontal (stop position) Frame horizontal (start position) Frame vertical stop position Frame vertical width (start position) Frame vertical (stop position) Frame vertical (start position) Frame vertical start position
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Description Data Read
Frame Display
signal with 8-bit precision; signal with 4-bit precision. Frame width bits types). frame details using following registers: RHFRS: frame horizontal start position RHFRE: frame horizontal stop position FHWS: frame horizontal width (start position) FHWE: frame horizontal width (stop position) RVFRS: frame vertical start position RVFRE: frame vertical stop position FVWS: frame vertical width (start position) FVWE: frame vertical width (stop position)
FVWS RVFRS
picture
FHWS
FHWE
RVFRE PHFRS FVWE RHFRE
Blanking Setting
signal timing using following registers. horizontal start stop positions, vertical start stop positions blanking.
PHYSAS PHYSAE
blanking RVYSAS RVYSCS
picture
picture
RVYSAE blanking
RVYSCE
RHYSCS
RHYSCE
horizontal start position system) horizontal stop position system) horizontal start position system) horizontal stop position system) vertical start position system) vertical stop position system)
vertical start position system) vertical stop position system) Blanking horizontal start position Blanking horizontal stop position Blanking vertical start position Blanking vertical stop position
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Settings Special Effect Functions
Scroll Down
Special effect function used when selecting 2-picture, 1-picure, display. function freezes image signal before selection then moves image after selection from top. 1-field display (24) FRFI (field display) FRISW (field display) Write stop (42) JWRTON (Write stop) Select channel change start Change channel after write actually stopped. Scroll down function environment setting (41) MAINRST WKYFRM (43) FIELD Scroll down start (43) JVSCRL Write start (42) JWRTON Scroll down standby time change frame processing during standby) NTSC 2BH: VSPD Number write lines (240 valid lines) (282 valid lines) Setting value 120Fr (4.0 141Fr (5.6 60Fr (2.0 70Fr (2.8 40Fr (1.3 47Fr (1.9 34Fr (1.1 40Fr (1.6 Write processing change (frame processing) 29h(41) WKYFRM (after field) 29h(41) MAINRST 2Bh(43) FIELD JVSCRL Read processing change (frame processing) After sending write processing data, count four fields read, then send following data. (After image signal written memory, frame displayed.) (24) FRFI FRISW
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Settings Special Effect Functions
Wipe Function
Wipe on/off (106) YSCMVON system wipe (H)/off YSAMVON system wipe (H)/off YSBMVON External wipe (H)/off Wipe signal center width settings (horizontal vertical) (100) RMHCNT Wipe signal horizontal reference (center) (101) RMVCNT Wipe signal vertical reference (center) (102) RMHTES Wipe signal horizontal phase adjustment (width) (103) RMVTES Wipe signal vertical phase adjustment (width) Wipe signal speed settings (count number vertical sync signal) (104) RMHMOV Wipe signal horizontal operating speed large slow (105) RMVMOV Wipe signal vertical operating speed large slow Wipe direction setting (106) RMVSEL4 (H)/off RMVSEL3 Down (H)/off RMHSEL4 Right (H)/off RMHSEL3 Left (H)/off Wipe type setting (105) RMWSEL window cross
small fast small fast
window
cross
Wipe operating control (106) RMHDH Wipe counter (L)/DOWN RMHUP Wipe counter reset reset Start from wipe close RMHDN RMHUP (wipe close: initial state) RMHDN RMHUP RMHDN RMHUP (wipe open) Start from wipe open RMHDN RMHUP (wipe open: initial state) RMHDN RMHUP RMHDN RMHUP (wipe close) Send order
When center changed, make initial settings.
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Maximum Ratings (VSS 25°C)
Characteristics Power supply voltage Symbol VSS, VIN1 Input voltage VIN2 (Note4) Storage temperature Tstg Rating -0.3 -0.3 (Note3) 2000 Unit
Power dissipation
Note3: Applicable WVDE, WHDE, WCKE, WVDS, WHDS, WCKS, RDAC0 RDAC7, RDAY0 RDAY7, RCK, RHD, RVD, SCL, pins. Note4: When using 25°C higher, reduce 20.0 degree.
Power Dissipation Reduction Against Higher Temperature (when mounted board)
2000
Power dissipation (mW)
1500
1100
Operating temperature (°C)
Recommended Operating Conditions (VSS
Characteristics Power supply voltage Input voltage Operating temperature Symbol Topr Test Condition Typ. Unit
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Electrical Characteristics
Characteristics Operating Conditions: VDD, 70°C,
Characteristics Power dissipation Symbol Test Circuit Test Condition NTSC Schmitt trigger input CMOS input Low-level input voltage VOH1 VOH2 level Schmitt trigger hysteresis voltage VOL1 VOL2 IOH1 IOH2 IOL1 IOL2 Typ. (Note7) (Note8) (Note6) 5.25 5.25 Unit (Note5) (Note9) (Note6) (Note5) (Note9) (Note6) (Note5) (Note6) (Note7) (Note8) Terminal
CMOS input High-level input voltage
Schmitt trigger input
High level Input current level High level Output voltage
Note5: TIN9-0, RMCKI, PWRST, TIMRST, IICNR, SADSEL, TST4-0, WHREFE, WHREFS, EWIEN, EWEN, EWRST, WIEN, WEN, WRST, WDAC7-0, WDAY7-0, REN, RRST, EREN, ERRST, RHREF, T107-100, EWMCK, WMCK, RMCK Note6: WVDE, WHDE, WVDS, WHDS, RHD, RVD, SCL, Note7: WHREFE, WHREFS, EWIEN, EWEN, EWRST, WIEN, WEN, WRST, WDAC7-0, WDAY7-0, REN, RRST, EREN, ERRST, RHREF, SDA, T107-100, EWMCK, WMCK, RMCK Note8: EWMCK, WMCK, RMCK Note9: WCKE, WCKS, RDAC0-7, RDAY0-7,
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Characteristics Operating Conditions: VDD, 70°C,
Characteristics Operating frequency condition TSUP1 Input setup time TSUP2 THLD1 Input hold time THLD2 Tpd1 Tpd2 Tpd3 Tpd4 Tpd5 Tpd6 Tpd7 Tpd8 Tpd9 Tpd10 Output transfer delay time Tpd11 Tpd12 Tpd13 Tpd14 Tpd15 Tpd16 Tpd17 Tpd18 Tpd19 Tpd20 10.8 37.8 37.8 Symbol Test Circuit Test Condition NTSC mode Operating frequency: Operating frequency: Typ. Unit Remarks
Characteristics Operating Conditions: 70°C,
Characteristics Non-linear error Symbol Test Circuit Test Condition DACK DACK DACK DACK Typ. Unit
Differential non-linear error
FULL Analog input voltage ZERO
VIFS
VIZS
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Clamp Multiplexer Operating Conditions: 70°C,
Characteristics Clamp Clamp Multiplexer Symbol Test Circuit Test Condition Typ. Unit
Characteristics Operating Conditions: 70°C,
Characteristics Non-linear error Symbol Test Circuit Test Condition DACK DACK DACK DACK Typ. Unit
Differential non-linear error
FULL Analog input voltage ZERO
VIFS
VIZS
VREF
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Characteristic Timing Charts
Write
Tpd1 WMCK Tpd3 WRST Tpd5 WENY Tpd7 WENC Tpd9 Tpd11 WDAY Tpd13 WDAC Tpd14 Tpd12 Tpd10 Tpd8 Tpd6 Tpd4 Tpd2
Read
Tpd15 RMCK Tpd17 RRST Tpd19 Tpd20 Tpd18 Tpd16
THLD1 RMCKI TSUP1
THLD2 RDAY TSUP2 RDAC
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Application Circuit
YOUT IOUT QOUT
TEST0
TEST1
TEST2
TEST3
TEST4
T100
T101
T102
T103
T104
T106
CNT3
CNT4
CNT6
CNT5
T107
T105
SADSEL
DAVSS
ADBIAS
VREF
DAVDD
DAVDD
SACN
IICNR
QOUT
YOUT
TESO
IOUT
TIMRST PWRST HYOJUN KAYS RHREF RMCKI RMCK ERRST EREN RRST RDAY7 RDAY6 RDAY5 RDAY4 RDAY3 RDAY2 RDAY1 RDAY0 RDAC7 RDAC6 RDAC5 RDAC4 RDAC3 RDAC2 RDAC1 RDAC0 WDAY0 WDAY1 MSM51V8221 (Y/S) TLC2933 TC7508F (Inverter)
YINS IINS QINS YINE IINE QINE
ADVDD YINS ADVSS IINS ADVDD QINS ADVSS VRTY VRBY VRTC VRBC ADVDD YINE ADVSS IINE AVDD QINE AVSS CNT2 CNT1 CNT0 TC90A66F
CLAMP TIN9 TIN8 TIN7 TIN6 TIN5 TIN4 TIN3 TIN2 TIN1 TIN0
WVDE WHDE WVDS WHDS
WVDE WHDE WHREFE WHREFS WCKE EWMCK WDAC7 WDAC6 WDAC5 WDAC4 WDAC3 WDAC2 WDAC1 WDAC0 EWRST WDAY7 WDAY6 WDAY5 WDAY4 WDAY3 WDAY2 EWIEN WMCK
WHDS
WVDS
WCKS
EWEN
HRST
WRST
WIEN
TC7508F (AND)
TC7508F (AND)
(C/E) MSM51V8221
TLC2933
TLC2933
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Package Dimensions
Weight: 4.64 (typ.)
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RESTRICTIONS PRODUCT
000707EBA
TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, comply with standards safety making safe design entire system, avoid situations which malfunction failure such TOSHIBA products could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent TOSHIBA products specifications. Also, please keep mind precautions conditions forth "Handling Guide Semiconductor Devices," "TOSHIBA Semiconductor Reliability Handbook" etc. TOSHIBA products listed this document intended usage general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products neither intended warranted usage equipment that requires extraordinarily high quality and/or reliability malfunction failure which cause loss human life bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, types safety devices, etc. Unintended Usage TOSHIBA products listed this document shall made customer's risk. products described this document subject foreign exchange foreign trade laws. information contained herein presented only guide applications products. responsibility assumed TOSHIBA CORPORATION infringements intellectual property other rights third parties which result from use. license granted implication otherwise under intellectual property other rights TOSHIBA CORPORATION others. information contained herein subject change without notice.
2001-06-07

Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monol

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