3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion Drive Features LVCH162823A: Balanced Output Drivers: ±12mA Switching Noise
IDT74LVCH162823A
DESCRIPTION:
LVCH162823A 18-bit interface register built using advanced dual metal CMOS technology. This high-speed, low-power register with clock enable (CLKEN) clear (CLR) controls ideal parity interfacing high-performance synchronous systems. control inputs organized operate device 9-bit registers 18-bit register. Flow-through organization signal pins simplifies layput. inputs designed with hysteresis improved noise margin. pins LVCH162823A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH162823A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been developed drive ±12mA designated threshold levels. LVCH162823A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1CLR 1CLK 1CLKEN
2CLR 2CLK 2CLKEN
EIGHT OTHER CHANNELS
EIGHT OTHER CHANNELS
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4683/-
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
CLKEN
Unit
Link
SO56-1 SO56-2 SO56-3
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
NOTE: applicable device type.
CLKEN
FUNCTION TABLE
Inputs xCLR xCLKEN xCLK
Outputs Load Hold Function High Clear
SSOP/ TSSOP/ TVSOP VIEW
DESCRIPTION
Names xCLK xCLKEN xCLR Description Data Inputs Clock Inputs Clock Enable Inputs (Active LOW) Asynchronous Clear Inputs (Active LOW) Output Enable Inputs (Active LOW) 3-State Outputs
NOTE: These pins have "Bus-hold". other pins standard inputs, outputs, I/Os.
NOTE: HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH Transition Level before indicated steady-state input conditions were established.
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
Link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
SWITCHING CHARACTERISTICS
2.7V Symbol tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tREM tSK(o) Parameter Propagation Delay xCLK Propagation Delay xCLR Output Enable Time Output Disable Time Set-up Time HIGH xCLK Hold Time HIGH xCLK Set-up Time HIGH xCLKEN xCLK Hold Time HIGH xCLKEN xCLK xCLK Pulse Width HIGH xCLR Pulse Width Recovery Time xCLR xCLK Output Skew(2) 3.3V±0.3V Unit
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE OUTPUT
TEST CIRCUITS OUTPUTS
ulse LOAD Open
ENABLE DISABLE TIMES
ENABLE OUTPUT CLOSED OPEN
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
ASYNCHRONOUS
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
SYNCHRONOUS
OUTPUT SKEW
PULSE WIDTH
OUTPUT OUTPUT
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH162823A 3.3V CMOS 18-BIT INTERFACE REGISTER, VOLT
ORDERING INFORMATION
Bus-Hold XXXX Device Type Package ange
823A
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Outline Package (SO56-3) 18-Bit Interface Register Double-Density esistors, ±12m
Bus-hold -40°C +85°C
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3.3V CMOS 18-BIT INTERFACE REGISTER WITH VOLT TOLERANT BUS-HOLD T

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