3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

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3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

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IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP, 0.40mm pitch TVSOP packages Extended commercial range 40°C 85°C 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Drive Features ALVCH16843: High Output Drivers: ±24mA Suitable heavy loads
IDT74ALVCH16843
DESCRIPTION:
ALVCH16843 built using advanced dual metal CMOS technology. This device 9-bit D-type latches featuring separate D-type inputs each latch 3-state outputs oriented applications. sections each register controlled independently latch enable (LE), clear (CLR), preset (PRE) output enable (OE) control pins. When low, data registers appear outputs. When high, outputs high impedance state. Operation input does affect state flip-flops. ALVCH16843 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH16843 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
3.3V High Speed Systems 3.3V lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5154/-
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
CONFIGURATION
1CLR 2CLR SO56-1 SO56-2 SO56-3 1PRE 2PRE
ABSOLUTE MAXIMUM RATING
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Unit
NEW16link
Max. ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25oC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NEW16link
NOTE: applicable device type.
SSOP/ TSSOP/TVSOP VIEW
FUNCTION TABLE(1)
Inputs XPRE XCLR Output
DESCRIPTION
Symbol XCLR XPRE Description Clear input (Active LOW) Output enable input (Active LOW) Preset input (Active LOW) Latch enable input Data inputs(1) 3-State Data outputs Ground (0V) Positive supply voltage
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance "off" state Level before indicated steady-state input conditions were established
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: 40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, 18mA 3.3V 3.6V input 0.6V, other inputs Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
NEW16link
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
NEW16link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
NEW16link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25oC
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
SWITCHING CHARACTERISTICS
Symbol Parameter Propagation Delay Propagation Delay Propagation Delay XPRE Propagation Delay xCLR 3-State Output Enable time 3-State Output Disable time Set-up time Hold time pulse width HIGH XPRE pulse width XCLR pulse width tREM Recovery time XPRE Recovery time XCLR tSK(0) Output Skew(2) 2.5V 0.2V Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
tPHL tPLH
tPZH tPZL tPHZ tPLZ
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
NEW16link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH LOAD/2 tPHZ tPLZ DISABLE LOAD/2
LOAD Open
D.U.T.
ALVC Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
ALVC Link NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
ALVC Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
NEW16link
tREM
Open
OUTPUT SKEW INPUT
tPHL1
tPLH1
PULSE WIDTH
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
ALVC Link
OUTPUT
OUTPUT tPLH2 tPHL2
tPLH2 tPLH1 tPHL2 tPHL1
ALVC Link
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH16843 3.3V CMOS 18-BIT INTERFACE D-TYPE LATCH
ORDERING INFORMATION
ALVC Device Type Package Range Bus-Hold
Shrink Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 18-Bit Interface D-Type Latch with 3-State Outputs Double-Density with Resistors, ±24mA Bus-Hold -40°C +85°C
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3.3V CMOS 18-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS BUS-H

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