This document contains detailed information power considerations, DC/A

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MPC8250EC/D Rev. 8/2003 MPC8250 Hardware Specifications
This document contains detailed information power considerations, DC/AC electrical characteristics, timing specifications MPC8250 PowerQUICC IIcommunications processor. following topics addressed: Topic Section 1.1, "Features" Section 1.2, "Electrical Thermal Characteristics" Section 1.2.1, Electrical Characteristics" Section 1.2.2, "Thermal Characteristics" Section 1.2.3, "Power Considerations" Section 1.2.4, Electrical Characteristics" Section 1.3, "Clock Configuration Modes" Section 1.3.1, "Local Mode" Section 1.3.2, "PCI Mode" Section 1.4, "Pinout" Section 1.5, "Package Description" Section 1.6, "Ordering Information" Page
MPC8250 available packages-the standard package (480 TBGA) alternate package (516 PBGA)-as described Section 1.4, "Pinout," Section 1.5, "Package Description." more information packages, contact your Motorola sales office. Note that throughout this document references MPC8250 inclusive version unless otherwise specified.
NOTE: Document Revision History Changes this document summarized Table page
Features
Figure shows block diagram MPC8250.
Kbytes I-Cache I-MMU Core System Interface Unit (SIU) Kbytes D-Cache D-MMU Interface Unit 60x-to-PCI Bridge 60x-to-Local Bridge Memory Controller Timers Parallel Baud Rate Generators 32-bit RISC Microcontroller Program Virtual IDMAs System Functions Interrupt Controller Kbytes Dual-Port Serial DMAs Clock Counter
bits,
Local
bits,
Communication Processor Module (CPM)
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
Time Slot Assigner Serial Interface
Ports
Ports
Non-Multiplexed
Figure MPC8250 Block Diagram
Features
Footprint-compatible with MPC8260 Dual-issue integer core core version EC603e microprocessor System core microprocessor supporting frequencies 150-200 Separate 16-Kbyte data instruction caches: Four-way associative Physically addressed replacement algorithm PowerPC architecture-compliant memory management unit (MMU) Common on-chip processor (COP) test interface High-performance (4.4-5.1 SPEC95 benchmark MHz; Dhrystones MIPS MHz) Supports snooping data cache coherency Floating-point unit (FPU)
major features MPC8250 follows:
MPC8250 Hardware Specifications
MOTOROLA
Features
Separate power supply internal logic (1.8 (3.3V) Separate PLLs core core different frequencies power/performance optimization Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, ratios Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, ratios 64-bit data 32-bit address supports multiple master designs Supports single- four-beat burst transfers 64-, 32-, 16-, 8-bit port sizes controlled on-chip memory controller Supports data parity address parity 32-bit data 18-bit address local Single-master bus, supports external slaves Eight-beat burst transfers 32-, 16-, 8-bit port sizes controlled on-chip memory controller 60x-to-PCI bridge Programmable host bridge agent 32-bit data bus, MHz, Synchronous asynchronous clock modes internal address space available external host memory block transfers PCI-to-60x address remapping
System interface unit (SIU) Clock synthesizer Reset controller Real-time clock (RTC) register Periodic interrupt timer Hardware monitor software watchdog timer IEEE 1149.1 JTAG test access port
Twelve-bank memory controller Glueless interface SRAM, page mode SDRAM, DRAM, EPROM, Flash other userdefinable peripherals Byte write enables selectable parity generation 32-bit address decodes with programmable bank size Three user programmable machines, general-purpose chip-select machine, page-mode pipeline SDRAM machine Byte selects width (60x) byte selects width (local) Dedicated interface logic SDRAM
core disabled device used slave mode external core
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MPC8250 Hardware Specifications
Features
Communications processor module (CPM) Embedded 32-bit communications processor (CP) uses RISC architecture flexible support communications protocols Interfaces core through on-chip 32-Kbyte dual-port controller Serial channels receive transmit serial channels Parallel registers with open-drain interrupt capability Virtual functionality executing memory-to-memory memory-to-I/O transfers Three fast communications controllers supporting following protocols: 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) Transparent HDLC-Up rates (clear channel) multichannel controller (MCC2) Handles serial, full-duplex, 64-Kbps data channels. split into four subgroups channels each. Almost combination subgroups multiplexed single multiple interfaces four interfaces Four serial communications controllers (SCCs) identical those MPC860, supporting digital portions following protocols: Ethernet/IEEE 802.3 CDMA/CS HDLC/SDLC HDLC Universal asynchronous receiver transmitter (UART) Synchronous UART Binary synchronous (BISYNC) communications Transparent serial management controllers (SMCs), identical those MPC860 Provide management devices general circuit interface (GCI) controllers timedivision-multiplexed (TDM) channels Transparent UART (low-speed operation) serial peripheral interface identical MPC860 inter-integrated circuit (I2C) controller (identical MPC860 controller) Microwire compatible Multiple-master, single-master, slave modes four interfaces Supports group four channels 2,048 bytes byte resolution Independent transmit receive routing, frame synchronization
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
Supports CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), user-defined serial interfaces Eight independent baud rate generators input clock pins supplying clocks FCCs, SCCs, SMCs, serial channels Four independent 16-bit timers that interconnected 32-bit timers bridge Specification Revision compliant supports frequencies On-chip arbitration Support memory memory streaming Host Bridge Peripheral capabilities Includes channels following transfers: PCI-to-60x 60x-to-PCI 60x-to-PCI PCI-to-60x PCI-to-60x PCI-to-60x 60x-to-PCI 60x-to-PCI Includes configuration registers (which automatically loaded from EPROM used configure MPC8265A) required standard well message doorbell registers Supports standard Hot-Swap friendly (supports Swap Specification defined PICMG R1.0 August 1998) Support MHz, specification 60x-PCI core logic which uses buffer pool allocate buffers each port Makes local signals, there need additional pins
1.2.1
Electrical Thermal Characteristics
Electrical Characteristics
This section provides electrical specifications thermal characteristics MPC8250.
This section describes electrical characteristics MPC8250. Table shows maximum electrical ratings.
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics Table Absolute Maximum Ratings1
Rating Core supply voltage2 supply voltage2 Symbol VCCSYN VDDH TSTG Value -0.3 -0.3 -0.3 GND(-0.3) (-55) (+150) Unit
supply voltage3 Input voltage4 Junction temperature Storage temperature range
Absolute maximum ratings stress ratings only; functional operation (see Table maximums guaranteed. Stress beyond those listed affect device reliability cause permanent damage. Caution: VDD/VCCSYN must exceed VDDH more than time, including during power-on reset. Caution: VDDH exceed VDD/VCCSYN during power reset more than mSec. VDDH should exceed VDD/VCCSYN more than during normal operation. Caution: must exceed VDDH more than time, including during power-on reset.
Table lists recommended operational voltage conditions.
Table Recommended Operating Conditions1
Rating Core supply voltage supply voltage supply voltage Input voltage Junction temperature (maximum) Ambient temperature
Symbol VCCSYN VDDH 1.92 1.92
Value 1.7-2.13 1.7-2.13 3.135 3.465 (-0.3) 3.465 1055 0-705 -2.24 1.9-2.24
Unit
Caution: These recommended tested operating conditions. Proper device operating outside these conditions guaranteed. frequency less than equal MHz. frequency greater than less than MHz. frequency greater than equal MHz. Note that extended temperature parts range (-40)T 105Tj.
NOTE: Core, PLL, Supply Voltages VDDH, VCCSYN, must track each other both must vary same direction-in positive direction (+5% +0.1 Vdc) negative direction (-5% -0.1 Vdc). This device contains circuitry protecting against damage high static voltage electrical fields; however, advised that normal precautions taken avoid application voltages higher than maximum-rated voltages this high-impedance circuit. Reliability operation enhanced unused inputs tied appropriate logic voltage level (either VCC). Figure shows undershoot overshoot voltage local memory interface MPC8280. Note that mode interface different.
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
GVDD GVDD
exceed tSDRAM_CLK
Figure Overshoot/Undershoot Voltage
Table shows electrical characteristics.
Table Electrical Characteristics1
Characteristic Input high voltage, inputs except CLKIN Input voltage CLKIN input high voltage CLKIN input voltage Input leakage current, VDDH2 Hi-Z (off state) leakage current, Signal input current, Signal high input current, Output high voltage, VDDH2 Symbol VIHC VILC 3.465 3.465 Unit
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics Table Electrical Characteristics1 (Continued)
Characteristic 7.0mA ABB/IRQ2 A[0-31] TT[0-4] TBST TSIZE[0-3] AACK ARTRY DBB/IRQ3 D[0-63] DP(0)/RSRV/EXT_BR2 DP(1)/IRQ1/EXT_BG2 DP(2)/TLBISYNC/IRQ2/EXT_DBG2 DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET HRESET SRESET RSTCONF QREQ Symbol Unit
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics Table Electrical Characteristics1 (Continued)
Characteristic 5.3mA CS[0-9] CS(10)/BCTL1 CS(11)/AP(0) BADDR[27-28] BCTL0 PWE(0:7)/PSDDQM(0:7)/PBS(0:7) PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LSDAMUX/LGPL5/PCI_MODCK MODCK1/AP(1)/TC(0)/BNKSEL(0) MODCK2/AP(2)/TC(1)/BNKSEL(1) MODCK3/AP(3)/TC(2)/BNKSEL(2) 3.2mA L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31 LCL_D(0-31)/AD(0-31) LCL_DP(0-3)/C/BE(0-3) PA[0-31] PB[4-31] PC[0-31] PD[4-31]
Symbol
Unit
default configuration pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) input. prevent excessive current, recommended either pull unused pins VDDH, configure them outputs. leakage current measured nominal VDD, VCCSYN, VDD.
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics
1.2.2
Thermal Characteristics
Table Thermal Characteristics
Value
Table describes thermal characteristics.
Characteristic
Symbol
TBGA package)
PBGA package)
Unit
Flow
Junction ambient- single-layer board1 Junction ambient- four-layer board Junction board2
Natural convection °C/W Natural convection °C/W °C/W
Junction case3
Assumes thermal vias Thermal resistance between printed circuit board JEDEC JESD51-8. Board temperature measured surface board near package. Thermal resistance between case surface measured cold plate method (MIL SPEC-883 Method 1012.1).
1.2.3
Power Considerations
average chip-junction temperature, obtained from following: where ambient temperature
package thermal resistance, junction ambient, °C/W
PINT PI/O PINT Watts (chip internal power) PI/O power dissipation input output pins (determined user) most applications PI/O PINT. PI/O neglected, approximate relationship between following: K/(TJ 273° Solving equations gives: 273°
where constant pertaining particular part. determined from equation measuring equilibrium) known Using this value values obtained solving equations iteratively value
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
1.2.3.1
Layout Practices
Each should provided with low-impedance path board's power supply. Each ground should likewise provided with low-impedance path ground. power supply pins drive distinct groups logic chip. power supply should bypassed ground using least four by-pass capacitors located close possible four sides package. capacitor leads associated printed circuit traces connecting chip ground should kept less than half inch capacitor lead. four-layer board recommended, employing inner layers planes. output pins MPC8250 have fast rise fall times. Printed circuit (PC) trace interconnection length should minimized order minimize overdamped conditions reflections caused these fast output switching times. This recommendation particularly applies address data buses. Maximum trace lengths inches recommended. Capacitance calculations should consider device loads well parasitic capacitances traces. Attention proper layout bypassing becomes especially critical systems with higher capacitive loads because these loads create higher transient currents circuits. Pull unused inputs signals that will inputs during reset. Special care should taken minimize noise levels supply pins. Table provides preliminary, estimated power dissipation various configurations. Note that suitable thermal management required conditions above (when ambient temperature greater) ensure junction temperature does exceed maximum specified value. Also note that power should included when determining whether heat sink.
Table Estimated Power Dissipation Various Configurations1
PINT(W)2 (MHz) Core Multiplier Multiplier (MHz) (MHz) Vddl Volts Nominal 66.66 66.66 66.66 66.66 83.33 83.33 83.33
Vddl Volts Nominal Maximum
Maximum
Test temperature room temperature (25° PINT Watts
1.2.4
Electrical Characteristics
following sections include illustrations tables clock diagrams, signals, outputs inputs MPC8250 device. Note that timings based 50-pf load. Typical output buffer impedances shown Table
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics Table Output Buffer Impedances1
Output Buffers Local Memory controller Parallel
Typical Impedance
These typical values impedance vary ±25% with process temperature.
Table lists output characteristics.
Table Characteristics Outputs1
Spec Number Characteristic sp36a sp36b sp40 sp38a sp38b sp42 sp42a
Delay (ns)
Delay (ns)
sp37a sp37b sp41 sp39a sp39b sp43 sp43a outputs-internal clock (NMSI) outputs-external clock (NMSI) outputs/SI SCC/SMC/SPI/I2C outputs-internal clock (NMSI) Ex_SCC/SMC/SPI/I2C outputs-external clock (NMSI) TIMER/IDMA outputs outputs
Output specifications measured from level rising edge CLKIN level signal. Timings measured pin.
Table lists input characteristics.
Table Characteristics Inputs1
Spec Number Characteristic sp16a sp16b sp20 sp18a sp18b sp22
Setup (ns)
Hold (ns)
sp17a sp17b sp21 sp19a sp19b sp23 inputs-internal clock (NMSI) inputs-external clock (NMSI) inputs/SI SCC/SMC/SPI/I2C inputs-internal clock (NMSI) SCC/SMC/SPI/I2C inputs-external clock (NMSI) PIO/TIMER/IDMA inputs
Input specifications measured from level signal level rising edge CLKIN. Timings measured pin.
Note that although specifications generally reference rising edge clock, following timing diagrams also apply when falling edge active edge.
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
Figure shows external clock.
Serial ClKin sp17b sp16b input signals sp36b/sp37b output signals
Note: When GFMR[TCI]
sp36b/sp37b output signals
Note: When GFMR[TCI]
Figure External Clock Diagram
Figure shows internal clock.
BRG_OUT sp17a sp16a input signals sp36a/sp37a output signals
Note: When GFMR.TCI
sp36a/sp37a
output signals
Note: When GFMR.TCI
Figure Internal Clock Diagram
Figure shows SCC/SMC/SPI/I2C external clock.
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics
Serial CLKin sp18b SCC/SMC/SPI/I2C input signals
(See note.)
sp19b
sp38b/sp39b SCC/SMC/SPI/I2C output signals
(See note.)
Note: There four possible timing conditions SPI: Input sampled rising edge output driven rising edge (shown). Input sampled rising edge output driven falling edge. Input sampled falling edge output driven falling edge. Input sampled falling edge output driven rising edge.
Figure SCC/SMC/SPI/I2C External Clock Diagram
Figure shows SCC/SMC/SPI/I2C internal clock.
BRG_OUT sp18a SCC/SMC/SPI/I2C input signals
(See note.)
sp19a
sp38a/sp39a SCC/SMC/SPI/I2C output signals
(See note.)
Note: There four possible timing conditions SPI: Input sampled rising edge output driven rising edge (shown). Input sampled rising edge output driven falling edge. Input sampled falling edge output driven falling edge. Input sampled falling edge output driven rising edge.
Figure SCC/SMC/SPI/I2C Internal Clock Diagram
Figure shows input output signals.
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
Serial CLKin sp20 input signals sp40/sp41 output signals Note: There four possible timing conditions: Input sampled rising edge output driven rising edge (shown). Input sampled rising edge output driven falling edge. Input sampled falling edge output driven falling edge. Input sampled falling edge output driven rising edge. sp21
Figure Signal Diagram
Figure shows PIO, timer, signals.
sp23 sp22 PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23 sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43 IDMA output signals sp42/sp43 sp42a/sp43a TIMER(sp42/43)/ PIO(sp42a/sp43a) output signals Note: TGATE asserted rising edge clock; deasserted falling edge.
Figure PIO, Timer, Signal Diagram
Table lists input characteristics.
MOTOROLA
MPC8250 Hardware Specifications
Electrical Thermal Characteristics Table Characteristics Inputs1
Spec Number Characteristic sp11 sp12 sp13 sp14 sp15
Setup (ns)
Hold (ns)
sp10 sp10 sp10 sp10 sp10 AACK/ARTRY/TA/TS/TEA/DBG/BG/BR Data normal mode Data PARITY modes pins other pins
Input specifications measured from level signal level rising edge CLKIN. Timings measured pin.
Table lists output characteristics.
Table Characteristics Outputs1
Spec Number Characteristic sp31 sp32 sp33a sp33b sp34 sp35
Delay (ns)
Delay (ns)
sp30 sp30 sp30 sp30 sp30 sp30 PSDVAL/TEA/TA ADD/ADD_atr./BADDR/CI/GBL/WT Data Memory controller signals/ALE other signals
Output specifications measured from level rising edge CLKIN level signal. Timings measured pin.
NOTE Activating data pipelining (setting BRx[DR] memory controller) improves timing. When data pipelining activated, sp12 used data setup even when PARITY used. Also, sp33a used specification signals. Figure shows interaction several signals.
MPC8250 Hardware Specifications
MOTOROLA
Electrical Thermal Characteristics
CLKin sp11 AACK/ARTRY/TA/TS/TEA/ DBG/BG/BR input signals sp12 DATA normal mode input signal sp15 other input signals sp31 PSDVAL/TEA/TA output signals sp32 ADD/ADD_atr/BADDR/CI/ GBL/WT output signals sp33a DATA output signals sp30 sp30 sp10 sp10 sp10
sp30
sp35
sp30
other output signals
Figure Signals
Figure shows signal behavior parity modes (including ECC, parity, standard parity).
CLKin sp10 sp13 DATA bus, ECC, PARITY mode input signals
sp10 sp14 mode input signal
sp33b/sp30 mode output signal
Figure Parity Mode Diagram
Figure shows signal behavior MEMC mode.
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MPC8250 Hardware Specifications
Electrical Thermal Characteristics
CLKin
V_CLK
Memory controller signals
sp34/sp30
Figure MEMC Mode Diagram
NOTE Generally, MPC8250 system output signals driven from rising edge input clock (CLKin). Memory controller signals, however, trigger four points within CLKin cycle. Each cycle divided four internal ticks: always occurs rising edge, falling edge, CLKin. However, spacing depends clock ratio selected, shown Table
Table Tick Spacing Memory Controller Signals
Tick Spacing Occurs Rising Edge CLKin) Clock Ratio 1:2, 1:3, 1:4, 1:5, 1:2.5 1:3.5 CLKin 3/10 CLKin 4/14 CLKin CLKin CLKin CLKin CLKin 8/10 CLKin 11/14 CLKin
Figure graphical representation Table
CLKin 1:2, 1:3, 1:4, 1:5,
CLKin
1:2.5
CLKin
1:3.5
Figure Internal Tick Spacing Memory Controller Signals
NOTE machine outputs change internal tick determined memory controller programming; specifications relative internal tick. Note that SDRAM GPCM machine outputs change CLKin's rising edge.
MPC8250 Hardware Specifications
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Clock Configuration Modes
Clock Configuration Modes
Table MPC8250 Clocking Modes
Pins Clocking Mode Local host Clock Frequency Range (MHZ) 50-66 25-50 50-66 agent 25-50 Table Table Table Table Reference Table Table
MPC8250 three clocking modes: local, host, agent. clocking mode according three input pins-PCI_MODE, PCI_CFG[0], PCI_MODCK-as shown Table
PCI_MODE
PCI_CFG[0] PCI_MODCK1
Determines clock frequency range. Refer Section 1.3.2, "PCI Mode."
each clocking mode, configuration bus, core, PCI, frequencies determined seven bits during power-up reset-three hardware configuration pins (MODCK[1-3]) four bits from hardware configuration word[28-31] (MODCK_H). Both PLLs dividers according selected MPC8250 clock operation mode described following sections. NOTE Clock configurations change only after asserted.
1.3.1
Local Mode
Table shows eight basic clock configurations MPC8250. Another configurations available using configuration (RSTCONF) driving four pins data bus.
Table Clock Default Configurations
MODCK[1-3] Input Clock Frequency Multiplication Factor Frequency Core Multiplication Factor Core Frequency
Table describes possible clock configurations when using hard reset configuration sequence. Note also that basic modes shown boldface type. frequencies listed purpose illustration only. Users must select mode input frequency that resulting configuration does exceed frequency rating user's device.
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MPC8250 Hardware Specifications
Clock Configuration Modes Table Clock Configuration Modes1
MODCK_H-MODCK[1-3] 0001_000 0001_001 0001_010 0001_011 0001_100 Core Multiplication Input Clock Multiplication Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2
0001_101 0001_110 0001_111 0010_000 0010_001
0010_010 0010_011 0010_100 0010_101 0010_110
0010_111 0011_000 0011_001 0011_010 0011_011
0011_100 0011_101 0011_110 0011_111 0100_000
MPC8250 Hardware Specifications
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Clock Configuration Modes Table Clock Configuration Modes1 (Continued)
MODCK_H-MODCK[1-3] 0100_001 0100_010 0100_011 0100_100 0100_101 0100_110 Core Multiplication Input Clock Multiplication Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2 Reserved
0100_111 0101_000 0101_001 0101_010 0101_011 0101_100
Reserved
0101_101 0101_110 0101_111 0110_000 0110_001 0110_010
0110_011 0110_100 0110_101 0110_110 0110_111 0111_000
0111_001 0111_010 0111_011 0111_100 0111_101 0111_110
MOTOROLA
MPC8250 Hardware Specifications
Clock Configuration Modes Table Clock Configuration Modes1 (Continued)
MODCK_H-MODCK[1-3] 0111_111 1000_000 1000_001 1000_010 1000_011 1000_100
Core Multiplication Input Clock Multiplication Core Factor2 Factor2 Frequency2,3 Frequency2 Frequency2
Because speed dependencies, possible configurations Table applicable. user should choose input clock frequency multiplication factors such that frequency equal greater than (150 extended temperature parts) ranges between 66-233 MHz. Input clock frequency given only purpose reference. User should MODCK_H-MODCK_L that resulting configuration does exceed frequency rating user's part.
1.3.2
Mode
mode selected according three input pins, shown Table addition, note following: NOTE: PCI_MODCK mode only, PCI_MODCK comes from LGPL5 MODCK_H[0-3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}. NOTE: Tval (Output Hold) minimum Tval when PCI_MODCK minimum Tval when PCI_MODCK Therefore, designers should clock configurations that this condition achieve PCI-compliant timing. NOTE Clock configurations change only after asserted.
1.3.2.1
Host Mode
frequencies listed purpose illustration only. Users must select mode input frequency that resulting configuration does exceed frequency rating user's device.
MPC8250 Hardware Specifications
MOTOROLA
Clock Configuration Modes Table Clock Default Configurations Host Mode (MODCK_HI 0000)
Input Clock Core Core Division Multiplication MODCK[1-3]1 Frequency Multiplication Frequency Frequency Factor2 Frequency2 (Bus) Factor Factor
66/33 66/33 55/28 55/28 55/28 66/33 66/33 66/33
Assumes MODCK_HI 0000. frequency depends value PCI_MODCK. PCI_MODCK high (logic `1'), frequency divided instead MHz, etc.) Refer Table
Table describes possible clock configurations when using MPC8250's internal bridge host mode.
Table Clock Configuration Modes Host Mode
MODCK_H MODCK[1-3]
Input Clock Frequency1 (Bus)
Core Core Division Multiplication Multiplication Frequency2 Frequency Frequency Factor2 Factor Factor 33/16 33/16 33/16 33/16
0001_000 0001_001 0001_010 0001_011
0010_000 0010_001 0010_010 0010_011
33/16 33/16 33/16 33/16
0011_0003 0011_0013 0011_0103 0011_0113
0100_0003 0100_0013 0100_0103
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MPC8250 Hardware Specifications
Clock Configuration Modes Table Clock Configuration Modes Host Mode (Continued)
MODCK_H MODCK[1-3]
Input Clock Frequency1 (Bus)
Core Core Division Multiplication Multiplication Frequency Frequency Factor2 Frequency2 Factor Factor
0100_0113
0101_000 0101_001 0101_010 0101_011 0101_100
66/33 66/33 66/33 66/33 66/33
0110_000 0110_001 0110_010 0110_011 0110_100
55/28 55/28 55/28 55/28 55/28
0111_000 0111_001 0111_010 0111_011 0111_100
66/33 66/33 66/33 66/33 66/33
1000_000 1000_001 1000_010 1000_011 1000_100
50/25 50/25 50/25 50/25 50/25
1001_000 1001_001 1001_010 1001_011 1001_100
58/29 58/29 58/29 58/29 58/29
1010_000 1010_001
66/33 66/33
MPC8250 Hardware Specifications
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Clock Configuration Modes Table Clock Configuration Modes Host Mode (Continued)
MODCK_H MODCK[1-3]
Input Clock Frequency1 (Bus)
Core Core Division Multiplication Multiplication Frequency Frequency Factor2 Frequency2 Factor Factor 66/33 66/33 66/33
1010_010 1010_011 1010_100
1011_000 1011_001 1011_010 1011_011 1011_100
62/31 62/31MHz 62/31 62/31 62/31
Input clock frequency given only purpose reference. User should MODCK_H-MODCK_L that resulting configuration does exceed frequency rating user's part. frequency depends value PCI_MODCK. PCI_MODCK high (logic `1'), frequency divided instead MHz, etc.). Refer Table this mode, PCI_MODCK must "0".
1.3.2.2
Agent Mode
frequencies listed purpose illustration only. Users must select mode input frequency that resulting configuration does exceed frequency rating user's device.
Table Clock Default Configurations Agent Mode (MODCK_HI 0000)
Input Clock Core Core Division Multiplication MODCK[1-3]1 Frequency Multiplication Frequency Frequency3 Factor Frequency4 (PCI)2 Factor Factor2
66/33 66/33 66/33 66/33 66/33 66/33 66/33 66/33
Assumes MODCK_HI 0000. frequency depends value PCI_MODCK. PCI_MODCK high (logic `1'), frequency divided instead MHz, etc.) multiplication factor multiplied Refer Table Core frequency (60x frequency)(core multiplication factor) frequency frequency division factor
Table describes possible clock configurations when using MPC8250's internal bridge agent mode.
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MPC8250 Hardware Specifications
Clock Configuration Modes Table Clock Configuration Modes Agent Mode
Core Division MODCK_H Frequency Multiplication Multiplication MODCK[1-3] Frequency Frequency3 Factor Frequency4 (PCI) Factor Factor 0001_001 0001_010 0001_011 0001_100 66/33 66/33 66/33 66/33 Input Clock Core
0010_001 0010_010 0010_011 0010_100
50/25 50/25 50/25 50/25
0011_000 0011_001 0011_010 0011_011 0011_100
66/33 66/33 66/33 66/33 66/33
110MHz 176MHz
0100_000 0100_001 0100_010 0100_011 0100_100
66/33 66/33 66/33 66/33 66/33
0101_0005 0101_0015 0101_0105 0101_0115 0101_1005
0110_000 0110_001 0110_010 0110_011 0110_100
50/25 50/25 50/25 50/25 50/25
MPC8250 Hardware Specifications
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Clock Configuration Modes Table Clock Configuration Modes Agent Mode (Continued)
Core Division MODCK_H Frequency Multiplication Multiplication MODCK[1-3] Frequency Frequency3 Factor Frequency4 (PCI) Factor Factor 0111_000 0111_001 0111_010 0111_011 66/33 66/33 66/33 66/33 Input Clock Core
1000_000 1000_001 1000_010 1000_011 1000_100 1000_101
66/33 66/33 66/33 66/33 66/33 66/33
1001_000 1001_001 1001_010 1001_011 1001_100
66/33 66/33 66/33 66/33 66/33
1010_000 1010_001 1010_010 1010_011 1010_100
66/33 66/33 66/33 66/33 66/33
1011_000 1011_001 1011_010 1011_011 1011_100
66/33 66/33 66/33 66/33 66/33
212MHz
frequency depends value PCI_MODCK. PCI_MODCK high (logic `1'), frequency divided instead MHz, etc.) multiplication factor multiplied Refer Table Input clock frequency given only purpose reference. User should MODCK_H-MODCK_L that resulting configuration does exceed frequency rating user's part. Core frequency (60x frequency)(core multiplication factor) frequency frequency division factor this mode, PCI_MODCK must "1".
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MPC8250 Hardware Specifications
Pinout
1.4.1
Pinout
Package
This section provides assignments pinout list MPC8250.
following figures table represent standard TBGA package. information alternate package, refer Section 1.4.2, Package" page
1.4.1.1
Assignments
Figure shows pinout package viewed from surface.
Scale
Figure Pinout TBGA Package Viewed from Surface
MPC8250 Hardware Specifications
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Pinout
Figure shows side profile TBGA package indicate direction surface view.
View
Copper Heat Spreader (Oxidized Insulation) Polymide Tape Soldermask Glob-Top Filled Area Glob-Top 1.27 Pitch Copper Traces Attach Etched Cavity Pressure Sensitive Adhesive
Figure Side View TBGA Package
Table shows pinout list package MPC8250. Table defines conventions acronyms used Table
Table MPC8250 Package Pinout List
Name ABB/IRQ2 Ball
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBB/IRQ3 Ball
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name Ball
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 Ball
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 Ball
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK L_A14/PAR L_A15/FRAME/SMI L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 Ball AA27 AA26 AA25 AB29 AB28 AB27
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST Ball AA29 AA28
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 PA22 Ball AC291 AC251 AE281 AG291 AG281 AG261 AE241 AH251 AF231 AH231 AE221 AH221 AJ211 AH201 AG191 AF181 AF171 AE161 AJ161 AG151 AJ131 AE131 AF121
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB5/FCC3_TXD2/L1TSYNCA2/L1GNTA2 PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB19/FCC2_RXD2/L1RQD2/L1RXD3A2 PB22/FCC2_TXD0/FCC2_TXD/L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB29/L1RSYNCB2/FCC2_MII_TX_EN Ball AG111 AH91 AJ81 AH71 AF71 AD51 AF11 AD31 AB51 AD281 AD261 AD251 AE261 AH271 AG241 AH241 AJ241 AG221 AH211 AG201 AF191 AJ181 AJ171 AE141 AF131 AG121 AH111 AH161 AE151 AJ91 AE91 AJ71 AH61 AE31 AE21
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 Ball AC51 AC41 AB261 AD291 AE291 AE271 AF271 AF241 AJ261 AJ251 AF221 AE211 AF201 AE191 AE181 AH181 AH171 AG161 AF151 AJ151 AH141 AG131 AH121 AJ111 AG101 AE101 AF91 AE81 AJ61 AG21 AF31 AF21 AE11 AD11 AC281
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name PD5/DONE1 PD6/DACK1 PD7/SMSYN1FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN CLKIN2 SPARE42 PCI_MODE3 SPARE62 THERMAL04 Ball AD271 AF291 AF281 AG251 AH261 AJ271 AJ231 AG231 AJ221 AE201 AJ201 AG181 AG171 AF161 AH151 AJ141 AH131 AJ121 AE121 AF101 AG91 AH81 AG71 AE41 AG11 AD41 AD21 AE11 AF25
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name THERMAL14 power Ball AG21, AG14, AG8, AJ1, AJ2, AH1, AH2, AG3, AF4, AE5, AC27, Y27, T27, P27, K26, G27, AE25, AF26, AG27, AH28, AH29, AJ28, AJ29, C14, C16, C20, C23, E10, A28, A29, B28, B29, C27, D26, E25, AA4, U28, U29, K28, K29, A19, B19, AC1, AC2, AH19, AJ19, AH10, AJ10, AA5, AF21, AF14, AF8, AE7, AF11, AE17, AE23, AC26, AB25, Y26, V25, T26, R25, P26, M25, K27, H25, G26, D10, D14, D16, D20, D23, E11, E13, E15, E19, E22, AA2,
Core Power
Ground
default configuration pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) input. prevent excessive current, recommended either pull unused pins VDDH, configure them outputs. Must pulled down left floating. desired, this should pulled left floating. information this pin, refer MPC8260 PowerQUICC Thermal Resistor Guide (AN2271/D) available
Symbols used Table described Table
Table Symbol Legend
Symbol OVERBAR Meaning Signals with overbars, such active low. Indicates that signal part media independent interface.
1.4.2
Package
following figures table represent alternate PBGA package. information standard package MPC8250, refer Section 1.4.1, Package" page
1.4.2.1
Assignments
Figure shows pinout package viewed from surface.
MPC8250 Hardware Specifications
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Pinout
Scale
Figure Pinout PBGA Package (View from Top)
Figure shows side profile PBGA package indicate direction surface view.
Transfer molding compound
Plated substrate
attach
Wire bonds
Ball bond Screen-printed solder mask substrate traces
pitch
resin glass epoxy
Figure Side View PBGA Package
Table shows pinout list MPC8250VR. Table defines conventions acronyms used Table
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List
Name ABB/IRQ2 Ball
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBB/IRQ3 Ball
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name Ball
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR Ball
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name CS10/BCTL1 CS11/AP0 BADDR27 BADDR28 BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 LWE0/LSDDQM0/LBS0/PCI_CFG0 LWE1/LSDDQM1/LBS1/PCI_CFG1 LWE2/LSDDQM2/LBS2/PCI_CFG2 LWE3/LSDDQM3/LBS3/PCI_CFG3 LSDA10/LGPL0/PCI_MODCKH0 LSDWE/LGPL1/PCI_MODCKH1 LOE/LSDRAS/LGPL2/PCI_MODCKH2 LSDCAS/LGPL3/PCI_MODCKH3 LGTA/LUPMWAIT/LGPL4/LPBS LGPL5/LSDAMUX/PCI_MODCK L_A14/PAR L_A15/FRAME/SMI Ball AE13 AD15
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name L_A16/TRDY L_A17/IRDY/CKSTP_OUT L_A18/STOP L_A19/DEVSEL L_A20/IDSEL L_A21/PERR L_A22/SERR L_A23/REQ0 L_A24/REQ1/HSEJSW L_A25/GNT0 L_A26/GNT1/HSLED L_A27/GNT2/HSENUM L_A28/RST/CORE_SRESET L_A29/INTA L_A30/REQ2 L_A31/DLLOUT LCL_D0/AD0 LCL_D1/AD1 LCL_D2/AD2 LCL_D3/AD3 LCL_D4/AD4 LCL_D5/AD5 LCL_D6/AD6 LCL_D7/AD7 LCL_D8/AD8 LCL_D9/AD9 LCL_D10/AD10 LCL_D11/AD11 LCL_D12/AD12 LCL_D13/AD13 LCL_D14/AD14 LCL_D15/AD15 LCL_D16/AD16 LCL_D17/AD17 LCL_D18/AD18 Ball AF16 AF15 AE15 AE14 AC17 AD14 AF13 AE20 AC14 AC19 AD13 AF21 AF22 AE21 AB14 AD20 AB10 AC10 AD10 AE10 AF10 AF11 AB12 AB11 AF12 AE11 AC13 AC12 AB13 AD12 AF14 AF17 AE16 AD16
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name LCL_D19/AD19 LCL_D20/AD20 LCL_D21/AD21 LCL_D22/AD22 LCL_D23/AD23 LCL_D24/AD24 LCL_D25/AD25 LCL_D26/AD26 LCL_D27/AD27 LCL_D28/AD28 LCL_D29/AD29 LCL_D30/AD30 LCL_D31/AD31 LCL_DP0/C0/BE0 LCL_DP1/C1/BE1 LCL_DP2/C2/BE2 LCL_DP3/C3/BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TRIS PORESET HRESET SRESET QREQ RSTCONF MODCK1/AP1/TC0/BNKSEL0 MODCK2/AP2/TC1/BNKSEL1 MODCK3/AP3/TC2/BNKSEL2 CLKIN1 Ball AC16 AB16 AF18 AE17 AD17 AB17 AE18 AD18 AC18 AE19 AF20 AD19 AB18 AE12 AA13 AC15 AF19
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name PA0/RESTART1/DREQ3 PA1/REJECT1/DONE3 PA2/CLK20/DACK3 PA3/CLK19/DACK4/L1RXD1A2 PA4/REJECT2/DONE4 PA5/RESTART2/DREQ4 PA7/SMSYN2 PA8/SMRXD2 PA9/SMTXD2 PA10/MSNUM5 PA11/MSNUM4 PA12/MSNUM3 PA13/MSNUM2 PA14/FCC1_RXD3 PA15/FCC1_RXD2 PA16/FCC1_RXD1 PA17/FCC1_RXD0/FCC1_RXD PA18/FCC1_TXD0/FCC1_TXD PA19/FCC1_TXD1 PA20/FCC1_TXD2 PA21/FCC1_TXD3 PA22 PA23 PA24/MSNUM1 PA25/MSNUM0 PA26/FCC1_MII_RX_ER PA27/FCC1_MII_RX_DV PA28/FCC1_MII_TX_EN PA29/FCC1_MII_TX_ER PA30/FCC1_MII_CRS/FCC1_RTS PA31/FCC1_MII_COL PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2 PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2 Ball AC201 AC211 AF251 AE241 AA211 AD251 AC241 AA221 AA231 Y261 W221 W231 V261 V251 T221 T251 R241 P221 N261 N231 K261 L231 K231 H261 F251 D261 D251 C251 C221 B211 A201 A191 AD211 AD221 AC221
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2 PB8/FCC3_RXD0/FCC3_RXD/TXD3 PB9/FCC3_RXD1/L1TXD2A2 PB10/FCC3_RXD2 PB11/FCC3_RXD3 PB12/FCC3_MII_CRS/TXD2 PB13/FCC3_MII_COL/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3 PB15/FCC3_MII_TX_ER/RXD2 PB16/FCC3_MII_RX_ER/CLK18 PB17/FCC3_MII_RX_DV/CLK17 PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2 PB19FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1 PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2 PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2 PB23/FCC2_TXD1/L1TXDD2 PB24/FCC2_TXD2/L1RSYNCC2 PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2 PB26/FCC2_MII_CRS/L1RXDC2 PB27/FCC2_MII_COL/L1TXDC2 PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1 PB29/L1RSYNCB2/ FCC2_MII_TX_EN PB30/FCC2_MII_RX_DV/L1RXDB2 PB31/FCC2_MII_TX_ER/L1TXDB2 PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2 PC1/DREQ2/BRGO6/L1RQA2 PC2/FCC3_CD/DONE2 PC3/FCC3_CTS/DACK2/CTS4 PC4/SI2_L1ST4/FCC2_CD PC5/SI2_L1ST3/FCC2_CTS PC6/FCC1_CD PC7/FCC1_CTS PC8/CD4/RENA4/SI2_L1ST2/CTS3 PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2 Ball AE261 AB231 AC261 AB261 AA251 W261 W251 V241 U241 R221 R231 M231 L241 K241 L211 P251 N251 E261 H231 C261 B261 A221 A211 E201 C201 AE221 AA191 AF241 AE251 AB221 AC251 AB251 AA241 Y241 U221
MPC8250 Hardware Specifications
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Pinout Table MPC8250 Package Pinout List (Continued)
Name PC10/CD3/RENA3 PC11/CTS3/CLSN3/L1TXD3A2 PC12/CD2/RENA2 PC13/CTS2/CLSN2 PC14/CD1/RENA1 PC15/CTS1/CLSN1/SMTXD2 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/CLK8/TOUT4 PC25/CLK7/BRGO4 PC26/CLK6/TOUT3/TMCLK PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3 PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2 PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1 PC30/CLK2/TOUT1 PC31/CLK1/BRGO1 PD4/BRGO8/FCC3_RTS/SMRXD2 PD5/DONE1 PD6/DACK1 PD7/SMSYN1/FCC1_TXCLAV2 PD8/SMRXD1/BRGO5 PD9/SMTXD1/BRGO3 PD10/L1CLKOB2/BRGO4 PD11/L1RQB2 PD12 PD13 PD14/L1CLKOC2/I2CSCL PD15/L1RQC2/I2CSDA PD16/SPIMISO Ball V231 U231 T261 R261 P261 P241 M261 L261 M241 L221 K251 J251 G261 F261 G241 E251 G231 B231 E221 E211 D211 B201 AF231 AE231 AB211 AD231 AD261 Y221 AB241 Y231 AA261 W241 V221 U261 T231
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MPC8250 Hardware Specifications
Pinout Table MPC8250 Package Pinout List (Continued)
Name PD17/BRGO2/SPIMOSI PD18/SPICLK PD19/SPISEL/BRGO1 PD20/RTS4/TENA4/L1RSYNCA2 PD21/TXD4/L1RXD0A2/L1RXDA2 PD22/RXD4L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3 PD24/TXD3 PD25/RXD3 PD26/RTS2/TENA2 PD27/TXD2 PD28/RXD2 PD29/RTS1/TENA1 PD30/TXD1 PD31/RXD1 VCCSYN VCCSYN1 GNDSYN CLKIN2 SPARE42 PCI_MODE3 SPARE62 THERMAL04 THERMAL14 power Ball R251 P231 N221 M251 L251 J261 K221 G251 H241 F241 H221 B221 D221 C211 E191 AD24 AA6, AA8, AA10, AA11, AA14, AA16, AA17, AB19, AB20, W21, U21, T21, P21, N21, M22, J22, H21, F21, F19, F17, E16, F14, E13, E12, F10, E10,
MPC8250 Hardware Specifications
MOTOROLA
Package Description Table MPC8250 Package Pinout List (Continued)
Name Core Power Ball AC11, AD11, AB15, U25, T24, J24, H25, F23, B19, D17, C17, D10, C18, AC4, AE7, AC23, Y25, N24, J23, A23, D23, D20, E18, A13, A16, K10, K11, K12, K13, K14, K15, K16, K17, L10, L11, L12, L13, L14, L15, L16, L17, M10, M11, M12, M13, M14, M15, M16, M17, N10, N11, N12, N13, N14, N15, N16, N17, P10, P11, P12, P13, P14, P15, P16, P17, R10, R11,R12, R13, R14, R15, R16, R17, T10, T11, T12, T13, T14, T15, T16, T17, U10, U11, U12, U13, U14, U15, U16,
Ground
default configuration pins (PA[0-31], PB[4-31], PC[0-31], PD[4-31]) input. prevent excessive current, recommended either pull unused pins VDDH, configure them outputs. Must pulled down left floating. desired, must pulled left floating. information this pin, refer MPC8260 PowerQUICC Thermal Resistor Guide (AN2271/D).
1.5.1
Package Description
Package Parameters
Table Package Parameters
following sections provide package parameters mechanical dimensions.
Package parameters provided Table
Package
Devices MPC8250 MPC8250VR
Outline (mm) 37.5 37.5
Type TBGA PBGA
Interconnects
Pitch (mm) 1.27
Nominal Unmounted Height (mm) 1.55 2.25
MOTOROLA
MPC8250 Hardware Specifications
Package Description
1.5.2
1.5.2.1
Mechanical Dimensions
Package Dimensions
Figure provides mechanical dimensions bottom surface nomenclature TBGA package.
Notes: Dimensions Tolerancing ASME Y14.5M-1994. Dimensions millimeters. Dimension measured maximum solder ball diameter, parallel primary data Primary data seating plane defined spherical crowns solder balls. Millimeters 1.45 0.60 0.85 0.25 0.65 1.65 0.70 0.95 0.85
37.50 35.56 1.27 37.50 35.56
Figure Mechanical Dimensions Bottom Surface Nomenclature-480 TBGA
MPC8250 Hardware Specifications
MOTOROLA
Package Description
1.5.2.2
Package Dimensions
Figure provides mechanical dimensions bottom surface nomenclature PBGA package.
Figure Mechanical Dimensions Bottom Surface Nomenclature-516 PBGA
MOTOROLA
MPC8250 Hardware Specifications
Ordering Information
Ordering Information
Figure provides example Motorola part numbering nomenclature MPC8250. addition processor frequency, part numbering scheme also consists part modifier that indicates enhancement(s) part from original production design. Each part number also contains revision code that refers mask revision number specified part numbering scheme identification purposes only. more information, contact your local Motorola sales office.
8250
Product Code Device Number Revision Level
Process Technology 0.25 micron) Temperature Range (Blank
Processor Frequency (CPU/CPM/Bus) Package TBGA PBGA
Figure Motorola Part Number Table Document Revision History
Revision Date 11/2001 Initial version 2/2002 Note Table (changes italics): ".greater than equal MHz, CPM." Table core frequency values following ranges MODCK_HMODCK: 0011_000 0011_100 1011_000 1011_1000 Table footnotes added pins AE11, AF25, Table modified notes pins AE11 AF25. Table added note pins (Therm0 Therm1). Table modified note AF25. Table Notes Addition note page 8:VDDH tracking Table Note Table Note Table Note Substantive Changes
3/2202 3/2002 5/2002
9/2002
Addition (516 PBGA) package information. Refer sections 1.2.2, 1.4.2, 1.5.
10/2002 Table Pinout": corrected ball assignment following pins-A12-A17, PD5, PC2. 10/2002 Table Pinout": Addition Core (VDDx) list (page 11/2002 Table Pinout": Addition Ground (GND) list (page
MPC8250 Hardware Specifications
MOTOROLA
Ordering Information Table Document Revision History (Continued)
Revision Date 8/2003 Substantive Changes Table Modification supply voltage ranges reflected notes Addition VCCSYN "Note: Core, PLL, Supply Voltages" following Table Addition Figure Addition note Table Table Changes Addition Table Figure Addition sp42a/sp43a Figure through Figure Addition notes modifications Table Change sp10 Table Table Table Removal bypass mode from clock tables Table Table Addition note Addition SPICLK PC19 Table Table documented correctly MPC8260 PowerQUICC IIFamily Reference Manual previously been omitted from Table Table
MOTOROLA
MPC8250 Hardware Specifications
Ordering Information
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MPC8250 Hardware Specifications
MOTOROLA
Ordering Information
THIS PAGE INTENTIONALLY LEFT BLANK
MOTOROLA
MPC8250 Hardware Specifications
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Information this document provided solely enable system software
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE:
implementers Motorola products. There express implied copyright licenses granted hereunder design fabricate integrated circuits integrated circuits based information this document. Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part.
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MPC8250EC/D

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