IEEE 802.5 Token-Ring Network Compatible IEEE 802.3 Blue Book Ethernet
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
IEEE 802.5 Token-Ring Network Compatible IEEE 802.3 Blue Book Ethernet Network Compatible Compatible With TI380FPA PacketBlasterToken-Ring Features 4-Megabit-per-Second Data Rates Supports 18K-Byte Frame Size (16-Mbps Operation Only) Supports Universal Local Network Addressing Early Token-Release Option (16-Mbps Operation Only) Compatible With TMS38054 Ethernet Features Megabit-per-Second Data Rate Half-Duplex Mode Megabit-per-Second Data Rate Full-Duplex Mode Compatible With Most Ethernet Serial-Network-Interface Devices Network-Speed Self-Test Feature Glueless Interface DRAMs High-Performance 16-Bit Communications-Protocol Processing 16.5-Megabyte-per-Second High-Speed Master Interface Low-Cost Host-Slave Interface Option 32-Bit Host Address Selectable Host System-Bus Options
Adapter Local-Bus Speed Switchable Between 80x8x 68xxx-Type Memory Organization 16-Bit Data 80x8x Buses Optional Parity Checking Dual-Port Direct Transfers Host Supports 16-Bit Pseudo-DMA Operation Enhanced-Address-Copy-Option (EACO) Interface Supports External Address-Checking Logic Bridging External Custom Applications
Built-In Real-Time Error Detection Bring-Up Self-Test Diagnostics With Loopback Automatic Frame-Buffer Management 33-MHz System-Bus Clock Slow-Clock Low-Power Mode Single Supply CMOS Technology 250-mA Typical Latch-Up Immunity 25°C Protection Exceeds 144-Pin Plastic Thin Quad Flat Package (PGE Suffix) Operating Temperature Range 70°C
Subsystem Attached System MHz) Transmit Network Receive
TI380C27
Token-Ring Ethernet Physical-Layer Circuitry
Memory
Figure Network-Commprocessor Applications Diagram
Token-Ring Network trademarks International Business Machines Corporation. PacketBlaster trademark Texas Instruments Incorporated. Ethernet trademark Xerox Corporation.
ADVANCE INFORMATION concerns products sampling preproduction phase development. Characteristic data other specifications subject change without notice.
Copyright 1995, Texas Instruments Incorporated
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Support Module High-Impedance In-Circuit Testing
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
assignments
PACKAGE VIEW
MRAS MCAS MAX2 MAX0 MDDIR SYNCIN OSCIN MROMEN MACS MREF VSSL VSSL MBIAEN VDDL MRESET MBCLK2 MBCLK1 OSCOUT RCVR RCLK NSELOUT1 PXTALIN VSSC WRAP TXEN DRVR DRVR WFLT/COLL NSRT LPBK FRAQ REDY/CRS VSSL MBEN MADH7 MADH6 MADH5 MADH4 MADH3 MADH2 MADH1 MADH0 MAXPH MBRQ MBGR MAXPL MADL7 MADL6 MADL5 MADL4 MADL3 MADL2 MADL1 MADL0 EXTINT3 EXTINT2 EXTINT1 EXTINT0 VSSL
VSSL XMATCH XFAIL TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 VSSD VSSC SADH6 SADH7 SUDS SRDY SDTACK SOWN SDBEN SBHE SRNW SHRQ SBRQ SADL0 SADL1 SADL2 VSSL
VDDL CLKDIV VSSC NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SBRLS SBBSY SHALT VSSL VSSL SRS2 SBERR VDDL SINTR SIRQ SHLDA SBGR SDDIR SRAS SLDS SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
description
TI380C27 single-chip network-communications processor (commprocessor) that supports token-ring Ethernet local area networks (LANs). Token ring data rate either Mbps Mbps Ethernet data rate either Mbps (half duplex) Mbps (full duplex) selected. flexible configuration scheme allows network type speed configured hardware software. This allows design subsystems that support both token-ring Ethernet networks electrically physically switched network front-end circuits. addition, TI380C27 used with TI380FPA PacketBlaster maximum performance. TI380C27 token-ring capability conforms 8802 IEEE 802.5 1992 standards been verified completely Token-Ring Network compatible. integrating essential control building blocks needed LAN-subsystem card into device, TI380C27 ensure that this compatibility maintained silicon. TI380C27 Ethernet capability conforms 8802 (ANSI IEEE Std. 802.3 CSMA standards Ethernet Blue Book standard.
TI380C27 provides 32-bit system-memory address reach with high-speed bus-master interface that supports rapid communications with host system. addition, TI380C27 supports direct low-cost 16-bit pseudo-DMA interface that requires only chip select work directly 80x8x 8-bit slave interface. Finally, selectable 80x8x 68xxx-type host-system memory organization design flexibility. TI380C27 supports addressing bytes local memory. This expanded memory capacity improve LAN-subsystem performance minimizing frequency host LAN-subsystem communications allowing larger blocks information transferred time. support large local memory important applications that require large data transfers (such graphics data-base transfers) heavily loaded networks where extra memory provide data buffers store data until processed host. proprietary used TI380C27 allows protocol software downloaded into stored local-memory space. moving protocols subsystem, overall system performance increased. This accomplished offloading processing from host system TI380C27, which also reduce LAN-subsystem-to-host communications. other protocol software developed, greater differentiation products with enhanced system performance will possible. addition, TI380C27 includes hardware counters that provide real-time error detection automatic frame-buffer management. These counters control system-bus retries, control burst size, track host LAN-subsystem buffer status. Previously, these counters needed maintained software. integrating them into hardware, software overhead removed LAN-subsystem performance improved. TI380C27 implements TI-patented enhanced-address-copy-option (EACO) interface. This interface supports external address-checking devices, such TMS380SRA source-routing accelerator. TI380C27 128-word external space memory support external address-checker devices other hardware extensions TMS380 architecture. major blocks TI380C27 include communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter-support function (ASF), shown functional block diagram. TI380C27 available 144-pin plastic thin quad flat package (PGE suffix) characterized operation from 70°C.
registered trademark Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.
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high degree integration TI380C27 makes virtual subsystem single chip. Protocol handling, host-system interfacing, memory interfacing, communications processing provided through TI380C27. complete LAN-subsystem design, only network-interface hardware, local memory, minimal additional components such devices crystal oscillators need added.
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
description (continued)
TI380C27 interface host system, interface local memory, interface physical-layer circuitry. names starting with letter attach host-system names starting with letter attach local-memory bus. Active-low signals have names with overbars; e.g., SCS.
functional block diagram
SADH0 SADH7 SADL0 SADL7 SBRLS SINTR/SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/SUDS SWR/SLDS SRDY/SDTACK SI/M SHLDA/SBGR SBHE/SRNW SRAS/SAS S8/SHALT SRESET SRS0 SRS1 SRS2/SBERR SRSX SHRQ/SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1
System Interface (SIF)
Memory Interface (MIF)
MADH0 MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MDDIR MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV EXTINT0 EXTINT3 TEST0 TEST5 XMATCH XFAIL
Control Control Control
DRAM Refresh Local-Bus Arbitrator Local-Bus Control Local Parity-Check Generator
ADVANCE INFORMATION
Clock Generator (CG)
AdapterSupport Function (ASF) Communications Processor Interrupts Test Function
RCLK REDY WFLT COLL RCVR PXTALIN
Protocol Handler (PH) Token-Ring Ethernet Interface
FRAQ NSRT LPBK WRAP TXEN DRVR DRVR
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions
NAME DESCRIPTION Bootstrap. value BTSTRP loaded into BOOT SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. BTSTRP indicates whether chapters memory ROM. these chapters RAM, TI380C27 denied access local-memory until CPHALT SIFACL register cleared. Chapters local memory based (see Note Chapters local memory based. Clock divider select (see Note CLKDIV 64-MHz OSCIN 4-MHz local 32-MHz OSCIN 4-MHz local 48-MHz OSCIN 6-MHz local
BTSTRP
MACS MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7
Reserved; must tied (see Note Local-memory address, data, status high byte. first quarter local-memory cycle, these lines carry address bits second quarter, they carry status bits; third fourth quarters, they carry data bits most significant MADH0 least significant MADH7. AX4, Memory Cycle Status
Signal
Local-memory address, data, status byte. first quarter local-memory cycle, these lines carry address bits A14; second quarter, they carry address bits third fourth quarters, they carry data bits most significant MADL0 least significant MADL7. Memory Cycle AX4,
Signal
Memory-address latch. strobe signal sampling address start memory cycle; used SRAMs EPROMs. full 20-bit word address valid MAX0, MAXPH, MAX2, MAXPL, MADH0 MADH7, MADL0 MADL7. Three 8-bit transparent latches used retain 20-bit static address throughout cycle. Rising edge signal latching Falling edge Allows above address signals latched Local-memory-extended address bit. MAX0 drives row-address time drives column-address data-valid times cycles. This signal latched MRAS. Driving eases interfacing ROM.
MAX0
Memory Cycle
Signal
input, output NOTES: internal pullup device maintain high-voltage level when left unconnected etch). TI380FPA TMS380SRA currently supported only with 4-MHz local either CLKDIV state. Expansion support 6-MHz local under development. Each must individually tied with pullup resistor. should connected ground.
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EXTINT0 EXTINT1 EXTINT2 EXTINT3
Reserved; must pulled high (see Note
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION Local-memory-extended address bit. MAX2 drives row-address time, which latched MRAS, drives column-address data-valid times cycles. Driving eases interfacing ROM. Memory Cycle Signal Local-memory-extended address parity high byte. first quarter memory cycle, MAXPH carries extended-address AX1; second quarter memory cycle, carries extended-address AX0; last half memory cycle, carries parity high-data byte. Memory Cycle Signal Parity Parity Local-memory-extended address parity byte. first quarter memory cycle, MAXPL carries extended-address AX3; second quarter memory cycle, carries extended-address AX2; last half memory cycle, carries parity low-data byte. Memory Cycle Signal Parity Parity Local-bus clock local-bus clock These signals referenced local-bus transfers. MBCLK2 lags MBCLK1 quarter cycle. These clocks operate according MBCLK1 MBCLK2 MBCLK[1:2] OSCIN CLKDIV
MAX2
MAXPH
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MAXPL
MBEN
Buffer enable. MBEN enables bidirectional buffer outputs MADH, MAXPH, MAXPL, MADL buses during data phase. This signal used conjunction with MDDIR, which selects buffer output direction. Buffer output disabled Buffer output enabled
MBGR
Reserved; must left unconnected. Burned-in address enable. MBIAEN output signal used provide output enable containing adapter's burned-in address (BIA).
MBIAEN
This signal driven high write accesses addresses between 00.0000 00.000F, accesses (read/write) other address. This signal driven read from addresses between 00.0000 00.000F.
MBRQ Reserved; must pulled high (see Note input, output NOTE Each must individually tied with pullup resistor.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION Column-address strobe DRAMs. MCAS valid 3/16 memory cycle following row-address portion cycle. MCAS driven every memory cycle while column address valid MADL0 MADL7, MAXPH, MAXPL, except when following conditions occurs: When address accessed 00.0000 00.000F) When address accessed EPROM memory (i.e., when BOOT SIFACL register zero access made between 00.0010 00.FFFF 1F.0000 1F.FFFF) When cycle refresh cycle, which case MCAS driven start cycle before MRAS (for DRAMs that have CAS-before-RAS refresh). DRAMs that support CASbefore-RAS refresh, necessary disable MCAS with MREF during refresh cycle.
MCAS
Data direction. MDDIR used direction control bidirectional drivers. This signal becomes valid before MBEN becomes active. MDDIR TI380C27 memory-bus write TI380C27 memory-bus read Memory output enable. used enable outputs DRAM memory during read cycle. This signal high EPROM read cycles. Disable DRAM outputs Enable DRAM outputs Row-address strobe DRAMs. address lasts first 5/16 memory cycle. MRAS driven every memory cycle while address valid MADL0 MADL7, MAXPH, MAXPL both cycles. also driven during refresh cycles when refresh address valid MADL0 MADL7. DRAM refresh cycle progress. MREF used indicate that DRAM refresh cycle occurring. also used disabling MCAS DRAMs that CAS-before-RAS refresh. MREF DRAM refresh cycle process DRAM refresh cycle Memory-bus reset. MRESET reset signal generated when either ARESET SIFACL register SRESET asserted. This signal used resetting external local-bus glue logic. MRESET External logic reset External logic reset enable. During first 5/16 memory cycle, MROMEN used provide chip select ROMs when BOOT SIFACL register zero (i.e., when code resident ROM, RAM). latched MAL. goes read from addresses 00.0010 00.FFFF 1F.0000 1F.FFFF when BOOT SIFACL register zero. MROMEN stays high writes these addresses, accesses other addresses, accesses address when BOOT During final three quarters memory cycle, MROMEN outputs address signal interfacing ROM. This means MBIAEN, MAX0, ROMEN, MAX2 together form glueless interface ROM. disabled enabled input, output
MRAS
MROMEN
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION Local-memory write. used specify write cycle local-memory bus. data MADH0 MADH7 MADL0 MADL7 buses valid while low. DRAMs latch data falling edge while SRAMs latch data rising edge local-memory write cycle Local-memory write cycle Nonmaskable interrupt request. must left unconnected. External oscillator input. OSCIN provides clock frequency TI380C27 4-MHz 6-MHz internal (see Note Note OSCIN CLKDIV OSCIN 4-MHz local 4-MHz local 6-MHz local
Oscillator output OSCOUT
PRTYEN
Parity enable. value PRTYEN loaded into SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. PRTYEN enables parity checking local memory. Local-memory data checked parity (see Note Local-memory data checked parity Network selection outputs. NSELOUT0 NSELOUT1 controlled host through corresponding bits SIFACL register. value these bits/signals changed only while TI380C27 reset.
NSELOUT0 NSELOUT1
NSELOUT0
NSELOUT1
DESCRIPTION Full-duplex Ethernet 16-Mbps token ring Half-duplex Ethernet 4-Mbps token ring
SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7
System address/data high byte (see Note 1).These lines make most significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADH0, least significant SADH7. Address multiplexing: Bits bits Data multiplexing: Bits
SADL0 System address/data byte (see Note These lines make least significant byte SADL1 each address word (32-bit address bus) data word (16-bit data bus). most significant SADL2 SADL0, least significant SADL7. SADL3 SADL4 Address multiplexing: Bits bits SADL5 Data multiplexing Bits SADL6 SADL7 input, output NOTES: internal pullup device maintain high-voltage level when left unconnected etch loads). expanded input voltage specification. maximum TI380C27 devices connected oscillator.
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CLKDIV
OSCOUT OSCIN OSCIN MHz, OSCOUT MHz; OSCIN MHz, OSCOUT OSCIN OSCIN MHz, then OSCOUT MHz)
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION System address-latch enable. SALE enable pulse used externally latch LSBs address from SADH0 SADH7 SADL0 SADL7 buses start cycle. Systems that implement address parity also externally latch parity bits (SPH SPL) latched address. System busy. TI380C27 samples value SBBSY during arbitration (see Note sample values: SBBSY busy. TI380C27 become master grant condition met. Busy. TI380C27 cannot become master. SBCLK System clock. TI380C27 requires SBCLK synchronize timings transfers. Valid frequencies MHz. SBHE used system byte high enable. SBHE 3-state output driven during DMA; input other times. Intel Mode Motorola Mode System byte high enabled (see Note System byte high enabled SRNW used system read write. SRNW serves control signal indicate read write cycle. Read cycle (see Note Write cycle
SALE
SBHE/SRNW
System release. SBRLS indicates TI380C27 that higher-priority device requires system bus. value SBRLS ignored when TI380C27 perfoming DMA. SBRLS internally synchronized SBCLK. SBRLS TI380C27 hold onto system (see Note TI380C27 should release system upon completion current cycle. transfer complete, rearbitrates system bus. System chip select. activates system interface TI380C27 read write. selected (see Note Selected System data-bus enable. SDBEN signals external data buffers begin driving data. SDBEN activated during both DMA. SDBEN Keep external data buffers high-impedance state Cause external data buffers begin driving data System data direction. SDDIR provides external data buffers signal indicating direction data moving. During writes reads, SDDIR (data direction into TI380C27). During reads writes, SDDIR high (data direction from TI380C27). When system interface involved operation, SDDIR high default. SDDIR SDDIR DATA DIRECTION output input read write write read
input, output NOTE internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION SHLDA used system hold acknowledge. SHLDA indicates that system hold request been acknowledged. internally synchronized SBCLK (see Note Hold request acknowledged Hold request acknowledged SBGR used system grant. SBGR active-low grant, defined standard 68xxx interface, internally synchronized SBCLK (see Note System granted System granted SHRQ used system hold request. SHRQ used request control system preparation transfer. SHRQ internally synchronized SBCLK. Intel Mode Motorola Mode System requested System requested SBRQ used system request. SBRQ used request control system preparation transfer. SBRQ internally synchronized SBCLK. System requested System requested
Intel Mode Motorola Mode
SHLDA/SBGR
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SHRQ/SBRQ
System interrupt acknowledge. SIACK from host processor acknowledge interrupt request from TI380C27. SIACK System interrupt acknowledged (see Note System interrupt acknowledged: TI380C27 places interrupt vector onto system bus. System Intel/Motorola mode select. value SI/M specifies system-interface mode. SI/M Intel-compatible interface mode selected. Intel interface 8-bit 16-bit mode (see S8/SHALT description Note Motorola-compatible interface mode selected. Motorola interface mode always bits. SINTR used system-interrupt request. TI380C27 activates SINTR signal interrupt request host processor. Intel Mode Motorola Mode Interrupt request TI380C27 interrupt request SIRQ used system-interrupt request. TI380C27 activates SIRQ signal interrupt request host processor. interrupt request Interrupt request TI380C27
SINTR/SIRQ
SOWN
System owned. SOWN indicates external devices that TI380C27 control system bus. SOWN drives enable signal transceiver chips that drive address bus-control signals. TI380C27 does have control system bus. TI380C27 control system bus.
System parity high. optional odd-parity each address data byte transmitted over SADH0 SADH7 (see Note System parity low. optional odd-parity each address data byte transmitted over SADL0 SADL7 (see Note
input, output NOTE internal pullup device maintain high-voltage level when left unconnected etch).
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION SRAS used system memory-address strobe (see Note SRAS used latch SRSX SRS2 register input signals. minimum-chip system, SRAS tied SALE output system bus. latching capability defeated since internal latch these inputs remains transparent long SRAS remains high. This permits SRAS pulled high signals SCS, SRSX SRS2, SBHE applied independently SALE strobe from system bus. During DMA, SRAS remains input. Falling edge Transparent mode Holds latched values SCS, SRSX SRS2, SBHE Latches SCS, SRSX SRS2, SBHE
Intel Mode
SRAS/SAS
Motorola Mode
used sytem-memory address strobe (see Note active-low address strobe that input during (although ignored address strobe) output during DMA. Address valid. Address valid transfer operation progress. used system read strobe (see Note active-low strobe indicating that read cycle performed system bus. input during output during DMA.
Intel Mode Read cycle occurring. DMA, host provides data system bus. DIO, provides data system bus. SUDS used upper-data strobe (see Note SUDS active-low upper-data strobe. SUDS input during output during DMA. valid data SADH0 SADH7 lines Valid data SADH0 SADH7 lines SRDY used system ready (see Note SRDY indicates master that data transfer complete. SRDY asynchronous during pseudo-DMA cycles, internally synchronized SBCLK. During cycles, SRDY must asserted before falling edge SBCLK state order prevent wait state. SRDY output when TI380C27 selected DIO; otherwise, input. System ready. Data transfer complete; system ready. SDTACK used system data-transfer acknowledge (see Note purpose SDTACK indicate master that data transfer complete. SDTACK internally synchronized SBCLK. During cycles, SDTACK must asserted before falling edge SBCLK state order prevent wait state. SDTACK output when TI380C27 selected DIO; otherwise, input. System ready. Data transfer complete; system ready. System reset. SRESET activated place TI380C27 into known initial state. Hardware reset puts most TI380C27 outputs into high-impedance state place blocks into reset state. Intel mode bus-width selection (S8) latched rising edge SRESET. SRESET system reset System reset Rising edge Latch width operations (for Intel-mode applications) input, output NOTE should tied with 4.7-k pullup resistor.
SRD/SUDS
Motorola Mode
Intel Mode
SRDY/SDTACK
Motorola Mode
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION SRSX SRS0 SRS2 used system-register select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS2 (see Note Register selected SRSX SRSX SRS0 SRS1 SRS2/SBERR SRS2/SBERR
Intel Mode
SRS0
SRS1
Motorola Mode
SRSX, SRS0 SRS1 used system-register select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS1 (see Note SRSX SRS1
Register selected
SRS0
SBERR used error. SBERR corresponds bus-error signal 68xxx microprocessor. SBERR internally synchronized SBCLK. This input driven during cycle indicate TI380C27 that cycle must terminated, (see Section 3.4.5.3 TMS380 Second-Generation Token Ring User's Guide (SPWU005) more information). used system-write strobe (see Note active-low write strobe that input during output during DMA. Intel Mode Motorola Mode Write cycle occurring. DMA, data driven from host bus. DIO, rising edge, data latched written selected register. SLDS used lower-data strobe (see Note SLDS input during output during DMA. valid data SADL0 SADL7 lines Valid data SADL0 SADL7 lines
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SWR/SLDS
SXAL
System-extended-address latch. SXAL provides enable pulse used externally latch most significant bits 32-bit system address during DMA. SXAL activated prior first cycle each block transfer, thereafter necessary (whenever increment address counter causes carry lower bits). Systems that implement parity addresses SXAL externally latch parity bits (available SPH) address extension. Reserved. SYNCIN must left unconnected (see Note used system 8/16-bit select. selects width used communications through system interface. rising edge SRESET, TI380C27 latches width; otherwise, value dynamically selects width. Selects 8-bit mode (see Note Selects 16-bit mode SHALT used system halt/bus error retry. SHALT asserted along with SBERR, adapter retries last cycle. This rerun operation defined 68xxx specification. BERETRY counter decremented SBERR when SHALT asserted (see Section 3.4.5.3 TMS380 Second-Generation Token Ring User's Guide (SPWU005) more information).
SYNCIN
Intel Mode
S8/SHALT
Motorola Mode
input, output NOTES: internal pullup device maintain high-voltage level when left unconnected etch). should tied with 4.7-k pullup resistor.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
Network Media Interface Token-Ring Mode TEST1 TEST2
NAME DRVR DRVR DESCRIPTION Differential-driver data output. DRVR DRVR differential outputs that send TI380C27 transmit data TMS38054 driving onto ring-transmit-signal pair. Frequency-acquisition control. FRAQ determines frequency- phase-acquisition mode TMS38054. FRAQ Wide range. Frequency centering PXTALIN TMS38054. Narrow range. Phase lock onto incoming data (RCVINA RCVINB) TMS38054. Insert-control signal TMS38054. NSRT enables phantom-driver outputs (PHOUTA PHOUTB) TMS38054, through watchdog timer, insertion onto token ring. NSRT Static high Static NSRT pulsed high Inactive, phantom current removed (due watchdog timer) Inactive, phantom current removed (due watchdog timer) Active, current output PHOUTA PHOUTB
PXTALIN
Ring-interface clock-frequency control (see Note 16-Mbps ring speed, PXTALIN must supplied 32-MHz signal. 4-Mbps ring speed, PXTALIN must output from OSCOUT. Ring-interface recovered clock (see Note RCLK clock recovered TMS38054 from token-ring received data. 16-Mbps operation, RCLK 32-MHz clock; 4-Mbps operation, RCLK 8-MHz clock. Ring-interface received data (see Note RCVR contains data received TMS38054 from token ring. Ring-interface ready. REDY indicates presence received data monitored TMS38054 energy-detect capacitor.
RCLK
RCVR
REDY
ready. Ignore received data. Ready. Received data. Wire-fault detect. WFLT input TI380C27 driven TMS38054. WFLT indicates current imbalance TMS38054 PHOUTA PHOUTB pins.
WFLT
wire fault detected Wire fault detected Internal wrap select. WRAP output from TI380C27 ring interface activate internal attenuated feedback path from transmitted data (DRVR) receive data (RCVR) signals bring-up diagnostic testing. When active, TMS38054 also cuts current drive transmission pair. Normal ring operation Transmit data drives receive data (loopback)
WRAP
input, output NOTE expanded input voltage specification.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
Network-Media Interface Ethernet Mode (TEST1 TEST2
NAME DRVR DRVR DESCRIPTION DRVR DRVR have Ethernet function should left unconnected. Ethernet transmit data. provides Ethernet PHY-layer circuitry with bit-rate from TI380C27. Data output synchronously TXC. normally connected Ethernet serial network interface (SNI) chip. Loopback. LPBK enables loopback Ethernet transmit data through Ethernet (SNI) device receive data. LPBK Wrap through front-end device Normal operation Ethernet transmit clock. 10-MHz clock input used synchronize transmit data from TI380C27 Ethernet layer circuitry. continuously running clock normally connected output Ethernet chip (see Note Ethernet receive clock. 10-MHz clock input used synchronize received data from Ethernet PHY-layer circuitry TI380C27. must present whenever active (although held maximum clock cycles after rising edge CRS). When inactive, permissible hold normally connected output Ethernet chip. TI380C27 requires maintained state when asserted (see Note Ethernet received data. signal provides TI380C27 with bit-rate network data from Ethernet front-end device. Data must synchronous with normally connected Ethernet chip (see Note Ethernet carrier sense. indicates TI380C27 that Ethernet PHY-layer circuitry network data present RXD. asserted (high) when first frame received deasserted after last frame received. Receiving data data network Ethernet collision detect. COLL indicates TI380C27 that Ethernet PHY-layer circuitry detected network collision. COLL must present least clock cycles ensure accepted TI380C27 normally connected COLL Ethernet chip. COLL also indication test signal. COLL detected device Normal operation Ethernet transmit enable. TXEN indicates Ethernet PHY-layer circuitry that bit-rate data present TXD. TXEN output synchronously normally connected Ethernet chip. Data line currently contains data transmitted valid data TXEN input, output NOTE expanded input voltage specification.
ADVANCE INFORMATION
COLL
TXEN
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Functions (Continued)
NAME DESCRIPTION Network select inputs. TEST0 TEST2 used select network speed type used TI380C27. These inputs should changed only during adapter reset. Connect TEST2 VDDL. TEST0 TEST1 TEST2 TEST0 TEST1 TEST2 DESCRIPTION Full-duplex Ethernet 16-Mbps token ring Half-duplex Ethernet 4-Mbps token ring Reserved
TEST3 TEST4 TEST5
Test inputs. TEST3 TEST5 should left unconnected (see Note Module-in-place test mode achieved tying TEST3 TEST4 ground. this mode, TI380C27 outputs high-impedance state. Internal pullups TI380C27 inputs disabled (except TEST3 TEST5). External fail-to-match signal. enhanced-address-copy-option (EACO) device uses XFAIL indicate TI380C27 that should copy frame ARI/FCI bits token-ring frame external address match.The ARI/FCI bits token-ring frame internal address-matched frame. EACO device used, XFAIL must left unconnected. XFAIL ignored when mode enabled [see table XMATCH description (see Note 1)]. address match external address checker External address-checker-armed state External match signal. enhanced-address-copy-option (EACO) device uses XMATCH indicate TI380C27 copy frame ARI/FCI bits token-ring frame. EACO device used, XMATCH must left unconnected. XMATCH ignored when mode enabled (see Note Address match recognized external address checker External address-checker-armed state XMATCH Hi-Z XFAIL Hi-Z FUNCTION Armed (processing frame data) externally match frame (XFAIL takes precedence). Copy frame externally match frame (XFAIL takes precedence). Reset state (adapter initialized)
XFAIL
XMATCH
VDDL
Positive-supply voltage digital logic. VDDL pins must attached common-system power-supply plane.
Positive-supply voltage output buffers. pins must attached common-system power-supply plane.
VSSC
Ground reference output buffers (clean ground). VSSC pins must attached common-system ground plane.
input, output NOTE internal pullup device maintain high-voltage level when left unconnected etch).
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Functions (Continued)
NAME DESCRIPTION
VSSL
Ground reference input buffers. VSSL pins must attached common-system ground plane.
Ground connections output buffers. pins must attached system ground plane.
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These pins should left unconnected.
input, output
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architecture
major blocks TI380C27 include communications processor (CP), system interface (SIF), memory interface (MIF), protocol handler (PH), clock generator (CG), adapter support function (ASF). functionality each block described following sections. communications processor (CP) performs control monitoring other functional blocks TI380C27. control monitoring protocols specified software (downloaded based) local memory. Available protocols include:
Media access control (MAC) software Logical link control (LLC) software (token-ring mode only) Copy frames (CAF) software
proprietary 16-bit central processing unit (CPU) with data cache single prefetch pipe pipelining instructions. These features enhance TI380C27's maximum performance capability about million instructions second (MIPS), with average about MIPS. system interface (SIF) performs interfacing subsystem host system. This interface require additional logic depending application. system interface transfer information/data using these three methods:
Direct memory access (DMA) Direct input output (DIO) Pseudo-direct memory access (PDMA)
PDMA) used transfer data to/from host memory from/to local memory. main uses loading software local memory initializing TI380C27. also allows command/status interrupts occur from TI380C27. system interface hardware selected either modes SI/M. mode selected determines memory organizations control signals used. These modes are:
Intel 80x8x families: 16-, 32-bit devices Motorola 68xxx microprocessor family: 32-bit devices
system interface supports host-system memory addressing bits (32-bit reach into host-system memory). This allows greater flexibility using/accessing host-system memory. System designers allowed customize system interface their particular
Programmable burst transfers cycle-steal operations Optional parity protection
These features implemented hardware reduce system overhead, facilitate automatic rearbitration after burst, repeat cycle when errors occur (parity bus). retries also supported. system-interface hardware also includes features enhance integrity TI380C27 data. These features include following:
Always internally maintain odd-byte parity regardless parity being disabled Monitor presence clock failure Switchable speeds
every cycle, system interface compares system clocks reference clock. clocks become invalid, TI380C27 enters slow-clock mode, which prevents latch-up TI380C27. SBCLK invalid, cycle terminated immediately; otherwise, cycle completed TI380C27 placed slow-clock mode.
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system interface (SIF) (continued) When TI380C27 enters slow-clock mode, clock that failed replaced slow free-running clock device placed into low-power reset state. When failed clock(s) return valid operation, TI380C27 must reinitialized. with 16-MHz clock, continuous transfer rate megabits second Mbps) obtained. with 25-MHz clock, continuous transfer rate megabits second Mbps) obtained. with clock, continuous transfer rate megabits second Mbps obtained.For 8-bit 16-bit pseudo-DMA, following data rates obtained:
LOCAL SPEED 8-BIT PDMA Mbps Mbps 16-BIT PDMA Mbps Mbps
Since main purpose downloading initialization, transfer rate significant issue. memory interface (MIF) performs memory management allow TI380C27 address bytes local memory. Hardware allows TI380C27 directly connected DRAMs without additional circuitry. This glueless DRAM connection includes DRAM refresh controller. also handles internal arbitration between these blocks. When required, then arbitrates external bus. responsible memory mapping task. memory DRAMs, EPROMs, burned-in addresses (BIA), external devices appropriately addressed when required system interface, protocol handler, transfer. memory interface capable 64-Mbps continuous transfer rate when using 4-MHz local 64-MHz device crystal 96-Mbps continuous transfer rate when using 6-MHz local bus. protocol handler (PH) performs hardware-based real-time protocol functions token-ring Ethernet LAN. Network type determined TEST0 TEST2. Token-ring network determined software either Mbps Mbps. Ethernet network either full duplex half duplex. These speeds fixed hardware software. converts parallel-transmit data serial-network data appropriate coding converts received serial data parallel data. data-management state machines direct transmission/reception data from local memory through MIF. PH's buffer-management state machines automatically oversee this process, directly sending/receiving linked lists frames without intervention. protocol handler contains many state machines that provide following features:
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Transmit receive frames Capture tokens (token ring) Provide token-priority controls (token ring) Automatic retry frame transmissions after collisions Ethernet) Implement random exponential backoff algorithm Ethernet) Manage TI380C27 buffer memory Provide frame-address recognition (group, specific, functional, multicast) Provide internal parity protection Control verify PHY-layer circuitry-interface signals
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protocol handler (PH) (continued) Integrity transmitted received data assured cyclic redundancy checks (CRC), detection network data violations, parity internal data paths. data paths registers optionally parity protected assure functional integrity. adapter support function (ASF) performs support functions contained other blocks. features are:
TI380C27 base timer Identification, management, service internal external interrupts Test-pin mode control, including unit-in-place mode board testing Checks illegal states, such illegal opcodes parity
clock generator (CG) performs generation clocks required other functional blocks, including local memory-bus clocks (MBCLK1, MBCLK2). also generates reference timer used sample input clocks (SBCLK, OSCIN, RCLK, PXTALIN). transition detected within period reference timer input clock signal, places TI380C27 into slow-clock mode. frequency reference timer range kHz.
user-accessible hardware registers TI380C27-internal pointers
following tables show access internal data pointers address registers host interface. SIFACL register, which directly controls device operation, described detail. adapter-internal pointers table following page defined only after TI380C27 initialization until OPEN command issued. These pointers defined TI380C27 software (microcode), this table describes release 1.xx software.
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Adapter-Internal Pointers Token Ring
ADDRESS 00.FFF8 00.FFFA 01.0A00 01.0A02 01.0A04 DESCRIPTION Pointer software microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TI380C27 addresses chapter Pointer node address Pointer group address Pointer functional address Pointer TI380C27 parameters chapter Pointer physical-drop number Pointer upstream neighbor address Pointer upstream physical-drop number Pointer last ring-poll address Pointer reserved Pointer transmit access priority Pointer source class authorization Pointer last attention code Pointer source address last received frame Pointer last beacon type Pointer last major vector Pointer ring status Pointer soft-error timer value Pointer ring-interface error counter Pointer local ring number Pointer monitor error code Pointer last beacon-transmit type Pointer last beacon-receive type Pointer last frame correlator Pointer last beaconing-station Pointer reserved Pointer last beaconing-station physical-drop number Pointer buffer special buffer used software transmit adapter generated frames) chapter Pointer counters chapter Pointer MAX_SAPs Pointer open SAPs Pointer MAX_STATIONs Pointer open stations Pointer available stations Pointer reserved Pointer 4-/16-Mbps word flag. zero, adapter Mbps. nonzero, adapter Mbps.
01.0A06
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01.0A08 01.0A0A
01.0A0C 01.0A0E
Pointer total TI380C27 found bytes allocation test chapter This table describes pointers release TI380C27 software. This address valid only microcode release
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Adapter-Internal Pointers Ethernet
ADDRESS 00.FFF8 00.FFFA 01.0A00 01.0A02 01.0A04 Software raw-microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TI380C27 addresses chapter Pointer node address Pointer group address Pointer functional address Pointer buffer special buffer used software transmit adapter generated frames) chapter Pointer counters chapter Pointer MAX_SAPs Pointer open SAPs Pointer MAX_STATIONs Pointer open stations Pointer available stations Pointer reserved Pointer 4-/16-Mbps word flag. zero, adapter Mbps. nonzero, adapter Mbps. DESCRIPTION
01.0A08 01.0A0A
01.0A0C
01.0A0E Pointer total TI380C27 found bytes allocation test chapter This table describes pointers release TI380C27 software. This address valid only microcode release
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User-Access Hardware Registers
80x8x 16-BIT MODE: (SI/M S8/SHALT WORD TRANSFERS SBHE SRS2 SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN NORMAL MODE SBHE SRS2 SBHE SRS2 SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN PSEUDO-DMA MODE ACTIVE SBHE SRS2 SBHE SRS2 SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SBHE SRS2 SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN
BYTE TRANSFERS SRSX SRS0 SRS1
SBHE SRS2 defined. 80x8x 8-BIT MODE: (SI/M S8/SHALT SRSX SRS0 SRS1 SRS2 NORMAL MODE SBHE SIFDAT SIFDAT SIFDAT/INC SIFDAT/INC SIFADR SIFADR SIFSTS SIFCMD SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN PSEUDO-DMA MODE ACTIVE SBHE SDMADAT SDMADAT DMALEN DMALEN SDMAADR SDMAADR SDMAADX SDMAADX SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN
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68xxx MODE: (SI/M WORD TRANSFERS SUDS SLDS SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN NORMAL MODE SUDS SLDS SUDS SLDS SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN PSEUDO-DMA MODE ACTIVE SUDS SLDS SUDS SLDS SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SUDS SLDS SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN
BYTE TRANSFERS SRSX SRS0 SRS1
68xxx mode always bit.
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adapter-control register (SIFACL)
SIFACL register allows host processor control some extent reconfigure TI380C27 under software control. SIFACL Register
SWHLDA
SWDDIR
SWHRQ
PSDMAEN
ARESET
CPHALT
BOOT
SINTEN
NSEL OUT0
NSEL OUT1
Bits
Value TEST0 TEST2 pins These bits read only always reflect value corresponding device pins. This allows host determine network type speed configuration. network speed type software configurable, these bits used determine which configurations supported network hardware.
TEST0 TEST1 TEST2 Description Full-duplex Ethernet 16-Mbps token ring Half-duplex Ethernet 4-Mbps token ring Reserved
Reserved. Read data indeterminate. SWHLDA Software Hold Acknowledge This allows function SHLDA SBGR emulated from software control pseudo-DMA mode.
PSDMAEN SWHLDA SWHRQ RESULT SWHLDA value SIFACL register cannot one. pseudo-DMA request pending Indicates pseudo-DMA request interrupt Pseudo-DMA process progress
value SHLDA SBGR ignored.
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Legend:
Read Write Write during ARESET only only Value after reset Value BTSTRP Value PRTYEN Indeterminate
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
adapter-control register (SIFACL) (continued)
SWDDIR Current SDDIR Signal Value This contains current value pseudo-DMA direction. This enables host easily determine direction transfers, which allows system controlled system software. Pseudo from host system TI380C27 Pseudo from TI380C27 host system SWHRQ Current SHRQ Signal Value This contains current value SHRQ/SBRQ when Intel mode, inverse value SHRQ/SBRQ Motorola mode. This enables host easily determine pseudo-DMA transfer requested. INTEL MODE (SI/M System requested System requested MOTOROLA MODE (SI/M System requested System requested
PSDMAEN Pseudo-System-DMA Enable This enables pseudo-DMA operation. Normal bus-master operation possible. Pseudo-DMA operation selected. Operation dependent values SWHLDA SWHRQ bits SIFACL register.
ARESET Adapter Reset This hardware reset TI380C27. This same effect SRESET except that interface SIFACL register maintained. This clock failure detected (OSCIN, PXTALIN, RCLK, SBCLK valid). TI380C27 operates normally. TI380C27 held reset condition.
CPHALT Communications-Processor Halt This controls TI380C27's processor access internal TI380C27 buses. This prevents TI380C27 from executing instructions before microcode been downloaded. TI380C27 processor access internal TI380C27 buses. TI380C27 processor prevented from accessing internal adapter buses.
BOOT Bootstrap Code This indicates whether memory chapters local-memory space ROM/PROM/EPROM. This controls operation MCAS MROMEN. ROM/PROM/EPROM memory chapters memory chapters
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adapter-control register (SIFACL) (continued)
Local-Bus Priority This controls priority levels devices local bus. external devices (such TI380FPA) used with TI380C27. external device (such TI380FPA) used with TI380C27. This allows external master operate necessary priorities local bus. system uses TMS380SRA only, must system uses both TMS380SRA TI380FPA, this must SINTEN System-Interrupt Enable This allows host processor enable disable system-interrupt requests from TI380C27. system-interrupt request from TI380C27 SINTR/SIRQ. following equation shows SINTR/SIRQ driven. table also explains results states. SINTR/SIRQ (PSDMAEN SWHRQ !SWHLDA) (SINTEN SYSTEM_INTERRUPT)
PSDMAEN SWHRQ SWHLDA SINTEN SYSTEM INTERRUPT (SIFSTS REGISTER) Pseudo active. TI380C27 generated system interrupt pseudo DMA. pseudo-DMA interrupt. TI380C27 generates system interrupt. TI380C27 does generate system interrupt. TI380C27 cannot generate system interrupt. RESULT
value SHLDA SBGR ignored.
Parity Enable This determines whether data transfers within TI380C27 checked parity. Data transfers checked parity. Data transfers checked correct parity. NSELOUT0, NSELOUT0 Network-Selection Outputs values these bits control NSELOUT0 NSELOUT1. These bits modified only while ARESET set. These bits used software configure multiprotocol TI380C27 follows: NSELOUT0 NSELOUT1 should connected TEST0 TEST1, respectively (TEST2 should left unconnected tied high). NSELOUT0 used select network speed NSELOUT1 used select network type shown table below:
NSELOUT0 NSELOUT1 SELECTION Full-duplex Ethernet 16-Mbps token ring Half-duplex Ethernet 4-Mbps token ring
power these bits corresponding 16-Mbps token ring (NSELOUT1 NSELOUT0
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SIFACL control pseudo-DMA operation
Pseudo software controlled five bits SIFACL register. logic model SIFACL register control pseudo-DMA operation shown Figure
Internal Signals
Motorola Mode
Host Interface SINTR/SIRQ
SYSTEM_INTERRUPT (SIFSTS register)
Request
SHRQ/SBRQ
Grant
SHLDA/SBGR
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DMADIR SWHLDA SWDDIR SWHRQ PSDMAEN SINTEN
SDDIR
SIFACL Register
Figure Pseudo-DMA Logic Related SIFACL Bits
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (see Note Input voltage range (see Note Output voltage range Power dissipation Operating free-air temperature range, 70°C Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE Voltage values with respect VSS.
recommended operating conditions
Supply voltage Supply voltage (see Note TTL-level signal High-level input voltage Low-level input voltage, TTL-level signal (see Note High-level output current Low-level output current (see Note Operating free-air temperature OSCIN RCLK, PXTALIN, RCVR 4.75 5.25 UNIT
Operating case temperature NOTES: pins should routed minimize inductance system ground. algebraic convention, where more negative (less positive) limit designated minimum, used logic-voltage levels only. Output current sufficient drive five low-power Schottky loads advanced low-power Schottky loads (worst case).
electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted)
PARAMETER ISCM High-level output voltage, TTL-level signal (see Note Low-level output voltage, TTL-level signal High impedance output current High-impedance Input current, input input output Supply current Supply current, slow-clock mode Input capacitance, input TEST CONDITIONS MIN, MIN, MAX, MAX, Others UNIT
MHz,
Output capacitance, output input output MHz, Others conditions shown MAX, appropriate value specified under recommended operating conditions. NOTE following signals require external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS, EXTINT0 EXTINT3, MBRQ.
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timing parameters
timing parameters signals TI380C27 shown following tables illustrated accompanying figures. purpose these figures tables quantify timing relationships among various signals. parameters numbered convenience. static signals following table lists signals that allowed change dynamically therefore have timing associated with them. They should strapped high, low, left unconnected required.
SIGNAL SI/M CLKDIV BTSTRP PRTYEN TEST0 Reserved Default bootstrap mode (RAM/ROM) Default parity select (enabled/disabled) Test terminal indicates network type Test terminal indicates network type Test terminal indicates network type Test terminal manufacturing test Test terminal manufacturing test FUNCTION Host-processor select (Intel/Motorola)
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TEST1 TEST2 TEST3 TEST4
TEST5 Test terminal manufacturing test unit-in-place test
timing parameter symbology Some timing parameter symbols have been created accordance with JEDEC Standard 100-A. order shorten symbols, some signal names other related terminology have been abbreviated shown below:
DRVR DRVR OSCIN SBCLK SRESET VDDL,
Lower case subscripts defined follows:
cycle time delay time hold time pulse duration (width) rise time skew setup time transition time
following additional letters phrases defined follows:
High Valid Falling edge Rising edge High impedance longer high longer
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PARAMETER MEASUREMENT INFORMATION
Outputs driven minimum high-logic level maximum low-logic level These levels compatible with devices. Output transition times specified follows: high-to-low transition either input output signal, level which signal said longer high level which signal said low-to-high transition, level which signal said longer level which signal said high shown below. rise fall times specified assumed those standard devices, which typically
(high) (low)
test measurement
test-load circuit shown Figure represents programmable load tester electronics that used verify timing parameters TI380C27 output signals.
Tester Electronics Output Under Test
VLOAD
Where: VLOAD
dc-level verification (all outputs) (all outputs) typical dc-level verification typical timing verification typical load-circuit capacitance
Figure Test-Load Circuit
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power SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, SRESET timing
tr(VDD) td(VDDH-SCKV) td(VDDH-OSCV) tc(SCK) tw(SCKH) tw(SCKL) tt(SCK) tc(OSC) tw(OSCH) Rise time, minimum VDD-high level Delay time, minimum VDD-high level first valid SBCLK longer high Delay time, minimum VDD-high level first valid OSCIN high Cycle time, SBCLK (see Note Pulse duration, SBCLK high Pulse duration, SBCLK Transition time, SBCLK Cycle time, OSCIN (see Note OSCIN Pulse duration, OSCIN high (see Note OSCIN OSCIN OSCIN tw(OSCL) tt(OSC) td(OSCV-CKV) th(VDDH-RSL) tw(RSH) tw(RSL) tsu(RST) th(RST) Pulse duration, OSCIN (see Note Transition time, OSCIN Delay time, OSCIN valid MBCLK1 MBCLK2 valid Hold time, SRESET after reaches minimum high level Pulse duration, SRESET high Pulse duration, SRESET Setup time, size SRESET high (Intel mode only) Hold time, size from SRESET high (Intel mode only) eighth local memory cycle One-eighth CLKDIV CLKDIV 2tc(OSC) tc(OSC) OSCIN OSCIN 1/OSCIN 30.3 UNIT
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This specification provided board design. assured during manufacturing testing. parameter cannot met, parameter must extended larger difference: real value parameter minus value listed. NOTES: SBCLK value between MHz. This data sheet describes system interface timing parameters case SBCLK MHz. value OSCIN OSCIN used generate PXTALIN, OSCIN tolerance must 0.01%. This assure duty-cycle crystal, provided that OSCIN meets recommended operating conditions
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SBCLK OSCIN MBCLK1 MBCLK2 Minimum VDD-High Level
SRESET S8/SHALT
NOTE order represent information illustration, nonactual phase timebase characteristics shown. Refer specified parameters precise information.
Figure Timing Power System Clocks, SYNCIN, SRESET
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memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Period MBCLK1 MBCLK2 Pulse duration, clock high Pulse duration, clock Hold time, MBCLK2 after MBCLK1 high Hold time, MBCLK1 high after MBCLK2 high Hold time, MBCLK2 high after MBCLK1 Hold time, MBCLK1 after MBCLK2 Setup time, address/enable MAX0, MAX2, MROMEN before MBCLK1 longer high Setup time, address MADL0 MADL7, MAXPH, MAXPL before MBCLK1 longer high Setup time, address MADH0 MADH7 before MBCLK1 longer high Setup time, high before MBCLK1 longer high Setup time, address MAX0, MAX2, MROMEN before MBCLK1 longer Setup time, column address MADL0 MADL7, MAXPH, MAXPL before MBCLK1 longer Setup time, status MADH0 MADH7 before MBCLK1 longer Setup time, valid before MBCLK1 Hold time, valid after MBCLK1 Delay time, MBCLK1 longer MRESET valid Hold time, column address/status after MBCLK1 longer Reference Periods Periods Periods 0.5tM 0.5tM 0.5tM Periods UNIT Periods
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OSCIN (when CLKDIV OSCIN (when CLKDIV
OSCOUT
MBCLK1 Note MBCLK2 Note NOTE MBCLK1 MBCLK2 have timing relationship OSCOUT. MBCLK1 MBCLK2 start OSCIN rising edge, depending when memory cycle starts execution.
Figure Clock Waveforms After Clock Stabilization
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MBCLK1 MBCLK2 MAX0, MAX2, MROMEN MAXPH, MAXPL, MADL0 MADL7 ADD/EN Address
MADH0 MADH7 Address
Status
Valid
MRESET
Valid
Figure Memory-Bus Timing: Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
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memory-bus timing: clocks, MRAS, MCAS, ADDRESS
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, address MADL0 MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0 MADL7, MAXPH, MAXPL after MRAS longer high Delay time, MRAS longer high MRAS longer high next memory cycle Pulse duration, MRAS Pulse duration, MRAS high Setup time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) before MCAS longer high Hold time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) after MCAS Hold time, column address (MADL0 MADL7, MAXPH, MAXPL) status (MADH0 MADH7) after MRAS longer high Pulse duration, MCAS Pulse duration, MCAS high, refresh cycle follows read write cycle Hold time, address MAXL0 MAXL7, MAXPH, MAXPL after Setup time, address MAXL0 MAXL7, MAXPH, MAXPL before longer high Pulse duration, high Setup time, address/enable MAX0, MAX2, MROMEN before longer high Hold time, address/enable MAX0, MAX2, MROMEN after Setup time, address MADH0 MADH7 before longer high Hold time, address MADH0 MADH7 after 1.5tM 11.5 4.5tM 3.5tM 0.5tM 2.5tM 1.5tM 1.5tM 1.5tM UNIT
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MAXPH, MAXPL, MADL0 MADL7
Column
Column
MRAS
MCAS MAX0, MAX2, MROMEN MADH0 MADH7 Address Status ADD/EN
Address
Status
Figure Memory-Bus Timing: Clocks, MRAS, MCAS, ADDRESS
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Address
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
memory-bus timing: read cycle
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Access time, address enable valid MAX0, MAX2, MROMEN valid data /parity Access time, address valid MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 valid data parity Access time, MRAS valid data parity Hold time, valid data parity after MRAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7 MADL0 MADL7 after MRAS high (see Note Access time, MCAS valid data parity Hold time, valid data parity after MCAS longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MCAS high (see Note Delay time, MCAS longer high Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7 before longer high Access time, valid data parity Pulse duration, Delay time, MCAS longer Hold time, valid data parity after longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after high (see Note Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7, before MBEN longer high Setup time, address status high-impedance state MAXPH, MAXPL, MADL0 MADL7, MADH0 MADH7 before MBIAEN longer high Access time, MBEN valid data parity Access time, MBIAEN valid data parity Pulse duration, MBEN Pulse duration, MBIAEN Hold time, valid data parity after MBEN longer Hold time, valid data parity after MBIAEN longer Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MBEN high (see Note Hold time, address high-impedance state MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 after MBIAEN high Hold time, MDDIR high after MBEN high, read follows write cycle Setup time, MDDIR before MBEN longer high 1.5tM 10.5 4.5tM 21.5 UNIT
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Hold time, MDDIR after MBEN high, write follows read cycle This specification been characterized meet stated value. assured during manufacturing testing. NOTE data parity that exists address lines will most likely reach high-impedance state sometime later than rising edge MRAS, MCAS, MOE, MBEN (between timing parameter will function memory being read. time given represents time from rising edge MRAS, MCAS, MOE, MBEN beginning next address, does represent actual high-impedance period address bus.
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MAX0, MAX2, MROMEN
Address Enable
Address Data Parity Address
MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7
Address
Address Status
MRAS
MCAS MBIAEN MDDIR MBEN
Figure Memory-Bus Timing: Read Cycle
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memory-bus timing: write cycle
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, before MRAS longer Setup time, before MCAS longer Setup time, valid data parity before longer high Pulse duration, Hold time, data parity valid after high Setup time, address valid MAX0, MAX2, MROMEN before longer Hold time, MRAS longer Hold time, MCAS longer Setup time, MBEN before longer high Hold time, MBEN after high Setup time, MDDIR high before MBEN longer high Hold time, MDDIR high after MBEN high MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0 MADH7, MADL0 MADL7 1.5tM 2.5tM 0.5tM 10.5 -11.5 5.5tM -11.5 1.5tM 13.5 0.5tM 1.5tM UNIT
ADVANCE INFORMATION
Address Enable
Address
Address
Data Parity
MRAS
MCAS MBEN MDDIR
Figure Memory-Bus Timing: Write Cycle
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memory-bus timing: DRAM-refresh timing
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Setup time, address MADL0 MADL7, MAXPH, MAXPL before MRAS longer high Hold time, address MADL0 MADL7, MAXPH, MAXPL after MRAS longer high Pulse duration, MRAS Pulse duration, MRAS high Setup time, MCAS before MRAS longer high Hold time, MCAS after MRAS Setup time, MREF high before MCAS longer high Hold time, MREF high after MCAS high 1.5tM 11.5 4.5tM 3.5tM 1.5tM -11.5 4.5tM UNIT
Address
MRAS MCAS MREF
Figure Memory Timing: DRAM-Refresh Cycle
XMATCH XFAIL timing
cycle time one-eighth local memory cycle (31.25 minimum 4-MHz local 20.83 minimum 6-MHz local bus).
Delay time, status high XMATCH XFAIL recognized Pulse duration, XMATCH XFAIL high UNIT
MADH7
Status
XMATCH, XFAIL
Figure XMATCH XFAIL Timing
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MADL0 MADL7
Refresh Address
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
token ring: ring-interface timing
154L 154H 158L 158H Period RCLK (see Note Pulse duration RCLK duration, Pulse duration, RCLK high duration 4Mbps Mbps Mbps nominal: 62.5 Mbps nominal: 15.625 Mbps nominal: 62.5 Mbps nominal: 15.625 31.25 0.01 31.25 UNIT
Setup time, RCVR valid before rising edge (1.8 RCLK Mbps Hold time, RCVR valid after rising edge (1.8 RCLK Mbps Pulse duration, ring baud clock duration Pulse duration, ring baud clock high duration Period OSCOUT PXTALIN (see Note Tolerance PXTALIN input frequency (see Note Mbps Mbps Mbps Mbps Mbps Mbps (for PXTALIN only)
ADVANCE INFORMATION
NOTE This parameter tested required IEEE 802.5 specification. 154H
RCLK 154L RCVR Valid
158H 158L OSCOUT, PXTALIN
Figure Ring-Interface Timing
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token ring: transmitter timing
tsk(DR) td(DR)H td(DR)L td(DRN)H t(DRN)L DRVR DRVR asymmetry Delay from DRVR rising edge (1.8 DRVR falling edge DRVR falling edge DRVR rising edge (1.8 Delay from RCLK PXTALIN) falling edge DRVR rising edge (1.8 Delay from RCLK PXTALIN) falling edge DRVR falling edge Delay from RCLK PXTALIN) falling edge DRVR falling edge Delay from RCLK PXTALIN) falling edge DRVR rising edge (1.8 d(DR)L Note Note Note Note ±1.5 UNIT
d(DRN)H
d(DR)H
d(DRN)L
When active-monitor mode, clock source PXTALIN; otherwise, clock-source either RCLK PXTALIN. NOTE This parameter tested minimum maximum measured used component required parameter 164.
RCLK PXTALIN
DRVR DRVR
Figure Skew Asymmetry From RCLK PXTALIN DRVR DRVR
ethernet timing clock signals
CLKPHS CLKPER Pulse duration, Cycle time, 1000 UNIT
Figure Ethernet Timing
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
ethernet timing XMIT signals:
tXDHLD tXDVLD Hold time, after high Delay time, high valid high TXEN high UNIT
0.45 TXEN 0.45
ADVANCE INFORMATION
Figure Ethernet Timing XMIT Signals:
ethernet timing signals: start frame
RXDSET RXDHLD CRSSET SAMDLY RXCHI RXCL0 Setup time, before longer Hold time, after high Setup time, high before longer first valid data sample Delay time, internally recognized first valid data sample (see Notes Pulse duration, high Pulse duration, UNIT clock cycles
NOTES: valid frame synchronization, following data sequences must received. other pattern delays frame synchronization until after next rising edge. followed occurrences followed where integer example, data sequence 010101011. followed occurrences followed where integer example, data sequence 1010101011. previous frame frame fragment completed without extra clock cycles (XTRCVC SAMDLY clock cycles.
Figure Ethernet Timing Signals: Start Frame
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
ethernet timing signals: frame
CRSSET CRSHLD XTRCYC Setup time, before longer determine last data seen previous longer (see Note Hold time, after longer determine last data seen previous longer Number extra clock cycles after last data (CRS low) (see Note UNIT cycle
NOTE TI380C27 operates correctly even with extra clock cycles, provided that does remain asserted longer than (see timing spec NORXC). Provided extra clocks affect receive-startup timing, timing spec SAMDLY.
Last Data
Figure Ethernet Timing Signals: Frame
ethernet timing signals:
NORXC Time with clock pulse RXC, when high (see Note NOTE NORXC exceeded, local-clock-failure circuitry become activated, resetting device. UNIT
(high)
Figure Ethernet Timing Signals:
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
ethernet timing XMIT signals: COLL
HBWIN COLPUL COLSET Delay time from high last transmitted data TXEN high) COLL sampled high, generate heart-beat error Minimum pulse duration COLL high assured sample Setup COLL high high cycle UNIT cycles
COLL
ADVANCE INFORMATION
TXEN
Figure Ethernet Timing XMIT Signals: COLL
ethernet timing XMIT signals:
JAMTIM COLSET COLPUL Time from COLL sampled high (TXC high) first transmitted (see Note Setup time, COLL high before high Pulse duration, COLL high assured sample, minimum cycle UNIT cycles
NOTE pattern delayed until after completion preamble pattern. TI380C27 transmits pattern
Data
Data
Data
COLL
Figure Ethernet Timing XMIT Signals:
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80x8x read-cycle timing
261a 266a 272a 273a 282a 282R 283R Delay time, SRDY either high Pulse duration, SRAS high Hold time, high-impedance state after (see Note Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SRDY Delay time, high high-impedance state (see Note Hold time, output data valid after high (see Note Setup time, SRSX, SRS0 SRS2, SCS, SBHE valid SRAS longer high (see Note Hold time, SRSX, SRS0 SRS2, SCS, SBHE valid after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0 SRS2 valid before longer high (see Note Hold time, SRSX, SRS0 SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SWR, high SRDY high (see Note Delay time, SWR, high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed Delay time, high SDBEN high (see Note Pulse duration, high between accesses (see Note tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) tc(SCK) tc(SCK) tc(SCK) 33-MHz OPERATION UNIT
tc(SCK) tc(SCK) tc(SCK) tc(SCK) This specification provided board design. assured during manufacturing testing. later that indicates start cycle. NOTES: inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SCS, SRSX, SRS0 SRS2, SBHE SRAS
Valid
Valid (see Note
266a SIACK
272a 273a
272a
273a
273a 272a High 282R 283R
ADVANCE INFORMATION
SDDIR
SDBEN 282a SRDY (see Note SADH0 SADH7, SADL0 SADL7, SPH, (see Note Hi-Z Hi-Z Output Data Valid 261a Hi-Z Hi-Z
NOTES: 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met. When TI380C27 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x mode reads, SADH0 SADH7 contain don't care data.
Figure 80x8x Read-Cycle Timing
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80x8x write-cycle timing
266a 272a 273a Delay time, SRDY either high Pulse duration, SRAS high Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before longer Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after high Setup time, SRSX, SRS0 SRS2, SCS, SBHE SRAS longer high (see Note Hold time, SRSX, SRS0 SRS2, SCS, SBHE after SRAS Setup time, SRAS high longer high (see Note Setup time, SRSX, SRS0 SRS2 before longer high (see Note Hold time, SRSX, SRS0 SRS2 valid after longer (see Note Setup time, SRD, SWR, SIACK high from previous cycle longer high Hold time, SRD, SWR, SIACK high after high Delay time, SRDY first access register SRDY immediately following access (see TMS380 Second-Generation Token Ring User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, high SRDY high (see Note Delay time, high SRDY high-impedance state Delay time, SDDIR (see Note Delay time, SDBEN SRDY (see TMS380 Second Generation Token Ring Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, high SDBEN longer Pulse duration high between accesses (see Note register ready waiting required) register ready (waiting required) 25-MHz OPERATION tc(SCK) tc(SCK) 4000 33-MHz OPERATION tc(SCK) tc(SCK) 4000 UNIT
tc(SCK) tc(SCK) tc(SCK)
tc(SCK) tc(SCK) tc(SCK)
282b
4000 tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)
282W 283W
tc(SCK) tc(SCK) later that indicates start cycle. This specification been characterized meet stated value. assured during manufacturing testing. This specification provided board design. assured during manufacturing testing. NOTES: inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SCS, SRSX, SRS0 SRS2, SBHE
Valid
SRAS
SIACK
266a 272a 273a
272a
273a 273a
272a
ADVANCE INFORMATION
SDDIR 282W SDBEN (see Note SRDY Hi-Z 282b SADH0 SADH7, SADL0 SADL7, SPH, (see Note Hi-Z Data Hi-Z Hi-Z 283W
NOTES: When TI380C27 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. 8-bit 80x8x-mode writes, value placed SADH0 SADH7 don't care.
Figure 80x8x Write-Cycle Timing
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80x8x interrupt-acknowledge-cycle timing: first SIACK pulse
Pulse duration, SIACK high between accesses (see Note Pulse duration, SIACK first pulse pulses 25-MHz OPERATION tc(SCK) tc(SCK) 33-MHz OPERATION tc(SCK) tc(SCK) UNIT
NOTE inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles. SRD, SWR, SIACK First Second
Figure 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse
80x8x interrupt-acknowledge-cycle timing: second SIACK pulse
261a 272a 273a 282a 282R Delay time, SRDY high Hold time, high-impedance state after SIACK (see Note Setup time, output data valid before SRDY Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK high (see Note Setup time, inactive data strobe high SIACK longer high Hold time, inactive data strobe high after SIACK high Delay time, SIACK high SRDY high (see Note Delay time, SRDY first access register SRDY immediately following access Delay time, SIACK high SRDY high-impedance state Delay time, SDBEN SRDY read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 33-MHz OPERATION UNIT
283R Delay time, SIACK high SDBEN high (see Note tc(SCK) tc(SCK) This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. NOTE inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SCS, SRSX, SRS0 SRS2, SBHE
Only needs inactive. others don't care.
SIACK 272a 272a 272a SDDIR High 282R 283R SDBEN SRDY (see Note 282a Hi-Z SADH0 SADH7, SADL0 SADL7, SPH, (see Note 261a Output Data Valid Hi-Z Hi-Z 273a 273a 273a
ADVANCE INFORMATION
Hi-Z
NOTES: SRDY active-low ready signal. must asserted before data output. 8-bit 80x8x mode writes, value placed SADH0 SADH7 don't care.
Figure 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse
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80x8x-mode bus-arbitration timing, takes control
Setup time, asynchronous signal SBBSY SHLDA before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SBBSY SHLDA after SBCLK assure recognition that cycle Delay time, SBCLK SADH0 SADH7, SADL0 SADL7, SPH, valid Delay time, SBCLK cycle SOWN Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high SHRQ high Delay time, SBCLK high cycle high, acquisition Hold time, high-impedance state after SOWN low, acquisition tc(SCK) 25-MHz OPERATION 208a 208b 224a 224c 241a tc(SCK) 33-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
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User Master Inputs: SBCLK 208a SBBSY, SHLDA Outputs: SHRQ (T4)
SRD, 241a SBHE SADH0 SADH7, SADL0 SADL7, SPH, Address Valid 224c Write SDDIR Read 224a SOWN (see Note NOTE While system-interface controls active (i.e., SOWN asserted), disabled.
Figure 80x8x-Mode Bus-Arbitration Timing, Takes Control
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Exchange
Master
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208b
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
80x8x-mode read-cycle timing
Setup time, SADL0 SADL7, SADH0 SADH7, SPH, valid before SBCLK cycle longer high Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after SBCLK cycle parameters 207a 207b Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after high Hold time, SADL0 SADL7, SADH0 SADH7, SPH, valid after SDBEN longer Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition this cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after SALE SXAL Delay time, SBCLK cycle high (see Note Delay time, SBCLK cycle SDBEN high Delay time, SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state Delay time, SBCLK cycle Hold time, SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state after SBCLK cycle Pulse duration, Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cyle SDBEN Setup time, data valid before SRDY parameter 208a 2tc(SCK) tw(SCKH) tc(SCK) 2tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
207a 207b
208a
216a 223R 225R 227R 237R
tw(SCKH)
tc(SCK)
This specification been characterized meet stated value. assured during manufacturing testing. NOTE While system-interface controls active (i.e., SOWN asserted), disabled.
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208b
SBCLK
SRAS SBHE (see Note (see Note
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SXAL
SALE SADH0 SADH7, SADL0 SADL7, SPH, (see Note Address Extended Address 208a (see Note SRDY 208b 225R 207b Data 207a Address
SDBEN (see Note SDDIR
NOTES: 8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. Motorola-style slaves hold SDTACK active until master deasserts SAS. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter i.e., held after high. parameter 208a met, valid data must present before SRDY goes low.
Figure 80x8x-Mode Read-Cycle Timing
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
TWAIT
Hi-Z
Valid High 227R 223R
216a
237R
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
80x8x-mode write-cycle timing
Setup time, asynchronous signal SRDY before SBCLK longer high assure recognition that cycle Hold time, asynchronous signal SRDY after SBCLK assure recognition that cycle Delay time, SBCLK SADH0 SADH7, SADL0 SADL7, SPH, valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, SADH0 SADH7, SADL0 SADL7, SPH, valid after high Delay time, SBCLK high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SWR, SUDS, SLDS high Delay time, SBCLK cycle Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SALE, SXAL longer high Delay time, SBCLK high cycle SDBEN tc(SCK) tc(SCK) tc(SCK) tw(SCKH) tc(SCK) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
208a
208b 216a 223W 225W 225WH 227W 237W
tw(SCKH) tc(SCK)
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SBCLK
SBHE (see Note High 227W
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SXAL 216a SALE SADL0 SADH7, SADH0 SADL7, SPH, (see Note SRDY 237W SDBEN 208b 225WH 225W Address Extended Address 208a Output Data
SDDIR
NOTES: 8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter i.e., held after high.
Figure 80x8x-Mode Write-Cycle Timing
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
TWAIT
High
Valid
223W
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
80x8x-mode bus-arbitration timing, returns control
Delay time, SBCLK cycle SADH0 SADH7, SADL0 SADL7, SPL, SPH, SRD, high-impedance state Delay time, SBCLK cycle SBHE high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high cycle SHRQ Setup time, SRD, SWR, SBHE high-impedance state before SOWN longer 25-MHz OPERATION 223b 224b 224d 33-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
Master SBCLK
Exchange (T1)
User Master (T2)
SHLDA Outputs: SHRQ (see Note SRD, 223b SBHE SADH0 SADH7, SADL0 SADL7, SPH, SDDIR Read 224b SOWN (see Note NOTES: 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. While system-interface controls active (i.e., SOWN asserted), disabled. 224d Write Hi-Z Hi-Z Hi-Z
Figure 80x8x-Mode Bus-Arbitration Timing, Returns Control
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
80x8x-mode bus-release timing
Setup time, asynchronous input SBRLS before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS after SBCLK assure recognition Hold time, SBRLS after SOWN high SBCLK 208a SBRLS (see Note 208b 25-MHz OPERATION 208a 208b 208c 33-MHz OPERATION UNIT
ADVANCE INFORMATION
SOWN 208c NOTES: system interface ignores assertion SBRLS does system bus. does when detects assertion SBRLS, completes internally started cycle relinquishes control bus. transfer internally started, system interface releases before starting another. SBERR asserted when system interface controls system bus, current transfer completed regardless value SRDY. BERETRY register zero, cycle retried. BERETRY register zero, system interface releases control system bus. system interface ignores assertion SBERR performing cycle system bus. When SBERR properly asserted BERETRY zero, however, system interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX, SDMALEN registers system interface defined after system-bus error. cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits. SDTACK sampled verify that deasserted. Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition.
Figure 80x8x-Mode Bus-Release Timing
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68xxx read-cycle timing
Delay time, SDTACK either SCS, SUDS, SLDS high Hold time, high-impedance state after SUDS SLDS (see Note Setup time, SADH0 SADH7, SADL0 SADL7, SPH, valid before SDTACK Delay time, SCS, SUDS, SLDS high SADH0 SADH7, SADL0 SADL7, SPH, high-impedance state (see Note Hold time, output data valid after SUDS SLDS longer (see Note Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Hold time, SRNW after SUDS SLDS high Hold time, SIACK high after SUDS SLDS high Delay time, SCS, SUDS, SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SDBEN SDTACK Delay time, SUDS SLDS SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) provided previous cycle completed Delay time, SUDS SLDS high SDBEN high (see Note Pulse duration, SUDS SLDS high between accesses (see Note tc(SCK) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
261a 273a 282a 282R 283R
tc(SCK)
4000
4000
tc(SCK) tc(SCK) tc(SCK) tc(SCK)
tc(SCK)
tc(SCK) tc(SCK) tc(SCK) tc(SCK)
This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. NOTES: inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SCS, SRSX, SRS0, SRS1 SIACK
Valid
273a SRNW SUDS, SLDS SDDIR High 282R 283R SDBEN SDTACK (see Note Hi-Z 282a SADH0 SADH7, SADL0 SADL7, SPH, Hi-Z 261a Output Data Valid Hi-Z Hi-Z
ADVANCE INFORMATION
NOTE SDTACK active-low ready signal. must asserted before data output.
Figure 68xxx Read-Cycle Timing
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68xxx write-cycle timing
272a 273a Delay time, SDTACK either SCS, SUDS SLDS high Setup time, write data valid before SUDS SLDS longer Hold time, write data valid after SUDS SLDS high Setup time, register address before SUDS SLDS longer high (see Note Hold time, register address valid after SUDS SLDS longer (see Note Setup time, SRNW before SUDS SLDS longer high (see Note Setup time, inactive SUDS SLDS high active data strobe longer high Hold time, SRNW after SUDS SLDS high Hold time, inactive SUDS SLDS high after active data strobe high Delay time, SCS, SUDS SLDS high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SUDS SLDS high SDTACK high-impedance state Delay time, SUDS SLDS SDDIR (see Note Delay time, SDBEN SDTACK (see TMS380 Second Generation TokenRing User's Guide, SPWU005, subsection 3.4.1.1.1) Delay time, SDDIR SDBEN Delay time, SUDS SLDS high SDBEN longer Pulse duration, SUDS SLDS high between accesses (see Note register ready waiting required) register ready (waiting required) 25-MHz OPERATION tc(SCK) tc(SCK) 33-MHz OPERATION tc(SCK) tc(SCK) UNIT
4000
4000
tc(SCK) tc(SCK) tc(SCK)
tc(SCK) tc(SCK) tc(SCK)
282b
tc(SCK) 4000 tc(SCK) tc(SCK) tc(SCK) 4000 tc(SCK) tc(SCK)
282W 283W
This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. later that indicates start cycle. NOTES: inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0 SRS2, must meet parameter 264. SRAS strapped high, parameters 266a irrelevant parameter must met.
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SRSX, SRS0, SRS1 SIACK SRNW 272a SUDS, SLDS (see Note SDDIR High
Valid
273a
273a
ADVANCE INFORMATION
282W SDBEN (see Note SDTACK (see Note Hi-Z 282b SADH0 SADH7, SADL0 SADL7, SPH, Hi-Z
283W
Hi-Z Data Note Hi-Z
NOTES: 68xxx mode, skew between SLDS SUDS must exceed Provided this limitation observed, events referenced data-strobe edge later occurring edge. Events defined data strobes edges, such parameter 286, measured between latest earlier edges. When TI380C27 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. SDTACK active-low ready signal. must asserted before data output.
Figure 68xxx Write-Cycle Timing
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx interrupt-acknowledge-cycle timing
261a 272a 273a 282a 282R 283R Delay time, SDTACK either SUDS, SIACK high Hold time, high-impedance state after SIACK longer high (see Note Setup time, output data valid before SDTACK longer high Delay time, SIACK high high-impedance state (see Note Hold time, output data valid after SIACK longer (see Note Setup time, register address before SIACK longer high (see Note Setup time, inactive high SIACK active data strobe longer high Hold time, inactive SRNW high after active data strobe high Delay time, SRNW high SDTACK high (see Note Delay time, SDTACK first access register SDTACK immediately following access Delay time, SIACK high SDTACK high-impedance state Delay time, SDBEN SDTACK read cycle Delay time, SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) provided previous cycle completed Delay time, SIACK high SDBEN high (see Note Pulse duration, SIACK high between accesses (see Note tc(SCK) tc(SCK) 25-MHz OPERATION tc(SCK) tc(SCK) 33-MHz OPERATION UNIT 4000 tc(SCK) tc(SCK) tc(SCK)
4000 tc(SCK) tc(SCK) tc(SCK)
tc(SCK) tc(SCK) tc(SCK) tc(SCK) This specification provided board design. assured during manufacturing testing. This specification been characterized meet stated value. assured during manufacturing testing. later that indicates start cycle. NOTE inactive chip select SIACK read write cycles, inactive chip select interrupt-acknowledge cycles.
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ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SCS, SRSX, SRS0, SRS1, SBHE
Only needs Inactive. others don't care.
SIACK 272a SRNW 273a SLDS SDDIR High 282R 283R SDBEN 282a SDTACK (see Note SADH0 SADH7, SADL0 SADL7, SPH, (see Note Hi-Z 261a Hi-Z Output Data Valid Hi-Z Hi-Z
ADVANCE INFORMATION
NOTES: SDTACK active-low ready signal. must asserted before data output. Internal logic drives SDTACK high verifies that reached valid high level before making 3-state signal.
Figure 68xxx Interrupt-Acknowledge-Cycle Timing
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx-mode bus-arbitration timing, takes control
Setup time, asynchronous input SBGR before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SBGR after SBCLK assure recognition this cycle Delay time, SBCLK address valid Delay time, SBCLK cycle SOWN (see Note Delay time, SBCLK cycle SDDIR read Delay time, SBCLK high either SHRQ SBRQ high Delay time, SBCLK high cycle SUDS SLDS high Hold time, SUDS, SLDS, SRNW, high-impedance state after SOWN low, acquisition tc(SCK) 25-MHz OPERATION 208a 208b 224a 224c 241a tc(SCK) 33-MHz OPERATION UNIT
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ADVANCE INFORMATION
This specification been characterized meet stated value. assured during manufacturing testing. NOTE Motorola-style slaves hold SDTACK active until master deasserts SAS.
User Master Inputs: SBCLK (T4)
SBGR
SBERR, SDTACK, SBBSY Outputs: SBRQ (see Note 208a SAS, SLDS, SUDS 208b Input Read SRNW Write SADH0 SADH7, SADL0 SADL7, SPH, Hi-Z 224c Write SDDIR Read 224a SOWN (see Note 241a Output
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NOTES: 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. While system interface controls active (i.e., SOWN asserted), input disabled.
Figure 68xxx-Mode Bus-Arbitration Timing, Takes Control
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Exchange
Master
208b 208a
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx-mode read-cycle timing
207a 207b 208a Setup time, input data valid before SBCLK cycle longer high Hold time, input data valid after SBCLK cycle parameters 207a 207b Hold time, input data valid after data strobe longer Hold time, input data valid after SDBEN longer Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, SBCLK address valid Delay time, SBCLK cycle high-impedance state Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK high Delay time, SBCLK cycle SUDS, SLDS, high (see Note Delay time, SBCLK cycle SDBEN high Hold time, high-impedance state after SBCLK cycle Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN Setup time, data valid before SDTACK parameter 208a tw(SCKL) tw(SCKH) tc(SCK) tw(SCKL) 25-MHz OPERATION 33-MHz OPERATION UNIT
208b 216a 223R 225R 233a 237R
tc(SCK)+ tw(SCKL)
tc(SCK)+ tw(SCKL) tw(SCKH) tc(SCK)
This specification been characterized meet stated value. assured during manufacturing testing. NOTE While system-interface controls active (i.e., SOWN asserted), disabled.
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ADVANCE INFORMATION
SBCLK (see Note SUDS, SLDS High SRNW SXAL SALE SADL0 SADH7, SADH0 SADL7, SPH, SDTACK (see Notes SDDIR 237R SDBEN (see Note NOTES: Motorola-style slaves hold SDTACK active until master deasserts SAS. pins should routed minimize inductance system ground. read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes longer active. parameter 208a met, valid data must present before SDTACK goes low. 225R Address Extended Address Note 208a 208b 233a 207a Data Hi-Z 207b 216a
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Figure 68xxx-Mode Read-Cycle Timing
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
TWAIT
223R
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx-mode write-cycle timing
Setup time, asynchronous input SDTACK before SBCLK longer high assure recognition this cycle Hold time, asynchronous input SDTACK after SBCLK assure recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay time, SBCLK high cycle SUDS SLDS active Delay time, output data valid SUDS SLDS longer high Delay time, SBCLK address valid Delay time, SBCLK high SALE SXAL high Hold time, SALE SXAL after SUDS high Delay time, SBCLK high SXAL cycle SALE cycle Hold time, address valid after SALE, SXAL Delay time, SBCLK cycle output data parity valid Hold time, output data, parity valid after SUDS SLDS high Delay time, SBCLK high Delay time, SBCLK SUDS, SLDS, high Delay time, SBCLK high cycle SDBEN high Hold time, SDBEN after SUDS SLDS high Setup time, address valid before SALE SXAL longer high Setup time, address valid before longer high Delay time, SBCLK high cycle SDBEN tc(SCK) tw(SCKL) tc(SCK) tc(SCK) tw(SCKL) tw(SCKH) tc(SCK) tc(SCK) tw(SCKL) tw(SCKH) tc(SCK) 25-MHz OPERATION 33-MHz OPERATION UNIT
208a
208b 211a 216a 223W 225W 225WH 233a 237W
tc(SCK)+ tw(SCKL)
tc(SCK)+ tw(SCKL) tw(SCKL)
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ADVANCE INFORMATION
SBCLK
233a SUDS, SLDS SRNW SXAL SALE SADL0 SADH7, SADH0 SADL7, SPL, Extended Address SDTACK (see Notes 208b Address Output Data 208a
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SDDIR SDBEN
NOTES: pins should routed minimize inductance system ground. read cycle, read strobe remains active until internal sample incoming data completed. Input data removed when either read strobe SDBEN becomes longer active.
Figure 68xxx-Mode Write-Cycle Timing
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
TWAIT
211a 237W
223W
216a
225W 225WH
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx-mode arbitration timing, returns control
Delay time, SBCLK cycle SAD, SPL, SPH, SUDS, SLDS high-impedance state, release Delay time, SBCLK cycle SBHE/SRNW high-impedance state Delay time, SBCLK cycle SOWN high Delay time, SBCLK cycle SDDIR high Delay time, SBCLK high either SHRQ SBRQ high Setup from, SUDS, SLDS, SRNW, control signals high-impedance state before SOWN longer 25-MHz OPERATION 223b 224b 224d 33-MHz OPERATION UNIT
This specification been characterized meet stated value. assured during manufacturing testing.
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ADVANCE INFORMATION
Master Inputs: SBCLK
SBGR
SDTACK Outputs: SBRQ (see Note SAS, SUDS, SLDS 223b Read SRNW Write SADH0 SADH7, SADL0 SADL7, SPH, 224d Write SDDIR Read 224b SOWN NOTE 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. Hi-Z Hi-Z
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Figure 68xxx-Mode Bus-Arbitration Timing, Returns Control
ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
Exchange
User
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
68xxx-mode bus-release error timing
208a 208b 208c Setup time, asynchronous input before SBCLK longer high assure recognition Hold time, asynchronous input SBRLS, SOWN, SBERR after SBCLK assure recognition Hold time, SBRLS after SOWN high Setup time, SBERR before SDTACK longer high parameter 208a 25-MHz OPERATION 33-MHz OPERATION UNIT
SBCLK 208a
SOWN 208a SBERR (see Note SDTACK
208b 208c
NOTES: system interface ignores assertion SBRLS does system bus. does when detects assertion SBRLS, completes internally started cycle relinquishes control bus. transfer internally started, system interface releases before starting another. SBERR asserted when system interface controls system bus, current transfer completed, regardless value SDTACK. BERETRY register nonzero, cycle retried. BERETRY register zero, system interface then releases control system bus. system interface ignores assertion SBERR performing cycle system bus. When SBERR properly asserted BERETRY zero, however, system interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX, SDMALEN registers system interface defined after system-bus error. cycle-steal mode, state present every system-bus transfer. burst mode, state present first transfer whenever increment address register carries beyond least significant bits. SDTACK sampled verify that deasserted. Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high impedance) until start that SBCLK transition.
Figure 68xxx-Mode Bus-Release Error Timing
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ADVANCE INFORMATION
SBRLS (see Note
208b
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
SBCLK
SDTACK
SBERR
SHALT NOTE Only relative placement edges SBCLK falling edge shown. Actual signal edge placement vary from waveforms shown.
Figure 68xxx-Mode Bus-Halt Retry, Normal Completion With Delayed Start
ADVANCE INFORMATION
SBCLK
SDTACK
SBERR
SHALT
SOWN NOTE Only relative placement edges SBCLK falling edge shown. Actual signal edge placement vary from waveforms shown.
Figure 68xxx-Mode Bus-Halt Retry, Rerun Cycle With Delayed Start
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TI380C27 DUAL-PROTOCOL COMMPROCESSOR
APPLICATION INFORMATION
Figure shows TI380C27 connected LEVEL LXT901universal Ethernet interface adapter. LXT901 provides active circuitry interfacing TI380C27 Base-T twisted-pair network.
Note Texas Instruments TI380C27 Dual-Protocol Comprocessor FRAQ WRAP TXEN PXTALIN RCLK RCVR REDY WFLT COLL NSRT LPBK 1N914 TEST0 NSELOUT0 LEDC Note AUTOSEL Remote Status Line Status Level LXT901 RJAB RCMPT PAUI LEDR LEDT/PDN LADL VCC1 RBISA VCC2 GND1 GND2 TPONB TPONA 37.5 37.5 Note TCLK RCLK BASE-T Twisted-Pair Network RJ45
CLKI
CLKO TPIN
TPIP
Programming Options
TPOPA TPOPB
Green
12.4 Note
NOTES: Half/full duplex selection controlled TI380C27 pins TEST0 NSELOUT0. NSELOUT0 (full duplex) NSELOUT0 (half duplex) half-duplex operation, diode 1N914 associate 10-k resistor needed: these components removed. Suitable transformers include Fil-Mag 23Z128, SM23Z128; Valor PT4069 ST7011; Pulse Engineering PE65994 PE65745; Belfuse S553-0716 A553-0716; Halo Electronics TD42-2006Q TD42-2006W1. RBIAS should located close isolated from other signals. Suitable crystals include MTRON MP-1 MP-2.
Figure Typical Schematic Full-Duplex Operation With TI380C27
LEVEL LTXT901 registered trademark LEVEL Communications, Inc.
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ADVANCE INFORMATION
TI380C27 DUAL-PROTOCOL COMMPROCESSOR
MECHANICAL DATA
PGE/S-PQFP-G144
0,27 0,17 0,50
PLASTIC QUAD FLATPACK
ADVANCE INFORMATION
0,127
17,50 20,10 19,90 22,10 21,90
1,45 1,35
0,05 Seating Plane 0,70 0,30
0°-7°
0,08 1,60
4040147/A-10/93 NOTES: linear dimensions millimeters. This drawing subject change without notice.
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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