IEEE 802.5 Token-Ring Network Compatible IEEE 802.3 Blue Book Ethernet
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TMS380C26 NETWORK COMMPROCESSOR
IEEE 802.5 Token-Ring Network Compatible IEEE 802.3 Blue Book Ethernet Network Compatible Software Compatible With TMS380C16 Configurable Network Type Speed: Selectable Host Software Control (Adapter Control Register) Selectable Network Front-End Readable from Host (Adapter Control Register) Token-Ring Features 4-Megabit-per-Second Data Rates Supports 18K-Byte Frame Size Mbps Operation Only) Supports Universal Local Network Addressing Early Token Release Option Mbps Operation Only) Compatible With TMS38054 Ethernet Features 10-Megabit-per-Second Data Rate Compatible With Most Ethernet Serial Network Interface Devices Full Duplex Ethernet Operation Allows Network Speed Self-test Expandable Local Subsystem Memory Space Megabytes Supports Multicast Addressing Network Group Addresses Through Hashing Glueless Interface DRAMs High-Performance 16-Bit Communications Protocol Processing Megabyte-per-Second High-Speed Master Interface
Low-Cost Host-Slave Interface Option 32-Bit Host Address Selectable Host System Options 80x8x 68xxx-Type Memory Organization 16-Bit Data 80x8x Buses Optional Parity Checking Dual-Port Direct Transfers Host Specification External Adapter-Bus Devices (SEADs) Supports External Hardware Interface User-Defined External Logic Enhanced Address Copy Option (EACO) Interface Supports External Address Checking Logic Bridging External Custom Applications Support Module High-Impedance In-Circuit Testing Built-in Real-Time Error Detection Bring-Up Self-Test Diagnostics With Loopback Automatic Frame Buffer Management Slow-Clock Low-Power Mode Single Supply 1-µm CMOS Technology Typical Latch-Up Immunity 25°C Protection Exceeds 2,000 132-Pin JEDEC Plastic Quad Flat Package Suffix) Operating Temperature Range
network commprocessor applications diagram
Subsystem Transmit Attached System TMS380C26 Token Ring Ethernet Physical Layer Circuitry Receive Memory Network
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1993, Texas Instruments Incorporated
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TMS380C26 NETWORK COMMPROCESSOR
pinout
assignments TMS380C26 (132-pin quad flat-pack) shown Figure
132-PIN QUAD FLAT PACK (TOP VIEW)
EXTINT0 EXTINT1 EXTINT2 EXTINT3 MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7 MAXPL MBGR MBGQ MAXPH MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 MBEN
VSS5 SADL2 SADL1 SADL0 SHRQ/SBRQ SBHE/SRNW SDBEN SOWN SRDY/SDTACK SRD/SUDS SADH7 SADH6 VSSC VDD6 VSS6 SADH5 SADH4 SADH3 SADH2 SADH1 SADH0 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 XFAIL XMATCH VDD1 VSSL
Figure TMS380C26 Pinout
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VDDL CLKDIV VSSC NSELOUT0 PRTYEN BTSTRP SIACK SRESET SRS1 SRS0 SRSX SBRLS SBBSY S8/SHALT SRS2/SBERR VDDL SI/M SINTR/SIRQ SHLDA/SBGR SDDIR SRAS/SAS SWR/SLDS VSSI SXAL SALE SBCLK SADL7 SADL6 SADL5 SADL4 SADL3 VDD5
VSSC MRAS MCAS MAX2 MAX0 MDDIR VDD2 SYNCIN OSCIN VSS2 MROMEN MACS MREF MBIAEN VDDL MRESET MBCLK2 MBCLK1 OSCOUT RCVR/RXD RCLK/RXC NSETOUT1 PXTALIN/TXC VSS1 WRAP/TXEN DRVR DRVR WFLT/COLL NSRT/LPBK FRAQ/TXD REDY/CRS
TMS380C26 NETWORK COMMPROCESSOR
description
TMS380C26 single-chip network communications processor (commprocessor) that supports token ring, Ethernet Local Area Networks (LANs). Either token ring data rates Mbps Mbps, Ethernet data rate Mbps, selected. flexible configuration scheme allows network type speed configured hardware software. This allows design subsystems which support both token ring Ethernet networks, electrically physically switched network front-end circuits. TMS380C26 conforms IEEE 802.5-1989 standards been verified completely IBMToken-Ring compatible. integrating essential control building blocks needed subsystem card into device, TMS380C26 ensure that this compatability maintained silicon. TMS380C26 conforms ISO/IEC 8802-3 (ANSI/IEEE 802.3) CSMA/CD standards, Ethernet "Blue Book" standard. high degree integration TMS380C26 makes virtual subsystem single chip. Protocol handling, host system interfacing, memory interfacing, communications processing provided through TMS380C26. complete subsystem design, only network interface hardware, local memory, minimal additional components such PALs crystal oscillators need added. TMS380C26 provides 32-bit system memory address reach with high-speed bus-master interface that supports rapid communications with host system. addition, TMS380C26 supports direct low-cost 8-bit pseudo-DMA interface that requires only chip select work directly 80x8x 8-bit slave interface. Finally, selectable 80x8x 68xxx-type host system memory organization design flexibility. TMS380C26 supports addressing Megabytes local memory. This expanded memory capacity improve subsystem performance minimizing frequency host subsystem communications allowing larger blocks information transferred time. support large local memory important applications that require large data transfers (such graphics data base transfers) heavily loaded networks where extra memory provide data buffers store data until processed host. proprietary used TMS380C26 allows protocol software downloaded into stored local memory space. moving protocols (such LLC) subsystem, overall system performance increased. This accomplished offloading processing from host system TMS380C26, which also reduce subsystem-to-host communications. other protocol software developed, greater differentiation products with enhanced system performance will possible. addition, TMS380C26 includes hardware counters that provide realtime error detection automatic frame buffer management. These counters control system retries, burst size, track host subsystem buffer status. Previously, these counters needed maintained software. integrating them into hardware, software overhead removed subsystem performance improved. TMS380C26 implements TI-patented Enhanced Address Copy Option (EACO) interface. This interface supports external address checking devices, such TMS380SRA Source Routing Accelerator. TMS380C26 128-word external space memory support external address-checker devices other hardware extensions TMS380 architecture. Hardware designed conformance with TI's Specification External Adapter-bus Devices (SEADs) registers into this external space post interrupts TMS380C26. major blocks TMS380C26 include Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), Adapter Support Function (ASF) shown Figure TMS380C26 available 132-pin JEDEC plastic quad flat pack rated from 70°C.
registered trademark International Business Machines Corporation.
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TMS380C26 NETWORK COMMPROCESSOR
block diagram signal descriptions
TMS380C26 interface host system, interface local memory, interface physical layer circuitry. rule thumb nomenclature descriptions that follow, names starting with letter attach host system names starting with letter attach local memory bus. Active-low signals have names with overbars, e.g., SCS.
SADH0 SADH7 SADL0 SADL7 SBRLS SINTR/SIRQ SDDIR SDBEN SALE SXAL SOWN SIACK SBCLK SRD/SUDS SWR/SLDS SRDY/SDTACK SI/M SHLDA/SBGR SBHE/SRNW SRAS/SAS S8/SHALT SRESET SRS0 SRS1 SRS2/SBERR SRSX SHRQ/SBRQ SBBSY BTSTRP PRTYEN NSELOUT0 NSELOUT1
System Interface (SIF)
Memory Interface (MIF)
MADH0 MADH7 MADL0 MADL7 MRAS MCAS MAXPH MAXPL MDDIR MAX0 MAX2 MRESET MROMEN MBEN MBRQ MBGR MACS MBIAEN MREF OSCIN OSCOUT MBCLK1 MBCLK2 SYNCIN CLKDIV EXTINT0 EXTINT3 TEST0 TEST5 XMATCH XFAIL
Control Control Control
DRAM Refresh Local Arbitrator Local Control Local Parity Check/ Generator
Clock Generator (CG)
Adapter Support Function (ASF) Communications Processor Interrupts Test Function
RCLK/RXC REDY/CRS WFLT/COLL RCVR/RXD PXTALIN/TXC
Protocol Handler (PH): Token Ring Ethernet Interface
FRAQ/TXD NSRT/LPBK WRAP/TXEN DRVR DRVR
Figure TMS380C26 COMMprocessor Block Diagram
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions
NAME DESCRIPTION Bootstrap. value this loaded into BOOT SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. This indicates whether chapters memory ROM. these chapters then TMS380C26 denied access local memory until CPHALT SIFACL register cleared. Chapters local memory RAM-based (see Note Chapters local memory ROM-based. Clock Divider Select. This must pulled high CLKDIV Indicates 64-MHz OSCIN (see Note Reserved.
BTSTRP
EXTINT0 EXTINT1 EXTINT2 EXTINT3 MACS MADH0 MADH1 MADH2 MADH3 MADH4 MADH5 MADH6 MADH7 MADL0 MADL1 MADL2 MADL3 MADL4 MADL5 MADL6 MADL7
Reserved; must pulled high (see Note
Reserved. Must tied (see Note Local memory Address, Data Status high byte. first quarter local memory cycle these lines carry address bits second quarter, they carry status bits; third fourth quarters, they carry data bits most significant MADH0 least significant MADH7. Memory Cycle Status D0-D7
Signal
AX4,A0-A6
D0-D7
Local Memory Address, Data Status byte. first quarter local memory cycle, these lines carry address bits A14; second quarter, they carry address bits third fourth quarters, they carry data bits most significant MADL0 least significant MADL7. Memory Cycle AX4,A0-A6
Signal
A7-A14
D8-D15
D8-D15
Memory Address Latch. This strobe signal sampling address start memory cycle; used SRAMs EPROMs. full 20-bit word address valid MAX0, MAXPH, MAX2, MAXPL, MADH0-MADH7, MADL0-MADL7. Three 8-bit transparent latches therefore used retain 20-bit static address throughout cycle. Rising edge signal latching. Falling edge Allows above address signals latched. Local Memory Extended Address Bit. This signal drives address time drives address DATA time cycles. This signal latched MRAS. Driving eases interfacing ROM. Memory Cycle
MAX0
Signal
MAX2
Local Memory Extended Address Bit. This signal drives address time, which latched MRAS, address, DATA time cycles. Driving eases interfacing ROM. Memory Cycle
Signal NOTES:
internal pullup device maintain high voltage level when left unconnected etch loads). should connected ground. should tied with 4.7-k pullup resistor. Each must individually tied with 1.0-k pullup resistor.
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued)
NAME DESCRIPTION Local Memory Extended Address Parity High Byte. first quarter memory cycle this signal carries extended address (AX1); second quarter memory cycle this signal carries extended address (AX0); last half memory cyle this signal carries parity high data byte. Memory Cycle Parity
MAXPH
Signal
Parity
MAXPL
Local Memory Extended Address Parity Byte. first quarter memory cycle this signal carries extended address (AX3), second quarter memory cycle this signal carries extended address (AX2); last half memory cycle this signal carries parity data byte. Memory Cycle Signal Parity Parity Local Clock1 local Clock These signals referenced local transfers. MBCLK2 lags MBCLK1 quarter cycle. These clocks operate 64-MHz OSCIN 48-MHz OSCIN, which twice memory cycle rate. MBCLK signals always divide-by-8 OSCIN frequency. Buffer Enable. This signal enables bidirectional buffer outputs MADH, MAXPH, MAXPL, MADL buses during data phase. This signal used conjunction with MDDIR which selects buffer output direction. Buffer output disabled. Buffer output enabled.
MBCLK1 MBCLK2
MBEN
MBGR
Reserved. Must left unconnected. Burned-In Address Enable. This output signal used provide output enable containing adapter's Burned-In Address (BIA).
MBIAEN
This signal driven high WRITE accesses addresses between >00.0000 >00.000F, accesses (Read/Write) other address. This signal driven READ from addresses between >00.0000 >00.000F. Reserved. Must pulled high (see Note Column Address Strobe DRAMs. column address valid 3/16 memory cycle following address portion cycle. This signal driven every memory cycle while column address valid MADL0-MADL7, MAXPH, MAXPL, except when following conditions occurs: When address accessed (>00.0000 >00.000F). When address accessed EPROM memory (i.e., when BOOT SIFACL register zero access made between >00.0010 >00.FFFF) >1F.0000 >1F.FFFF). When cycle refresh cycle, which case MCAS driven start cycle before MRAS (for DRAMs that have CAS-before-RAS refresh). DRAMs that support CASbefore-RAS refresh, necessary disable MCAS with MREF during refresh cycle.
MBRQ
MCAS
Data Direction. This signal used direction control bidirectional drivers. signal becomes valid before MBEN active. MDDIR TMS380C26 memory write. TMS380C26 memory read. NOTE Each must individually tied with 1.0-k pullup resistor.
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Terminal Functions (continued)
NAME DESCRIPTION Memory Output Enable. This signal used enable outputs DRAM memory during read cycle. This signal high EPROM read cycles. Disable DRAM outputs. Enable DRAM outputs. Address Strobe DRAMs. address lasts first 5/16 memory cycle. This signal driven every memory cycle while address valid MADL0-MADL7, MAXPH, MAXPL both cycles. also driven during refresh cycles when refresh address valid MADL0-MADL7. DRAM Refresh Cycle Progress. This signal used indicate that DRAM refresh cycle occurring. also used disabling MCAS DRAMs that before-RAS refresh. MREF DRAM refresh cycle process. DRAM refresh cycle. Memory Reset. This reset signal generated when either ARESET SIFACL register SRESET asserted. This signal used resetting external local glue logic. External logic reset. External logic reset. Enable. During first 5/16 memory cycle, this signal used provide chip select ROMs when BOOT SIFACL register zero (i.e., when code resident ROM, RAM). latched MAL. goes read from addresses >00.0010 >00.FFFF >1F.0000 >1F.FFFF when Boot SIFACL register zero. stays high writes these addresses, accesses other addresses, accesses address when BOOT one. During final three quarters memory cycle, outputs address signal interfacing ROM. This means MBIAEN, MAX0, ROMEN, MAX2 together form glueless interface ROM. disabled. enabled. Local Memory Write. This signal used specify write cycle local memory bus. data MADH0-MADH7 MADL0-MADL7 buses valid while low. DRAMs latch data falling edge while SRAMs latch data rising edge local memory write cycle. Local memory write cycle. OSCIN Non-Maskable Interrupt Request. This must left unconnected. External Oscillator Input. This line provides clock frequency TMS380C26 4-MHz internal bus. OSCIN should signal (see Note Oscillator Output. With OSCIN CLKDIV pulled high, this provides output which used TMS3054 Mbps operation without need additional crystal. OSCOUT CLKDIV OSCOUT Reserved OSCIN/8
MRAS
MRESET
MROMEN
(Reserved) OSCIN MHz, then OSCOUT MHz).
NOTE expanded input voltage specification.
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Terminal Functions (continued)
NAME DESCRIPTION Parity Enable. value this loaded into SIFACL register reset (i.e., when SRESET asserted ARESET SIFACL register set) form default value. This enables parity checking local memory. Local memory data checked parity (see Note Local memory data checked parity. Network Selection Outputs. These output signals controlled host through corresponding bits SIFACTL register. value these bits/signals only changed while TMS380C26 reset. NSELOUT0 NSELOUT1 NSELOUT0 NSELOUT1 Description Reserved Mbps token ring Ethernet (802.3/Blue Book) Mbps token ring
PRTYEN
NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
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Terminal Functions (continued)
System Interface Intel Mode (SI/M
NAME SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 DESCRIPTION System Address/Data Bus-high byte (see Note 1).These lines make most significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADH0, least significant SADH7. Address Multiplexing Bits bits Data Multiplexing Bits
System Address/Data Bus-low byte (see Note These lines make least significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADL0, least significant SADL7. Address Multiplexing Bits bits Data Multiplexing Bits System Address Latch Enable. This enable pulse used externally latch LSBs address from SADH0 SADH7 SADL0 SADL7 buses start cycle. Systems that implement address parity also externally latch parity bits (SPH SPL) latched address. System Busy. TMS380C26 samples value this during arbitration. sample values (see Note
SALE
SBBSY
busy. TMS380C26 become Master grant condition met. Busy. TMS380C26 cannot become Master.
SBCLK
System Clock. TMS380C26 requires external clock synchronize timings transfers. System Byte High Enable. This three-state output that driven during input other times.
SBHE/SRNW
System Byte High enabled (see Note System Byte High enabled. System Release. This indicates TMS380C26 that higher-priority device requires system bus. value this ignored when TMS380C26 perfoming DMA. This signal internally synchronized SBCLK.
SBRLS
TMS380C26 hold onto system (see Note TMS380C26 should release system upon completion current cycle. transfer complete, will rearbitrate system bus. System Chip Select. Activates system interface TMS380C26 read write.
selected (see Note Selected. System Data Enable. This output signals external data buffers begin driving data. This output activated during both DMA.
SDBEN
Keep external data buffers high-impedance state. Cause external data buffers begin driving data.
Typical ordering Intel Motorola processor buses. NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued)
System Interface Intel Mode (SI/M
NAME DESCRIPTION System Data Direction. This output provides external data buffers signal indicating direction which data moving. During writes reads, SDDIR (data direction input TMS380C26). During reads writes, SDDIR high (data direction output from TMS380C26). When system interface involved operation, then SDDIR high default. SDDIR DATA DIRECTION output input read write write read
SDDIR
SHLDA/SBGR
System Hold Acknowledge. This indicates that system hold request been acknowledged. internally synchronized SBCLK (see Note Hold request acknowledged. Hold request acknowledged. System Hold Request. This used request control system preparation transfer. This internally synchronized SBCLK.
SHRQ/SBRQ
System requested. System requested. System Interrupt Acknowledge. This signal from host processor acknowledge interrupt request from TMS380C26.
SIACK
System interrupt acknowledged (see Note System interrupt acknowledged: TMS380C26 places interrupt vector onto system bus. System Intel/Motorola Mode Select. value this specifies system interface mode.
SI/M
Intel-compatible interface mode selected. Intel interface 8-bit 16-bit mode (see S8/SHALT description Note Motorola-compatible interface mode selected. System Interrupt Request. TMS380C26 activates this output signal interrupt request host processor.
SINTR/SIRQ
Interrupt request TMS380C26. interrupt request. System Owned. This signal indicates external devices that TMS380C26 control system bus. This signal drives enable signal transceiver chips, which drive address control signals. TMS380C26 does have control system bus. TMS380C26 control system bus.
SOWN
System Parity High. optional odd-parity each address data byte transmitted over SADH0-SADH7 (see Note System Parity Low. optional odd-parity each address data byte transmitted over SADL0-SADL7 (see Note
NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued)
System Interface Intel Mode (SI/M
NAME DESCRIPTION System Memory Address Strobe (see Note This used latch SCS, SRSX SRS2 register input signals. minimum-chip system, SRAS tied SALE output System Bus. latching capability defeated since internal latch these inputs remains transparent long SRAS remains high. This permits SRAS pulled high signals SCS, SRSX SRS2, SBHE applied independently SALE strobe from system bus. During this remains input. High Falling edge transparent mode Holds latched values SCS, SRSX-SRS2, SBHE latches SCS, SRSX SRS2, SBHE
SRAS/SAS
System Read Strobe (see Note Active-low strobe indicating that read cycle performed system bus. This input during output during DMA. SRD/SUDS Read cyle occurring. DMA: host provides data system bus. DIO: provides data system bus. System Ready (see Note 3).The purpose this signal indicate master that data transfer complete. This signal asynchonous, during pseudo-DMA cycles internally synchronized SBCLK. During cycles, must asserted before falling edge SBCLK state order prevent wait state. This signal output when TMS380C26 selected DIO, input otherwise. System ready. Data transfer complete; system ready. System Reset. This input signal activated place TMS380C26 into known initial state. Hardware reset will most TMS380C26 output pins into high-impedance state place blocks into reset state. width selection latched rising edge SRESET. SRESET system reset. System reset. Rising edge Latch width operation. SRSX SRS0 SRS1 SRS2/SBERR System Register Select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS2 (see Note Registered selected SRSX SRS0 SRS1 SRS2/SBERR
SRDY/SDTACK
System Write Strobe (see Note This serves active-low write strobe. This input during output during DMA. SWR/SLDS Write cycle occurring. DMA: data drivien from host bus. DIO: rising edge, data latched written selected register. System Extended Address Latch. This output provides enable pulse used externally latch most significant bits 32-bit system address during DMA. SXAL activated prior first cycle each block transfer, thereafter necessary (whenever increment address counter causes carry-out lower bits). Systems that implement parity addresses SXAL externally latch parity bits (available SPH) address extension.
SXAL
NOTES: internal pullup device maintain high voltage level when left unconnected etch loads). should tied with 4.7-k pullup resistor.
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued)
System Interface Intel Mode (SI/M
NAME SYNCIN DESCRIPTION Reserved. This signal must left unconnected (see Note System 8/16-bit select. This selects width used communications through system interface. rising edge SRESET, TMS380C26 latches width; otherwise value this dynamically selects width. Selects 8-bit mode (see Note Selects 16-bit mode. NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
S8/SHALT
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Terminal Functions (continued) System Interface Motorola Mode (SI/M
NAME SADH0 SADH1 SADH2 SADH3 SADH4 SADH5 SADH6 SADH7 SADL0 SADL1 SADL2 SADL3 SADL4 SADL5 SADL6 SADL7 DESCRIPTION System Address/Data Bus-high byte (see Note 1).These lines make most significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADH0, least significant SADH7. Address Multiplexing Bits bits Data Multiplexing Bits
System Address/Data Bus-low byte (see Note These lines make least significant byte each address word (32-bit address bus) data word (16-bit data bus). most significant SADL0, least significant SADL7. Address Multiplexing Bits bits Data Multiplexing Bits System Address Latch Enable. This enable pulse used externally latch LSBs address from SADH0 SADH7 SADL0 SADL7 buses start cycle. Systems that implement address parity also externally latch parity bits (SPH SPL) latched address. System Busy. TMS380C26 samples value this during arbitration. sample values (see Note
SALE
SBBSY
busy. TMS380C26 become Master grant condition met. Busy. TMS380C26 cannot become Master.
SBCLK
System Clock. TMS380C26 requires external clock synchronize timings transfers. System Read Write. This serves control signal indicate read write cycle.
SBHE/SRNW
Read Cycle (see Note Write Cycle System Release. This indicates TMS380C26 that higher-priority device requires system bus. value this ignored when TMS380C26 perfoming DMA. This signal internally synchronized SBCLK.
SBRLS
TMS380C26 hold onto system (see Note TMS380C26 should release system upon completion current cycle. transfer complete, will rearbitrate system bus. System Chip Select. Activates system interface TMS380C26 read write.
selected (see Note Selected. System Data Enable. This output signals external data buffers begin driving data. This output activated during both DMA.
SDBEN
Keep external data buffers high-impedance state. Cause external data buffers begin driving data.
Typical ordering Intel Motorola processor buses. NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued) System Interface Motorola Mode (SI/M
NAME DESCRIPTION System Data Direction. This output provides external data buffers signal indicating direction which data moving. During writes reads, SDDIR (data direction input TMS380C26). During reads writes, SDDIR high (data direction output from TMS380C26). When system interface involved operation, then SDDIR high default. DATA SDDIR DIRECTION output read write input write read System Grant. This serves active-low grant, defined standard 68000 interface, internally synchronized SBCLK (see Note SHLDA/SBGR System granted, System granted. System Request. This used request control system preparation transfer. This internally synchronized SBCLK. SHRQ/SBRQ System requested. System requested. System Interrupt Acknowledge. This signal from host processor acknowledge interrupt request from TMS380C26. SIACK System interrupt acknowledged (see Note System interrupt acknowledged: TMS380C26 places interrupt vector onto system bus. System Intel/Motorola Mode Select. value this specifies system interface mode. SI/M Intel-compatible interface mode selected. Motorola-compatible interface mode selected. Motorola interface mode always bits. System Interrupt Request. TMS380C26 activates this output signal interrupt request host processor. SINTR/SIRQ interrupt request. Interrupt request TMS380C26. System Owned. This signal indicates external devices that TMS380C26 control system bus. This signal drives enable signal transceiver chips, which drive address control signals. TMS380C26 does have control system bus. TMS380C26 control system bus. System Parity High. optional odd-parity each address data byte transmitted over SADH0-SADH7 (see Note System Parity Low. optional odd-parity each address data byte transmitted over SADL0-SADL7 (see Note Sytem Memory Address Strobe (see Note This active-low address strobe that input during (although ignored address strobe) output during DMA. SRAS/SAS Address valid Address valid transfer operation progress. NOTES: internal pullup device maintain high voltage level when left unconnected etch loads). should tied with 4.7-k pullup resistor.
SDDIR
SOWN
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Terminal Functions (continued) System Interface Motorola Mode (SI/M
NAME DESCRIPTION Upper Data Strobe (see Note This serves active-low upper data strobe. This input during output during DMA. SRD/SUDS valid data SADH0-SADH7 lines. Valid data SADH0-SADH7 lines. System Data Transfer Acknowledge (see Note purpopse this signal indicate master that data transfer complete. This signal internally synchronized SBCLK. During cycles, must asserted before falling edge SBCLK state order prevent wait state. This signal output when TMS380C26 selected DIO, input otherwise. System ready. Data transfer complete; system ready. System Reset. This input activated place adapter into known initial state. Hardware reset will most TMS380C26 output pins into high-impedance state place blocks into reset state. system reset. System reset. SRSX SRS0 SRS1 System Register Select. These inputs select word byte transferred during system access. most significant SRSX least significant SRS1 (see Note Register Selected SRSX SRS0 SRS1
SRDY/SDTACK
SRESET
SRS2/SBERR
Error. Corresponds error signal 68000 microprocessor. internally synchronized SBCLK. This input driven during cycle indicate TMS380C26 that cycle must terminated. Section 3.4.5.3 TMS380 Second-Generation Token Ring User's Guide (SPWU005) more information (see Note Lower Data Strobe (see Note This input during output during DMA. This serves active-low lower data strobe.
SWR/SLDS
valid data SADL0-SADL7 lines. Valid data SADL0-SADL7 lines. System Extended Address Latch. This output provides enable pulse used externally latch most significant bits 32-bit system address during DMA. SXAL activated prior first cycle each block transfer, thereafter necessary (whenever increment address counter causes carry-out lower 16-bits). Systems that implement parity addresses SXAL externally latch parity bits (available SPH) address extension. Reserved. This signal must left unconnected (see Note System Halt/Bus Error Retry. this signal asserted along with errror (SBERR), adapter will retry last cycle. This re-run operation defined 68000 specification. BERETRY counter decremented SBERR when SHALT asserted. Section 3.4.5.3 TMS380 Second-Generation Token Ring User's Guide (SPWU005) more information.
SXAL
SYNCIN
S8/SHALT
NOTES: internal pullup device maintain high voltage level when left unconnected etch loads). should tied with 4.7-k pullup resistor.
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TMS380C26 NETWORK COMMPROCESSOR
Terminal Functions (continued)
Network Media Interface Token-Ring Mode (TEST1 TEST2
NAME DRVR DRVR DESCRIPTION Differential Driver Data Output. These pins differential outputs that send TMS380C16 transmit data TMS38054 driving onto ring transmit signal pair. Frequency Acquisition Control. This output determines frequency phase acquisition mode TMS38054. FRAQ/TXD Wide range. Frequency centering PXTALIN TMS38054. Narrow range. Phase-lock onto incoming data (RCVINA TMS38054.
RCVINB)
Insert Control Signal TMS38054. This output signal enables phantom driver outputs (PHOUTA PHOUTB) TMS38054, through watchdog timer, insertion onto Token-Ring. NSRT/LPBK Static High Static NSRT Pulsed High PXTALIN/TXC Inactive, phantom current removed (due watchdog timer) Inactive, phantom current removed (due watchdog timer) Active, current output PHOUTA PHOUTB
Ring Interface Clock Frequency Control (see Note 16-Mbps ring speed, this input must supplied 32-MHz signal. 4-Mbps ring speed, input signal must 8-MHz output from OSCOUT pin. Ring Interface Recovered Clock (see Note This input signal clock recovered TMS38054 from Token-Ring received data.
RCLK/RXC
16-Mbps operation 32-MHz clock. 4-Mbps operation 8-MHz clock.
RCVR/RXD
Ring Interface Received Data (see Note This input signal contains data received TMS38054 from token ring. Ring Interface Ready. This input provides indication presence received data, monitored TMS38054 energy detect capacitor.
REDY/CRS
ready. Ignore received data. Ready. Received data. Wire Fault Detect. This signal input TMS380C16 driven TMS38054. indicates current imbalance TMS38054 PHOUTA PHOUTB pins.
WFLT/COLL
wire fault detected. Wire fault detected. Internal Wrap Select. This signal output from TMS380C16 ring interface activate internal attenuated feedback path from transmitted data (DRVR) receive data (RCVR) signals bring-up diagnostic testing. When active, TMS38054 also cuts current drive transmission pair. Normal ring operation. Transmit data drives receive data (loopback).
WRAP/TXEN
NOTE expanded input voltage specification.
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Terminal Functions (continued)
Network Media Interface Ethernet Mode (TEST1 TEST2
NAME DRVR DRVR FRAQ/TXD DESCRIPTION These pins have Ethernet function. Ethernet Mode these pins placed their token ring reset state DRVR High, DRVR Low. Ethernet Transmit Data. This output signal provides Ethernet physical layer circuitry with bit-rate from TMS380C26. Data this output synchronously transmit clock TXC. normally connected Ethernet Serial Network Interface (SNI) chip. Loopback. This enables loopback Ethernet transmit data through Ethernet (SNI) device recieve data. NSRT/LPBK Wrap through front device Normal operation PXTALIN/TXC Ethernet Transmit Clock. clock input used synchronize transmit data from TMS380C26 Ethernet physical layer circuitry. This continuously running clock. normally connected output Ethernet chip (see Note Ethernet Receive Clock. clock input used synchronize received data from Ethernet physical layer circuitry TMS380C26. This clock must present whenever signal active (although held maximum clock cycles after rising edge CRS). When signal inactive permissable hold this clock phase. normally connected output Ethernet Serial Network Interface (SNI) chip. TMS380C26 requires this maintained state when asserted (see Note Ethernet Received Data. This input signal provides TMS380C26 with rate network data from Ethernet front device. Data this must synchronous with receive clock RXC. normally connected Ethernet chip (see Note Ethernet Carrier Sense. This input signal indicates TMS380C26 that Ethernet physical layer circuitry network data present pin. This signal asserted high when first frame received deasserted after last frame received. Receiving data. data network. Ethernet Collision Detect. This input signal indicates TMS380C26 that Ethernet physical layer circuitry detected network collision. This signal must present least clock cycles ensure accepted TMS380C26. normally connected COLL Ethernet chip. This signal also indication test signal. COLL detected device. Normal operation. Ethernet Transmit Enable. This output signal indicates Ethernet physical layer circuitry that bit-rate data present pin. This signal output synchronously transmit clock TXC. normally connected Ethernet chip. Data line currently contains data transmitted. valid data TXEN. NOTE expanded input voltage specification.
RCLK/RXC
RCVR/RXD
REDY/CRS
WFLT/COLL
WRAP/TXEN
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Terminal Functions (continued)
NAME DESCRIPTION Network Select inputs. These pins used select network speed type used TMS380C26. These inputs should only changed during adapter reset. TEST TEST TEST TEST0 TEST1 TEST2 Description Reserved Mbps token ring Ethernet (802.3/Blue Book) Mbps token ring Reserved
TEST3 TEST4 TEST5
Test Inputs. These pins should left unconnected (see Note Module-in-Place test mode achieved tying TEST TEST pins ground. this mode, TMS380C26 output pins high impedance. Internal pullups TMS380C26 inputs will disabled (except TEST3-TEST5 pins). External Fail-to-Match signal. enhanced address copy option (EACO) device uses this signal indicate TMS380C26 that should copy frame ARI/FCI bits token ring frame external address match.The ARI/FCI bits token ring frame internal address matched frame. enhanced address copy option (EACO) device used, then this must left unconnected. This ignored when mode enabled. table given below XMATCH description (see Note address match external address checker. External address checker armed state. External Match signal. enhanced address copy option (EACO) device uses this signal indicate TMS380C26 copy frame ARI/FCI bits token ring frame. enhanced address copy option (EACO) device used, then this must left unconnected. This ignored when mode enabled (see Note Address match recognized external address checker. External address checker armed state.
XFAIL
XMATCH
XMATCH HI-Z XFAIL HI-Z Function Armed (Processing frame data). externally match frame. (XFAIL takes precedence) COPY frame. externally match frame. (XFAIL takes precedence) Reset state (adapter initialized).
VDDL VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VSSC VSSI
Positive supply voltage digital logic. pins must attached common system power supply plane.
Positive supply voltage output buffers. pins must attached common system power supply plane.
Ground reference output buffers (clean ground). pins must attached common system ground plane. Ground reference input buffers. pins must attached common system ground plane.
NOTE internal pullup device maintain high voltage level when left unconnected etch loads).
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Terminal Functions (continued)
NAME VSSL VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 DESCRIPTION Ground reference digital logic. pins must attached common system ground plane.
Ground connections output buffers. pins must attached system ground plane.
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architecture
major blocks TMS380C26 include Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), Adapter Support Function (ASF). functionality each block described following sections. communications processor (CP) Communications Processor (CP) performs control monitoring other functional blocks TMS380C26. control monitoring protocols specified software (downloaded ROM-based) local memory. Available protocols include:
Media Access Control (MAC) software, Logical Link Control (LLC) software, (token ring version only), Copy Frames (CAF) software.
proprietary 16-bit central processing unit (CPU) with data cache single prefetch pipe pipelining instructions. These features enhance TMS380C26's maximum performance capability about million instructions second (MIPS), with average about MIPS. system interface (SIF) System Interface (SIF) performs interfacing subsystem host system. This interface require additional logic depending application. system interface transfer information/data using these three methods:
Direct Memory Access (DMA), Direct Input/Output (DIO), Pseudo-Direct Memory Access (PDMA).
PDMA) used transfer data to/from host memory from/to local memory. DIO's main uses loading software local memory initializing TMS380C26. also allows command/status interrupts occur from TMS380C26. system interface hardware selected either modes SI/M pin. mode selected determines memory organizations control signals used. These modes are:
Intel 80x8x families: 16-, 32-bit members Motorola 68000 microprocessor family: 32-bit members
system interface supports host system memory addressing bits (32-bit reach into host system memory). This allows greater flexibility using/accessing host system memory. System designers allowed customize system interface their particular
Programmable burst transfers cycle-steal operations Optional parity protection
These features implemented hardware reduce system overhead, facilitate automatic rearbitration after burst, repeat cycle when errors occur (parity bus). retries also supported. system interface hardware also includes features enhance integrity TMS380C26 data. These features following:
Always internally maintain byte parity regardless parity disabled, Monitor presence clock failure.
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every cycle system interface compares system clocks reference clock. clocks become invalid, TMS380C26 enters slow clock mode, which prevents latchup TMS380C26. SBCLK invalid, cycle terminated immediately; otherwise, cycle completed then TMS380C26 placed slow clock mode. When TMS380C26 enters slow clock mode, clock that failed replaced slow free-running clock device placed into low-power reset state. When failed clock(s) return valid operation, TMS380C26 must re-initialized. Using DMA, continuous transfer rate Mbits second (Mbps), which MBytes second (MBps), obtained. pseudo-DMA continuous transfer rate Mbps MBps) obtained when using 16-MHz clock. transfer rate significant issue, since main purpose downloading initialization. comparison, continuous transfer rated approximately Mbps. memory interface (MIF) Memory Interface (MIF) performs memory management allow TMS380C26 address MBytes local memory. Hardware allows TMS380C26 directly connected DRAMs without additional circuitry. This glueless DRAM connection includes DRAM refresh controller. also handles internal arbitration between these blocks. When required, then arbitrates external bus. responsible memory mapping task. memory DRAMs, EPROMs, Burned-in Addresses (BIA), External Devices appropriately addressed when required System Interface (SIF), Protocol Handler (PH), transfer. memory interface capable Mbps continuous transfer rate when using 4-MHz local (64-MHz device crystal). protocol handler (PH) Protocol Handler (PH) performs hardware-based realtime protocol functions token ring Ethernet Local Area Network (LAN). Network type determined test pins TEST0-2. Token ring network determined software either 16-Mbps 4-Mbps. These speeds fixed hardware, software. (PH) converts parallel transmit data serial network data appropriate coding, converts received serial data parallel data. data management state machines direct transmission/reception data to/from local memory through MIF. PH's buffer management state machines automatically oversee this process, directly sending/receiving linked-lists frames without intervention.
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Protocol Handler contains many state machines which provide following features:
Transmit receive frames Capture tokens (token ring) Provide token-priority controls (token ring) Automatic retry frame transmissions after collisions (Ethernet) Implement Random Exponential Backoff algorithm (Ethernet) Manage TMS380C26 buffer memory Provide frame address recognition (group, specific, functional, multicast) Provide internal parity protection Control verify physical layer circuitry interface signals
Integrity transmitted received data assured cyclic redundancy checks (CRC), detection network data violations, parity internal data paths. data paths registers optionally parity-protected assure functional integrity. adapter support function (ASF) Adapter Support Function (ASF) performs support functions contained other blocks. features are:
TMS380C26 base timer, Identification, management, service internal external interrupts, Test mode control, including unit-in-place mode board testing, Checks illegal states, such illegal opcodes parity.
clock generator (CG) Clock Generator (CG) performs generation clocks required other functional blocks local memory clocks. This block also generates reference clock sampled determine TMS380C26 needs placed into slow clock mode. This reference clock free floating range kHz.
user-accessible hardware registers TMS380C26-internal pointers
following tables show access internal data pointers address registers host interface. SIFACL register, which directly controls device operation, described detail. NOTE: Adapter-Internal Pointers Table defined only after TMS380C26 initialization until OPEN command issued. These pointers defined TMS380C26 software (microcode), this table describes release 1.00 software.
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Adapter-Internal Pointers Token-Ring
ADDRESS >00.FFF8 >00.FFFA >01.0A00 >01.0A02 >01.0A04 DESCRIPTION Pointer software microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TMS380C26 addresses chapter Pointer node address. Pointer group address. Pointer functional address. Pointer TMS380C26 parameters chapter Pointer physical drop number. Pointer upstream neighbor address. Pointer upstream physical drop number. Pointer last ring poll address. Pointer reserved. Pointer transmit access priority. Pointer source class authorization. Pointer last attention code. Pointer source address last received frame. Pointer last beacon type. Pointer last major vector. Pointer ring status. Pointer soft error timer value. Pointer ring interface error counter. Pointer local ring number. Pointer monitor error code. Pointer last beacon transmit type. Pointer last beacon receive type. Pointer last frame correlator. Pointer last beaconing station UNA. Pointer reserved. Pointer last beaconing station physical drop number. Pointer buffer special buffer used software transmit adapter generated frames) chapter Pointer counters chapter Pointer MAX_SAPs. Pointer open SAPs. Pointer MAX_STATIONs. Pointer open stations. Pointer available stations. Pointer reserved. Pointer 4-/16-Mbps word flag. zero, then Mbps. nonzero, then adapter 16-Mbps data rate.
>01.0A06
>01.0A08 >01.0A0A
>01.0A0C >01.0A0E
Pointer total TMS380C26 found Kbytes allocation test chapter This table describes pointers release 1.00 TMS380C26 software. This address valid only microcode release 2.x.
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Adapter-Internal Pointers Ethernet
ADDRESS >00.FFF8 >00.FFFA >01.0A00 >01.0A02 >01.0A04 DESCRIPTION Software microcode level chapter Pointer starting location copyright notices. Copyright notices separated character terminated character chapter Pointer burned-in address chapter Pointer software level chapter Pointer TMS380C26 addresses chapter Pointer node address. Pointer group address. Pointer functional address. Pointer buffer special buffer used software transmit adapter generated frames) chapter Pointer counters chapter Pointer MAX_SAPs. Pointer open SAPs. Pointer MAX_STATIONs. Pointer open stations. Pointer available stations. Pointer reserved. Pointer 4-/16-Mbps word flag. zero, then Mbps. nonzero, then adapter 16-Mbps data rate.
>01.0A08 >01.0A0A
>01.0A0C
>01.0A0E Pointer total TMS380C26 found Kbytes allocation test chapter This table describes pointers release 1.00 TMS380C26 software. This address valid only microcode release 2.x.
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User-Access Hardware Registers
808x 16-Bit Mode: (SI/M S8/SHALT Word Transfers Byte Transfers SRSX SRS0 SRS1 SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SBHE SRS2 Normal Mode SBHE SRS2 SBHE SRS2 Pseudo-DMA Mode Active SBHE SRS2 SBHE SRS2 SBHE SRS2
(SBHE SRS2 defined)
808x 8-Bit Mode: (SI/M S8/SHALT SRSX SRS0 SRS1 SRS2 Normal SBHE SIFDAT SIFDAT SIFDAT/INC SIFDAT/INC SIFADR SIFADR SIFSTS SIFCMD SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN Pseudo-DMA SBHE SDMADAT DMALEN DMALEN SDMAADR SDMAADR SDMAADX SDMAADX SIFACL SIFACL SIFADR SIFADR SIFADX SIFADX DMALEN DMALEN
68xxx Mode: (SI/M Word Transfers Byte Transfers SRSX SRS0 SRS1 SIFDAT SIFDAT/INC SIFADR SIFCMD SIFACL SIFADR SIFADX DMALEN SIFDAT SIFDAT/INC SIFADR SIFSTS SIFACL SIFADR SIFADX DMALEN DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SDMADAT DMALEN SDMAADR SDMAADX SIFACL SIFADR SIFADX DMALEN SUDS SLDS Normal Mode SUDS SLDS SUDS SLDS Pseudo-DMA Mode Active SUDS SLDS SUDS SLDS SUDS SLDS
68xxx Mode always 16-bit.
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Adapter Control Register (SIFACL)
SIFACL register allows host processor control some extent reconfigure TMS380C26 under software control. SIFACL Register
SWHLDA
SWDDIR
SWHRQ
PSDMAEN
ARESET
CPHALT
BOOT
RES0
SINTEN
NSEL OUT0
NSEL OUT1
RP-0
RP-1
Read, Write, Write during ARESET only, Only, Value after reset Value BTSTRP pin, Value PRTYEN pin, Indeterminate) Bits 0-2: TEST Value TEST pins. These bits read only always reflect value corresponding device pins. This allows host determine network type speed configuration. network speed type software configurable, these bits used determine which configurations supported network hardware.
TEST0 TEST1 TEST2 Description Reserved Mbps token ring Ethernet (802.3/Blue Book) Mbps token ring Reserved
Reserved. Read data indeterminate. SWHLDA Software Hold Acknowledge This allows SHLDA/SBGR pin's function emulated from software control pseudo-DMA.
PSDMAEN SWHLDA SWHRQ RESULT SWHLDA value SIFACL register cannot one. pseudo-DMA request pending. Indicates pseudo-DMA request interrupt. Pseudo-DMA process progress.
value SHLDA/SBGR ignored.
SWDDIR Current SDDIR Signal Value This contains current value pseudo-DMA direction. This enables host easily determine direction transfers, which allows system controlled system software. Pseudo-DMA from host system TMS380C26. Pseudo-DMA from TMS380C26 host system.
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SWHRQ Current SHRQ Signal Value This contains current value SHRQ/SBRQ when Intel mode, inverse SHRQ/SBRQ when Motorola mode. This enables host easily determine pseudo-DMA transfer requested. INTEL MODE (SI/M System requested System requested MOTOROLA MODE (SI/M System requested System requested
PSDMAEN Pseudo-System-DMA Enable This enables pseudo-DMA operation Normal master operation possible. Pseudo-DMA operation selected. Operation dependent values SWHLDA SWHRQ bits SIFACL register.
ARESET Adapter Reset This hardware reset TMS380C26. This same effect SRESET pin, except that interface SIFACL register maintained. This will clock failure detected (OSCIN, PXTALIN, RCLK, SBCLK valid). TMS380C26 operates normally. TMS380C26 held reset condition.
CPHALT Communications Processor Halt This prevents TMS380C26's processor from accessing internal TMS380C26 buses. This prevents TMS380C26 from executing instructions before microcode been downloaded. TMS380C26's processor access internal TMS380C26 buses. TMS380C26's processor prevented from accessing internal adapter buses.
BOOT Bootstrap Code This indicates whether memory chapters local memory space ROM/PROM/EPROM. This then controls operation MCAS MROMEN pins. ROM/PROM/EPROM memory chapters memory chapters
RES0 Reserved. This must zero
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SINTEN System-Interrupt Enable This allows host processor enable disable system interrupt requests from TMS380C26. system interrupt request from TMS380C26 SINTR/SIRQ pin. following equation shows SINTR/SIRQ driven. table also explains results states. SINTR/SIRQ (PSDMAEN SWHRQ !SWHLDA) (SINTEN SYSTEM_INTERRUPT)
PSDMAEN SWHRQ SWHLDA SINTEN SYSTEM INTERRUPT (SIFSTS Reg.) RESULT Pseudo-DMA active. TMS380C26 generated system interrupt pseudo-DMA. pseudo-DMA interrupt. TMS380C26 will generate system interrupt. TMS380C26 will generate system interrupt. TMS380C26 generate system interrupt.
value SHLDA/SBGR ignored.
Adapter Parity Enable This determines whether data transfers within TMS380C26 checked parity. Data transfers checked parity Data transfers checked correct parity.
NSELOUT Network selection outputs. values these bits control output pins NSELOUT0 NSELOUT1. These bits only modified while ARESET set. These bits used software configure multi-protocol TMS380C26, follows: NSELOUT0 NSELOUT1 pins should connected TEST0 TEST1 pins respectively (TEST2 should left unconnected tied high). NSELOUT0 should used select network speed NSELOUT1 network type, shown table below: NSELOUT0 NSELOUT1 Reserved Mbps token ring Ethernet (802.3/Blue Book) Mbps token ring
power-up these bits NSELOUT1 NSELOUT0 corresponding Mbps token ring.
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SIFACL Control Pseudo-DMA Operation
Pseudo-DMA software controlled five bits SIFACL register. logic model SIFACL register control pseudo-DMA operation shown Figure
Internal Signals
Motorola Mode
Host Interface SINTR/SIRQ
SYSTEM_INTERRUPT (SIFSTS Register)
Request
SHRQ/SBRQ
Grant
SHLDA/SBGR
DMADIR SWHLDA SWDDIR SWHRQ SIFACL Register PSDMAEN SINTEN
SDDIR
Figure Pseudo-DMA Logic Related SIFACL Bits
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range (see Note Output voltage range Power dissipation Operating free-air temperature range 70°C Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE Voltage values with respect VSS.
recommended operating conditions
Supply voltage Supply voltage (see Note High-level input voltage TTL-level signal OSCIN RCLK, PXTALIN, RCVR OSCIN other 4.75 5.25 VDD+0.3 VDD+0.3 VDD+0.3 UNIT
Low-level level input voltage TTL-level signal (see Note voltage, level High level output current level output current (see Note
Operating free-air temperature minimum level specified result manufacturing test environment. This signal been characterized minimum level over full temperature range. maximum level specified result manufacturing test environment. This signal been characterized maximum level over full temperature range. NOTES: pins should routed minimize inductance system ground. algebraic convention, where more negative (less positive) limit designated minimum, used this data sheet logic voltage levels only. Output current sufficient drive five low-power Schottky loads advanced low-power Schottky loads (worst case).
electrical characteristics over full ranges recommended operating conditions (unless otherwise noted)
PARAMETER High-level output voltage, TTL-level signal (see Note Low-level output voltage, TTL-level signal High impedance output current High-impedance Input current, input input/output Supply current Input capacitance, input TEST CONDITIONS (see Note min, min, max, max, MHz, other pins UNIT
Output capacitance, output input/output MHz, other pins NOTES: conditions shown MAX, appropriate value specified under recommended operating conditions. following signals require external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS, EXTINT0-EXTINT3, MBRQ.
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PARAMETER MEASUREMENT INFORMATION
Outputs driven minimum high-logic level volts maximum low-logic level volts. These levels compatible with devices. Output transition times specified follows: high-to-low transition either input output signal, level which signal said longer high volts, level which signal said volts. low-to-high transition, level which signal said longer volts, level which signal said high volts, shown below. rise fall times specified assumed those standard devices, which typically
(High) (Low)
test measurement
test load circuit shown Figure represents programmable load tester electronics which used verify timing parameters TMS380C26 output signals.
Tester Electronics Output Under Test
VLOAD
Where:
level verification (all outputs) (all outputs) VLOAD typical level verification typical timing verification typical load circuit capacitance Figure Test Load Circuit
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PARAMETER MEASUREMENT INFORMATION
Reference Periods Periods Periods Periods Periods
OSCIN
When CLKDIV
OSCOUT
MBCLK1
MBCLK2
MBCLK1 MBCLK2 signals have timing relationship OSCOUT signal. MBCLK1 MBCLK2 signals start OSCIN rising edge, depending when memory cycle starts execution.
Figure Clock Waveforms After Clock Stabilization
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PARAMETER MEASUREMENT INFORMATION timing parameters
timing parameters pins TMS380C26 shown following tables illustrated accompanying figures. purpose these figures tables quantify timing relationships among various signals. parameters numbered convenience.
static signals
following table lists signals that allowed change dynamically therefore have timing associated with them. They should strapped high required.
SIGNAL SI/M CLKDIV BTSTRP PRTYEN TEST0 TEST1 TEST2 TEST3 TEST4 Reserved Default bootstrap mode. (RAM/ROM) Default parity select. (enabled/disabled) Test pin, indicates network type Test pin, indicates network type Test pin, indicates network type Test manufacturing test. Test manufacturing test. FUNCTION Host processor select. (Intel/Motorola)
TEST5 Test manufacturing test. unit-in-place test.
timing parameter symbology
Timing parameter symbols have been created accordance with JEDEC standard 100. order shorten symbols, some names other related terminology have been abbreviated shown below:
DRVR DRVR OSCIN SBCLK SRESET VDDL, VDDB
Lower case subscripts defined follows:
cycle time delay time hold time pulse duration (width) rise time skew setup time transition time
following additional letters phrases defined follows:
High Valid Falling edge Rising edge High impedance longer high longer
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PARAMETER MEASUREMENT INFORMATION power SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, SRESET timing
PARAMETER tr(VDD) td(VDDH-SCKV) td(VDDH-OSCV) tc(SCK) tw(SCKH) tw(SCKL) tt(SCK) tc(OSC) tw(OSCH) tw(OSCL) tt(OSC) td(OSCV-CKV) th(VDDH-RSL) tw(RSH) tw(RSL) tsu(RST) th(RST) Rise time from minimum high level Delay time from minimum high level first valid SBCLK longer high Delay time from minimum high level first valid OSCIN high Cycle time SBCLK Pulse duration SBCLK high Pulse duration SBCLK Transition time SBCLK Cycle time OSCIN (see Note Pulse duration OSCIN high Pulse duration OSCIN Transition time OSCIN Delay time from OSCIN valid MBCLK1 MBCLK2 valid Hold time SRESET after reaches minimum high level Pulse duration SRESET high Pulse duration SRESET Setup time size SRESET high (Intel mode only) Hold time size from SRESET high (Intel mode only) One-eighth local memory cycle 2tc(OSC) 15.6 62.5 UNIT
This specification provided board design. parameter cannot met, parameter must extended larger difference: real value parameter minus value listed. NOTE OSCIN used generate PXTALIN, specification tolerance OSCIN equal 0.01%.
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PARAMETER MEASUREMENT INFORMATION
SBCLK OSCIN MBCLK1 MBCLK2 SRESET S8/SHALT NOTE order represent information figure, non-actual phase timebase characteristics shown. Please refer specified parameters precise information. Minimun High Level
Figure Power SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, SRESET Timing
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PARAMETER MEASUREMENT INFORMATION memory timing: clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
cycle time one-eighth local memory cycle (31.25 minimum)
Period MBCLK1 MBCLK2 Pulse duration clock high Pulse duration clock Hold time MBCLK2 after MBCLK1 high Hold time MBCLK1 high after MBCLK2 high Hold time MBCLK2 high after MBCLK1 Hold time MBCLK1 after MBCLK2 Setup time address/enable MAX0, MAX2, MROMEN before MBCLK1 longer high Setup time address MADL0-MADL7, MAXPH, MAXPL before MBCLK1 longer high Setup time address MADH0-MADH7 before MBCLK1 longer high Setup time high before MBCLK1 longer high Setup time address MAX0, MAX2, MROMEN before MBCLK1 longer Setup time column address MADL0-MADL7, MAXPH, MAXPL before MBCLK1 longer Setup time status MADH0-MADH7 before MBCLK1 longer Setup time valid before MBCLK1 Hold time valid after MBCLK1 Delay time from MBCLK1 longer MRESET valid Hold time column address/status after MBCLK1 longer low. PARAMETER 0.5tM 0.5tM 0.5tM UNIT
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PARAMETER MEASUREMENT INFORMATION
MBCLK1 MBCLK2 MAX0, MAX2, MROMEN MAXPH, MAXPL, MADL0-MADL7 MADH0-MADH7 Valid MRESET Valid Address Address Status
ADD/EN
Figure Memory Timing: Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, ADDRESS
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PARAMETER MEASUREMENT INFORMATION memory timing: clocks, MRAS, MCAS, ADDRESS
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Setup time address MADL0-MADL7, MAXPH, MAXPL before MRAS longer high Hold time address MADL0-MADL7, MAXPH, MAXPL after MRAS longer high Delay time from MRAS longer high MRAS longer high next memory cycle Pulse duration MRAS Pulse duration MRAS high Setup time column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) before MCAS longer high Hold time column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) after MCAS Hold time column address (MADL0-MADL7, MAXPH, MAXPL) status (MADH0-MADH7) after MRAS longer high Pulse duration MCAS Pulse duration MCAS high, refresh cycle follows read write cycle Hold time address MAXL0-MAXL7, MAXPH, MAXPL after Setup time address MAXL0-MAXL7, MAXPH, MAXPL before longer high Pulse duration high Setup time address/enable MAX0, MAX2, MROMEN before longer high Hold time address/enable MAX0, MAX2, MROMEN after Setup time address MADH0-MADH7 before longer high Hold time address MADH0-MADH7 after 1.5tM 11.5 4.5tM 3.5tM 0.5tM 2.5tM 1.5tM 1.5tM 1.5tM UNIT
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PARAMETER MEASUREMENT INFORMATION
MAXPH, MAXPL, MADL0-MADL7 MRAS MCAS MAX0, MAX2, MROMEN MADH0-MADH7 Address Status Address Status ADD/EN Address Column Column
Figure Memory Timing: Clocks, MRAS, MCAS, ADDRESS
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PARAMETER MEASUREMENT INFORMATION memory timing: read cycle
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Access time from address/enable valid MAX0, MAX2, MROMEN valid data/parity Access time from address valid MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 valid data/parity Access time from MRAS valid data/parity Hold time valid data/parity after MRAS longer Hold time address high impedance MAXPH, MAXPL, MADH0-MADH7 MADL0-MADL7 after MRAS high (see Note Access time from MCAS valid data/parity Hold time valid data/parity after MCAS longer Hold time address high impedance MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MCAS high (see Note Delay time from MCAS longer high Setup time address/status high impedance MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7 before longer high Access time from valid data/parity Pulse duration Delay time from MCAS longer Hold time valid data/parity after longer Hold time address high impedance MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after high (see Note Setup time address/status high impedance MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7, before MBEN longer high Setup time address/status high impedance MAXPH, MAXPL, MADL0-MADL7, MADH0-MADH7 before MBIAEN longer high Access time from MBEN valid data/parity Access time from MBIAEN valid data/parity Pulse duration MBEN Pulse duration MBIAEN Hold time valid data/parity after MBEN longer Hold time valid data/parity after MBIAEN longer Hold time address high impedance MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MBEN high (see Note Hold time address high impedance MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 after MBIAEN high Hold time MDDIR high after MBEN high, read follows write cycle Setup time MDDIR before MBEN longer high Hold time MDDIR after MBEN high, write follows read cycle 1.5tM -10.5 4.5tM 21.5 UNIT
This specification been characterized meet stated value. NOTE data/parity that exists address lines will most likely achieve high-impedance condition sometime later than rising edge, MRAS, MCAS, MOE, MBEN (between timing parameter will function memory being read. Hence, time given represents time from rising edge MRAS, MCAS, MOE, MBEN beginning next address, does represent actual high-impedance period address bus.
POST OFFICE 1443 HOUSTON, TEXAS 77251-1443
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MAX0, MAX2, MROMEN Address/ Enable MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 Address Address/ Status MRAS MCAS MBIAEN MDDIR MBEN
Address Data/Parity Address
Figure Memory Timing: Read Cycle
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: write cycle
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Setup time before MRAS longer Setup time before MCAS longer Setup time valid data/parity before longer high Pulse duration Hold time data/parity valid after high Setup time address valid MAX0, MAX2, MROMEN before longer Hold time from MRAS longer Hold time from MCAS longer Setup time MBEN before longer high Hold time MBEN after high Setup time MDDIR high before MBEN longer high Hold time MDDIR high after MBEN high 1.5tM 1.5tM 0.5tM -11.5 2.5tM 0.5tM 10.5 -11.5 5.5tM -11.5 1.5tM 13.5 0.5tM 1.5tM UNIT
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 Address/ Enable Address
Address
ADD/STS
Data/Parity
MRAS
MCAS MBEN MDDIR
Figure Memory Timing: Write Cycle
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: TMS380C26 releases control
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Hold time output after MBCLK1 rising edge, release Hold time MBEN valid after MBCLK1 rising edge, release Delay time from MBCLK1 high output high impedance, release Delay time from MBCLK1 high MBEN output high impedance, release Setup time MBRQ before MBCLK1 falling edge, release Hold time MBRQ after MBCLK1 low, release Setup time MBGR before MBCLK1 rising edge, release 0.5tM 0.5tM UNIT
MBCLK1
MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7
MRAS MCAS
Figure Memory Timing: TMS380C26 Releases Control
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MBCLK1
MBCLK2
MBEN MDDIR MBIAEN
MBRQ MBGR
Figure Memory Timing: TMS380C26 Releases Control (continued)
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: TMS380C26 resumes control
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Hold time output high impedance after MBCKL1 rising edge, resume Delay time from MBCLK1 high output vallid, resume Setup time MBRQ valid before MBCLK1 falling edge, resume Hold time MBRQ valid after MBCLK1 low, resume Setup time MBGR high before MBCLK1 rising edge, resume UNIT
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MBCLK1
MAX0, MAX2, MOROMEN MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7
MRAS MCAS
Figure Memory Timing: TMS380C26 Resumes Control
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MBCLK1
MBCLK2
MBEN MDDIR MBIAEN
MBRQ MBGR
Figure Memory Timing: TMS380C26 Resumes Control (continued)
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: external master read from TMS380C26
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Setup time address MAX0 MAX2 before MBCLK1 falling edge, external master access Hold time address MAX0 MAX2 after MBCLK1 low, external master access Setup time valid address before MBCLK1 falling edge, external master access Hold time valid address after MBCLK1 low, external master access Setup time address high impedance before MBCLK1 falling edge, external master read Setup time data/parity valid before MBCLK2 falling edge, external master read Hold time valid data/parity after MBCLK2 low, external master read Setup time data/parity high impedance before MBCLK2 rising edge, external master read Setup time MDDIR before MBCLK2 falling edge, external master read Hold time MDDIR after MBCLK2 low, external master read Setup time MACS before MBCLK2 falling edge, external master read Hold time MACS after MBCLK2 low, external master read 1.5tM UNIT
This specification been characterized meet stated value.
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
MBCLK1
MBCLK2 Address MAX0, MAX2 MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 Address MDDIR MACS Data/Parity Address Address
Figure Memory Timing: External Master Read From TMS380C26
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: external master write TMS380C26
PARAMETER Setup time valid data/parity before MBCLK2 falling edge, external master write Hold time valid data/parity after MBCLK2 low, external master write Setup time MDDIR high before MBCLK2 falling edge, external master write Hold time MDDIR high after MBCLK2 low, external master write UNIT
MBCLK1 Address MAX0, MAX2 Address
MAXPH, MAXPL, MADH0-MADH7, MADL0-MADL7 Address MDDIR MACS Data/Pty Address
Figure Memory Timing: External Master Write TMS380C26
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION memory timing: DRAM refresh timing
cycle time one-eighth local memory cycle (31.25 minimum)
PARAMETER Setup time address MADL0-MADL7, MAXPH, MAXPL before MRAS longer high Hold time address MADL0-MADL7, MAXPH, MAXPL after MRAS longer high Pulse duration MRAS Pulse duration MRAS high Setup time MCAS before MRAS longer high Hold time MCAS after MRAS Setup time MREF high before MCAS longer high Hold time MREF high after MCAS high 1.5tM -11.5 4.5tM 3.5tM 1.5tM -11.5 4.5tM UNIT
MADL0-MADL7
Refresh Address
Address
MRAS MCAS MREF
Figure Memory Timing: DRAM Refresh Cycle
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION XMATCH XFAIL timing
cycle time one-eighth local memory cycle (31.25 minimum)
Pulse duration XMATCH XFAIL high PARAMETER Delay from status high XMATCH XFAIL recognized UNIT
MADH7
Status
XMATCH, XFAIL
Figure XMATCH XFAIL Timing
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION token ring ring interface timing
154L 154H 158L 158H Period RCLK (see Note Pulse duration RCLK Pulse duration RCLK high PARAMETER 4Mbps Mbps Mbps nominal: 62.5 Mbps nominal: 15.625 Mbps nominal: 62.5 Mbps nominal: 15.625 Mbps Mbps Mbps Mbps Mbps Mbps (for PXTALIN only) 31.25 0.01 31.25 UNIT
Setup RCVR valid before rising edge (1.8 RCLK Mbps Hold RCVR valid after rising edge (1.8 RCLK Mbps Pulse duration ring baud clock Pulse duration ring baud clock high Period OSCOUT PXTALIN (see Note Tolerance PXTALIN input frequency (see Note
NOTE This parameter tested required IEEE 802.5 specification.
154H
RCLK 154L RCVR Valid
158H 158L OSCOUT, PXTALIN
Figure Token Ring Ring Interface Timing
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION token ring transmitter timing (see Figure
PARAMETER Delay from DRVR rising edge (1.8 DRVR falling edge (1.0 DRVR falling edge (1.0 DRVR rising edge (1.8 Delay from RCLK PXTALIN) falling edge (1.0 DRVR rising edge (1.8 Delay from RCLK PXTALIN) falling edge (1.0 DRVR falling edge (1.0 Delay from RCLK PXTALIN) falling edge (1.0 DRVR falling edge (1.0 Delay from RCLK PXTALIN) falling edge (1.0 DRVR rising edge (1.8 DRVR/DRVR Asymmetry d(DR)L (see Note (see Note (see Note (see Note ±1.5 UNIT
d(CRN)H
d(DR)H
d(DRN)L
When active-monitor mode, clock source PXTALIN; otherwise, clock-source either RCLK PXTALIN. NOTE This parameter tested minimum maximum measured used component required parameter 164.
RCLK PXTALIN
2.60 1.50 0.60 2.40 1.50 0.60 2.40 1.50 0.60
DRVR
DRVR
Figure Skew Asymmetry from RCLK PXTALIN DRVR DRVR
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION ethernet timing clock signals
CLKPHS CLKPER Pulse duration Cycle time PARAMETER 1000 UNIT
0.45
Figure Ethernet Timing Clock Signals
ethernet timing XMIT signals
tXDHLD tXDVLD PARAMETER Hold time after high Delay time from high valid Delay time from high TXEN high UNIT
0.45 TXEN 0.45
Figure Ethernet Timing XMIT Signals
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION ethernet timing signals start frame
RXDSET RXDHLD CRSSET SAMDLY RXCHI RXCL0 Hold after high Setup high before longer first valid data sample Delay internally recognized first valid data sample (see Notes Pulse duration high Pulse duration PARAMETER Setup before longer nominal cycles UNIT
NOTES: valid frame synchronization following data sequences must received. other pattern will delay frame synchronization until after next rising edge. (10) where integer greater than equal (10) previous frame frame fragment completed without extra clock cycles (XTRCVC then SAMDLY clock cycles.
Figure Ethernet Timing Signals Start Frame
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION ethernet timing signals frame
CRSSET CRSHLD XTRCYC PARAMETER Setup time before longer determine last data "seen" previous longer (see Note Hold time after longer low, determine last data "seen" previous longer Number extra clock cycles after last data (CRS low) (see Note UNIT cycle
NOTE TMS380C26 will operate correctly even with extra clock cycles, providing that does remain asserted longer than (see timing spec, NDRXC). Providing extra clocks affect receive startup timing, timing spec, SAMDLY.
Last Data
Figure Ethernet Timing Signals Frame
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION ethernet timing signals
NORXC PARAMETER Time with clock pulse RXC, when high (see Note UNIT
NOTE NORXC exceeded local clock failure circuitry become activated, resetting device.
Figure Ethernet Timing Signals
ethernet timing XMIT signals
HBWIN COLPUL COLSET PARAMETER Delay time from high last transmitted data (TXEN high) COLL sampled high, generate "heart-beat" error Minimum pulse duration COLL high guaranteed sample Setup COLL high high cycle UNIT cycles
COLL
TXEN
Figure Ethernet Timing XMIT Signals
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION ethernet timing XMIT signals
JAMTIM COLSET COLPUL PARAMETER Time from COLL sampled high (TXC high) first transmitted "JAM" (see Note Setup COLL high before high Minimum pulse duration COLL high guaranteed sample cycle UNIT cycles
NOTE pattern delayed until after completion preamble pattern. TMS380C26 transmits pattern "1"s.
Data
Data
Data
COLL
Figure Ethernet Timing XMIT Signals
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x read timing
261a 266a 272a 273a 282a 282R 283R Pulse duration, SRAS high Hold high-impedance after (see Note Setup SADH0-SADH7, SADL0-SADL7, valid before SRDY Delay from high high-impedance (see Note Hold output data valid after high (see Note Setup SRSX, SRS0-SRS2, SCS, SBHE valid SRAS longer high (see Note Hold SRSX, SRS0-SRS2, SCS, SBHE valid after SRAS Setup SRAS high longer high (see Note Setup SRSX, SRS0-SRS2 valid before longer high (see Note Hold SRSX, SRS0-SRS2 valid after longer (see Note Setup time SRD, SWR, SIACK high from previous cycle longer high Hold time SRD, SWR, SIACK high after high Delay from SWR, high SRDY high (see Note Delay from SWR, high SRDY high impedance Delay from SDBEN SRDY read cycle Delay from SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed. Delay from high SDBEN high (see Note Pulse duration, high between accesses (see Note PARAMETER Delay from SRDY either high UNIT
This specification provided board design. later that indicates start cycle. NOTES: "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0 SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, then parameters 266a irrelevant, parameter must met.
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
SCS, SRSX, SRS0-SRS2, SBHE SRAS 266a SIACK Valid Valid (see Note
272a
273a
272a 272a (High) SDDIR 282R SDBEN 282a SRDY HI-Z SADH0-SADH7, SADL0-SADL7, SPH, (see Note HI-Z Output Data Valid 261a 283R
273a
273a
HI-Z
HI-Z
When TMS380C26 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. NOTES: 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, then parameters 266a irrelevant, parameter must met. 8-bit 80x8x mode reads, SADH0-SADH7 contain don't care data.
Figure 80x8x Read Timing
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x write timing
266a 272a 273a 281a Pulse duration, SRAS high Setup SADH0-SADH7, SADL0-SADL7, SPH, valid before longer Hold SADH0-SADH7, SADL0-SADL7, SPH, valid after high Setup SRSX, SRS0-SRS2, SCS, SBHE SRAS longer high (see Note Hold SRSX, SRS0-SRS2, SCS, SBHE after SRAS Setup SRAS high longer high (see Note Setup SRSX, SRS0-SRS2 before longer high (see Note Hold SRSX, SRS0-SRS2 valid after longer (see Note Setup time SRD, SWR, SIACK high from previous cycle longer high Hold time SRD, SWR, SIACK high after high Delay from SRDY first access register SRDY immediately following access (see TMS380 Second-Generation Token Ring User's Guide, SPWU005, subsection 3.4.1.1.1) Delay from high SRDY high (see Note Delay from high SRDY high impedance Delay from SDDIR (see Note Delay from high SDDIR high (see note Hold SDDIR after longer active (see Note register ready waiting Delay from SDBEN SRDY (see TMS380 Second Generation Token-Ring required) User's Guide, SPWU005, subsection 3.4.1.1.1) register ready (waiting required) Delay from SDDIR SDBEN Delay from high SDBEN longer 4000 PARAMETER Delay from SRDY either high UNIT
282b
282W 283W
Pulse duration high between accesses (see Note later that indicates start cycle. This specification been characterized meet stated value. This specification provided board design. NOTES: "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, then parameters 266a irrelevant, parameter must met.
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION
SCS, SRSX, SRS0-SRS2, SBHE
Valid
SRAS 266a 272a 272a 273a
SIACK
273a 273a 281a 282W 283W
272a
SDDIR
(High)
SDBEN SRDY HI-Z 282b SADH0-SADH7, SADL0-SADL7, SPH, (see Note HI-Z Data HI-Z HI-Z
When TMS380C26 begins drive SDBEN inactive, already latched write data internally. Parameter must input data buffers. NOTE 8-bit 80x8x mode writes, value placed SADH0-SADH7 don't care.
Figure 80x8x Write Timing
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TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x interrupt acknowledge timing first SIACK pulse
PARAMETER Pulse duration, SIACK high between accesses (see Note Pulse duration, SIACK first pulse pulses 62.5 UNIT
NOTE "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles. SRD, SWR, SIACK First Second
Figure 80x8x Interrupt Acknowledge Timing First SIACK Pulse
80x8x interrupt acknowledge timing second SIACK pulse
261a 272a 273a 282a 282R Delay from SRDY high Hold high-impedance after SIACK (see Note Setup output data valid before SRDY Delay from SIACK high high-impedance (see Note Hold output data valid after SIACK high (see Note Setup inactive data strobe high SIACK longer high Hold inactive data strobe high after SIACK high Delay from SIACK high SRDY high (see Note Delay from SRDY first access register SRDY immediately following access Delay from SIACK high SRDY high impedance Delay from SDBEN SRDY read cycle Delay from SIACK SDBEN (see TMS380 Second Generation User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed 4000 PARAMETER UNIT
Token-Ring
283R Delay from SIACK high SDBEN high (see Note This specification provided board design. This specification been characterized meet stated value. NOTE "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles.
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PARAMETER MEASUREMENT INFORMATION
SCS, SRSX, SRS0-SRS2, SBHE
Only needs inactive. others Don't Care.
SIACK 272a 272a 272a SDDIR (High) 282R 283R SDBEN SRDY 282a HI-Z SADH0-SADH7, SADL0-SADL7, SPH, (see Note 261a Output Data Valid HI-Z HI-Z 273a 273a 273a
HI-Z
SRDY active-low ready signal. must asserted before data output. NOTE 8-bit 80x8x mode writes, value placed SADH0-SADH7 don't care.
Figure 80x8x Interrupt Acknowledge Timing Second SIACK Pulse
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PARAMETER MEASUREMENT INFORMATION 80x8x mode arbitration timing, takes control
208a 208b 224a 224c 241a PARAMETER Setup asynchronous signal SBBSY SHLDA before SBCLK longer high guarantee recognition that cycle Hold asynchronous signal SBBSY SHLDA after SBCLK guarantee recognition that cycle Delay from SBCLK SADH0-SADH7, SADL0-SADL7, SPH, valid Delay from SBCLK cycle SOWN Delay from SBCLK cycle SDDIR read Delay from SBCLK high SHRQ high Delay from SBCLK high cycle high, acquisition tc(SCK) UNIT
Hold high-impedance after SOWN low, acquisition This specification been characterized meet stated value.
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TMS380C26 NETWORK COMMPROCESSOR
User Master Inputs: SBCLK SBBSY, SHLDA Outputs: SHRQ
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PARAMETER MEASUREMENT INFORMATION
Exchange (T4)
Master
208a
208b
SRD, 241a SBHE SADH0-SADH7, SADL0-SADL7, SPH, Address Valid 224c Write SDDIR Read 224a SOWN (see Note NOTE While system interface controls active (i.e., SOWN asserted), input disabled.
Figure 80x8x Mode Arbitration Timing, Takes Control
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x mode read timing
207a 207b 208a 208b 216a 223R 225R 227R 237R PARAMETER Setup SADL0-SADL7, SADH0-SADH7, SPH, valid before SBCLK cycle longer high Hold SADL0-SADL7, SADH0-SADH7, SPH, valid after SBCLK cycle parameters 207a 207b Hold SADL0-SADL7, SADH0-SADH7, SPH, valid after high Hold SADL0-SADL7, SADH0-SADH7, SPH, valid after SDBEN longer Setup asynchronous signal SRDY before SBCLK longer high guarantee recognition this cycle Hold asynchronous signal SRDY after SBCLK guarantee recognition this cycle Delay from SBCLK address valid Delay from SBCLK cycle SADH0-SADH7, SADL0-SADL7, SPH, high-impedance Pulse duration, SALE SXAL high Delay from SBCLK high SALE SXAL high Hold SALE SXAL after high Delay from SBCLK high SXAL cycle SALE cycle Hold SADH0-SADH7, SADL0-SADL7, SPH, valid after SALE SXAL Delay from SBCLK cycle high (see Note Delay from SBCLK cycle SDBEN high Delay from SADH0-SADH7, SADL0-SADL7, SPH, high-impedance Delay from SBCLK cycle Hold SADH0-SADH7, SADL0-SADL7, SPH, high-impedance after SBCLK cycle Pulse duration, Setup SADH0-SADH7, SADL0-SADL7, SPH, valid before SALE, SXAL longer high Delay from SBCLK high cyle SDBEN 2tc(SCK) tw(SCKL) tw(SCKH) tw(SCKL) tc(SCK) UNIT
Setup data valid before SRDY parameter 208a This specification been characterized meet stated value. NOTE While system interface controls active (i.e., SOWN asserted), input disabled.
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SBCLK SRAS SBHE (see Note (see Note
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PARAMETER MEASUREMENT INFORMATION
TWAIT
HI-Z Valid (High) 227R 216a Address Extended Address 208a 207b Data 207a Address 223R
SXAL
SALE
SADH0-SADH7, SADL0-SADL7, SPH, (see Note
SRDY 208b 225R
237R SDBEN (see Note SDDIR
parameter 208A then valid data must present before SRDY goes low. NOTES: Motorola-style slaves hold SDTACK active until master deasserts SAS. 8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter i.e., held after high.
Figure 80x8x Mode Read Timing
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x mode write timing
208a 208b 216a 223W 225W 225WH 227W 237W PARAMETER Setup asynchronous signal SRDY before SBCLK longer high guarantee recognition that cycle Hold asynchronous signal SRDY after SBCLK guarantee recognition that cycle Delay from SBCLK SADH0-SADH7, SADL0-SADL7, SPH, valid Pulse duration, SALE SXAL high Delay from SBCLK high SALE SXAL high Hold SALE SXAL after high Delay from SBCLK high SXAL cycle SALE cycle Hold address valid after SALE, SXAL Delay from SBCLK cycle output data parity valid Hold SADH0-SADH7, SADL0-SADL7, SPH, valid after high Delay from SBCLK high Delay from SBCLK high cycle SDBEN high Hold SDBEN after SWR, SUDS, SLDS high Delay from SBCLK cycle Pulse duration, Setup SADH0-SADH7, SADL0-SADL7, SPH, valid before SALE, SXAL longer high Delay from SBCLK high cycle SDBEN 2tc(SCK) tw(SCKL) tw(SCKL) tc(SCK) tw(SCKH) tw(SCKL) tc(SCK) UNIT
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TMS380C26 NETWORK COMMPROCESSOR
SBCLK SBHE (see Note
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PARAMETER MEASUREMENT INFORMATION
TWAIT
Valid
(HIGH) 227W SXAL SALE SADL0-SADH7, SADH0-SADL7, SPH, (see Note SRDY 237W SDBEN 208b 225W 225WH Address Extended Address 208a Output Data 216a 223W
SDDIR
(HIGH)
NOTES: 8-bit 80x8x mode, SBHE/SRNW don't care input during inactive (high) output during DMA. 8-bit 80x8x mode, most significant byte address maintained SADH address maintained according parameter i.e., held after high.
Figure 80x8x Mode Write Timing
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 80x8x mode arbitration timing, returns control
223b 224b 224d PARAMETER Delay from SBCLK cycle SADH0-SADH7, SADL0-SADL7, SPL, SPH, SRD, high-impedance Delay from SBCLK cycle SBHE high-impedance Delay from SBCLK cycle SOWN high Delay from SBCLK cycle SDDIR high Delay from SBCLK high cycle SHRQ Setup SRD, SWR, SBHE high-impedance before SOWN longer UNIT
This specification been characterized meet stated value.
Master SBCLK
Exchange (T1)
User Master (T2)
SHLDA Outputs: SHRQ (see Note SRD, 223b SBHE SADH0-SADH7, SADL0-SADL7, SPH, SDDIR READ 224b SOWN (see Note NOTES: 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. While system interface controls active (i.e., SOWN asserted), input disabled. 224d WRITE HI-Z HI-Z HI-Z
Figure 80x8x Mode Arbitration Timing, Returns Control
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PARAMETER MEASUREMENT INFORMATION 80x8x mode release timing
208a 208b 208c PARAMETER Setup asynchronous input SBRLS before SBCLK longer high guarantee recognition Hold asynchronous input SBRLS after SBCLK guarantee recognition Hold SBRLS after SOWN high SBCLK 208a SBRLS (see Note 208b UNIT
SOWN 208c NOTES: System Interface ignores assertion SBRLS does system bus. does bus, then when detects assertion SBRLS, will complete internally started cycle relinquish control bus. transfer internally started, then System Interface will release before starting another. SBERR asserted when System Interface controls system bus, then current transfer completed, regardless value SRDY. BERETRY register non-zero, cycle will retried. BERETRY register zero, System Interface will then release control system bus. System Interface ignores assertion SBERR performing cycle system bus. When SBERR properly asserted BERETRY zero, however, System Interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX, SDMALEN registers System Interface defined after system error. cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment Address Register carries beyond least significant bits. SDTACK sampled verify that deasserted. Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high-impedance) until start that SBCLK transition.
Figure 80x8x Mode Release Timing
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PARAMETER MEASUREMENT INFORMATION 68xxx read timing
261a 273a 282a 282R 283R PARAMETER Delay from SDTACK either SCS, SUDS, SLDS high Hold high-impedance after SUDS SLDS (see Note Setup SADH0-SADH7, SADL0-SADL7, SPH, valid before SDTACK Delay from SCS, SUDS, SLDS high SADH0-SADH7, SADL0-SADL7, SPH, high-impedance (see Note Hold output data valid after SUDS SLDS longer (see Note Setup register address before SUDS SLDS longer high (see Note Hold register address valid after SUDS SLDS longer (see Note Setup SRNW before SUDS SLDS longer high (see Note Hold SRNW after SUDS SLDS high Hold SIACK high after SUDS SLDS high Delay from SCS, SUDS, SLDS high SDTACK high (see Note Delay from SDTACK first access register SDTACK immediately following access Delay from SUDS SLDS high SDTACK high impedance Delay from SDBEN SDTACK Delay from SUDS SLDS SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) provided previous cycle completed Delay from SUDS SLDS high SDBEN high (see Note 4000 UNIT
Pulse duration, SUDS SLDS high between accesses (see Note This specification provided board design. This specification been characterized meet stated value. NOTES: "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, then parameters 266a irrelevant, parameter must met.
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PARAMETER MEASUREMENT INFORMATION
SCS, SRSX, SRS0, SRS1 SIACK
Valid
273a SRNW SUDS, SLDS SDDIR (High) 282R 283R SDBEN SDTACK HI-Z 282a SADH0-SADH7, SADL0-SADL7, SPH, HI-Z 261a Output Data Valid HI-Z HI-Z
SDTACK active-low ready signal. must asserted before data output.
Figure 68xxx Read Timing
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PARAMETER MEASUREMENT INFORMATION 68xxx write timing
272a 273a 281a PARAMETER Delay from SDTACK either SCS, SUDS SLDS high Setup write data valid before SUDS SLDS longer Hold write data valid after SUDS SLDS high Setup register address before SUDS SLDS longer high (see Note Hold register address valid after SUDS SLDS longer (see Note Setup SRNW before SUDS SLDS longer high (see Note Setup inactive SUDS SLDS high active data strobe longer high Hold SRNW after SUDS SLDS high Hold inactive SUDS SLDS high after active data strobe high Delay from SCS, SUDS SLDS high SDTACK high (see Note Delay from SDTACK first access register SDTACK immediately following access Delay from SUDS SLDS high SDTACK high impedance Delay from SUDS SLDS SDDIR (see Note Delay from SUDS SLDS high SDDIR high (see Note Hold SDDIR after SUDS SLDS longer active (see Note register ready waiting required) register ready (waiting required) 4000 4000 UNIT
282b
Delay from SDBEN SDTACK (see TMS380 Second Generation TokenRing User's Guide, SPWU005, subsection 3.4.1.1.1)
282W 283W
Delay from SDDIR SDBEN Delay from SUDS SLDS high SDBEN longer
Pulse duration, SUDS SLDS high between accesses (see Note This specification provided board design. This specification been characterized meet stated value. later that indicates start cycle. NOTES: "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles. 80x8x mode, SRAS used strobe values SBHE, SRSX, SRS0-SRS2, SCS. When used SRAS must meet parameter 266a, SBHE, SRS0-SRS2, must meet parameter 264. SRAS strapped high, then parameters 266a irrelevant, parameter must met.
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PARAMETER MEASUREMENT INFORMATION
SRSX, SRS0, SRS1 SIACK SRNW 272a SUDS, SLDS (see Note 273a SDDIR (High) 282W SDBEN SDTACK HI-Z 282b SADH0-SADH7, SADL0-SADL7, SPH, HI-Z (see Note Data HI-Z HI-Z 283W 281a 273a
Valid
SDTACK active-low ready signal. must asserted before data output. When TMS380C16 begins drive SDBEN inactive, already latched write date internally. Parameter must input data buffers. NOTE 68xxx mode, skew between SLDS SUDS must exceed Provided this limitation observed, events referenced data strobe edge later occurring edge. Events defined data strobes edges, such parameter 286, measured between latest earlier edges.
Figure 68xxx Write Timing
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PARAMETER MEASUREMENT INFORMATION 68xxx interrupt acknowledge cycle timing
261a 272a 273a 282a 282R 283R PARAMETER Delay from SDTACK either SUDS, SIACK high Hold high-impedance after SIACK longer high (see Note Setup output data valid before SDTACK longer high Delay from SIACK high high-impedance (see Note Hold output data valid after SIACK longer (see Note Setup register address before SIACK longer high (see Note Setup inactive high SIACK active data strobe longer high Hold inactive SRNW high after active data strobe high Delay from SRNW high SDTACK high (see Note Delay from SDTACK first access register SDTACK immediately following access Delay from SIACK high SDTACK high impedance Delay from SDBEN SDTACK read cycle Delay from SIACK SDBEN (see TMS380 Second Generation Token-Ring User's Guide, SPWU005, subsection 3.4.1.1.1) provided previous cycle completed Delay from SIACK high SDBEN high (see Note Pulse duration, SIACK high between accesses (see Note 4000 UNIT
This specification provided board design. This specification been characterized meet stated value. later that indicates start cycle. NOTE "inactive" chip select SIACK read write cycles, "inactive" chip select interrupt acknowledge cycles.
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PARAMETER MEASUREMENT INFORMATION
SCS, SRSX, SRS0, SRS1, SBHE
Only needs Inactive. Others Don't Care.
SIACK 272a SRNW 273a SLDS SDDIR (High) 282R 283R SDBEN 282a SDTACK HI-Z SADH0-SADH7, SADL0-SADL7, SPH, (see Note 261a HI-Z Output Data Valid HI-Z HI-Z
SDTACK active-low ready signal. must asserted before data output. NOTE Internal logic will drive SDTACK high verify that reached valid high level before three-stating signal.
Figure 68xxx Interrupt Acknowledge Cycle Timing
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PARAMETER MEASUREMENT INFORMATION 68xxx mode arbitration timing, takes control
208a 208b 224a 224c 241a PARAMETER Setup asynchronous input SBGR before SBCLK longer high guarantee recognition this cycle Hold asynchronous input SBGR after SBCLK guarantee recognition this cycle Delay from SBCLK address valid Delay from SBCLK cycle SOWN (see Note Delay from SBCLK cycle SDDIR read Delay from SBCLK high either SHRQ SBRQ high Delay from SBCLK high cycle SUDS SLDS high Hold SUDS, SLDS, SRNW, high-impedance after SOWN low, acquisition tc(SCK) UNIT
This specification been characterized meet stated value. NOTE Motorola-style slaves hold SDTACK active until master deasserts SAS.
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User Master Inputs: SBCLK (T4) SBGR SBERR, SDTACK, SBBSY Outputs:
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PARAMETER MEASUREMENT INFORMATION
Exchange Master
208b 208a
SBRQ (see Note 208a SAS, SLDS, SUDS 208b Output READ SRNW WRITE SADH0-SADH7, SADL0-SADL7, SPH, HI-Z 224c WRITE SDDIR READ 224a SOWN (see Note 241a
(Input)
NOTES: 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. While system interface controls active (i.e., SOWN asserted), input disabled.
Figure 68xxx Mode Arbitration Timing, Takes Control
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 68xxx mode read timing
207a 207b 208a 208b 216a 223R 225R 233a 237R PARAMETER Setup input data valid before SBCLK cycle longer high Hold input data valid after SBCLK cycle parameters 207a 207b Hold input data valid after data strobe longer Hold input data valid after SDBEN longer Setup asynchronous input SDTACK before SBCLK longer high guarantee recognition this cycle Hold asynchronous input SDTACK after SBCLK guarantee recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay from SBCLK high cycle SUDS SLDS active Delay from SBCLK address valid Delay from SBCLK cycle high-impedance Pulse duration, SALE SXAL high Delay from SBCLK high SALE SXAL high Hold SALE SXAL after SUDS high Delay from SBCLK high SXAL cycle SALE cycle Hold address valid after SALE, SXAL Delay from SBCLK high Delay from SBCLK cycle SUDS, SLDS, high (see Note Delay from SBCLK cycle SDBEN high Hold high-impedance after SBCLK cycle Setup address valid before SALE SXAL longer high Setup address valid before longer high Delay from SBCLK high cycle SDBEN Pulse duration, SAS, SUDS, SLDS 2tc(SCK)+ tw(SCKH) tw(SCKL) tw(SCKL) tw(SCKH) tw(SCKL) tc(SCK) tc(SCK)+ tw(SCKL) UNIT
Setup data valid before SDTACK parameter 208a This specification been characterized meet stated value. NOTE While system interface controls active (i.e., SOWN asserted), input disabled.
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SBCLK (see Note SUDS, SLDS
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PARAMETER MEASUREMENT INFORMATION
TWAIT
223R (High) SRNW SXAL SALE SADL0-SADH7, SADH0-SADL7, SPH, SDTACK (see Notes 208b SDDIR 237R SDBEN (see Note parameter 208a met, then valid data must present before SDTACK goes low. NOTES: Motorola-style slaves hold SDTACK active until master deasserts SAS. pins should routed minimize inductance system ground. read cycle, read strobe remains active until internal sample incoming data completed. Input-data removed when either read strobe SDBEN becomes longer active. 225R 233a Address Extended Address 208a Data 207a HI-Z 207b 216a
Figure 68xxx Mode Read Timing
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 68xxx mode write timing
208a 208b 211a 216a 223W 225W 225WH 233a 237W PARAMETER Setup asynchronous input SDTACK before SBCLK longer high guarantee recognition this cycle Hold asynchronous input SDTACK after SBCLK guarantee recognition this cycle Pulse duration, SAS, SUDS, SLDS high Delay from SBCLK high cycle SUDS SLDS active Delay output data valid SUDS SLDS longer high Delay from SBCLK address valid Pulse duration, SALE SXAL high Delay from SBCLK high SALE SXAL high Hold SALE SXAL after SUDS high Delay from SBCLK high SXAL cycle SALE cycle Hold address valid after SALE, SXAL Delay from SBCLK cycle output data parity valid Hold output data, parity valid after SUDS SLDS high Delay from SBCLK high Delay from SBCLK SUDS, SLDS, high Delay from SBCLK high cycle SDBEN high Hold SDBEN after SUDS SLDS high Setup address valid before SALE SXAL longer high Setup address valid before longer high Delay from SBCLK high cycle SDBEN pulse duration Pulse duration, SUDS SLDS 2tc(SCK)+ tw(SCKH) tc(SCK)+ tw(SCKH) tw(SCKL) tw(SCKL) tw(SCKL) tc(SCK) tw(SCKH) tw(SCKL) tc(SCK) tw(SCKL) tc(SCK)+ tw(SCKL) UNIT
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SBCLK SUDS, SLDS SRNW
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PARAMETER MEASUREMENT INFORMATION
TWAIT
223W
233a 211a SXAL SALE SADL0-SADH7, SADH0-SADL7, SPL, Extended Address SDTACK (see Notes 208b 225W SDDIR SDBEN NOTES: pins should routed minimize inductance system ground. read cycle, read strobe remains active until internal sample incoming data completed. Input-data removed when either read strobe SDBEN becomes longer active. 237W 225WH Address Output Data 208a 216a
Figure 68xxx Mode Write Timing
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 68xxx mode arbitration timing, returns control
223b 224b 224d PARAMETER Delay from SBCLK cycle SAD, SPL, SPH, SUDS, SLDS high-impedance, release Delay from SBCLK cycle SBHE/SRNW high-impedance Delay from SBCLK cycle SOWN high Delay from SBCLK cycle SDDIR high Delay from SBCLK high either SHRQ SBRQ high Setup SUDS, SLDS, SRNW, control signals high-impedance before SOWN longer UNIT
This specification been characterized meet stated value.
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Inputs: SBCLK SBGR SDTACK Outputs:
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PARAMETER MEASUREMENT INFORMATION
Master Exchange User
SBRQ (see Note SAS, SUDS, SLDS 223b READ SRNW WRITE SADH0-SADH7, SADL0-SADL7, SPH, 224d WRITE SDDIR READ 224b SOWN NOTE 80x8x mode, system interface deasserts SHRQ rising edge SBCLK following state last system transfer controls. 68xxx mode, system interface deasserts SBRQ rising edge SBCLK state first system transfer controls. HI-Z HI-Z
Figure 68xxx Mode Arbitration Timing, Returns Control
TMS380C26 NETWORK COMMPROCESSOR
PARAMETER MEASUREMENT INFORMATION 68xxx mode release error timing
208a 208b 208c PARAMETER Setup asynchronous input before SBCLK longer high guarantee recognition Hold asynchronous input SBRLS, SOWN, SBERR after SBCLK guarantee recognition Hold SBRLS after SOWN high Setup SBERR before SDTACK longer high parameter 208a UNIT
SBCLK 208a SBRLS (see Note SOWN
208b
208b 208a 208c
SBERR (see Note SDTACK NOTES: System Interface ignores assertion SBRLS does system bus. does bus, then when detects assertion SBRLS, will complete internally started cycle relinquish control bus. transfer internally started, then System Interface will release before starting another. SBERR asserted when System Interface controls system bus, then current transfer completed, regardless value SDTACK. BERETRY register non-zero, cycle will retried. BERETRY register zero, System Interface will then release control system bus. System Interface ignores assertion SBERR performing cycle system bus. When SBERR properly asserted BERETRY zero, however, System Interface releases upon completion current transfer halts further system side. error synchronized local stops local sides. value SDMAADR, SDMADDRX, SDMALEN registers System Interface defined after system error. cycle-steal mode, state present every system transfer. burst mode, state present first transfer whenever increment Address Register carries beyond least significant bits. SDTACK sampled verify that deasserted. Unless otherwise specified, signals specified maximum delay from SBCLK transition signal valid, signal also specified hold previous value (including high-impedance) until start that SBCLK transition.
Figure 68xxx Mode Release Error Timing
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PARAMETER MEASUREMENT INFORMATION
normal completion with delayed start
SBCLK
SDTACK
SBERR
SHALT
rerun cycle with delayed start
SBCLK
SDTACK
SBERR
SHALT
SOWN Only relative placement edges SBCLK falling edge shown. Actual signal edge placement vary from waveforms shown.
Figure 68xxx Halt Retry Cycle Waveforms
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MECHANICAL DATA JEDEC plastic leaded quad flat package suffix)
Each these chip carrier packages consists circuit mounted lead frame encapsulated within electrically nonconductive plastic compound. compound withstands soldering temperatures with deformation, circuit performance characteristics remain stable when devices operated high-humidity conditions. packages intended surface mounting solder lands 0,635 (0.025) centers. Leads require additional cleaning processing when used soldered assembly.
0,254 (0.010) 0,635 (0.025)
4,57 (0.180) 4,06 (0.160) 0,76 (0.030)
JEDEC OUTLINE MO-069-AD MO-069-AE
TERMINALS
15,32 (0.603) 20,40 (0.803)
15,16 18,97 19,13 22,28 22,43 (0.877) (0.883) (0.747) (0.753) (0.597) 27,36 27,50 24,05 24,21 20,24 (1.077) (1.083) (0.947) (0.953) (0.797)
LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOM
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