Integrated serial communications controller system core logic device
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Remote Access Coprocessor
Integrated serial communications controller system core logic device
Direct interface i960®Jx family CPUs
GT-96010A
Preliminary Revision 8/21/98
Please contact Galileo Technology possible updates before finalizing design.
Interface i960Hx i486 with minimal glue logic Interface RC32364, Motorola Coldfire, PowerPC 401GF with minimal glue logic DRAM controller 128Mbyte address space 256K-4M device depth banks supported directly device controller chip selects Programmable timing 8-,16- 32-bit width device support Four timer/counters 2-stage watchdog timer (NMI, Reset) 16-bit general purpose port Simple control Inputs generate maskable interrupt general purpose pins read/write operations Engines serial channels support communications controllers Moves data between communications controllers DRAM independent memory memory, device memory, device device data movement Chaining linked list descriptors Supports cascaded GT-96010A system design Perfect Filtering Ethernet Controller
10/20-Mbps full duplex Direct interface external devices Perfect filtering 8,000 addresses (both physical multicast) Recognizes broadcast addresses Multi-Protocol Serial Controllers (MPSCs) channels supporting HDLC, BISYNC, Transparent UART protocols channels have simultaneous guaranteed bandwidth 2Mbit/s full-duplex channel guaranteed bandwidth 8Mbit/s full-duplex (independent 2Mbit channels) Capable ADSL (8Mbit/sec 1Mbit/sec) rate operation multiple channels simultaneously drive dedicated pins TDMs Dedicated DPLL clock recovery data encoding/decoding Supports NRZ, NRZI, FM0, FM1, Manchester Differential Manchester Flex-TDM channels Time slot assigner serial control channels Supports Basic Rate ISDN interfaces (2B+D) IDL-10 mode Fully programmable dual-port memory Supports HDLC over asynchronous channel UART mode Four baud rate generators with multiple clock sources Advanced interrupt controller Drives priority encoded vector Allows implementation style autovector 3.3V supply, tolerant 208-pin PQFP Industrial Temperature range (-40 +85C)
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i960Jx
ADDR LEDS
DRAM
GT-96010A
FLASH
IDL/ ETH-SIA ISDN 2B+D ADSL down/ 640Kb EIA-232 Drivers EIA-232
Cost ISDN/ADSL Remote Access System Configuration using GT-96010A
www.galileoT.com
info@galileoT.com
Tel: +1-408.367.1400
Fax: +1-408.367.1401
GT-96010A Remote Access Coprocessor
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Table Contents
Introduction
Communications Unit Core Logic Functions Logic Symbols. Functions Assignments Interface Arbitration. Address Space Decode DRAM Controller Device Controller 3.6.1 Serial Features (SDMA) 3.6.2 Independent Features (IDMA) Communications Unit. General Purpose Port. Watchdog Timer Timer/Counters Reset Configuration Interrupts Revision Register Access Register Map. Address Space Decoding Register Definitions 4.4.1 DRAM, Device, Internal Address Decode Registers
4.4.1.1 4.4.1.2 4.4.1.3 4.4.1.4 4.4.1.5 4.4.1.6 DRAM Address Space, Offset: 0x000. Device Address Space, Offset: 0x004 Device Address Space, Offset: 0x008 Device Address Space, Offset: 0x00C. Boot Device Address Space, Offset: 0x010 Internal Address Space Decode Control, Offset: 0x01C RAS[0] Decode Address, Offset: 0x400 RAS[1] Decode Address, Offset: 0x404 RAS[2] Decode Address, Offset: 0x408 RAS[3] Decode Address, Offset: 0x40 CS[0] Decode Address, Offset: 0x410 CS[1] Decode Address, Offset: 0x41 CS[2] Decode Address, Offset: 0x418 BootCS Decode Address, Offset: 0x41c. Refresh Configuration, Offset: 0x420 DRAM Parameters, Offset: 0x424 Device Bank0 Parameters, Offset: 0x428 Device Bank1 Parameters, Offset: 0x42c Device Bank2 Parameters, Offset: 0x430
Information
Functional Overview.
3.10 3.11 3.12 3.13
Address Space
4.4.2
Decode Registers
4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4
4.4.3
Decode Registers
4.4.3.1 4.4.3.2 4.4.3.3 4.4.3.4
4.4.4 4.4.5 4.4.6
DRAM Refresh Configuration Registers
4.4.4.1 4.4.5.1 4.4.6.1 4.4.6.2 4.4.6.3
DRAM Parameter Registers Device Parameter Registers
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4.4.6.4
Device Boot Bank Parameters, Offset: 0x434
4.4.7 4.4.8 4.4.9
Descriptors RAM. MPSC Address Space Internal Registers
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IDMA.
IDMA Record IDMA Channel Byte Count (IBC), Offset: 0x1800 IDMA Channel Source Pointer (ISP), Offset: 0xT804 IDMA Channel Destination Pointer (IDP), Offset: 0x1808 IDMA Channel Next Record Pointer (INP), Offset: 0x180C IDMA Channel Command. 5.2.1 IDMA Channel Command (ICM), Offset: 0x1820 IDMA Cascaded GT-96010A Designs IDMA Error IDMA Programming Notes 5.5.1 Initialization: 5.5.2 Restarting disabled IDMA: 5.5.3 Burst Size 5.5.4 Reprogramming active IDMA: 5.5.5 IDMA Byte Swap.
5.1.1 5.1.2 5.1.3 5.1.4
Timer/Counters
Timer/Counters Register Timer/Counters Mode Register (TCMR). Timer/Counters Configuration Register (TCCR). 32-bit Counter Operation Gating Operation Generation Pulses Waveforms Capturing External Events Using External Clocks Watchdog Register Watch Configuration (WDC) 7.2.1 Watch Value register (WDV) Watchdog Operation. General Purpose Ports Register Map. General Purpose Pins A/B/C 8.2.1 GPPA/B/C Configuration Registers (GPPA, GPPB, GPPC). General Purpose Interface 8.3.1 Configuration Register (GPCR) 8.3.2 Value Register (GPVR) 8.3.3 Interrupts Overview.
Watchdog Timer.
General Purpose Ports
Communications.
Address/Data Arbitration.
10.1 Arbitration Priority Scheme. 10.2 BSTAT.
Serial (SDMA)
11.1 Overview. 11.2 SDMA Descriptors
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11.2.1 11.2.2 11.2.3 11.2.4 11.2.5
Command/Status, Offset: Buffer Size, Byte Count Descriptor), Offset: Byte Count, Shadow Byte Count Descriptor), Offset: Buffer Pointer, Offset: Next Descriptor Pointer, Offset:
11.3 SDMA configuration register (SDC) 11.3.1 SDMA Configuration Register (SDCx). 11.4 SDMA Command Register (SDCMx) 11.4.1 SDMA Command Register (SDCMx). 11.5 SDMA Descriptor Pointer Registers 11.5.1 SDMA Current Receive Descriptor Pointer (SCRDP) 11.5.2 SDMA Current Transmit Descriptor Pointer (SCTDP) 11.5.3 SDMA First Transmit Descriptor Pointer (SFTDP) 11.6 Transmit SDMA. 11.6.1 Transmit SDMA Definitions 11.6.2 Transmit SDMA Flow. 11.6.3 Retransmit HDLC (LAP-D) mode. 11.6.4 Transmit SDMA Notes 11.7 Receive SDMA 11.7.1 Receive SDMA Definitions. 11.7.2 Receive SDMA Flow 11.7.3 Notes 11.8 SDMA Interrupt Mask register (SDI SDM) 11.8.1 Resource Error Interrupt 11.8.2 Descriptor Closed Interrupt 11.9 SDMA Auto Mode
Baud Rate Generators (BRGs).
12.1 12.2 12.3 12.4 Inputs Outputs Baud Tuning Configuration Register (BCR) Format Baud Tuning register (BTR) Format.
Multi Protocol Serial Controller (MPSC)
13.1 DPLL 13.1.1 Data Encoding/Decoding 13.1.2 DPLL Clock Source 13.1.3 Receive DPLL Clock Recovery 13.2 MPSCx Main Configuration Register (MMCRx) 13.2.1 MPSCx Main Configuration Register (MMCRLx) 13.2.2 MPSCx Main Configuration Register High (MMCRHx) 13.3 MPSCx Protocol Configuration Registers (MPCRx) 13.4 Channel Registers (CHxRx) 13.5 HDLC Mode 13.5.1 HDLC Receive/Transmit Operation 13.5.2 SDMAx Command/Status Field HDLC Mode 13.5.3 MPSCx Protocol Configuration Register (MPCRx) HDLC 13.5.4 Channel Registers (CHxRx) HDLC Mode
13.5.4.1 13.5.4.2 13.5.4.3 13.5.4.4 13.5.4.5 13.5.4.6 13.5.4.7 13.5.4.8 13.5.4.9 CHR1 Sync/Abort Register (SYNR) CHR2 Command Register (CR) CHR3 Maximum Frame Length Register (MFLR). CHR4 Address Filtering Register (ADFR). CHR5 Short Frame Register (SHFR) CHR6 Address Register (ADLR) CHR7 Address Register (ADHR) CHR8 Reserved CHR9 Reserved
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13.5.4.10 CHR10 Event Status Register (ESR)
13.6 BISYNC Mode 13.6.1 BISYNC Transmit Operation. 13.6.2 BISYNC Receive Operation
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13.6.2.1 13.6.2.2
BISYNC Normal Receive Mode. BISYNC Auto Transparent Receive Mode.
13.6.3 13.6.4 13.6.5
SDMAx Command/Status Field BISYNC Mode. MPSCx Protocol Configuration Register (MPCRx) BISYNC Channel Registers (CHxRx) BISYNC Mode
13.6.5.1 13.6.5.2 13.6.5.3 13.6.5.4 13.6.5.5 13.6.5.6 CHR1 SYNC/DLE Register (SDR) CHR2 Command Register (CR) CHR4 Control Filtering Register (CFR) CHR5-8 BISYNC Control Character Registers CHR9 Reserved CHR10 BISYNC Event Status Register (ESR)
13.7 UART Mode .105 13.7.1 UART Receive/Transmit Operation
13.7.1.1 13.7.1.2 Asynchronous Mode Isochronous Mode
13.7.2 13.7.3 13.7.4 13.7.5
SDMAx Command/Status Field UART Mode MPSCx Protocol Configuration Register (MPCRx) UART Mode UART Stop Reception Framing Error Channel Registers (CHxRx) UART Mode
13.7.5.1 13.7.5.2 13.7.5.3 13.7.5.4 13.7.5.5 13.7.5.6 13.7.5.7
CHR1 UART Break/Stuff Register (UBSR) CHR2 Command Register (CR) CHR3 Idle Register (MIR) CHR4 Control Filtering Register (CFR) CHR5-8 UART Control Character Registers CHR9 Address Register (ADR) CHR10 UART Event Status Register (ESR)
13.8 Transparent Protocol .115 13.8.1 SDMAx Command/Status Field Transparent Mode. 13.8.2 Channel Registers (CHxRx) Transparent Mode
13.8.2.1 13.8.2.2 13.8.2.3 CHR1 SYNC Register (SYNR) CHR2 Command Register (CR) CHR10 Transparent Event Status Register (ESR)
Ethernet Controller
14.1 14.2 14.3 14.4 14.5 14.6 Ethernet Configuration Register (ECR) .120 Ethernet Command Register (ECMR) .123 Ethernet Counters Register (EMCR) .125 Ethernet Event Register (EEVR) .126 Ethernet Hash Table Pointer (EHTP) .126 Ethernet Descriptor Command/Status Field .127
Flex-TDM Units (FTDM)
Flex-TDM Registers .130 Flex-TDM Micro Architecture .130 Flex-TDM DPRAM .130 Flex-TDM Programing Modes .132 Flex-TDM Configuration (TCR) .133 Flex-TDM Synchronization .134 Mode .135 15.7.1 IOM1 Frames 15.7.2 IOM2-TE Frames 15.7.3 IOM2-CL Frames 15.8 IDL-10 Mode. .136 15.9 Highway Mode .137 15.1 15.2 15.3 15.4 15.5 15.6 15.7
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GT-96010A Remote Access Coprocessor
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15.10 Data Rate Adoption. 15.11 Flex-TDM Auxiliary Channels 15.11.1 Auxiliary Channel 15.11.2 Auxiliary Channel 15.12 GCI/IDL-10 Programing 15.12.1 GCI/IDL-10 Programming 15.12.2 IOM2-TE1 GCI/IDL-10 Programming 15.12.3 IOM2-CL (Connected channel GCI/IDL-10 Programming 15.12.4 IDL-10 GCI/IDL-10 Programming 15.13 Transparent Channel over
Serial Control Port (SCP)
16.1 16.2 16.3 16.4 Registers. Configuration Register (SCPC). Transmit Data Receive Data Registers (SCTD SCRD) Transmit/Receive Format
Interrupt Controller
17.1 17.2 17.3 17.4 Interrupt Priority Structure Interrupt Vector Mapping. Interrupt Register Interrupt Cause registers. 17.4.1 ICR1 SDMA IDMA Cause Register 17.4.2 ICR2, ICR3, ICR4 MPSCx Cause Registers
17.4.2.1 17.4.2.2 17.4.2.3 17.4.2.4 MPSCx Cause Register (HDLC Mode) .150 MPSCx Cause Register (BISYNC Mode) .150 MPSC Cause Register (UART Mode). .151 MPSC Cause Register (Transparent Mode) .151
17.4.3 17.4.4
ICR5 Ethernet, Flex-TDM Cause Register ICR6 GPI, SCP, Baud Tuning, Timer/Counter Cause Register
17.5 Interrupt Mask Registers (IMSK).
RESTRICTIONS
18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 Interface Device Controller Memory Mapping IDMA SDMA MPSCs Flex TDM. Cascaded GT-96010A Systems
Physical Signal Routing
19.1 Signal Routing. 19.2 Clock Routing 19.2.1 Clock Routing Register (RCRR). 19.2.2 Clock Routing Register (TCRR)
Mechanical Data.
20.1 PQFP (sorted number) 20.2 PQFP Package. 20.2.1 LEAD PQFP PACKAGE OUTLINE.
CHARACTERISTICS PRELIMINARY/SUBJECT CHANGE
21.1 Absolute Maximum Ratings 21.2 Recommended Operating Conditions 21.3 Electrical Characteristics Over Operating Range
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TIMING PRELIMINARY/SUBJECT CHANGE
Parallel (System) Clock Domain Characteristic .168 Interrupt Controller Characteristic. .170 Timing Reduced Loads .170 Parallel Clock Wave Forms .171 22.4.1 DRAM Access. 22.4.2 Slave GT-96010A Access External DRAM 22.4.3 Device Controller 22.5 Serial (Communication) Clock Domain Characteristic .179 22.5.1 Flex-TDM Receive Timing Normal Clock 22.5.2 Flex-TDM Transmit Timing Normal Speed Clock 22.5.3 Flex-TDM Timing. 22.5.4 Flex-TDM Receive Timing Double Speed Clock 22.5.5 Flex-TDM Transmit Timing Double Speed Clock 22.5.6 Receive Timing 22.5.7 Transmit Timing 22.5.8 Wave Forms. 22.5.9 Ethernet Collision Timing 22.5.10 Ethernet Receive Timing. 22.5.11 Ethernet Transmit Timing 22.5.12 Timing (CP=0) 22.5.13 Timing (CP=1) 22.6 JTAG Characteristics .190 22.1 22.2 22.3 22.4
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Boundary Scan (JTAG).
IEEE Standard 1149.1 .191 Controller .191 Instruction Register (IR) .191 Bypass Register (BR) .191 Boundary Scan Chain. .191 Register .191 23.6.1 Manufacturer Code. 23.6.2 Part Number 23.6.3 Version Number 23.6.4 23.7 Performance .192 23.8 BSDL File .192 23.1 23.2 23.3 23.4 23.5 23.6
GT-96010A GT-96010 Revision History.
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GT-96010A Remote Access Coprocessor
Introduction
GT-96010A Remote Access Controller advanced communications peripheral designed wide area networking remote access market. GT-96010A provides system peripherals needed build wide array devices including edge routers, remote access equipment, ISDN/xDSL adapters.
Communications Unit
core GT-96010A high-performance communications unit. This unit includes multi-protocol serial controllers, perfect filtering Ethernet controller, Flex-TDM time slot assigners engines. GT-96010A directly support many interfaces including ISDN (two channels), frame relay, T1/E1, xDSL 8Mbit/s.) multi-protocol serial controllers (MPSCs) integrated GT-96010A support UART, HDLC, BISYNC, transparent protocols. Five MPSCs support guaranteed minimum full-duplex data rates 2Mbps supports guaranteed full-duplex data rates 8Mbps. Asymmetric protocols, such ADSL, multiple channels 8Mbit 1Mbit (see MPSC chapter performance details.) MPSCs implemented hardware, thus allowing superior performance compared microcoded implementations. HDLC mode, MPSCs perform framing operations such stuffing/stripping flag generation, part data link operations (e.g. address recognition functions). MPSCs directly support common HDLC protocols including those used ISDN frame relay. Each MPSC communicate over dedicated package pins through Flex-TDM time slot assigners. There Flex-TDM channels (time slot assigners) GT-96010A. Flex-TDMs support Highway, IOM1, IOM2 (GCI), IDL10 formats allow connection most framer devices. Flex-TDM unit includes auxiliary channels that multiplexed onto highway with data from MPSCs. They optimized supporting Monitor channels. GT-96010A also includes controller support bus. There 10/20-Mbps full duplex Ethernet controller GT-96010A that supports industry's most popular SIAs (Serial Interface Adapters, also called "PHYs"). GT-96010A's Ethernet controller includes Galileo's advanced address filtering capability programmed accept reject packets based addresses, thus allowing complicated bridging, routing, firewall capabilities accelerated hardware. 8,000 individual addresses filtered. Ethernet controller also supports backpressure half-duplex mode `drop packets' half duplex full duplex mode. communications capability GT-96010A significantly exceeds that other solutions market today. table below shows number typical technologies that directly supported single GT-96010A device. Note that performance values this table largely unaffected traffic separate Ethernet controller. Table GT-96010A Serial Performance Typical Applications Technology Basic rate ISDN Non-Channelized E1/T1 MDSL/HDSL Frame Relay rate) ADSL Number Channels Performance/Comment 2B+D channels directly supported HDLC controllers Flex-TDMs. Full speed full-duplex 2.048Mbits/sec.
8Mbit/sec downstream (Tx), 1Mbit/sec upstream (Rx) HDLC framing. Performance gated other serial-interface/DMA/CPU activity.
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GT-96010A Remote Access Coprocessor
Table GT-96010A Serial Performance Typical Applications Technology ADSL Number Channels Performance/Comment 8Mbit/sec upstream (Rx), 1Mbit/sec downstream (Tx) HDLC framing. Performance gated other serial-interface/DMA/CPU activity. Full-duplex 20-Mbps. Ethernet traffic does materially affect performance other serial interfaces except under extreme load conditions.
Ethernet
Core Logic Functions
addition communications engines, GT-96010A provides core logic needed build high-performance i960-based system. GT-96010A directly controls system DRAM, ROM, Flash, peripherals. Also included four baud rate generators, four 16-bit general purpose counters (cascadable into 32-bit counters), bits general purpose pins, 16-bit general purpose interface (GPI). inputs routed on-chip interrupt controller request interrupt service. on-chip interrupt controller provides 5-bit encoded vector that directly compatible with i960 mixed-mode interrupts. interrupt vector also used generate style autovectors with minimal glue logic. Customers wishing GT-96010A with based processors (such i960RP) bridge GT96010A's local using inexpensive bridge devices (please check website information.)
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GT-96010A Remote Access Coprocessor
Information
Logic Symbols
ECRS#\CTS6# ECDT#\CD6# ERXC#\SCLK6 ERXD\RXD6 ETEN#\RTS6# ETXC#\TSCLK6 ETXD\TXD6
CLK1 CLK2 CLK3 CLK4 BRGO1 BRGO2 BRGO3 BRGO4 TGATE1# TGATE2# TO1# TO2# TO3# TO4# W/R# ADS# HoldA Hold RdyRcv# BE#[3:0] BSTAT BLAST# AD[31:0] DAdr[10:0] RAS#[3:0] CAS#[3:0] DWr# DMAReq# DMAAck#
SAUX
PORT
Eport/MPSCP6
PORT
MPSC1/GPP
RXD1/GPP16 TXD1/GPP17 RTS1#/GPP18 CTS1#/GPP19 CD1#/GPP20 SCLK1
DRAM
PORT
MPSC2/GPP
RXD2/GPP21 TXD2/GPP22 RTS2#/GPP23 CTS2#/GPP24 CD2#/GPP25 SCLK2
GT-96010A
PORT
MPSC3/GPP/SCP RXD3/GPP26/SCRX TXD3/GPP27/SCTX RTS3#/GPP28/SCCLK CTS3#/GPP29 CD3#/GPP30 SCLK3 TDSTRB1[1:0] TDCLK1 TRXD1/RXD4 TTXD1/TXD4 TRCLK1/SCLK4 TTCLK1/TSCLK4 TTSYNC1 TRSYNC1/CD4# TDREQ1/RTS4# TDGNT1/CTS4#
AdBusGnt AdBusReq BootCS# DevCS#[2:0] We#[3:0] Ready# BufOE#
Device
RST# INT#[4:0] NMI# WDE#
PORT
TDM1/MPSC4
Test PORT
TDM2/MPSC5
Revision
TDGNT2\CTS5# TDREQ2\RTS5# TRSYNC2\CD5# TTSYNC2 TTCLK2\TSCLK5 TRCLK2\SCLK5 TTXD2\TXD5 TRXD2\RXD5 TDCLK2 TDSTRB2[1:0]
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GPI[15:0]
TRST TCLK
GT-96010A Remote Access Coprocessor
Functions Assignments
Width Name Description
Symbol Interface AD[31:0] W/R#
Address/Data Address latch Write/Read#
Multiplexed address data communication between processor, devices, GT-96010A. strobe latching address GT-96010A external latch device addresses. Indicates access write read access. input during external master access output during access. Indicates valid address starts transition. indication that processor relinquished GT-96010A. request from GT-96010A acquire bus. Indicates that data sampled removed. During device turn time, tells drive address bus. Indicates last transfer access. BLAST# asserted last data transfer burst non-burst accesses. BLAST# remains active long wait states inserted RdyRcv# pin. BLAST# becomes inactive after final data transfer cycle. Selects which four bytes participates current access. Indicates that processor soon stall unless sufficient access bus. When asserted, GT-96010A will relinquish after completing arbitration cycle. When deasserted, GT-96010A will relinquish only when there pending requests.
ADS# HoldA Hold RdyRcv#
Address Strobe Hold Acknowledge Hold Ready/Recover
BLAST#
Burst Last
BE#[3:0] BSTAT
Byte Enable Status
Total Interface DMAReq# DMAAck# Total DRAM Interface
request Acknowledge
request operation directed internal arbiter. internal arbiter grants operation requesting device.
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GT-96010A Remote Access Coprocessor
Symbol DAdr[10:0] RAS#[3:0] CAS#[3:0] DWr# DRAM Total Device ADBusReq ADBusGnt BootCS# DevCS#[2:0] WE#[3:0] Ready# BufOE#
Width
Name Dram Addresses Addresses Strobe Column Address Select Dram Write
Description Eleven multiplexed address bits DRAM. addresses support four DRAM banks. Supports byte read/write DRAM Signals write access DRAM.
Request Grant Boot Chip Select Device Chip Select Write Enable Ready Buffer Output Enables
Signals request external agent. Signals that GT-96010A grants mastership external agent. Programmable chip select signal boot device Programmable chip select signals devices Byte write enable devices When active, extends access device adding wait cycles. Indicates data transfer cycles during access. This signal similar functionality DEN# signal i960Jx. used along with BufDir control external data transceivers.
Device Total Port SIP1 RXD1/GPP16 TXD1/GPP17 RTS1#/GPP18
PA[0] PA[1] PA[2]
Multiplexed signal: Serial receive data input MPSC1/General Purpose Multiplexed signal: Serial transmit data output from MPSC1/General Purpose Multiplexed signal: Request Send indicates that MPSC1 ready transmit data/General Purpose Multiplexed signal: Clear Send indicates MPSC1 that data transmission begin/General Purpose Multiplexed signal: Carrier Detect indicates that MPSC1 begin reception data/General Purpose Input clock MPSC1.
CTS1#/GPP19
PA[3]
CD1#/GPP20
PA[4]
SCLK11 Port Total
PA[5]
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GT-96010A Remote Access Coprocessor
Symbol Port SIP2 RXD2/GPP21 TXD2/GPP22 RTS2#/GPP23
Width
Name
Description
PB[0] PB[1] PB[2]
Multiplexed signal: Serial receive data input MPSC2/General Purpose Multiplexed signal: Serial transmit data output from MPSC2/General Purpose Multiplexed signal: Request send indicates that MPSC2 ready transmit data/General Purpose Multiplexed signal: Clear send indicates MPSC2 that data transmission begin/General Purpose Multiplexed signal: Carrier detect indicates that MPSC2 begin reception data/General Purpose Input clock MPSC2.
CTS2#/GPP24
PB[3]
CD2#/GPP25
PB[4]
SCLK21 Port Total Port SIP3/SCP RXD3/GPP26/ SCRX TXD3/GPP27/ SCTX RTS3#/GPP28/ SCCLK CTS3#/GPP29
PB[5]
PC[0]
Multiplexed signal: Serial receive data input MPSC3/General Purpose serial data input. Multiplexed signal: Serial transmit data output from MPSC3/General Purpose 27/SCP serial data output. Multiplexed signal: Request send indicates that MPSC3 ready transmit data/General Purpose 28/SCP output clock. Multiplexed signal: Clear send indicates MPSC3 that data transmission begin/General Purpose Multiplexed signal: Carrier detect indicates that MPSC3 begin reception data/General Purpose Input clock MPSC3.
PC[1]
PC[2]
PC[3]
CD3#/GPP30
PC[4]
SCLK31 Port Total
PC[5]
Port Flex-TDM SIP4 TDCLK1 TDSTRB1[1:0] PD[0] PD[2:1] Serial data rate clock. output data rate clock when input clock data rate. data strobe output. used gate clocks external devices that have built TDM.
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GT-96010A Remote Access Coprocessor
Symbol TRXD1/RXD4
Width
Name PD[3]
Description Multiplexed signal: Serial receive data time domain multiplexed channels/Serial receive data MPSC4 Multiplexed signal: Serial transmit data from time domain multiplexed channels/Serial transmit data from MPSC4. Multiplexed signal: Receive clock channels/Receive clock MPSC4. Multiplexed signal: Transmit clock channels/Transmit clock MPSC4. Transmit data sync signal channels. Multiplexed signal: Receive sync signal channels/Carrier Detect Multiplexed signal: interface request transmit Channel/MPSC4 request send. Multiplexed signal: Interface Channel grant signal/MPSC4 clear send.
TTXD1/TXD4
PD[4]
TRCLK1/ SCLK41 TCLK1/ TSCLK41 TSYNC1 TRSYNC1/ CD4# TDREQ1/RTS4# TDGNT1/CTS4# Port total
PD[5] PD[6] PD[7] PD[8] PD[9] PD[10]
Port Flex-TDM SIP5 TDCLK2 TDSTRB2[1:0] PE[0] PE[2:1] Serial data rate clock. output data rate clock when input clock data rate. data strobe output. used gate clocks external devices that have built TDM. Multiplexed signal: Serial receive data time domain multiplexed channels/Serial receive data MPSC5. Multiplexed signal: Serial transmit data from time domain multiplexed channels/Serial transmit data from MPSC5. Multiplexed signal: Receive clock channels/Receive clock MPSC5. Multiplexed signal: Transmit clock channels/Transmit clock MPSC5. Transmit data sync signal channels. Multiplexed signal: Receive sync signal channels/Carrier Detect Multiplexed signal: interface request transmit Channel/MPSC5 request send.
TRXD2/RXD5
PE[3]
TTXD2/TXD5
PE[4]
TRCLK2/ SCLK51 TCLK2/ TSCLK51 TSYNC2 TRSYNC2/ CD5# TDREQ2/RTS5#
PE[5] PE[6] PE[7] PE[8] PE[9]
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GT-96010A Remote Access Coprocessor
Symbol TDGNT2/CTS5# Port total
Width
Name PE[10]
Description Multiplexed signal: Interface Channel grant signal/MPSC5 Clear send
Port Ethernet MPSC6 ETXD/TXD6 ETEN#/RTS# ERXC#/SCLK61 ERXD/RXD6 ECDT#/CD6# ECRS#/CTS6# ETXC#/ TSCLK61 Total PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] Multiplexed signal: Ethernet transmit data output/ MPSC6 transmit data output. Multiplexed signal: Ethernet Transmit Enable/ MPSC6 Request Send. Multiplexed signal: Ethernet receive clock/MPSC6 serial clock. Multiplexed signal: Ethernet receive data input/ MPSC6 receive data input. Multiplexed signal: Ethernet Collision Detect/ MPSC6 Carrier Detect. Multiplexed signal: Ethernet Carrier Sense/MPSC6 Clear Send Multiplexed signal: Ethernet transmit clock/MPSC6 transmit serial clock.
Serial Auxiliary Port CLK[4:1] BRGO[4:1] TGATE[2:1]# TO[4:1]# Clock Baud Rate Generators Output Timer Gate Timer Output Baud rate generators' input clocks from which will derive baud rates. Baud rate generators' outputs. Allows baud rate generators externally. Timer gates. Enables/disables timer counting function. Output waveforms (pulse/toggle) from timer result reference value being reached. pins sampled during reset define GT96010A configuration. Time reference inputs. signals used when timers need work function counter. Used with TO[4] during RESET define configuration
TI[4:1] Mode_960_ SAUX Total System Port
Timer Input Configuration
System Input Clock
System input clock. Used various GT96010A's Interface Units channels defines i960Jx Device speed.
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Symbol RST# INT#[4:0] NMI# WDE#
Width
Name Reset Interrupt Maskable Interrupt Watchdog Expired
Description System Hardware Reset. Active low. Interrupt signals used request interrupt service from CPU. Request non-maskable interrupt service from CPU. Watchdog timer expired signal. used second stage watchdog event system reset other emergency procedure.
System Total Misc. Port GPP[15:0]
General Purpose Port
General Purpose pins system (LED control, SROM interface, etc.). GPP[2:0] sampled during reset define Ethernet Port configuration.
Misc. Total Test Access Port TRST TCLK FN0-FN1 Test Total Data Total Power Reserved Count
Schmitt Input
Test Data Input Test Data Output Test Reset Test Clock Test Mode Select Function Select
JTAG (IEEE 1149.1) serial data input pin. JTAG (IEEE 1149.1) serial data output pin. Asynchronously reset Test Access Port (TAP) controller. Clock input JTAG logic Selects desired function JTAG. These pins must connected
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Functional Overview
Interface
GT-96010A glueless interface Intel i960Jx family processors with frequencies between 16MHz 33MHz. External agents take control access GT-96010A resources. GT96010A handles priorities between internal resources, CPU, external agents. Upon request from external agent, GT-96010A will request from relinquish external agent. systems that need extension capabilities offered GT-96010A, eight GT-96010A devices support CPU. example, with four GT-96010As, system have 512MBytes DRAM, independent channels, HDLC channels, Ethernet channels, variety serial interfaces (i.e. EIA-232 GCI).
Arbitration
There three major clients GT-96010A's internal arbiter recognizes: Internal clients internal channel requests. External client(s) through AdBusReq pin. system BSTAT pin. GT-96010A uses fixed arbitration scheme where internal resources have highest priority lowest priority. ports receive highest priority since failure service serial interfaces could result loss communications link.
Address Space Decode
GT-96010A decodes address space stages. first stage, decoding done groups that include following: Four spaces MBytes devices MBytes DRAM MBytes internal address space decoding first stage done comparing high order address bits with Address Space register's values. This way, four groups devices provided order enable mappings 32-bit devices same system, using different PMCONs (PMCONs i960Jx's Physical Memory Configuration registers, used configure width different memory regions). second decode stage, there additional decoding specific device bank register each group. subdecoding DRAM device banks programmable, while sub-decoding internal registers fixed. Each DRAM bank have programmable address space 1MByte 64MBytes that located anywhere DRAM address space. progammability address space size enables continuous address space when accessing different DRAM banks even when banks have different sizes. decoding performed comparing address bits 25:20 between values (High Low) DRAM bank registers. Each device bank have programmable address space 2MBytes 32MBytes that located anywhere device address space. Similar DRAM banks, enables continuous address space different device bank sizes. decoding performed comparing address bits 24:21 between values (High Low) device bank registers. internal address space sub-decoded control status registers that reside GT-96010A. base address internal register space programmable configured Reset strapping options. GT-96010A will respond addresses that allocated those address spaces reserved system other devices.
DRAM Controller
DRAM controller supports banks fast page mode DRAMs. DRAM types supported those with 0.5K,
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refresh, well asymmetric RAS/ addressing. depth DRAM devices vary each bank separately from 256K width banks fixed 32-bits. With these options, each DRAM bank size vary from 1MByte 16MBytes. DRAM timing optimized different frequencies device types supported. read access pattern from standard DRAMs will xxDxDxDxDx, meaning wait-states first data wait-state each additional word. This fixed speeds from 16MHz 33Mhz. GT-96010A serial interface (SDMA) independent (IDMA) DRAM burst access will always xxDxDxDxD; there will always wait states first data wait state between consecutive data accesses. Refresh programmed different periods 16-bit refresh counter. Staggered non-staggered refresh modes supported. staggered mode, four banks DRAM refreshed with cycle delay between each bank, while non-staggered mode four banks refreshed simultaneously. systems that require more than 64MBytes DRAM, possible more DRAM banks with simple external logic, 128MBytes DRAM with control signals.
Device Controller
GT-96010A supports four devices bus, boot device three general purpose devices such Flash, SRAM, ROM, peripherals. External logic sub-decode four chip-selects number, using address sub-decoding. device controller several control signals enable read write accesses (including chip selects, reads, writes, buffer control). Each chip-select programmable address space 2MBytes 32MBytes. Contiguous address space possible between different banks. Byte writes supported through four write enable signals. write signals shaped specifying following Device Bank Parameters registers: number cycles from assertion DevCS* first assertion write (CsToWr) number cycles write pulse active (WrActive) number cycles write signal nonactive between consecutive writes (WrHigh). timing parameters write signals determine length active DevCS* DMAAck* (when allocated device). read cycles, following parameters programmable: number cycles from assertion chip-select rising edge clock that samples first data (DelayToFirst) number cycles from when data sampled next time data sampled during burst (DelayToNext) number cycles between deassertion DevCS* cycle (TurnOff). Each device configured 32-bits wide, programming appropriate PMCON register i960 processor) desired width mapping appropriate Device Address Space decode register into this address space. Each PMCON configures width memory region with specific Addr[31:29] while Device Address Space decode register maps device into region with specific Addr[31:25]. device controller supports read write bursts four data elements. burst address supported 2bit wide address that multiplexed with least significant bits DRAM address (DAdr[1:0]) when device 32-bits wide. GT96010 supports bursts only 32-bit devices. 8-bit 16-bit devices must accessed with read write operation time. Ready* enables extension device cycle beyond values that programmed Device Bank Parameters register. control signals will held their present state when Ready* signal sampled inactive, held until becomes active. internal state machine counters will continue count programmed values, even when Ready* deasserted (HIGH). control signals will change only when Ready* signal asserted (LOW) wait-state counters terminal count. Ready* signal optional each bank through programmable Device Bank Parameters registers. NOTE: confuse device Ready* with CPU's RdyRcv* signal. Ready* controls assertion
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RdyRcv* back processor accesses controlled Device Controller only.
There serial (SDMA) channels GT-96010A dedicated MPSC Ethernet communication channels. SDMA channels transfer data from on-chip communications FIFOs from DRAM. There independent (IDMA) channel GT-96010A available system use. IDMA controller execute DRAM-to-DRAM transfers, move data between devices move data from devices DRAM. arbiter will always give MPSC0 channel highest priority IDMA channel lowest priority. ethernet port second highest priority. remaining MPSCs have same priority selected using round robin arbitration scheme. 3.6.1 Serial Features (SDMA)
SDMA channels transfer data from MPSCs ethernet port from DRAM internal FIFOs. FIFO depth bytes MPSCs bytes ethernet interface. Channels 1-12 allocated MPSC16. Channels allocated ethernet controller. SDMA channels only chain base process. SDMA channels programed generate interrupts buffer boundaries. receive SDMAs freely when enabled always expect find valid descriptor when required. When receive SDMA channel accesses invalid descriptor, receive SDMA process will halt with resource error status. transmit SDMAs freely when enabled until they reach descriptor chain. expected that descriptor chain will also marked frame descriptor. When transmit SDMA accesses invalid descriptor last descriptor marked frame descriptor, transmit SDMA process will halt with resource error status. 3.6.2 Independent Features (IDMA)
IDMA accesses initiated external request asserting DMAReq (demand mode), setting internal register (block mode). Accesses nonaligned both source destination, 64KBytes data transferred each transaction. transfer data ways: through internal 16-byte FIFO, directly between DRAM device ("fly-by"). internal mode, data transferred from source device into internal FIFO, from internal FIFO destination device. length each access limited 32-bit words. IDMA controller supports non-chained chained modes operation. non-chained mode, programs IDMA channel each IDMA transaction. chained mode, controller programs itself next IDMA operation fetching information from linked list records memory. non-chained mode, IDMA will assert interrupt every time Byte Count reaches terminal count. Independent transactions limited devices. chained mode, IDMA controller programmed assert interrupt every IDMA transaction when Next Pointer Register NULL Byte Count reaches terminal count.
Communications Unit
GT-96010A's communications unit (WCU) incorporates multi-protocol serial controllers (MPSC) ethernet controller. chip baud rate generators digital phase-locked loops (DPLLs) also included.
General Purpose Port.
GT-96010A includes 16-bit wide General Purpose Port (GPP). pins configured work input output pins. When functioning input pins, pins generate maskable interrupt. interrupts level sensitive with programmable polarity. Unused pins serial ports also used expansion pins giving general purpose pins. only restriction that PORTA-C pins cannot generate interrupts.
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Watchdog Timer
GT-96010A stage watch timer. watchdog counter based 32-bit free running down-counter. When watchdog enabled, starts count down from preset value processor clock rate. normal use, watchdog counter serviced periodically resetting it's value preset value. When watchdog counter serviced time, will until it's value reaches Watchdog Value register count. When this occurs non-maskable interrupt generated. When watchdog counter reach WDE# asserted cycle. WDE# used reset CPU.
3.10
Timer/Counters
GT-96010A includes four 16-bit counters that cascaded into 32-bit counters. clock source GT-96010A Timer/Counters selected from processor clock external input clock. counters gated using external input pin. Free auto-reset modes supported.
3.11
Reset Configuration
GT-96010A must acquire some knowledge system before configured software. following configuration pins sampled when Rst* asserted, until clock cycles after Rst* deasserted: TO1/2/3 Indicates three MSBs GT-96010A internal address space decode, bits 31:29. These bits sampled into Internal Address Space Decode Control register bits [5:3]. Indicates GT-96010A four devices address (bit 31). sampled into Device Address Space registers. When pulled during reset, GT-96010A configured boot GT-96010A enabling access boot ROM. Mode_960_ Used with TO[4] during RESET define configuration. Restriction: GT-96010A always answers address (either device DRAM). Special attention should used with designing GT-96010A slave Motorola Coldfire. slave GT-96010A's should isolated boot time prevent contention with Coldfire, which also accesses address 0x0. order prevent contention Table Boot Vector Reset Value Mode_960_ TO[4] i960/RC32364 slave i960 master Coldfire RC32364 Boot Vector 0xFEF00000 0x1FC00000 Boot None Boot device Dev0 Boot device
between boot device internal address space, Mode_960_ TO[4] inputs also affect DRAM address space along with other devices. Table lists reset values DRAM device address space. Table DRAM Device Reset Address Space REGNAME DRAM ADDRESS SPACE DRAM ADDRESS SPACE DRAM ADDRESS SPACE DRAM ADDRESS SPACE DEV0 ADDRESS SPACE mode_960_ TO[4] ResetValue 0x1f 0x3f
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Table DRAM Device Reset Address Space REGNAME DEV0 ADDRESS SPACE DEV0 ADDRESS SPACE DEV0 ADDRESS SPACE DEV1 ADDRESS SPACE DEV1 ADDRESS SPACE DEV1 ADDRESS SPACE DEV1 ADDRESS SPACE DEV2 ADDRESS SPACE DEV2 ADDRESS SPACE DEV2 ADDRESS SPACE DEV2 ADDRESS SPACE DEV3 ADDRESS SPACE DEV3 ADDRESS SPACE DEV3 ADDRESS SPACE DEV3 ADDRESS SPACE RAS[0] decode address RAS[0] decode address BootCs decode address BootCs decode address mode_960_ TO[4] ResetValue 0x7f 0x3f 0x7f 0x3f 0x7f 0x3f 0x7f 0x3c0 0xff0 0x77 0xee
GPP[2:0] Configures Ethernet port polarity clock driving edge. Section more details Ethernet port configuration.
3.12
Interrupts
GT-96010A uses i960Jx mixed interrupt mode efficient interrupt handling. GT-96010A drives requested interrupt vector INT#[4:0] pins. intelligent priority mechanism resolves which interrupt should served first drives it's vector interrupt pins.
3.13
Revision
Bits 28:24 Ethernet Configuration Register (see Section 14.1 page 120) read only, return revision part. table below revision number information.
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Device GT-96010-P-0 GT-96010A-P-0
0x00 0x01
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Address Space
Register Access
GT-96010A internal registers memory mapped most accessed reads writes. Registers that read written specifically marked read write only. user should avoid writing reserved addresses within GT-96010A internal address space. Writing reserved addresses produce unpredictable results. registers' address comprised value bits [5:0] Internal Address Space Decode Control register register's offset. Immediately after reset, value Internal Address Space Decode Control register bits [5:0] determined values pins TO[3:1] (bits [5:3] TO[3:1], bits [2:0] preprogrammed "011"). example, access "Ethernet Main Configuration Register" (offset 0xD80) immediately after reset, assuming that during reset value TO[3:1] "110", value Internal Address Space Decode Control register bits [5:0] will "110011". bits [31:26] must match "110011". offset 0x0D80 makes AD[25:0], which will result 32-bit address 0xCC000D80 required access register. Figure Internal Address Space Decode Control Register Reset Bits Name Decode Reserved REndian HoldMask ExtOwn ISDEndian Reset Value {TO[3:1],0,1,1}
Figure Access Ethernet Main Configuration Register Immediately After Reset
Following reset, location registers memory space changed changing value programmed into Internal Address Space Decode Control register, independent TO[3:1] pins. example, after changing value Internal Address Space Decode Control register writing register value "0x28", access "Ethernet Main Configuration Register" will with address 0xa0000D80.
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Figure Internal Address Space Decode Control Register following write
Figure Normal access Ethernet Main Configuration Register
GT-96010A's internal registers 32-bits wide; therefore, appropriate memory region must configured 32-bit region. Note: GT-96010A does support burst access into it's internal address space Note: GT-96010A internal address space accessed little endian according Internal Address Space Decode Control register.
Register
Group Address Space DRAM Address Space Device Address Space Device Address Space Device Address Space Boot Device Address Space 0x000 0x004 0x008 0x00C 0x010
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Reserved Reserved Internal Address Space Decode Control DRAM Address Space RAS[0] Decode Address RAS[1] Decode Address RAS[2] Decode Address RAS[3] Decode Address Device Address Space CS[0] Decode Address CS[1] Decode Address CS[2] Decode Address BootCS Decode Address DRAM Refresh Configuration Refresh Configuration DRAM Parameters DRAM Parameters Device Parameters Device Bank0 Parameters Device Bank1 Parameters Device Bank2 Parameters Device Boot Bank Parameters Descriptors Channel1 Descriptor Channel1 Descriptor Channel2 Descriptor Channel2 Descriptor Channel3 Descriptor Channel3 Descriptor Channel4 Descriptor Channel4 Descriptor Channel5 Descriptor
0x014 0x018 0x01C
0x400 0x404 0x408 0x40C
0x410 0x414 0x418 0x41C
0x420
0x424
0x428 0x42c 0x430 0x434
0X0800-0X080C 0X0810-0X081C 0X0820-0X082C 0X0830-0X083C 0X0840-0X084C 0X0850-0X085C 0X0860-0X086C 0X0870-0X087C 0X0880-0X088C
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Channel5 Descriptor Channel6 Descriptor Channel6 Descriptor Channel7 Descriptor (Ethernet) Channel7 Descriptor (Ethernet) Channel1 SDMA Configuration Register (SDC1) Channel1 Command Register (SDCM1) Channel1 SDMA Current Descriptor Pointer (SCRDP1) Channel1 SDMA First Descriptor Pointer (SFTDP1) Channel1 SDMA Current Descriptor Pointer (SCTDP1) Channel2 SDMA Configuration Register (SDC2) Channel2 Command Register (SDCM2) Channel2 SDMA Current Descriptor Pointer (SCRDP2) Channel2 SDMA First Descriptor Pointer (SFTDP2) Channel2 SDMA Current Descriptor Pointer (SCTDP2) Channel3 SDMA Configuration Register (SDC3) Channel3 Command Register (SDCM3) Channel3 SDMA Current Descriptor Pointer (SCRDP3) Channe3 SDMA First Descriptor Pointer (SFTDP3) Channel3 SDMA Current Descriptor Pointer (SCTDP3) Channel4 SDMA Configuration Register (SDC4) Channel4 Command Register (SDCM4) Channel4 SDMA Current Descriptor Pointer (SCRDP4) Channe4 SDMA First Descriptor Pointer (SFTDP4)
0X0890-0X089C 0X08A0-0X08AC 0X08B0-0X08BC 0X08C0-0X08CC 0X08D0-0X08DC 0x0900 0x0908 0x0910 0x0918 0x091C 0x0940 0x0948 0x0950 0x0958 0x095C 0x0980 0x0988 0x0990 0x0998 0x099C 0x09C0 0x09C8 0x09D0 0x09D8
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Channel4 SDMA Current Descriptor Pointer (SCTDP4) Channel5 SDMA Configuration Register (SDC5) Channel5 Command Register (SDCM5) Channel5 SDMA Current Descriptor Pointer (SCRDP5) Channel5 SDMA First Descriptor Pointer (SFTDP5) Channel5 SDMA Current Descriptor Pointer (SCTDP5) Channel6 SDMA Configuration Register (SDC1) Channel6 Command Register (SDCM1) Channel6 SDMA Current Descriptor Pointer (SCRDP6) Channel6 SDMA First Descriptor Pointer (SFTDP6) Channel6 SDMA Current Descriptor Pointer (SCTDP6) Channel7 SDMA Configuration Register (SDC7) Channel7 Command Register (SDCM7) Channel7 SDMA Current Descriptor Pointer (SCRDP7) Channe7 SDMA First Descriptor Pointer (SFTDP7) Channel7 SDMA Current Descriptor Pointer (SCTDP7) MPSC1-6/Ethernet MPSC1 Main Configuration (MMCRL1) MPSC1 Main Configuration High (MMCRH1) MPSC1 Protocol Configuration (MPCR1) Channel1 Register1 (CH1R1) Channel1 Register2 (CH1R2) Channel1 Register3 (CH1R3) Channel1 Register4 (CH1R4) Channel1 Register5 (CH1R5) Channel1 Register6 (CH1R6)
0x09DC 0x0A00 0x0A08 0x0A10 0x0A18 0x0A1C 0x0A40 0x0A48 0x0A50 0x0A58 0x0A5C 0x0A80 0x0A88 0x0A90 0x0A98 0x0A9C
0x0C00 0x0C04 0x0C08 0x0C0C 0x0C10 0x0C14 0x0C18 0x0C1C 0x0C20
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Channel1 Register7 (CH1R7) Channel1 Register8 (CH1R8) Channel1 Register9 (CH1R9) Channel1 Register10 (CH1R10) Channel1 Register11 (CH1R11) MPSC2 Main Configuration (MMCRL2) MPSC2 Main Configuration High (MMCRH2) MPSC2 Protocol Configuration (MPCR2) Channel2 Register1 (CH2R1) Channel2 Register2 (CH2R2) Channel2 Register3 (CH2R3) Channel2 Register4 (CH2R4) Channel2 Register5 (CH2R5) Channel2 Register6 (CH2R6) Channel2 Register7 (CH2R7) Channel2 Register8 (CH2R8) Channel2 Register9 (CH2R9) Channel2 Register10 (CH2R10) Channel2 Register11 (CH2R11) MPSC3 Main Configuration (MMCRL3) MPSC3 Main Configuration High (MMCRH3) MPSC3 Protocol Configuration (MPCR3) Channel3 Register1 (CH3R1) Channel3 Register2 (CH3R2) Channel3 Register3 (CH3R3) Channel3 Register4 (CH3R4) Channel3 Register5 (CH3R5) Channel3 Register6 (CH3R6) Channel3 Register7 (CH3R7) Channel3 Register8 (CH3R8) Channel3 Register9 (CH3R9) Channel3 Register10 (CH3R10)
0x0C24 0x0C28 0x0C2C 0x0C30 0x0C34 0x0C40 0x0C44 0x0C48 0x0C4C 0x0C50 0x0C54 0x0C58 0x0C5C 0x0C60 0x0C64 0x0C68 0x0C6C 0x0C70 0x0C74 0x0C80 0x0C84 0x0C88 0x0C8C 0x0C90 0x0C94 0x0C98 0x0C9C 0x0CA0 0x0CA4 0x0CA8 0x0CAC 0x0CB0
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Channel3 Register11 (CH3R11) MPSC4 Main Configuration (MMCRL4) MPSC4 Main Configuration High (MMCRH4) MPSC4 Protocol Configuration (MPCR4) Channel4 Register1 (CH4R1) Channel4 Register2 (CH4R2) Channel4 Register3 (CH4R3) Channel4 Register4 (CH4R4) Channel4 Register5 (CH4R5) Channel4 Register6 (CH4R6) Channel4 Register7 (CH4R7) Channel4 Register8 (CH4R8) Channel4 Register9 (CH4R9) Channel4 Register10 (CH4R10) Channel4 Register11 (CH4R11) MPSC5 Main Configuration (MMCRL5) MPSC5 Main Configuration High (MMCRH5) MPSC5 Protocol Configuration (MPCR5) Channel5 Register1 (CH5R1) Channel5 Register2 (CH5R2) Channel5 Register3 (CH5R3) Channel5 Register4 (CH5R4) Channel5 Register5 (CH5R5) Channel5 Register6 (CH5R6) Channel5 Register7 (CH5R7) Channel5 Register8 (CH5R8) Channel5 Register9 (CH5R9) Channel5 Register10 (CH5R10) Channel5 Register11 (CH5R11) MPSC6 Main Configuration (MMCRL6) MPSC6 Main Configuration High (MMCRH6) MPSC6 Protocol Configuration (MPCR6)
0x0CB4 0x0CC0 0x0CC4 0x0CC8 0x0CCC 0x0CD0 0x0CD4 0x0CD8 0x0CDC 0x0CE0 0x0CE4 0x0CE8 0x0CEC 0x0CF0 0x0CF4 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D14 0x0D18 0x0D1C 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D40 0x0D44 0x0D48
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Channel6 Register1 (CH6R1) Channel6 Register2 (CH6R2) Channel6 Register3 (CH6R3) Channel6 Register4 (CH6R4) Channel6 Register5 (CH6R5) Channel6 Register6 (CH6R6) Channel6 Register7 (CH6R7) Channel6 Register8 (CH6R8) Channel6 Register9 (CH6R9) Channel6 Register10 (CH6R10) Channel6 Register11 (CH6R11) Ethernet Configuration Register (ECR) Ethernet Command Register (ECMR) Ethernet Counters (EMCR) Ethernet Event Register (EEVR) Ethernet Hash Table Pointer (EHTP)) IDMA Registers IDMA Byte Count (IBC) IDMA Source Pointer (ISP) IDMA Destination Pointer IDMA Next Record Pointer (INP) IDMA Command (ICM) Watchdog Watchdog Configuration Register (WDC) Watchdog Value (WDV) Timers/Counters Counter Counter (TCNTA) Counter Counter (TCNTB) Timer Counter Mode Register (TCMR) Timer Counter Configuration Register (TCCR) Timer Counter Capture1 (TCC1) Read Only Timer Counter Capture2 (TCC2) Read Only
0x0D4C 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 0x0D68 0x0D6C 0x0D70 0x0D74 0x0D80 0xD84 0xD88 0xD8C 0xD90
0x1800 0x1804 0x1808 0x180c 0x1820
0x1B00 0x1B04
0x1B80 0x1B84 0x1B88 0x1B8C 0x1BC0 0x1BC4
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Timer Counter Reference Value1 (TCRV1) Timer Counter Reference Value2 (TCRV2) Flex-TDM1 Transmit Dual Port (TDPR1) Receive Dual Port (RDPR1) Transmit Read Pointer (TRP1) Receive Read Pointer (RRP1) Configuration Register (TCR) Flex-TDM1 Auxiliary ChannelA Register (ATA1) Flex-TDM1 Auxiliary ChannelA Register (ARA1) Flex-TDM 1Auxilary ChannelB Register (ATB1) Flex-TDM1 Auxiliary ChannelB Register (ARB1) Flex-TDM2 Transmit Dual Port (TDPR2) Receive Dual Port (RDPR2) Transmit Read Pointer (TRP2) Receive Read Pointer (RRP2) Flex-TDM2 Configuration Register (TCR2) Flex-TDM2 Auxiliary ChannelA Register (ATA2) Flex-TDM2 Auxiliary ChannelA Register (ARA1) Flex-TDM2 Auxiliary ChannelB Register (ATB1) Flex-TDM2 Auxiliary ChannelB Register (ARB1) Routing Registers Main Routing Register (MRR) Receive Clock Routing Register (RCRR) Transmit Clock Routing Register (TCRR) General Purpose Ports Port General Purpose Register (GPPA) Port General Purpose Register (GPPB) Port General Purpose Register (GPPC) General Purpose Port Configuration Register (GPCR) General Purpose Port Value Register (GPVR)
0x1BC8 0x1BDc
0x1C00-0x1CFF 0x1D00-0x1DFF 0x1E00 0x1E04 0x1E08 0x1E0C 0x1E10 0x1E14 0x1E18
0x2C00-0x2CFF 0x2D00-0x2DFF 0x2E00 0x2E04 0x2E08 0x2E0C 0x2E10 0x2E14 0x2E18
0x3C00 0x3C04 0x3C08
0x3C0C 0x3C10 0x3C14 0x3C40 0x3C44
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Configuration Register (SCPC) Data Register (SCTD) Data Register (SCRD) Baud Rate Generators BRG1 Configuration Register (BCR1) BRG1 Baud Tuning Register (BTR1) BRG2 Configuration Register (BCR2) BRG1 Baud Tuning Register (BTR2) BRG3 Configuration Register (BCR3) BRG1 Baud Tuning Register (BTR3) BRG4 Configuration Register (BCR4) BRG1 Baud Tuning Register (BTR4) Interrupts Interrupt's Cause Register (ICR1) Interrupt's Cause Register (ICR2) Interrupt's Cause Register (ICR3) Interrupt's Cause Register (ICR4) Interrupt's Cause Register (ICR5) Interrupt's Cause Register (ICR6) Interrupt1 Mask Register (IMR1) Interrupt1 Mask Register (IMR2) Interrupt1 Mask Register (IMR3) Interrupt1 Mask Register (IMR4) Interrupt1 Mask Register (IMR5) Interrupt1 Mask Register (IMR6)
0x3C80 0x3C84 0x3C88
0x4C00 0x4C04 0x4C08 0x4C0C 0x4C10 0x4C14 0x4C18 0x4C20
0x5C00 0x5C04 0x5C08 0x5C0C 0x5C10 0x5C14 0x5C20 0x5C24 0x5C28 0x5C2C 0x5C30 0x5C34
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Address Space Decoding
GT-96010A decodes addresses stages. high level decode (group address space), addresses decoded into major segments: DRAM address space, device 0,1, address spaces, boot device address space, internal registers address space. After address decoded high level, subdecoded within each segments. example, let's examine decoding access DRAM bank Assume that DRAM address space 64MB continuous space from 0xA000.000 0xA7FF.FFFF. space divided into four banks; bank from 0xA000.0000 0xA07F.FFFF. will decode address 0xA008.0000. order correctly decode access DRAM bank high level, bits [4:0] DRAM Address Space register must programmed with "10100". Therefore, "10100" AD[31:27] will send address Decode Registers subdecoding. subdecoding level, AD[25:20] compared high level comparison fields each bank. order correctly decode address bank high field bank must programmed with "000011" field with "000000". Therefore, address 0xA008.000 will greater than equal field less than equal high field, will activate RAS[0]. high level subdecoding example shown below. Figure DRAM address space
64Mb DRAM Space
0xA7FF.FFFF
0xA07F.FFFF Bank 0xA008.0000 0xA000.000
Figure DRAM Address Space Register Bits Name Decode Description DRAM banks will accessed when bits 31:27 match value programmed bits 4:0. Figure RAS[0] Decode Address Register Bits 11:6 Name High Description Lowest decoded address value RAS[0] activation. Highest decoded address value RAS[0] activation. Reset Value 0x0f Reset Value 0x00
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Figure Example high level decode subdecode access DRAM
High level decode access DRAM
AD31 AD30 DRAM ADDR Space[4] Decode? DRAM ADDR Space[3] DRAM ADDR Space[2] DRAM ADDR Space[1] DRAM ADDR Space[0] AD29 AD28 AD27 AD26 AD25 AD24
Progress subdecode? Subdecode access DRAM Bank
AD25 AD24 AD23 AD22 AD21 AD20
Field Decode[5] Decode[4] Decode[3] Decode[2] Decode[1] Decode[0]
High Field Decode[11] Decode? Decode[10] Decode[9] Decode[8] Decode[7] Decode[6]
activated?
Note that AD26 decoded high decode level subdecode level. This means that address 0xA07x will mapped both 0xA07x 0xA47x. External logic used generated separate signals.
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Figure external logic generate multiple signals from AD26 RAS0A
RAS0B
4.4.1
Register Definitions
DRAM, Device, Internal Address Decode Registers
4.4.1.1
Bits
DRAM Address Space, Offset: 0x000
Name Decode Description DRAM banks will accessed when bits 31:27 match value programmed bits 4:0. Reset Value Table page
4.4.1.2
Bits
Device Address Space, Offset: 0x004
Name Decode Description device bank will accessed when bits 31:25 match value programmed bits 6:0. Reset Value Table page
4.4.1.3
Bits
Device Address Space, Offset: 0x008
Name Decode Description device bank will accessed when bits 31:25 match value programmed bits 6:0. Reset Value Table page
4.4.1.4
Bits
Device Address Space, Offset: 0x00C
Name Decode Description device bank will accessed when bits 31:25 match value programmed bits 6:0. Reset Value Table page
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4.4.1.5
Bits
Boot Device Address Space, Offset: 0x010
Name Decode Description device bank will accessed when bits 31:25 match value programmed bits 6:0. Reset Value Table page
4.4.1.6
Bits
Internal Address Space Decode Control, Offset: 0x01C
Name Decode Description Registers inside GT-96010A will accessed when bits 31:26 match value programmed bits 5:0. Reset Value {TO[3:1],0,1,1} (Bits [5:3] sampled during reset from TO[3:1] pins)
Reserved REndian endianess interface. Affects byte swapping when accessing GT96010 internal address space Little endian endian mask Hold request signal. Enables processor disable requests. Enable requests Mask requests External Agent regardless state ADBusReq signal, long this `1'. Release endianess interface. Affects byte swapping IDMA transaction when GT96010 access SDMA descriptors.
HoldMask
ExtOwn
ISDEndian
4.4.2
Decode Registers
values Address Decode registers determine which physical DRAM bank will accessed when issues address. address decoding done comparing address bits 25:20 equal higher than value fields, equal lower than value High fields. Note that address part internal decoding used external decoding generate DRAM banks' RASs using GT-96010A RAS.
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4.4.2.1
Bits 11:6
RAS[0] Decode Address, Offset: 0x400
Name High Description Lowest decoded address value RAS[0] activation. Highest decoded address value RAS[0] activation. Reset Value Table page Table page
4.4.2.2
Bits 11:6
RAS[1] Decode Address, Offset: 0x404
Name High Description Lowest decoded address value RAS[1] activation. Highest decoded address value RAS[1] activation. Reset Value 0x10 0x1f
4.4.2.3
Bits 11:6
RAS[2] Decode Address, Offset: 0x408
Name High Description Lowest decoded address value RAS[2] activation. Highest decoded address value RAS[2] activation. Reset Value 0x20 0x2f
4.4.2.4
Bits 11:6
RAS[3] Decode Address, Offset: 0x40
Name High Description Lowest decoded address value RAS[3] activation. Highest decoded address value RAS[3] activation. Reset Value 0x30 0x3f
4.4.3
Decode Registers
values Address Decode registers determine which physical device bank will accessed when issues address. address decoding done comparing address bits 24:21 equal higher than value fields, equal lower than value High fields.
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4.4.3.1
Bits
CS[0] Decode Address, Offset: 0x410
Name High Description Lowest decoded address value CS[0] activation. Highest decoded address value CS[0] activation. Reset Value
4.4.3.2
Bits
CS[1] Decode Address, Offset: 0x41
Name High Description Lowest decoded address value CS[1] activation. Highest decoded address value CS[1] activation. Reset Value
4.4.3.3
Bits
CS[2] Decode Address, Offset: 0x418
Name High Description Lowest decoded address value CS[2] activation. Highest decoded address value CS[2] activation. Reset Value
4.4.3.4
Bits
BootCS Decode Address, Offset: 0x41c
Name High Description Lowest decoded address value BootCS activation. Highest decoded address value BootCS activation. Reset Value
4.4.4
DRAM Refresh Configuration Registers
This register specifies refresh parameters. time between DRAM refresh cycles programmable, with option refresh banks same time staggered fashion.
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4.4.4.1
Bits 15:0
Refresh Configuration, Offset: 0x420
Name RefIntCnt Description Refresh interval count value. number processor clock cycles between refreshes. GT-96010A will perform before refreshes every `RefIntCnt' clock cycles. Staggered refresh. signals asserted simultaneously refresh. Staggered refresh. Reset Value 0xf8
StagRef
4.4.5
DRAM Parameter Registers
This register specifies DRAM timing parameters DRAM's refresh type support. parameter BanknRef, which configures refresh type support, each DRAM bank independently.
4.4.5.1
Bits
DRAM Parameters, Offset: 0x424
Name Reserved Bank0Ref DRAM refresh type support. 1/2K Refresh bits row, bits column) Refresh bits row, bits column) Refresh bits row, bits column) used DRAM refresh type support. 1/2K Refresh bits row, bits column) Refresh bits row, bits column) Refresh bits row, bits column) used DRAM refresh type support. 1/2K Refresh bits row, bits column) Refresh bits row, bits column) Refresh bits row, bits column) used DRAM refresh type support. 1/2K Refresh bits row, bits column) Refresh bits row, bits column) Refresh bits row, bits column) used Description Reset Value 0x00
Bank1Ref
Bank2Ref
11:10
Bank3Ref
4.4.6
Device Parameter Registers
Device parameters different each bank. shape different control signals that active device
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access programmed. access time number cycles) device during read accesses should programmed into AccToFirst field, time data from device will ready sampled GT-96010A. AccToNext should programmed with time data from device sampled consecutive accesses during burst accesses. DevCS* will deasserted after last data latched. prevent contention TurnOff field specifies number cycles (from deassertion DevCS*) beginning next transaction. write signals' pulse shaped well. parameters specify number cycles from beginning cycle assertion write signals (CSToWr), number cycles write active (WrActive), number cycles write signals inactive (WrHigh) between consecutive writes burst access. Ready* signal that assert wait states device access enabled bank Ready field.
4.4.6.1
Bits
Device Bank0 Parameters, Offset: 0x428
Name TurnOff AccToFirst Description number cycles between deassertion DevCS* cycle. number cycles from DevCS* active first data (determined access time device). Actual value (`00' allowed). number cycles between sampling data next sampling point data (time difference between sampling points burst sequence). Actual value n+1. number cycles from DevCS* first assertion WrEn* Actual value (`00' allowed). number cycles WrEn* active. Actual value n+1. number cycles between deassertion assertion WrEn*. Actual value (`00' allowed 32-bit devices only). Controls cycle extension. disabled DevCS*. Enabled, will extend cycle Disabled Determines width configuration device. device configured 8-bits wide. device configured bits wide. Reset Value
AccToNext
CSToWr
11:10 13:12
WrActive WrHigh
Ready
DevWidth
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4.4.6.2
Bits
Device Bank1 Parameters, Offset: 0x42c
Name TurnOff AccToFirst Description number cycles between deassertion DevCS* cycle. number cycles from DevCS* active first data (determined access time device). Actual value (`00' allowed). number cycles between sampling data next sampling point data (time difference between sampling points burst sequence). Actual value n+1. number cycles from DevCS* first assertion WrEn* Actual value (`00' allowed). number cycles WrEn* active. Actual value n+1. number cycles between deassertion assertion WrEn*. Actual value (`00' allowed 32-bit devices only). Controls cycle extension. disabled DevCS*. Enabled, will extend cycle Disabled Determines width configuration device. device configured 8-bits wide. device configured bits wide. Reset Value
AccToNext
CSToWr
11:10 13:12
WrActive WrHigh
Ready
DevWidth
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4.4.6.3
Bits
Device Bank2 Parameters, Offset: 0x430
Name TurnOff AccToFirst Description number cycles between deassertion DevCS* cycle. number cycles from DevCS* active first data (determined access time device). Actual value (`00' allowed). number cycles between sampling data next sampling point data (time difference between sampling points burst sequence). Actual value n+1. number cycles from DevCS* first assertion WrEn* Actual value (`00' allowed). number cycles WrEn* active. Actual value n+1. number cycles between deassertion assertion WrEn*. Actual value (`00' allowed 32-bit devices only). Controls cycle extension. disabled DevCS*. Enabled, will extend cycle Disabled Determines width configuration device. device configured 8-bits wide. device configured bits wide. Reset Value
AccToNext
CSToWr
11:10 13:12
WrActive WrHigh
Ready
DevWidth
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4.4.6.4
Bits
Device Boot Bank Parameters, Offset: 0x434
Name TurnOff AccToFirst Description number cycles between deassertion DevCS* cycle. number cycles from DevCS* active first data (determined access time device). Actual value (`00' allowed). number cycles between sampling data next sampling point data (time difference between sampling points burst sequence). Actual value n+1. number cycles from DevCS* first assertion WrEn* Actual value (`00' allowed). number cycles WrEn* active. Actual value n+1. number cycles between deassertion assertion WrEn*. Actual value (`00' allowed 32-bit devices only). Controls cycle extension. disabled DevCS*. Enabled, will extend cycle Disabled Determines width configuration device. device configured 8-bits wide. device configured bits wide. Reset Value
AccToNext
CSToWr
11:10 13:12
WrActive WrHigh
Ready
DevWidth
4.4.7
Descriptors
GT-96010A uses Dual Port (DPRAM) store SDMA descriptor's working set. This DPRAM memory mapped within GT-96010A's internal address space accessed CPU. Addresses 0x0800-0x08DC used store descriptor sets should accessed during normal data processing. (They read diagnostic purposes; note however, excessive will reduce GT96010 serial bandwidth.). Addresses 0x0900-0x0BDC store SDMA initialization current pointers. access these addresses when initializes channel clears channel after severe error occurs. Detailed descriptions these registers given corresponding sections this data sheet.
4.4.8
MPSC Address Space
MPSC Address Space allocated within GT-96010A's internal address space that allows user
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access each MPSC creating structure with preset offsets changing only base address. MPSC address space shown table below. Register Channelx SDMA Configuration Register (SDCx) Channelx SDMA Command Register (SDCMx) Channelx SDMA Current Descriptor Pointer (SCRDx) Channelx SDMA First Descriptor Pointer (SFTDPx) Channelx SDMA Current Descriptor Pointer (SCTDPx) MPSCx Main Configuration (MMCRLx) MPSCx Main Configuration High (MMCRHx) MPSCx Protocol Configuration (MPCRx) Channelx Register1 (CHxR1) Channelx Register2 (CHxR2) Channelx Register3 (CHxR3) Channelx Register4 (CHxR4) Channelx Register5 (CHxR5) Channelx Register6 (CHxR6) Channelx Register7 (CHxR7) Channelx Register8 (CHxR8) Channelx Register9 (CHxR9) Channelx Register10 (CHxR10) Channelx Register11 (CHxR11) Offset 0x0000 0x0008 0x0010 0x0018 0x001C 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0318 0x031C 0x0320 0x0324 0x0328 0x032C 0x0330 0x0334
example, Channel Configuration Register (SDC1) offset 0x0900 internal register SDC2 0x0940. This corresponds structure base Channel 0x0900 structure base Channel 0x0940 offset Configuration Register 0x0000. Using this structure, Channel Current Descriptor Pointer (SCTDP1) accessed adding structure offset 0x001C structure base 0x0900 internal register location 0x091C, while SCTDP2 accessed adding same structure offset 0x001C structure base 0x0940 internal register location 0x095C. Detailed descriptions these registers given corresponding sections this data sheet.
4.4.9
Internal Registers
Detailed descriptions registers IDMA, watchdog timer, timer/counters, Flex-TDMS, routing, general purpose ports, serial control port, baud rate generators, interrupts given corresponding sections this data sheet.
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GT-96010A Remote Access Coprocessor
IDMA
GT-96010A types DMA: serial (SDMA) independent (IDMA). SDMA channels support MPSCs Ethernet port. IDMA used move data between devices memory, memory memory.
IDMA Record
Each IDMA channel record includes four registers: byte count, source address, destination address, pointer next record. active record written controller process fetching record from memory. structure record illustrated following example.
Figure IDMA Transfer
IDMA Register Byte Count (ByteCt) Source Address (SrcAdd) Destination Address (DestADD) Next Record Pointer (NextRecPtr): 0x10
Register Name IBC[15:0] ISP[31:0] IDP[31:0] INP[31:0]
0x10 0x14 0x18 0x1c 0x100 0x104 0x108 0x10c
ByteCt SrcAdd DestAdd NextRecPtr:0x100 ByteCt SrcAdd DestAdd NextRecPtr:0xY
Transfer
Transfer
0xY+4 0xY+8 0xY+c ByteCt SrcAdd DestAdd NextRecPtr:0x100 Transfer
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5.1.1 31:30
IDMA Channel Byte Count (IBC), Offset: 0x1800 Source Width Bits 31:0 defines width source device 32-bits Reserved Reserved Reserved Bits 29:28 defines width destination device 32-bits Reserved Reserved Reserved External Source Source connected local device/DRAM Source connected external device/ DRAM (i.e. DRAM that controlled GT-96010A) External Destination Destination connected local device/ DRAM Destination connected external/ DRAM device (i.e. DRAM that controlled GT-96010A) External Descriptor Descriptor reside local Device/DRAM (master). Descriptor resides external Device/ DRAM (slave) `00' number bytes that left IDMA transfer. 0x00
29:28
Destination Width
0x00
ExtSource
ExtDest
ExtDescriptor
24:16 15:0
Reserved ByteCt
only case that source address controlled GT-96010A (i.e. local DRAM device). This happen cascaded GT-96010A systems designs that another system controller like GT-32090. only case that destination address controlled GT-96010A (i.e. local DRAM device). This happen cascaded GT-96010A systems design that another system controller like GT-32090 only case that system DRAM connected GT-96010A DRAM controller. This happen cascaded GT-96010A systems design that another system controller like GT-32090.
Note: GT-96010A supports burst transfers only 32-bit wide devices. Bits 27:25 used cascaded GT-96010A designs where device/DRAM connected another GT-96010A. above bits instruct GT-96010A access it's local resources. Instead GT-96010A will generate "CPU like" transaction accessing address space external device.
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5.1.2 31:0
IDMA Channel Source Pointer (ISP), Offset: 0xT804 Sarcoid address that IDMA controller will read data from.
5.1.3 31:0
IDMA Channel Destination Pointer (IDP), Offset: 0x1808 SrcAdd address that IDMA controller will read data from.
5.1.4 31:0
IDMA Channel Next Record Pointer (INP), Offset: 0x180C
NextRecPtr address next record IDMA. value means NULL pointer (end chained list).
IDMA Channel Command
IDMA channel command register mode operation. IDMA programmed transfer data through GT-96010A (internal) directly between DRAM devices (fly-by). internal mode, IDMA reads data from source address (devices DRAM) into internal 16-byte FIFO. From internal FIFO, data written destination address (devices DRAM) that independent from source address. fly-by mode, data transferred only between 32-bit wide DRAM 32-bit device through bus. controller will generate addresses DRAM DMAAck* device. transfer direction (DRAM device device DRAM) programmed Control register's FlyByDir field. Source addresses destination addresses programmed increment, decrement, hold same value throughout transfer. devices that absorb limited number bytes time, IDMA programmed limit number bytes transferred each cycle. accesses initiated external source (demand mode) asserting DMAReq pin, internal request (block mode) until byte count reaches zero. IDMA supports chaining linked lists records. When chaining mode enabled, IDMA controller will fetch information (the record) transfer directly memory without involving CPU. location next record Next Record Pointer register (NextRecPtr) IDMA controller will fetch records every transfer until reaches NULL pointer (NULL pointer zero). There several mechanisms status control operations. status interrupt programmed asserted every time byte count reaches zero, only when byte count reaches zero record last record chain (the NextRecPtr NULL). addition, there status that indicates whether IDMA active not. IDMA active when enabled byte count other than zero, chained mode when both byte count equal zero NextRecPtr equal NULL, when disabled internal FIFO empty. IDMA controlled disabling temporarily, next record fetch forced chained mode even current ended.
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5.2.1
IDMA Channel Command (ICM), Offset: 0x1820 FlyBy Selection fly-by normal operation. fly-by mode, data read into DMA's FIFO then written destination address. Fly-by mode, data transferred to/from devices to/from DRAM This meaningful only fly-by mode. Read from DRAM Write DRAM Source Direction. Increment source address Decrement source address Hold same value allowed Destination Direction. Increment destination address Decrement destination address Hold same value. allowed Data Transfer Limit each access. bytes bytes Reserved bytes Reserved byte bytes Reserved Chained Mode. Chained mode; when access terminated, parameters next access will come from record memory that NextRecPtr register points Non-chained mode; only values that programmed directly into ByteCt, SrcAdd, DestAdd registers used. Interrupt Mode. Interrupt asserted every time byte count reaches terminal count. Interrupt every NULL pointer Chained mode).
FlyByDir
SrcDir
DestDir
DataTransLim
ChainMod
IntMode
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GT-96010A Remote Access Coprocessor
TransMod
Transfer Mode. Demand. IDMA controlled external hardware using DMAReq# DMAAck# pins. Block. IDMA controlled software ChanEn (bit 12). Channel Enable. Disable channel accesses Enable channel accesses Fetch Next Record. Normal state (this never written `0', this toggle state after fetch completed). Forces fetch next record (even current ended). This reset after fetch completed (meaningful only Chained mode). Activity Status (read only). Channel active Channel active
ChanEn
FetNexRec
DMAActSt
IDMA Cascaded GT-96010A Designs
IDMA work single GT-96010A systems cascaded GT-96010A systems. cascaded GT-96010A systems, DRAM connected Master GT-96010A (also know Boot GT-96010A). Other GT-96010As board called Slave GT-96010As. Devices connected master GT-96010A slave GT-96010As. user programs GT-96010A access local external devices DRAM setting bits 27:25 register Byte Count field descriptor (chain mode). Note: FlyBy allowed only master GT-96010A when both device DRAM controlled same master GT-96010A. Note: FlyBy mode, device AccToNext parameters must greater than zero. Caution: Setting (i.e. external address) supplying local address descriptor, destination source might lead system halt.
IDMA Error
When accessing local address (i.e. address DRAM device that controlled GT-96010A) expected that address will mapped address spaces that mapped GT-96010A. address found, IDMA will halt process maskable IDMA error interrupt generated.
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GT-96010A Remote Access Coprocessor
Note: GT-96010A supports burst transfers only 32bit wide devices. Access 16bit 8bit devices limited read/write time. Setting Source Destination device 8/16bit, overrides DataTransLim parameters.
5.5.1
IDMA Programming Notes
Initialization:
Non-Chained mode, Source, Destination, Byte Count should initialized prior enabling IDMA. ChainMod should `1'. Chained mode, IDMA record's parameters current transaction (Source, Byte Count, Destination Next Record Pointer) should initialized DRAM Devices. address first record should initialized writing NextRecPtr channel. IDMA should enabled ChanEn=1, FetNexRec should ChainMod should `0'. 5.5.2 Restarting disabled IDMA:
Non-Chained mode, ChanEn should `1'. Chained mode, software should find first fetch took place. did, only ChanEn should `1'. not, FetNexRec should also `1'. 5.5.3 Burst Size
32bit bytes 5.5.4 Reprogramming active IDMA:
channel should first disabled ChanEn=0. Then must assured that channel longer active (for example polling DMAActSt channel). parameters should programmed prior re-enabling channel ChanEn=1. 5.5.5 IDMA Byte Swap
IDMA supports both endian little endian systems. default configuration little endian. change writing Internal Address Space Decode Control register.
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GT-96010A Remote Access Coprocessor
Timer/Counters
There four 16-bit counters GT-96010A. counters cascaded into 32-bit counters. counters gated from outside, generate output waveforms, latch external events. counters also programmed work free restart mode. restart mode, counter will count preset reference value than start count from zero again.
Timer/Counters Register
Figure Timer/Counters Register
TCNTA TCNTB TCMR TCCR TCC1 TCC2 TCRV1 TCRV2
TCCR4 TCCR3 TCCR2 Counter Counter Counter Counter TCS4 TCS3 TCS2 TCS1
offset 0x1B80 0x1B84 0x1B88 0x1B8C 0x1BC0 0x1BC4 0x1BC8 0x1BCC
TCCR1
Counter Capture Value Counter4 Capture Value Counter2 Reference Value Counter2 reference Value
Counter1 Capture Value Counter3 Capture Value Counter1 Reference Value Counter1Reference Value
Timer/Counters Mode Register (TCMR).
Offset 0x1B88 Bits Name TCS1 Description Counter Clock Source Counter clock source system clock. Counter clock source TL1. Counter Clock Source Counter clock source system clock. Counter clock source TL2. Counter Clock Source Counter clock source system clock. Counter clock source TL3. Counter Clock Source Counter clock source system clock. Counter clock source TL4. Cascade Counter Counter cascaded. Counters cascaded form 32bit counter, counter Reset Value
TCS2
TCS3
TCS4
CSA1
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GT-96010A Remote Access Coprocessor
Bits
Name CSB2
Description Cascade Counter Counter cascaded. Counters cascaded form 32bit counter, counter Reserved.
Reset Value
31:6
When set, TCCR2 have effect. When set, TCCR4 have effect.
Timer/Counters Configuration Register (TCCR)
Offset 0x1B8C TCCR divided into 8-bit configuration registers. Each configuration registers controls 16-bit counters. format TCCRx registers given below. value each TCCRx register after reset 0xC0. Bits Name Description Free Running/Restart Free Run. Counter always counts 0xFFFF (0xFFFF.FFFF 32bit counter) before wraparound Restart. Counter reset restarts counting when reaches it's reference value. Reset Counter Reset. Counter disabled Enable. Counter enabled. Reserved Output mode. Control TOx# pins behavior. Pulse Mode. Asserted low, system cycle clock pulse will generated when counter reaches it's reference value. Toggle Mode. counter output will toggled whenever timer reaches it's reference value. Capture Enable. effect when TCSx set. Disable Capture Function. Capture rising edge generate interrupt. Capture falling edge generate interrupt. Capture edge generate interrupt. Reset Value
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GT-96010A Remote Access Coprocessor
Bits
Name
Description Gate Enable Enable Gate operation. Disable Gate operation. Gate Mode Restart Mode. TGATEx# falling edge enables restarts counter. TGATEx# rising edge disables counter. Normal Mode. TGATEx# falling edge enables counter. TGATEx# rising edge disables counter.
Reset Value
32-bit Counter Operation
When counters cascaded form 32-bit counter TCCR1 used control counter TCCR2 have effect counter When counters cascaded form 32-bit counter TCCR3 used control counter TCCR4 have effect counter
Gating Operation
TGATE[2:1]# pins used gate counters. 16-bit mode, Counters controlled TGATE1# pin. Counters controlled TGATE2# pin. 32-bit counter mode, Counter gated TGATE1# counter gated TGATE2# When gating enabled counter TCCRx rising edge TGATEx disables counter counter holds current value. restart mode TCCRx falling edge TGATEx restarts counter from zero. normal mode TCCRx falling edge TGATEx restarts counter from current value. Figure Counter Gating Operation
TGATE1 Counter Counter Restart Mode Normal Mode
Generation Pulses Waveforms
TO[4:1]# pins used generate pulses shape waves system use. corresponds output from Counter both pulse toggle mode, counter must restart mode (FRR TCCRx pulse mode TCCRx counter will count reference value. Then cycle pulse, asserted low, will generated corresponding pin. reference value changed dynamically change distance between pulses. toggle mode TCCRx counter will count reference value. Then corresponding will transition high-to-low low-to-high. reference value changed dynamically change duty cycle.
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Figure Generating Output Pulses Waveforms
Counter Reference Counter count
Reference Pulse Mode Toggle Mode
Capturing External Events
TL[4:1] pins used capture external events. When capture feature enabled TCCRx, capture rising edge, capture falling edge, capture edge), counter's value latched counter capture value register upon appropriate transition corresponding pin. then read this value. maskable interrupt generated when capture feature enabled.
Using External Clocks
TL[4:1] pins used external clock sources counters. enabled clock source Counter TCS1x TCMR `1'. When using TL[4:1] clock sources, they will synchronized system clock before feeding counters. maximum allowed frequency TL[4:1] this mode system_clock/4
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GT-96010A Remote Access Coprocessor
Watchdog Timer
GT-96010A internal watchdog timer 32-bit count-down counter that used generate non-maskable interrupt reset system event unpredictable software behavior. After watchdog enabled, free running counter that needs serviced periodically order prevent expiration.
Watchdog Register
Figure Watchdog Register
CTL2 CTL1 Preset_VAL NMI_VAL
register
offset 0x1B00 0x1B04
Watch Configuration (WDC)
Offset 0x1B00. Bits 23:0 Name Preset_VAL Description This field holds most significant bits which watchdog counter will load each time enabled serviced. After reset, this field 0xFF.FFFF. preset value equal 0xPreset_VAL,FF. write sequence `01' followed `10' into CTL1 disables/enables watchdog. write sequence `01' followed `10' CTL2 services watchdog timer. Reserved. Maskable Interrupt. When watchdog counter reach value holds NMI_VAL, this set, asserting NMI# pin. This used input processor NMI# pin. This read only. Watchdog Expiration. When watchdog counter reaches 0x0000.0000, this set, asserting WDE# pin. WDE# used reset entire system. This read only. Enable. This read only. Watchdog disabled, counter loaded with Preset_VAL, reset `0'. Watchdog enabled. Reset Value 0xFF.FFFF
24:25 27:26
CTL1 CTL2
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7.2.1
Watch Value register (WDV)
Offset 0x1B04. Bits 23:0 Name NMI_VAL Description NMI_VAL least significant bits 32-bit value. upper bits `00'. value 0x00,NMI_VAL. After reset value NMI_VAL 0x000.0000. Reserved.
31:24
Watchdog Operation.
After reset, watchdog enabled begins counting down from 0xFFFF.FFFF zero. watchdog must serviced periodically order avoid reset (WDE#). Watchdog service performed writing `01' CTL2, then writing `10' CTL2. Upon watchdog service, GT-96010A clears bits set) reloads Preset_VAL into watchdog counter. write sequence `01' followed `10' into CTL1 disables/enables watchdog. current status watchdog read WDC. When disabled, GT-96010A clears bits set) reloads Preset_VAL into watchdog counter. Preset_VAL NMI_VAL changed while watchdog enabled. However, Preset_VAL will affect watchdog only after loaded into watchdog counter (e.g. after watchdog service). watchdog serviced before counter reaches zero there watchdog expiration. set, asserting WDE# pin. order deassert WDE#, GT-96010A must reset. GT-96010A holds WDE# asserted another system cycles after reset assertion.
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General Purpose Ports
GT-96010A General Purpose Ports include dedicated 16-bit General Purpose Interface that generate interrupts (GPI pins 0-15) General Purpose Pins (GPP pins 16-30 GPPA/B/C). general purpose pins ports pins when those ports use.
General Purpose Ports Register
Figure General Purpose Ports Register
GPPA GPPB GPPC GPCR GPVR
Level GD30GD25GD20 GD29GD24GD19 GD28GD23GD18 GD27GD22GD17 GD26GD21GD16 Value GI20 GI19 GI18 GI17 GI16
0x3C0C 0x3C10 0x3C14 0x3C40 0x3C44
8.2.1
General Purpose Pins A/B/C
GPPA/B/C Configuration Registers (GPPA, GPPB, GPPC)
GPPA/B/C registers used interface port general purpose pins. Each port dedicated register. Bits 16-20 GPPx registers called bits. bits define corresponding pins working inputs outputs. Setting configures work input pin; setting configures work output pin. Bits GPPx registers called bits. bits used store data. They read only input pins read/write output pins. reads input data input pins from bits. writes output data output pins bits.
8.3.1
General Purpose Interface
Configuration Register (GPCR)
General Purpose Interface Configuration Register used control dedicated 16-bit general purpose interface. Bits 0-15 control direction pins. Setting configures associated input pin; setting configures associated output pin. Bits 16-31 configured polarity input pin. Setting configures associated asserted low; setting configures associated asserted high. GT-96010A will negate asserted input before latching inside. Note: level bits affect output pins. GT-96010A will always drive data without changes through it's output pins.
GI30 GI29 GI28 GI27 GI26
GI25 GI24 GI23 GI22 GI21
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8.3.2
Value Register (GPVR)
Each dedicated pins associated GPVR. pins that configured input pins, associated GPVR bits read only contain value pin. When input configured asserted writing polarity GPCR), value GPVR will negated value input pin. pins that configured output pins, associated GPVR bits read written from CPU. read value input reading GPVR drive value pins writing GPVR. 8.3.3 Interrupts
Input pins generate maskable interrupts. Bits 0-15 Interrupt Cause register (ICR6) used hold interrupt events driven from GPP. When input GPVR `1', corresponding ICR6 will `1'. cause will stay asserted until clears writing GT-96010A interrupts level sensitive. external agent must keep interrupt request signal asserted until clears interrupt source. Note: external agent must keep interrupt request signal asserted until clears interrupt source. Failure will lead unpredictable results.
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Communications
Overview
GT-96010A's communications unit includes several functional blocks: Multi Protocol Serial Controllers (MPSCs), Ethernet controller, flexible time division multiplexers (Flex-TDMs), serial control port (SCP). Integral operation these units several support functions: address/data arbitration scheme, serial channels (SDMAs), baud rate generators. MPSCs process data that received transmitted into appropriate format protocol various modes supported (i.e. Ethernet, HDLC, BISYNC, etc.). There dedicated receive transmit DPLLs each MPSC. DPLL encodes/decodes serial stream into popular codes including NRZ, NRZI FM0. receive DPLL also recover receive clock from receive stream. MPSCs described detail other sections this data sheet. transmit receive clocks generated four on-chip baud rate generators from serial input associated with MPSC. Ethernet controller handles ethernet stream compatible with most popular SIAs. responsible various procedures such address recognition, error detection collision backoff. ethernet controller returns status that needed software-based counters ethernet descriptors. There Serial (SDMA) channels GT-96010A. SDMA channels mechanism used transfer data between communications channels (the MPSCs Ethernet port) DRAM. SDMA channel allocated MPSC0 SDMA1 MPSC0 SDMA channel allocated Ethernet Ethernet receive operations, MPSC Ethernet controller moves data into dedicated FIFOs corresponding SDMA. Then, using descriptors user, SDMA moves data into buffers DRAM. transmit operations, SDMA uses descriptors user move data buffers DRAM dedicated MPSC Ethernet controller moves data communications link. SDMA channel descriptors chained data structure. They work without interference after appropriate initialization. SDMA channels programed generate interrupts buffer boundaries. receive SDMAs freely when enabled always expect find valid descriptor when required. When receive SDMA channel accesses invalid descriptor, receive SDMA process will halt with resource error status. transmit SDMAs freely when enabled until they reach descriptor chain. When transmit SDMA reaches descriptor chain last descriptor marked end-of-frame descriptor, transmit SDMA process will halt with resource error status. SDMAs arbitrate transmit data from descriptors buffers DRAM.
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GT-96010A Remote Access Coprocessor
Figure
BRG1 BRG2 BRG3 BRG4
GT-96010A
SCLK
MPSC
RxCLK TxCLK
SDMA FIFO
DPLL
Protocol Processing /Data Path
(performs clock data recovery)
16-bits (depends mode)
DMAReq Done
arbiter
Buffer Note that MPSC4-6 TSCLK input TxCLK Buffer Buffer
Descriptor Descriptor Descriptor
DRAM
DRAM
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GT-96010A Remote Access Coprocessor
Address/Data Arbitration
internal agents: ethernet address recognition controller MPSCs ethernet controller IDMA external agents: Another GT-96010A Acontroller etc. external
GT-96010A arbiter receives requests from three main resources. They are:
10.1
Arbitration Priority Scheme
GT-96010A arbiter grants request according scheme shown below. arbiter fixed priority controller. After serving higher priority request controller will service next lower priority request even another higher priority request pending. Priority takes precedence only when scheduling concurrent requests. Figure Arbitration Scheme
hashReq?
hashGNT
HoldA internalReq? internalGNT
HoldA
Hold
externalReq?
externalGNT
bstatReq?
CpuOwn
anyReq?
Hold
internal arbiter grants requests from internal agents according following priority: Ethernet address recognition controller MPSC0 MPSC0 Ethernet controller Ethernet controller
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GT-96010A Remote Access Coprocessor
MPSC1-5 round robin each channel, priority over IDMA When there pending request from more resources (1)-(6), internal arbiter asserts internalReq signal. When ADbus arbiter asserts internalGnt signal, internal arbiter will then grant resources (1)-(6) burst access according it's priority. When there pending request (Hold=0), owns bus. When there pending request, GT-96010A asserts Hold signal. When GT-96010A owns (HoldA=1), arbiter grants according above arbitration scheme. BSTAT asserted, will relinquished only there other pending requests. Note: BSTAT control signal i960 processor which indicates request from bus. BSTAT allows gain access even when there other requests pending.
10.2
BSTAT
When there pending requests, GT-96010A always relinquishes control regarding BSTAT status. Also, when there neither Hash Requests (i.e., Ethernet Controller off), External Requests (i.e., AdBusReq signal), GT-96010A deasserts Hold (thus relinquishing bus) cycle between consecutive SDMA bursts. following table summarizes maximum number bursts GT-96010A might execute before returning control CPU.
System Configuration MPSCs IDMA Only
BSTAT State Don't Care Deasserted
Number Bursts burst Until pending requests served Bursts Until pending requests served Bursts Until pending requests served Three Bursts
MPSCs IDMA Ethernet Asserted Deasserted MPSCs IDMA Master device Asserted Deasserted MPSC IDMA Ethernet Master device Asserted
MPSC/SDMA maximum burst length four long words descriptor fetch. IDMA maximum burst length four long words. External Agent hold prolonged periods time, depending system design device being access example, slow ADbus devices require long burst durations. hash DRAM access always long word burst. GT-96010A looks BSTAT during decision cycle. user should keep BSTAT asserted until after GT-96010A deasserts Hold.
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GT-96010A Remote Access Coprocessor
11.1
Serial (SDMA)
Overview
There SDMA channels GT-96010A. SDMA channels mechanism used transfer data between communications channels (the MPSCs Ethernet port) DRAM. SDMA channel allocated MPSC0 SDMA1 MPSC0 SDMA channel allocated Ethernet Ethernet Each SDMA channel dedicated FIFO data buffering (for total FIFOs). FIFOs 0-12 MPSCs 0-6, bytes deep. FIFOs 13-14 serve Ethernet controller, bytes deep. receive operations, MPSC Ethernet controller moves data into dedicated FIFOs corresponding SDMA. Then, using descriptors user, SDMA moves data into buffers DRAM. transmit operations, SDMA uses descriptors user move data buffers DRAM into dedicated MPSC Ethernet controller moves data onto communications link. SDMA channel descriptors chained data structure. They work without interference after appropriate initialization. SDMA channels programed generate interrupts buffer boundaries. receive SDMAs freely when enabled always expect find valid descriptor when required. When receive SDMA channel accesses invalid descriptor, receive SDMA process will halt with resource error status. transmit SDMAs freely when enabled until they reach descriptor chain. When transmit SDMA accesses invalid descriptor last descriptor marked frame descriptor, transmit SDMA process will halt with resource error status. SDMAs arbitrate transmit data from descriptors buffers DRAM.
11.2
SDMA Descriptors
SDMA data transfers done chained link descriptors. following rules must followed when using GT-96010A SDMA descriptors: Each descriptor 32-bit words must quad-word aligned (i.e. AD[3:0] 0x00). descriptors reside anywhere address space pointed 32-bit pointer. normal mode (HDLC, Ethernet, Transparent) buffers associated with descriptors must 32-bit word aligned. latency, byte, mode (BISYNC, UART, Transparent) buffers size alignment. buffers associated with descriptors start byte location. SDMA buffers 64Kbytes length pointed 32-bit pointer. Ethernet buffers must least bytes long. Ethernet buffers must least bytes long.
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GT-96010A Remote Access Coprocessor
Figure SDMA Descriptor Format Descriptor Offset Command Status Buffer Size Buffer Pointer Next Descriptor Pointer Descriptor Command Status Byte Count Shadow Byte Count Buffer Pointer Next Descriptor Pointer Reserved Value Byte Mode Byte Count
11.2.1 Command/Status, Offset:
Bits 31:0
Name Command/Status
Description This field contains commands bits that instruct SDMA process buffer status bits that SDMA updates upon closing descriptor. uses status bits evaluate buffer status. Except bits definition bits vary depending which mode being used. sections MPSCs Ethernet controller these definitions. Owner Bit. When this buffer processed GT-96010A. When this "0", buffer processed CPU. SDMA process will halt when descriptor with owner fetched. Auto Mode. When Set, SDMA will clear Owner descriptor buffer processing. Determined mode selected.
Reset Value
29:24
Enable Interrupt. GT-96010A will generate maskable interrupt when closing descriptor with set.
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Bits 22:16 15:0
Name
Description Determined mode selected.
Reset Value
First Bit. Indicates descriptor start frame. Last Bit. Indicates descriptor frame. Determined mode selected.
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GT-96010A Remote Access Coprocessor
11.2.2 Buffer Size, Byte Count Descriptor), Offset: Bits 31:18 Name Buffer Size Description buffer size field valid only receive descriptors reserved transmit descriptors.The field written read GT-96010A. When buffer byte counter SDMA receive channel reaches buffer size value, SDMA will close buffer descriptor will move next buffer. Buffer Size must multiple when working with 16-bit data path (normal mode). Buffer Size size when working with 8-bit data path (low bandwidth mode). 17:16 15:0 Byte Count Reserved Byte count number bytes that were written SDMA into buffer. This number will never greater than Buffer Size. must initialize Byte Count field with 0x0000. Reset Value
11.2.3 Byte Count, Shadow Byte Count Descriptor), Offset: Bits 31:16 Name Byte Count Description Byte count number bytes transmitted. Zero byte counters supported with retransmission. zero byte buffers with Ethernet LAP-D protocols. must initialize this field identical Byte Count field. GT-96010A subtracts number bytes actually transmitted from this parameter. Usually GT-96010A writes this field when closing descriptor. However, when transmit SDMA halts transmit error, this number used determine number bytes that were fetched into GT-96010A. Setting both Byte Count Shadow Byte Count will cause SDMA close descriptor move next descriptor, both neither bits set. Setting Byte Count Buffer Size transmit descriptors with bits will lead unpredictable behavior. Reset Value
15:0
Shadow Byte Count
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GT-96010A Remote Access Coprocessor
11.2.4 Buffer Pointer, Offset: Bits 31:0 Name Buffer Pointer Description 32-bit Buffer Pointer field points beginning buffer that associated with descriptor. buffer reside anywhere 128Mbyte DRAM address space1. location buffer's address space programmed before releases descriptor GT-96010A use. Reset Value
When using local DRAM controller, buffer pointer should point valid address within allocated DRAM space. When working with external controller (e.g. slave mode), buffer pointer point address address space long valid address (i.e. address allocated within DRAM, SRAM, SDRAM etc.)
11.2.5 Next Descriptor Pointer, Offset: Bits 31:4 Name Next Descriptor Pointer (bits 31:4) Description 32-bit Next Descriptor field points beginning next descriptor descriptors chain list. descriptor reside anywhere 128Mbyte DRAM address space1. Bits [3:0] Next Descriptor Pointer must to'0'. Descriptors page aligned. GT-96010A encounters NULL address (all address) Next Descriptor Pointer will fetch next descriptor process will stop. must restart channel order restart Rx/Tx process. Must `0'. Reset Value
Next Descriptor Pointer (bits 3:0)
When using local DRAM controller, buffer pointer should point valid address within allocated DRAM space. When working with external controller (e.g. slave mode), buffer pointer point address address space long valid address (i.e. address allocated within DRAM, SRAM, SDRAM etc.)
11.3
SDMA configuration register (SDC)
Each SDMA dedicated configuration register (SDCx). must initialized before enabling SDMA channel. Figure SDMAx Configuration Register (SDCx)
BLMT BLMR
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GT-96010A Remote Access Coprocessor
11.3.1 SDMA Configuration Register (SDCx) Bits 31:9 Name Description Reserved Local DRAM. This used cascaded GT-96010A systems when DRAM attached another GT96010A GT32090 device. Local DRAM. SDMA access memory will routed on-chip DRAM controller. System DRAM. SDMA access memory will routed device bus. BLMT Big/Little Endian Transmit Mode. GT96010A supports little endian configuration channel maximum system flexibility. BLMT only affects data movements DRAM.1 Little endian convention. endian convention Little/Endian Receive Mode. GT-96010A supports little endian configuration channel maximum system flexibility. BLMR only affects data movements DRAM. Descriptors always considered Little Endian. Little endian convention. endian convention Retransmit Count. collision modes (LAP-D Ethernet), after executing backoff procedure times, SDMA will close buffer with Retransmit Limit (RL) error, maskable interrupt will generated, SDMA will state. Transmit Demand command should issued order start transmission process. When field 0x00, GT-96010A will retransmit forever. needs issue abort command order stop retransmit process. Reset Value
BLMT
BLMR
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GT-96010A Remote Access Coprocessor
Bits
Name
Description Single Frame Mode Multi frame mode. GT-96010A will read many frames needed into FIFO order keep transmit FIFO full. FIFO handle more than frame time. Single frame mode. first descriptor will fetched before current frame's last descriptor closed. Note: must HDLC Collision mode, BISYNC protocols. also recommended UART. Note: hardwired Ethernet channel. Reading this always returns `1'. Note: When "0", Lost cannot reported correct descriptor/ frame. Ethernet HDLC modes must proper operation.
Reset Value
Receive FIFO Threshold Bytes Half FIFO bytes) MPSC, 32Bytes Ethernet Note: When working with 8-bit data path, threshold always byte regardless value. recommended that this case. Note: When `0', SDMA will burst. will transfer long word bits) each transfer.)
user define SDMA descriptors area endian setting ISEndian Internal Address Space Decode Control Register
11.4
SDMA Command Register (SDCMx)
Each MPSC Ethernet channel dedicated SDMA Command Register (SDCMx) register control process. Figure SDMA Command Register (SDCMx).
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GT-96010A Remote Access Coprocessor
11.4.1 SDMA Command Register (SDCMx)
Bits
Name
Description Abort Transmit. sets when needs abort transmit SDMA channel operation. When set, SDMA aborts operation goes IDLE state. descriptor closed. GT-96010A clears both bits when entering IDLE state. must poll When `0', GT-96010A completed abort sequence. After abort should write first descriptor address than `1'. Reserved
Reset Value
30:24
Demand. When this `1', will fetch descriptor will start transmission process. GT-96010A will clear when successfully ends SDMA transmit process. will also clear when resource error occurs, when transmit process halted channel error (i.e. CTS# lost), when issues abort command. Reserved
22:17
Stop SDMA will stop transmission frame (i.e. buffer with `1'). After transmitting last buffer, transmit SDMA goes IDLE state. GT-96010A clears when entering IDLE state. After SDMA stops, should write first descriptor address than `1'. GT-96010A signals with interrupt when stop procedure accomplished. Abort Receive. sets when needs abort receive SDMA channel operation. When set, SDMA aborts operation goes IDLE state. descriptor closed. GT-96010A clears both bits when entering IDLE state. must poll When `0', GT-96010A completed abort sequence. After abort should write descriptor address then `1'. Reserved
14:8
Enable DMA. When this `1', SDMA will fetch descriptor will ready receive frame. GT-96010A will clear when GT-96010A receive SDMA resource error when issues abort command. Reserved
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GT-96010A Remote Access Coprocessor
11.5
SDMA Descriptor Pointer Registers
Each SDMA channel three 32-bit registers that reside special descriptor's Dual Port Ram, located internal address space GT-96010A. Figure SDMA Descriptor Pointer Registers.
SDMAx Current Receive Descriptor Pointer (SCRDPx) SDMAx Current Transmit Descriptor Pointer (SCTDPx) SDMAx First Transmit Descriptor Pointer (SFTDPx)
11.5.1 SDMA Current Receive Descriptor Pointer (SCRDP) SCRDPx points current receive descriptor DRAM. must write this register with first descriptor address before enabling SDMA receive channel. When SDMA receive channel enabled will fetch first descriptor pointed SCRDPx part start SDMA procedure. 11.5.2 SDMA Current Transmit Descriptor Pointer (SCTDP) SCTDPx points current transmit descriptor DRAM. must write this register with first descriptor address before enabling SDMA transmit channel. When SDMA transmit channel enabled will fetch first descriptor pointed SCRDPx part start SDMA procedure. 11.5.3 SDMA First Transmit Descriptor Pointer (SFTDP) SFTDPx points first descriptor transmit frame. must write this register with first descriptor address before enabling SDMA transmit channel. SDMA transmit controller uses SFTDP when needs restart transmission after collision (HDLC Ethernet mode only). GT-96010A updates content SFTDP each time fetches descriptor with (first) "1". Note: must write SCTDP SFTDP same address before enabling corresponding SDMA transmit channel.
11.6
Transmit SDMA
11.6.1 Transmit SDMA Definitions (Start Frame descriptor): Descriptor with (First) (End Frame descriptor): Descriptor with (Last) bits before releasing descriptor GT-96010A transmission. frame starts with descriptor ends with descriptor. frame contained buffer split over many buffers. frame stored buffer, associated descriptor will have both bits non-frame oriented protocol (e.g. BISYNC UART), recommended that both bits each buffer.
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GT-96010A Remote Access Coprocessor
11.6.2 Transmit SDMA Flow following steps executed during normal transmit SDMA process: Before enabling SDMA channel must prepare valid descriptor with owner `1'. must then write first descriptor address SCTDP SFTDP registers. issues Transmit Demand command. SDMA controller will then fetch first descriptor will start SDMA process. When buffer completed, SDMA will close buffer descriptor setting correct transmit status writing Owner Bit, returning buffer CPU. 11.6.3 Retransmit HDLC (LAP-D) mode When working collision mode (see Section 13.5.3 page 87), GT-96010A will retransmit collision occurs before SDMA fetches descriptor. frame constructed from more than buffers, user must assure that there enough data first buffers compensate this behavior. GT-96010A buffer bytes internal FIFO data path. This should considered when preparing LAP-D transmit frame.
11.6.4 Transmit SDMA Notes transmit SDMA process frame oriented. Transmit SDMA will clear first frame descriptor owner until last frame descriptor closed. transmit SDMA will then write first descriptor Owner generate interrupt first descriptor set. transmit SDMA will stop process whenever reaches descriptor with NULL (0x00000000) address field when fetches descriptor with Owner "0". such case SDMA controller will clear before returning IDLE state. normal operation, transmit SDMA never expects find NULL address Not-Owned descriptor middle frame process (i.e. current descriptor "0"). this situation occurs, transmit SDMA controller will abort, will cleared, RESOURCE ERROR maskable interrupt will generated. Note: collision mode, collision occurs exactly clock cycle after resource error, GT-96010A will ignore resource error retransmit frame. When wants interfere with transmit process without corrupting ongoing transmit process, issue STOP command writing bit. transmit SDMA controller will than continue process until reaching first descriptor chain with "1". When issuing command will reset upon entering IDLE state. then issue Transmit Demand command order restart SDMA process.
11.7
Receive SDMA
11.7.1 Receive SDMA Definitions (Start Frame descriptor): Descriptor with (First) (End Frame descriptor): Descriptor with (Last)bit bits before releasing descriptor GT-96010A. frame starts with descriptor ends with descriptor. frame contained buffer split over many buffers. frame stored buffer, associated descriptor will have both bits Refer various protocols buffer handling done.
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GT-96010A Remote Access Coprocessor
11.7.2 Receive SDMA Flow following steps executed during normal transmit SDMA process: Before enabling SDMA channel must prepare valid descriptor with owner must then write descriptor address SCRDP register before enabling receive SDMA chann
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