APPLICATION BENEFITS 64-bit LANCAM facilitates numerous operation

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APPLICATION BENEFITS 64-bit LANCAM facilitates numerous operation

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MU9C5480A/L LANCAMs®
APPLICATION BENEFITS
64-bit LANCAM facilitates numerous operations: speed grade allows processing both within equivalent 111, Base-T Base-T Ethernet ports Full features allow operations mask, basis Expanded powerful instruction list processing needs Fully compatible with MUSIC LANCAM series, cascadable practical length without performance penalties Shiftable Comparand mask registers assist proximate matching algorithms
DISTINCTIVE CHARACTERISTICS
64-bit CMOS content-addressable memory (CAM) 16-bit Fast compare speed Dual configuration register rapid context switching 16-bit CAM/RAM segments with MUSIC's patented partitioning output flags enable faster system performance Readable Device Selectable faster operating mode with wait states after no-match Validity setting accessible from Status register Single cycle reset Segment Control register 44-Pin PLCC package Volt (5480A) Volt (5480L) operation
URCE ARAND*
ADDRE
ADDRE ADDRE
FLAG
Block Diagram
LANCAM, MUSIC logo, phrase "MUSIC Semiconductors" registered trademarks MUSIC Semiconductors. MUSIC trademark MUSIC Semiconductors. Certain features this device patented under Patent 5,383,146.
October 1998 Rev.
MU9C5480A/L
GENERAL DESCRIPTION
MU9C5480A MU9C5480L LANCAMs 64-bit content-addressable memories (CAMs), with 16-bit wide interface. They compatible with devices MUSIC LANCAM family. Content-addressable memories, also known associative memories, operate converse random access memories (RAM). RAM, input device address output data stored that address. CAM, input data sample output flag indicate match address matching data. result, searches large databases matching data short, constant time period, matter many entries database. ability search data words bits wide allows large address spaces searched rapidly efficiently. patented architecture links each entry associated data makes this data available after successful compare operation. MUSIC LANCAMs ideal address filtering translation applications switches routers. LANCAMs also well suited encryption, database accelerators, image processing.
OPERATIONAL OVERVIEW
LANCAM, user loads data into Comparand register, which automatically compared valid locations. device then indicates whether more valid locations contains data that matches target data. status each location determined validity bits each memory location. bits encoded render four validity conditions: Valid, Empty, Skip, RAM, shown Table memory partitioned into associated segments 16-bit boundaries, using available mask registers, CAM/RAM partitioning arbitrary size between zero bits. LANCAM's internal data path bits wide rapid internal comparison data movement. Vertical cascading additional LANCAMs daisy chain fashion extends memory depth large databases. Cascading requires external logic. Loading data Control, Comparand, mask registers automatically triggers compare. Compares also initiated command device. Associated data available immediately after successful compare operation. Status register reports results compares including flags addresses. mask registers available used different ways: mask comparisons mask data writes. random access validity type allows additional masks stored array where they retrieved rapidly. simple four-wire control interface commands loaded into Instruction decoder control device. powerful instruction increases control flexibility minimizes software overhead. Additionally, dedicated pins match multiple-match flags enhance performance when device controlled state machine. These other features make LANCAM powerful associative memory that drastically reduces search delays.
Skip
Empty
Entry Type Valid Empty Skip
HIGH HIGH
HIGH HIGH
Cycle Type Command Write cycle Data Write cycle Command Read cycle Data Read cycle
Table Entry Types Validity Bits Rev.
Table Cycles
MU9C5480A/L
DESCRIPTIONS
signals implemented CMOS technology with levels. Signal names that start with slash ("/") active LOW. Inputs should never left floating. architecture draws large currents during compare operations, mandating good layout bypassing techniques. Refer Electrical Characteristics section more information.
(Chip Enable, Input, TTL) input enables device while LOW. falling edge registers control signals /CM, /EC. rising edge locks daisy chain, turns pins, clocks Destination Source Segment counters. four cycle types enabled shown Table (Write Enable, Input, TTL) input selects direction data flow during device cycle. selects Write cycle HIGH selects Read cycle. (Data/Command Select, Input, TTL) input selects whether input signals DQ15-0 data commands. selects Command cycles HIGH selects Data cycles. (Enable Daisy Chain, Input, TTL) signal performs functions. input enables output show results comparison, shown Figure page falling edge given cycle, output enabled. Otherwise, output held HIGH. signal also enables /MF- daisy chain, which serves select device with highest-priority match string LANCAMs. Tables
page explain effect signal device with without match both Standard Enhanced modes. must HIGH during initialization. DQ15-0 (Data Bus, I/O, TTL) DQ15-0 lines convey data, commands, status from LANCAM. control direction nature information that flows from device. When HIGH, DQ15-0 HIGH-Z. (Match Flag, Output, TTL) output goes when more valid matches occur during compare cycle. becomes valid after goes HIGH cycle that enables daisy chain first cycle that registered previous falling edge Figure page 14). daisy chain, valid match(es) higher priority devices passed from input /MF. daisy chain enabled match flag disabled Control register, output only depends input device (/MF=/MI). HIGH there match when daisy chain disabled goes HIGH when HIGH previous falling edge /E). System Match flag last device daisy chain. will reset when active configuration register changed. (Match Input, Input, TTL) input prioritizes devices vertically cascaded systems. connected output previous device daisy chain. first device chain must tied HIGH.
44-Pin PLCC 4(Top View) (Top
ESET
(Device Match Flag, Output, TTL) output when more valid matches occur during current last previous compare cycle. output qualified /MI, reflects match flag from that specific device's Status register. will reset when active register changed. (Device Multiple Match Flag, Output, TTL) output when more than valid match occurs during current last previous compare cycle. output qualified /MI, reflects multiple match flag from that specific device's Status register. will reset when active register changed.
Pinout Diagram Rev.
MU9C5480A/L
DESCRIPTIONS Continued
(Full Flag, Output, TTL) enabled Control register, output goes when empty memory locations exist within device (and daisy chain above device indicated pin). System Full flag last device daisy chain, Next Free address resides device with HIGH. disabled Control register, output only depends input (/FF /FI). (Full Input, Input, TTL) input generates CAM-Memory-System-Full indication vertically cascaded systems. connected output previous device daisy chain. first device chain must tied LOW. /RESET (Reset, Input, TTL) /RESET must driven place device known state before operation, which will reset device conditions shown Table page LANCAM devices have hardware reset that operates parallel with internal Power-on-reset circuitry, sets device same condition. compatibility with MU9C1480, /RESET internal pull-up resistor left unconnected. /RESET should driven levels, directly timeout. must kept HIGH during /RESET. TEST1, TEST2 (Test, Input, TTL) These pins enable MUSIC production test modes that usable application. They should connected ground, either directly through pull-down resistor, they left unconnected. These pins implemented versions these products. VCC, (Positive Power Supply, Ground) These pins power supply connections LANCAM. must meet voltage supply requirements Operating Conditions section relative pins, which volts (system reference potential), correct operation device. ground power pins must connected their respective planes with adequate bulk high frequency bypassing capacitors close proximity device. MU9C5480A MU9C5480L compatible with original MU9C1480 connections, operated slower switching characteristics without connections pins connections pins
FUNCTIONAL DESCRIPTION
LANCAM content-addressable memory (CAM) with 16-bit network address filtering translation, virtual memory, data compression, caching, table lookup applications. memory consists static CAM, organized 64-bit data fields. Each data field partitioned into subfield 16-bit boundaries. contents memory randomly accessed associatively accessed compare. During automatic comparison cycles, data Comparand register automatically compared with "Valid" entries memory array. Device read using instruction (see Table page 22). data inputs outputs LANCAM multiplexed data instructions over 16-bit bus. Internally, data handled 64-bit basis, since Comparand register, mask registers, each memory entry bits wide. Memory entries globally configurable into segments 16-bit boundaries, described Patent 5,383,146 assigned MUSIC Semiconductors. Seven different CAM/RAM splits possible, with width going from four segments, remaining width going from three zero segments. Finer resolution compare width possible invoking mask register during compare, which does global masking basis. subfield
Rev.
contains associative data, which enters into compares, while subfield contains associated data, which compared. bridges, subfield could hold, example, port-address aging information related destination source address information held subfield given location. translation application, field could hold dictionary entries, while field holds translations, with almost instantaneous response. Each entry validity bits (known Skip Empty bit) associated with define particular type: Empty, Valid, Skip, RAM. When data written active Comparand register, active Segment Control register reaches terminal count, contents Comparand register automatically compared with portion valid entries memory array. added versatility, Comparand register barrelshifted right left time. Compare instruction then used force another compare between Comparand register portion memory entries four validity types. After Read Move from Memory operation, validity bits location read moved will copied into Status register, where they read using Command Read cycles.
MU9C5480A/L
FUNCTIONAL DESCRIPTION Continued
Data moved from data registers (CR, MR1, MR2) memory location that based results last comparison (Highest-Priority Match Next Free), absolute address, location pointed active Address register. Data also written directly memory from using above addressing modes. Address register directly loaded increment decrement, allowing DMA-type reading writing from memory. sets configuration registers (Control, Segment Control, Address, Mask Register Persistent Source Destination) provided permit rapid context switching between foreground background activities. currently active configuration registers controls writes, reads, moves, compares. foreground typically would pre-loaded with values useful comparing input data, often called filtering, while background would pre-loaded with values useful housekeeping activities such purging entries. Moving from foreground task filtering background task purging done issuing single instruction change current configuration registers. match condition device reset whenever active register changed. active Control register determines operating conditions within device. Conditions this register's contents reset, enable disable Match flag, enable disable Full flag, CAM/RAM partitioning, disable select masking conditions, disable select auto-incrementing auto-decrementing Address register, select Standard Enhanced mode. active Segment Control register contains separate counters control writing 16-bit data segments selected persistent destination, control reading 16-bit data segments from selected persistent source. There active mask registers time, which selected mask comparisons data writes. Mask Register both foreground background mode support rapid context switching. Mask Register does have this mode, shifted left right time. masking comparisons, data stored active selected mask register determines which bits comparand compared against valid contents memory. HIGH mask register, same position Comparand register becomes "don't care" purpose comparison with memory locations. During Data Write cycle instruction, data specified active mask register also determine
which bits destination will updated. HIGH mask register, corresponding destination unchanged. match line associated with each memory address into priority encoder where multiple responses resolved, address highest-priority responder (the lowest numerical match address) generated. applications, multiple response might indicate error. other applications existence multiple responders valid. Four input control signals commands loaded into instruction decoder control LANCAM. four input control signals determine cycle type. control signals tell device whether data represents data command, input output. Instruction logic control moves, forced compares, validity manipulations, data path within device decode commands. Registers (Control, Segment Control, Address, Next Free Address, etc.) accessed using Temporary Command Override instructions. data path from to/from data resources (comparand, masks, memory) within device until changed Select Persistent Source Destination instructions. After Compare cycle (caused either data write Comparand mask registers, write Control register, forced compare), Status register contains address Highest-Priority Matching location that device, concatenated with page address, along with flags indicating internal match, multiple match, full. When Status register read with Command Read cycle, device with Highest-Priority match will respond, outputting System Match address bus. internal Match (/MA) Multiple Match (/MM) flags also output pins. Another flags (/MF /FF) that qualified match full flags previous devices system directly available output pins, independently daisy-chained provide System Match Full flags vertically cascaded LANCAM arrays. such arrays, match occurs during comparison, read access memory registers except Next Free register denied prevent device contention. daisy chain, devices will respond Command Data Write cycles, depending conditions shown Tables page unless operation involves Highest-Priority Match address Next Free address; which case, only specific device having Highest-Priority match Next Free address will respond.
Rev.
MU9C5480A/L
FUNCTIONAL DESCRIPTION Continued
Page Address register each device simplifies vertical expansion systems using more than LANCAM. This register loaded with specific device address during system initialization, which then serves higher order address bits. Device Select register allows user target specific device within vertically cascaded system setting equal Page Address Register value, address devices string same time setting Device Select value FFFFH. Figure shows expansion using daisy chain. Note that system flags generated without need external logic. Page Address register allows each device vertically cascaded chain supply address event match, eliminating need external priority encoder calculate complete Match address expense ripple-through time resolve HighestPriority match. Full flag daisy-chaining allows Associative writes using Move Next Free Address instruction, which does need supplied address. Figure shows external implementation simple priority encoder that eliminates daisy chain ripplethrough delays systems requiring maximum performance from many CAMs.
OPERATIONAL CHARACTERISTICS
Throughout following, "aaaH" represents three-digit hexadecimal number "aaa," while "bbB" represents twodigit binary number "bb." memory locations written read from 16-bit segments. Segment corresponds lowest order bits (bits 15-0) Segment corresponds highest order bits (bits 63-48). Comparand register, Mask Register Mask Register Memory array. default destination Command Write cycles Instruction decoder, while default source Command Read cycles Status register. Temporary Command Override (TCO) instructions provide access Control register, Page Address register, Segment Control register, Address register, Next Free Address register, Device Select register. instructions active only Command Read Write cycle after being loaded into Instruction decoder. data control interfaces LANCAM synchronous. During Write cycle, Control Data inputs registered falling edge When writing persistently selected data destination, Destination Segment counter clocked rising edge During Read cycle, Control inputs registered falling edge Data outputs enabled while LOW. When reading from persistently selected data source, Source Segment counter clocked rising edge
CONTROL
Refer Block Diagram page following discussion. inputs Chip Enable (/E), Write Enable (/W), Command Enable (/CM), Enable Daisy Chain (/EC) primary control mechanism LANCAM. input Control enables Match flag output when controls daisy chain operation. Instructions secondary control mechanism. Logical combinations Control inputs, coupled with execution Select Persistent Source (SPS), Select Persistent Destination (SPD), Temporary Command Override (TCO) instructions allow operations from DQ15-0 lines internal resources, shown Table page Comparand register default source destination Data Read Write cycles. This default state overridden independently executing Select Persistent Source Select Persistent Destination instruction, selecting different source destination data. Subsequent Data Read Data Write cycles will access that source destination until another instruction executed. currently selected persistent source destination read back through instruction. sources destinations available persistent access those resources 64-bit bus:
Rev.
REGISTER
Control, Segment Control, Address, Mask Register Persistent Source Destination registers duplicated, with termed Foreground other Background set. active chosen issuing Select Foreground Registers Select Background Registers instructions. default, Foreground
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
active after reset. Having alternate sets registers that determine device configuration allows rapid return foreground network filtering task from background housekeeping task. Writing value Control register writing data last segment Comparand either mask register will cause automatic comparison occur between contents Comparand register words segments memory marked valid, masked selected Control register. Instruction Decoder Instruction decoder write-only decode logic instructions default destination Command Write cycles. instruction's Address Field flag (bit two-cycle instruction that executed immediately. next cycle only, data from Command Write cycle loaded into Address register instruction then completes that address. Address register then will increment, decrement, stay same value depending setting Control Register bits CT2. Address Field flag set, memory access occurs address currently contained Address register. Control Register (CT) Control register contains number switches that configure LANCAM, shown Table page written read using instruction. value written during device reset (and other bits ignored). Table page Reset states. always reads back write Control register causes automatic compare occur (except case reset). Either Foreground Background Control register will active, depending which register been selected, only active Control register will written read from. Match Flag disabled through internal match condition, /MA(int), used determine daisy-chained device's response forced HIGH shown Tables page that Case possible, effectively removing device from daisy chain. With Match Flag disabled, /MF=/MI operations directed Highest-Priority Match locations ignored. Normal operation device with enabled. Match Flag Enable field effect output pins Status Register bits. These bits always reflect true state device.
15-0 15-0
LANCAM
15-0
LANCAM
LANCAM
15-0
LANCAM
ATCH
Figure Vertical Cascading
Figure External Prioritizing Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Full Flag disabled through device behaves full ignores instructions Next Free address. Also, writes Page Address register disabled. other instructions operate normally. Additionally, with disabled, /FF=/FI. Normal operation device with enabled. Full Flag Enable field effect Status Register bit. This always reflects true state device. IEEE Translation control used enable translation hardware writes 64-bit resources device. When translation enabled, bits reordered shown Figure Control Register bits control CAM/RAM partitioning. portion each word sized from full bits down bits 16-bit increments. portion either 64-bit word. Compare masks selected Mask Register Mask Register neither selected mask compare operations. address register behavior controlled increment, decrement, neither after memory access. operating mode: Standard shown Table page Enhanced shown Table page device will reset Standard mode, follow operating responses original 1480 Table When operating Enhanced mode, necessary unlock daisy chain with instruction before command data writes after non-matching compare, required Standard mode. Segment Control Register (SC) Segment Control register, shown Table page accessed using instruction. read cycles, D15, D10, will always read back Either Foreground Background Segment Control register will active, depending which register been selected, only active Segment Control register will written read from. Segment Control register contains dual independent incrementing counters with limits, data reads data writes. These counters control which 16-bit segment 64-bit internal resource accessed during particular data cycle 16-bit data bus. actual destination data writes source data reads (called persistent destination source) independently with instructions, respectively. Each counters consists start limit, limit, current count value that points segment accessed next data cycle. current count value segment, even outside range start limits. counters count from current count value limit then jump back start limit. current count greater than limit, current count value will increment three, then roll over zero continue incrementing until limit reached; then jumps back start limit. sequence data writes reads interrupted, Segment Control register reset initial start limit values using instruction. After LANCAM reset, both Source Destination counters count from Segment Segment with initial value Page Address Register (PA) Page Address register loaded using instruction followed Command Write cycle user selected 16-bit value (not FFFFH). entry register used give unique address different devices daisy chain. daisy chain, value each device loaded using instruction advance next device, shown "Setting Page Address Register Values" section page software reset (using Control register) does affect Page Address register. Device Select Register (DS) Device Select register used select specific (target) device. instruction sets 16-bit register value following Command Write cycle. register read. device selected when equal value. daisy chain, setting FFFFH will select devices. However, this case, ability read information device restricted shown Tables page software reset (using Control register) does affect Device Select register.
Figure IEEE 802.3/802.5 Format Mapping Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Cycle Type Write Status Operation Notes Load Instruction decoder Load Address register Load Control register Load Page Address register Load Segment Control register Load Device Select register Deselected Read Next Free Address register Read Address register Read Status Register bits 15-0 Read Status Register bits 31-16 Read Control register Read Page Address register Read Segment Control register Read Device Select register Read Current Persistent Source Destination 3,11 HIGH-Z Deselected Load Comparand register Load Mask Register Load Mask Register Write Memory Array address Write Memory Array Next Free address Write Memory Array Highest-Priority match Deselected Read Comparand register Read Mask Register Read Mask Register Read Memory Array address Read Memory Array Highest-Priority match HIGH-Z Deselected HIGH-Z Deselected
Read
Data Write
Data Read
Notes: Default Command Write cycle destination (does require instruction). Default Command Write cycle destination instruction required) Address Field flag instruction loaded previous cycle. Loaded read Command Write Read cycle immediately following instruction. Active Command Write Read cycle only. register cannot loaded this way. Default Command Read cycle source (does require instruction). Default Command Read cycle source (does require instruction) previous cycle Command Read Status Register Bits 15-0. next cycle Command Read cycle, subsequent Command Read cycle will access Status Register Bits 15-0. Default persistent source destination power-up after Reset. other resources were sources destinations, restores Comparand register destination source. Selected executing Select Persistent Destination instruction. Selected executing Select Persistent Source instruction. Access require multiple 16-bit Read Write cycles. Segment Control register used control selection desired 16-bit segment(s) establishing Segment counters' start limits count values. Device deselected Device Select register setting does equal Page Address register setting, unless Device Select Register FFFFH, which allows only write access device. (Writes Device Select register always active.) Device also deselected under locked daisy chain conditions shown Tables page Command Read cycle after reads back Instruction decoder bits that were last select persistent source destination. instruction will also read back Device
Table Input/Output Operations Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Status Validity bits memory locations Match Full Flag outputs IEEE 802.3-802.5 Input Translation CAM/RAM Partitioning Comparison Masking Address register auto-increment auto-decrement Source Destination Segment counters count ranges Address register Next Free Address register Page Address Device Select registers Control register after reset (including CT15) Persistent Destination Command writes Persistent Source Command reads Persistent Source Destination Data reads writes Operating Mode Configuration Register /RESET Condition Skip Empty (empty) Enabled translated bits CAM, bits Disabled Disabled 11B; loaded with Contain Contain change software reset) Contains 0008H Instruction decoder Status register Comparand register Standard Foreground
Table Device Control State After Reset
Address Register (AR) Address register points memory location operated upon when M@[AR] M@aaaH part instruction. loaded directly using instruction indirectly using instruction requiring absolute address, such aaaH,CR,V.0 After being loaded, Address register value will then used next memory access referencing Address register. reset sets Address register zero. Control Register bits Address register automatically increment decrement change) during sequences Command Data cycles. Address register will change after executing instruction that includes M@[AR] M@aaaH, after data access limit segment Segment Control register) when persistent source destination M@[AR] M@aaaH. Either Foreground Background Address register will active, depending which register been selected, only active Address register will written read from. Next Free Address Register (NF) LANCAM automatically stores address first empty memory location Next Free Address register, which then used memory address pointer M@NF operations. Next Free Address register, shown Table page read using instruction. taking during instruction cycle, only device with HIGH will output contents Next Free Address register, which gives Next Free address system daisy-chained devices. Next Free address read from specific device
Rev.
chain setting Device Select register value desired device's Page address leaving HIGH. Full Flag daisy chain causes only device whose input output HIGH respond instruction using Next Free address. After reset, Next Free Address register zero. Status Register 32-bit Status register, shown Table page default source Command Read cycles. internal Full flag, which will particular device empty memory locations. internal Multiple Match flag, which will Multiple match detected. Skip Empty Validity bits, which reflect validity last memory location read. After reset, Skip Empty bits will read until read move from memory occurred. rest Status register down contains Page address device address HighestPriority match. After reset no-match condition, match address bits will internal Match flag, which will match found this particular device. Comparand Register (CR) 64-bit Comparand register default destination data writes reads, using Segment Control register select which 16-bit segment Comparand register loaded read out. persistent source destination data writes reads changed mask registers memory instructions. During automatic forced compare, Comparand
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
register simultaneously compared against portion memory locations with correct validity condition. Automatic compares always compare against valid memory locations, while forced compares, using instructions, compare against memory locations tagged with specific validity condition. Comparand register shifted time right left issuing Shift Right Shift Left instruction, with right left limits wrap-around determined CAM/RAM partitioning Control register. During shift rights, bits shifted partition will reappear partition. Likewise, bits shifted partition will reappear during shift lefts. Mask Registers (MR1, MR2) mask registers used different ways: either mask compares mask data writes moves. Either mask register selected Control register mask every compare, selected instructions participate data writes moves from Memory. selected mask register corresponding Comparand register will enter into masked compare operation. Mask corresponding Comparand register will enter into masked compare operation. Bits mask register cause corresponding bits destination register memory location updated when masking data writes moves, while will prevent that destination from being changed. Either Foreground Background active, after reset, Foreground active default. incorporates sliding mask, where data replicated time right left with wraparound issuing Shift Right Shift Left instruction. right left limits determined CAM/RAM partitioning Control register. Shift Right upper limit replicated next lower bit, while Shift Left lower limit replicated next higher bit. assigned least-significant most-significant portion each entry. CAM/RAM partitioning allowed 16-bit boundaries, permitting selection configuration shown Table page bits (e.g., "001" sets MSBs LSBs RAM). Memory Array bits designated used store retrieve data associated with content same memory location. Memory Access There general ways data into Memory array: directly moving data means Comparand mask registers. first way, through direct reads writes, issuing Persistent Destination (SPD) Persistent Source (SPS) command. addresses direct access supplied directly; supplied from Address register, supplied from Next Free Address register, supplied Highest-Priority Match address. Additionally, direct writes masked either mask register. second move data means Comparand mask registers. This accomplished issuing Data Move commands (MOV). Moves using Comparand register also masked either mask registers.
CYCLES
LANCAM supports four basic cycles: Data Read, Data Write, Command Read, Command Write. states control inputs determine type cycle. These signals registered beginning cycle falling edge Table page shows signals select cycle type. During Read cycles, DQ15-0 outputs enabled after goes LOW. During Write cycles, data command written captured from DQ15-0 beginning cycle falling edge Figures page show Read Write cycles respectively. Figure page shows typical cycle-to-cycle timing with Match flag valid Comparand Write. Data writes reads comparand, mask registers, memory occur four 16-bit cycles, depending settings Segment Control register. Compare operation automatically occurs during Data writes Comparand mask registers when destination segment counter reaches count Segment Control register. there match, second cycle reads status associated data, depending state /CM. cascaded devices, needs start
Rev.
MEMORY ARRAY
Memory Organization Memory array organized into 64-bit words with each word having additional validity bits (Skip Empty). default, words configured cells. However, bits Control register divide each word into field field. field
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Case Internal /EC(int) Internal (int) External Device Select Register DS=FFFFH DS=PA DSFFFFH DSPA
Command Data Write Write1 YES3
Command Read
Data Read
YES4
Table Standard Mode Device Select Response Case Internal /EC(int) Internal (int) External Device Select Register FFFFH FFFFH Command Data Write Write1 YES3 YES3 YES3,6
Command Read
Data Read
YES4 YES4 YES4,7
NOTES: Exceptions are: write Device Select register always active devices; write Page Address register active device with HIGH; Full Flag (SFF) instruction active device with HIGH. disabled Control register, (Int) forced HIGH preventing Case response. This instruction involving Memory Next Free address HIGH device full. This Persistent Destination Memory Next Free address HIGH device full. Command read following instruction, this device contains first empty location daisy chain (i.e., HIGH) does not. This instruction involving Memory Highest-Priority match. This Persistent Destination Memory Highest-Priority match.
Table Enhanced Mode Device Select Response
cycle prior cycle that requires locked daisy chain, such Status register associated data read after match. there match Standard mode, output buffers stay HIGH-Z, daisy chain must unlocked taking HIGH during other non-functioning cycle, indicated Table Figure page shows internal timing holds daisy chain locking effect over into next cycle. Enhanced mode, this needed before data command writes following non-matching compare, indicated Table single-chip system does require daisy-chained match flag operation, hence could tied HIGH flag Status register used instead /MF, allowing access device regardless match condition.
Rev.
minimum timings control signal given Switching Characteristics section page Note that minimum timings signal non-symmetrical that different cycle types have different timing requirements, given Table page
COMPARE OPERATIONS
During Compare operation, data Comparand register compared locations Memory array simultaneously. mask register used during compares must selected beforehand Control register. There ways compares initiated: Automatic compare Forced compare.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Figure Read Cycle
Figure Write Cycle
Figure Cycle Cycle Timing Example
Automatic compares perform compare contents Comparand register against Memory locations that tagged "Valid," occur whenever following happens:
Destination Segment counter Segment
Control register reaches limit during writes Comparand mask registers. After command write executed (except software reset), that compare executed with settings Control register.
forced compare against "Empty" locations automatically masks bits data find locations with validity bits "Empty," while other forced compares only masked selected Control register.
VERTICAL CASCADING
LANCAMs vertically cascaded increase system depth. Through flag daisy-chaining, multiple devices will respond integrated system. flag daisy chain allows commands issued globally, with response only device containing HighestPriority Matching Next Free location. When connected
Rev.
Forced compares initiated instructions using four validity conditions:
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
daisy chain, last device's Full flag Match flag accurately report condition whole string. system which LANCAMs vertically cascaded using daisy-chaining flags shown Figure page operate daisy chain, Device Select registers FFFFH enable devices execute Command Write Data Write cycles. normal operation, read cycles enabled from device with Highest-Priority match locking daisy chain (see "Locked Daisy Chain" section). individual device chain targeted read write operation temporarily setting Device Select registers Page address target device. Setting Device Select registers back FFFFH restores operation entire daisy chain. Match Flag Cascading Match Flag daisy chain cascading used three purposes: first, allow operations Highest-Priority Match addresses issued globally over whole string; second, provide system wide match flag; third, lock devices except with HighestPriority match instructions such Status reads after match. Match flag logic causes only highest-priority device operate Highest-Priority Match location while devices with lower-priority matches ignore HighestPriority Match operations. lock-out feature enabled match flag cascading control signal, shown Tables page ripple delay flags when connected daisy chain requires extension HIGH time until logic devices settled out. string devices, HIGH time should greater than tEHMFV tMIVMFV last device's Match flag required external logic state machine before start next cycle, additional tMIVMFV should added HIGH time along with setup time delays external logic. Locked Daisy Chain locked daisy chain, highest-priority device with HIGH LOW. Standard mode, only this device will respond command data reads writes, until daisy chain been unlocked taking HIGH. This allows reading associated data field from only Highest-Priority Match location anywhere string devices, Match address from Status register device with match. also permits updating entry stored Highest-Priority Match location. Enhanced mode, devices enabled respond some command data writes, noted Table command data reads. Table (Standard mode) Table (Enhanced mode) show when device will respond reads writes when will not, based state /EC(int), internal match condition, other control inputs. latched falling edge /EC(int) registered from latched signal rising edge controls what happens next cycle, shown Figure When first taken string LANCAM devices (and assuming Device Select registers FFFFH), devices will respond that command write data write. From then daisy chain will remain locked each subsequent cycle long held falling edge current cycle. When daisy chain locked Standard mode, only Highest-Priority Match device will respond (See Case Table 5a). example, memory locations were empty, there would match, would stay HIGH. Since none devices could then Highest-Priority Match device, none will respond reads writes until daisy chain unlocked taking HIGH asserting cycle. there match between data Comparand register more locations memory, then only Highest-Priority Match device will respond cycle, such associated data Status Register read. there match, then with HIGH needs inserted before issuing instructions, such Write Next Free Address instruction learn data. Since Next Free operations controlled /FI-/FF daisy chain, only device with first empty location will respond. instruction used unlock daisy
Figure /EC(Int) Timing Diagram Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
chain will work only Highest-Priority Match device, exists. none exists, instruction will have effect except unlock daisy chain. read Status registers specific devices when there match requires command DS=PA each device. Single chip systems HIGH read Status register pins monitor match conditions, daisy chain lock-out feature needed this configuration. This removes need insert case no-match. When Control register Enhanced mode, continue write data Comparand register issue Move Next Free Address instruction without first having issue with HIGH unlock daisy chain after Compare cycle with match, indicated cases Table page Enhanced mode, data write cycles well command write cycles enabled devices even when LOW. Exceptions data writes, moves, instructions involving which occur only device with highest match; data writes move instructions involving which occur only device with HIGH. Enhanced mode speeds system performance eliminating need unlock daisy chain before Command Data Write cycles. Full Flag Cascading Full Flag daisy chain cascading used three purposes: first, allow instructions that address Next Free locations operate globally; second, provide system wide Full flag; third, allow loading Page Address registers during initialization using instruction. full flag logic causes only device containing first empty location respond Next Free instructions such "MOV NF,CR,V", which will move contents Comparand register first empty location string devices that location Valid, will available next automatic compare. With devices connected Figure page output last device string provides full indication entire string. IEEE 802.3/802.5 Format Mapping support symmetrical mapping between address formats IEEE 802.3 IEEE 802.5, LANCAM provides translation facility. Formally expressed, input bit, D(n), maps output bit, Q(x), through following expressions: D(n) Q(7-n) D(n) Q(23-n) Setting Control Register selects whether persistently translate, persistently translate, data written onto 64-bit internal bus. default condition after Reset command translate incoming data. Figure page shows mapping between formats.
INITIALIZING LANCAM
Initialization LANCAM required configure various registers device. Since Control register reset establishes operating conditions shown Table page restoration operating conditions better suited application required after reset, whether using Control Register reset, /RESET pin. When device powers memory registers unknown state, /RESET must asserted place device known state. Setting Page Address Register Values vertically cascaded system, user must individual Page Address registers unique values using Page Address initialization mechanism. Each Page Address register must contain unique value prevent contention. This process allows individual device selection. Page Address register initialization works follows: Writes Page Address registers only active devices with HIGH. initialization, devices empty, thus device string will respond instruction, load register. advance next device string, Full Flag (SFF) instruction used, which also active only device with HIGH. instruction changes first device's LOW, although device really empty, which allows next device string respond instruction load register. initialization proceeds through chain similar manner filling registers turn. Each device must have unique Page Address value stored register, contention will result. After registers filled, entire string reset through Control register, which does change values stored individual registers. After reset, Device Select registers usually FFFFH enable operation Case Table page Control registers Segment Control registers then their normal operating values application.
Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
Vertically Cascaded System Initialization Table shows example code that initializes daisychained string LANCAM devices. initialization example shows Page Address registers each devices chain through Full Flag instruction, Control registers Segment counters LANCAM devices typical application. Each Page Address register must contain unique value (not FFFFH) prevent contention. typical daisy chain operation, data loaded into Comparand registers devices string simultaneously setting DS=FFFFH. Since reading prohibited when DS=FFFFH (except device with match), diagnostic operation need select specific device setting DS=PA desired device able read from Refer Tables page preconditions reading writing. Initialization single LANCAM similar. Device Select register this case usually equal Page Address register normal operations. Also, dedicated flag output used instead /MF, allowing tied HIGH.
Cycle Type Command read Command write Command write Commandwrite Command write Command write Command write Command write Command write Commandwrite Command write Command write Command write Command write Command write Notes:
Op-Code FFFFH 0000H nnnnH 0000H 8040H 3808H M@HM
Control
Comments Clear power-up anomalies. Target Device Select register disable local device selection. Disable Device Select feature. Target Control register reset. Causes Reset. Target Page Address register page cascaded operation. Page Address value. Full flag; allows access next device (repeat previous cycles plus this each device chain. Target Control register reset Full flags, Page address. Causes Reset. Target Control register initial values. Control register value. Target Segment Count Control register both Segment counters write Segment read from Segment Data reads from Segment Highest-Priority match.
Notes
Toggling /RESET generates same effect this reset Control register, good programming practice dictates software reset initialization account possible prior conditions. This instruction omitted single LANCAM application. last will cause last chip daisy chain LOW. daisy chain, needs equal read particular chip prior match condition. typical LANCAM control environment: Enable match flag; Enable full flag; bits, bits; Disable comparison masking; Enable address increment. Table page Control Register assignments.
Table Example Initialization Routine
Rev.
MU9C5480A/L
INSTRUCTION DESCRIPTIONS*
Instruction: Select Persistent Source (SPS) Binary Op-Code: 0000 f000 0000 0sss Address Field flag Selected source This instruction selects persistent source data reads, until another instruction changes reset occurs. default source after reset Data Read cycles Comparand register. Setting persistent source M@aaaH loads Address register with "aaaH" first access that persistent source will aaaH, after which value increments decrements Control register. M@[AR] instruction does same except current Address Register value used. Instruction: Select Persistent Destination (SPD) Binary Op-Code: 0000 f001 mmdd dvvv Address Field flag Mask Register select Selected destination Validity setting Memory Location destinations This instruction selects persistent destination data writes, which remains until another instruction changes reset occurs. default destination Data Write cycles Comparand register after reset. When destination Comparand register Memory array, data written masked either Mask Register Mask Register that only destination bits corresponding bits mask register will modified. automatic compare will occur after writing last segment Comparand mask registers, after writing Memory. Setting persistent destination M@aaaH loads Address register with "aaaH," first access that persistent destination will aaaH, after which value increments decrements Control register. M@[AR] instruction does same except current Address Register value used. Instruction: Temporary Command Override (TCO) Binary Op-Code: 0000 0010 00dd d000 Register selected source destination only next Command Read Write cycle instruction selects register source destination only next Command Read Write cycle, value loaded read register. Subsequent Command Read Write cycles revert reading Status register writing Instruction decoder. registers written read from. Status register only available through non-TCO Command Read cycles. Reading register also outputs Device bits 15-4 shown Table page Instruction: Data Move (MOV) Binary Op-Code: 0000 f011 mmdd dsss 0000 f011 mmdd dvss Address Field flag Mask Register select Destination data Source data Validity setting destination Memory location instruction performs 64-bit move data selected source selected destination. source destination aaaH, Address register "aaaH." instructions from aaaH [AR], Address register will increment decrement from that value after move completes, Control register. Data transfers between Memory array Comparand register masked either Mask Register Mask Register which case, only those bits destination that correspond bits selected mask register will changed. Memory location used destination instruction Valid left unchanged. source destination same register, change occurs NOP). Instruction: Validity Control (VBC) Binary Op-Code: 0000 f100 00dd dvvv Address Field flag Destination data Validity setting Memory location instruction sets Validity bits selected memory locations selected state. This feature used find valid entries using repetitive sequence through mask followed target aaaH, Address register "aaaH." instructions from aaaH [AR], Address register will increment decrement from that value after operation completes, Control register. Instruction: Compare (CMP) Binary Op-Code: 0000 0101 0000 0vvv Validity condition instruction forces Comparison Valid, Skipped, Random entries against Comparand register through mask register, selected. During instruction, compare only done Validity bits data bits automatically masked.
Rev.
MU9C5480A/L
INSTRUCTION DESCRIPTIONS* Continued
Instruction: Special Instructions Binary Op-Code: 0000 0110 00dd drrr Target resource Operation These instructions special LANCAM accommodate added features over MU9C1480. alternate sets configuration registers selected using Select Foreground Select Background Registers instructions. These registers Control, Segment Control, Address, Mask Register registers. instruction resets Segment Control register count values both Destination Source counters original Start limits. Shift instructions shift designated register right left. right left limits shifting determined CAM/RAM partitioning Control register. Comparand register barrel-shifter, example device bits executing Shift Comparand Right instruction, moved moved moved Shift Comparand Left instruction, moved moved moved acts sliding mask, where Shift Right instruction moved while "falls end," replicated Shift Mask Left instruction, replicated moved "falls end." With shorter width fields, limits right left move match width field. Instruction: Full Flag (SFF) Binary Op-Code: 0000 0111 0000 0000 instruction special instruction used force Full flag permit setting Page Address register vertically cascaded systems. Instruction: Operation (NOP) Binary Op-Code: 0000 0011 0000 0000 (No-OP) belongs instructions, where register moved itself. change occurs within device. This instruction useful unlocking daisy chain Standard mode. Notes:
Instruction cycle lengths given Table page f=1, instruction requires absolute address supplied following cycle Command write. value supplied second cycle instruction will update address register. After operations involving M@[AR] M@aaaH, Address register will increment decrement depending setting Control register.
Rev.
MU9C5480A/L
INSTRUCTION SUMMARY
MNEMONIC FORMAT dst,src[msk],val
INS: Instruction mnemonic dst: Destination data src: Source data msk: Mask register used val: Validity condition location written
Instruction: Select Persistent Destination Cont. Operation Mnemonic Op-Code
Mem. Highest-Prio. Match, Emp. M@HM,E Masked M@HM[MR1],E Masked M@HM[MR2],E Mem. Highest-Prio. Match, Skip M@HM,S Masked M@HM[MR1],S Masked M@HM[MR2],S Mem. High.-Prio. Match, Random M@HM,R Masked M@HM[MR1],R Masked M@HM[MR2],R Mem. Next Free Addr., Valid M@NF,V Masked M@NF[MR1],V Masked M@NF[MR2],V Mem. Next Free Addr., Empty M@NF,E Masked M@NF[MR1],E Masked M@NF[MR2],E Mem. Next Free Addr., Skip Masked Masked M@NF,S M@NF[MR1],S M@NF[MR2],S 012DH 016DH 01ADH 012EH 016EH 01AEH 012FH 016FH 01AFH 0134H 0174H 01B4H 0135H 0175H 01B5H 0136H 0176H 01B6H 0137H 0177H 01B7H
Instruction: Select Persistent Source Operation Mnemonic Op-Code
Comparand Register Mask Register Mask Register Memory Array Addr. Reg. Memory Array Address Mem. Highest-Prio. Match M@[AR] M@aaaH M@HM 0000H 0001H 0002H 0004H 0804H 0005H
Instruction: Select Persistent Destination Operation Mnemonic Op-Code
Comparand Register Masked Masked Mask Register Mask Register Mem. Addr. Reg. Valid Masked Masked Mem. Addr. Reg. Empty Masked Masked Mem. Addr. Reg. Skip Masked Masked CR[MR1] CR[MR2] M@[AR],V M@[AR][MR1],V M@[AR][MR2],V 0100H 0140H 0180H 0108H 0110H 0124H 0164H 01A4H
Mem. Next Free Addr., Random M@NF,R Masked M@NF[MR1],R Masked M@NF[MR2],R
Instruction: Temporary Command Override Operation Mnemonic Op-Code
Control Register Page Address Register Segment Control Register Read Next Free Address Address Register Device Select Register Read Persistent Source Read Persistent Destination 0200H 0208H 0210H 0218H 0220H 0228H 0230H 0238H
M@[AR],E 0125H M@[AR][MR1],E 0165H M@[AR][MR2],E 01A5H M@[AR],S 0126H M@[AR][MR1],S 0166H M@[AR][MR2],S 01A6H
Mem. Addr. Reg. Random M@[AR],R 0127H Masked M@[AR][MR1],R 0167H Masked M@[AR][MR2],R 01A7H Memory Address Valid Masked Masked Memory Addr. Empty Masked Masked Memory Address Skip Masked Masked Mem. Address Random Masked Masked M@aaaH,V 0924H M@aaaH[MR1],V 0964H M@aaaH[MR2],V09A4H M@aaaH,E 0925H M@aaaH[MR1],E 0965H M@aaaH[MR2],E 09A5H M@aaaH,S 0926H M@aaaH[MR1],S 0966H M@aaaH[MR2],S 09A6H M@aaaH,R 0927H M@aaaH[MR1],R 0967H M@aaaH[MR2],R 09A7H 012CH 016CH 01ACH
Instruction: Data Move Operation
Comparand Register from: Operation Mask Register Mask Register Memory Address Reg. Masked Masked Memory Address Masked Masked
Mnemonic
Op-Code
0300H 0301H 0302H 0304H 0344H 0384H
CR,MR1 CR,MR2 CR,[AR] CR,[AR][MR1] CR,[AR][MR2]
CR,aaaH 0B04H CR,aaaH[MR1] 0B44H CR,aaaH[MR2] 0B84H 0305H 0345H 0385H
Mem. Highest-Prio. Match CR,HM Masked CR,HM[MR1] Masked CR,HM[MR2]
Mem. Highest-Prio. Match, Valid M@HM,V Masked M@HM[MR1],V Masked M@HM[MR2],V
Rev.
MU9C5480A/L
INSTRUCTION SUMMARY Continued
Instruction: Data Move Continued Operation Mnemonic
Mask Register from: Comparand Register Operation Mask Register Memory Address Reg. Memory Address Mem. Highest-Prio. Match Mask Register from: Comparand Register Mask Register Operation Memory Address Reg. Memory Address Mem. Highest-Prio. Match MR1,CR MR1,MR2 MR1,[AR] MR1,aaaH MR1,HM
Op-Code
0308H 0309H 030AH 030CH 0B0CH 030DH
Instruction: Data Move Continued Operation Mnemonic
Op-Code
MR2,CR MR2,MR1 MR2,[AR] MR2,aaaH MR2,HM
0310H 0311H 0312H 0314H 0B14H 0315H
Memory Next Free Address, Change Validity bits, from: Comparand Register NF,CR 0330H Masked NF,CR[MR1] 0370H Masked NF,CR[MR2] 03B0H Mask Register NF,MR1 0331H Mask Register NF,MR2 0332H Memory Next Free Address, Location Valid, from: Comparand Register NF,CR,V 0334H Masked NF,CR[MR1],V 0374H Masked NF,CR[MR2],V 03B4H Mask Register NF,MR1,V 0335H Mask Register NF,MR2,V 0336H
Instruction: Validity Control Operation Mnemonic
Validity bits Address Register Valid [AR],V Empty [AR],E Skip [AR],S Random Access [AR],R Validity bits Address Valid Empty Skip Random Access Validity bits Valid Empty Skip Random Validity bits Valid Empty Skip Random
Op-Code
0424H 0425H 0426H 0427H
Memory Address Register, Change Validity bits, from: Comparand Register [AR],CR 0320H Masked [AR],CR[MR1] 0360H Masked [AR],CR[MR2] 03A0H Mask Register [AR],MR1 0321H Mask Register [AR],MR2 0322H Memory Address Register, Location Valid, from: Comparand Register [AR],CR,V 0324H Masked [AR],CR[MR1],V 0364H Masked [AR],CR[MR2],V 03A4H Mask Register [AR],MR1,V 0325H Mask Register [AR],MR2,V 0326H Memory Address, Change Validity bits, from: Comparand Register aaaH,CR Masked aaaH,CR[MR1] Masked aaaH,CR[MR2] Mask Register aaaH,MR1 Mask Register aaaH,MR2 Memory Address, Location Valid, from: Comparand Register aaaH,CR,V Masked aaaH,CR[MR1],V Masked aaaH,CR[MR2],V Mask Register aaaH,MR1,V Mask Register aaaH,MR2,V Memory Highest-Priority Match, Change bits, from: Comparand Register HM,CR Masked HM,CR[MR1] Masked HM,CR[MR2] Mask Register HM,MR1 Mask Register HM,MR2 Memory Highest-Priority Match, Location Valid, Comparand Register HM,CR,V Masked HM,CR[MR1],V Masked HM,CR[MR2],V Mask Register HM,MR1,V Mask Register HM,MR2,V
aaaH,V aaaH,E aaaH,S aaaH,R
0C24H 0C25H 0C26H 0C27H
0B20H 0B60H 0BA0H 0B21H 0B22H
Highest-Priority Match HM,V HM,E HM,S Access HM,R Matching Locations ALM,V ALM,E ALM,S Access ALM,R
042CH 042DH 042EH 042FH 043CH 043DH 043EH 043FH
0B24H 0B64H 0BA4H 0B25H 0B26H Validity 0328H 0368H 03A8H 0329H 032AH from: 032CH 036CH 03ACH 032DH 032EH
Instruction: Compare Operation
Compare Valid Locations Compare Empty Locations Compare Skipped Locations Comp. Random Access Locations
Mnemonic
Op-Code
0504H 0505H 0506H 0507H
Instruction: Special Instructions Operation Mnemonic
Shift Comparand Right Shift Comparand Left Shift Mask Register Right Shift Mask Register Left Select Foreground Registers Select Background Registers Reset Seg. Cont. Reg. Initial Val.
Op-Code
0600H 0601H 0610H 0611H 0618H 0619H 061AH
Instruction: Miscellaneous Instructions Operation Mnemonic Op-Code
Operation Full Flag 0300H 0700H
Rev.
MU9C5480A/L
INSTRUCTION SUMMARY Continued
CYCLE LENGTH Short CYCLE TYPE Command Write Command Read Data Write Comparand register (not last segment) Mask register (not last segment) Data Read
Medium
Long
reg, (except L-70) (except (non-reset, invalid) SPS, SPD, SBR, (except L-70) reg, Status register reg, (L-70) 16-bit register (reset) (NFA invalid) (L-70) mem, (non-reset, valid) (NFA valid)
Memory array (NFA invalid)
Comparand register Mask register
Memory array (NFA valid) Comparand register (last segment) Mask register (last segment)
Memory array
Note: specific timing requirements Short, Medium, Long cycles given Switching Characteristics section under tELEH parameter. cycle Command Writes (TCO instruction with "aaaH" source destination), first cycle short, second cycle will length given. Table Instruction Cycle Lengths
REGISTER ASSIGNMENTS
Mode
Match Flag
Enable Disable Change
Full Flag Translation
Enable Disable Change Input Translated Input Translated Change
CAM/RAM Part.
CAM/0 CAM/16 CAM/32 CAM/48 RAM/16 RAM/32 RAM/48 Change
Comp. Mask Inc/Dec
None Change
Increment Standard Mode Decrement Enhanced Mode Disable Reserved Change Change
Note: reads back Table Control Register Assignments
Rev.
MU9C5480A/L
REGISTER ASSIGNMENTS Continued
Dest. Seg. Limits Chng.
Source Seg. Limits Chng.
SCEL
Load Dest. Seg. Count Chng.
Load Src. Seg. Count Chng.
SSCV
DCSL
Destination Count Start Limit 00-11
DCEL
Destination Count Limit 00-11
SCSL
Source Count Start Limit 00-11
DSCV
Destination Seg. Count Value 00-11
Source Count Limit 00-11
Source Seg. Count Value 00-11
Note:
D15, D10, read back
Table Segment Control Register Assignments
Page Address, PA5-PA0
Next Free Address, NF8-0
Note: Next Free Address register read only, accessed performing Command Read cycle immediately following instruction. Table Next Free Address Register Assignments
Skip Empty
Page Address Bits, PA15-PA5 Match Address, AM8-AM0
Page Address, PA4-PA0
Note: Status register read only, accessed performing Command Read cycles. first cycle, bits 15-0 will output, second Command Read cycle issued immediately after first Command Read cycle, bits 31-16 will output. Table Status Register Assignments
Device 541H Note: Persistent Source register read only, accessed performing Command Read cycle immediately following instruction. Table Persistent Source Register Assignments
Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Voltage other pins Temperature under bias Storage Temperature Output Current 5480A 5480L -0.5 Volts -0.5 Volts -0.5 +0.5 Volts Volts measured point) -55°C 125°C -55°C 125°C (per output, time, second duration.
Stresses exceeding those listed under Absolute Maximum Ratings include failure. Exposure absolute maximum ratings extended periods reduce reliability. Functionality above these conditions implied. voltages referenced GND.
OPERATING CONDITIONS (voltages referenced device pin) Symbol Parameter Operating Supply Voltage Input Voltage Logic Input Voltage Logic Ambient Operating Temperature Commercial Industrial 5480A 5480L Typical 4.75 -0.5 5.25 Units Volts Volts Volts Volts Still Notes
ELECTRICAL CHARACTERISTICS Symbol Parameter Average Power Supply Current 5480A 5480L ICC(SB) Stand-by Power Supply Current Output Voltage Logic Output Voltage Logic Input Leakage Current Others /RESET
TEST1, TEST2
Typical
Units Volts
Notes tELEL tELEL (min) HIGH -2.0mA 4.0mA VCC;10 VOUT VCC; High Impedance
5480A 5480L
Volts Kohms
Output Leakage Current
CAPACITANCE Symbol Parameter COUT Input Capacitance Output Capacitance Units Notes MHz, MHz, VOUT Rev.
MU9C5480A/L
OPERATIONAL CHARACTERISTICS Continued
TEST CONDITIONS
Input Signal Transitions Input Signal Rise Time Input Signal Fall Time Input Timing Reference Level Output Timing Reference Level Volts Volts Volts Volts
SWITCHING TEST FIGURES
Under
Figure Test Load
Figure Input Signal Waveform
SWITCHING TEST FIGURES COMPONENT VALUES
Parameter C1(includes jig) 5480A 5480L Units Volts Ohms Ohms
Test Load Test Load
Rev.
MU9C5480A/L
SWITCHING CHARACTERISTICS (see Note
Available Consult factory availability
Cycle Time 5480A 5480L
Notes
Symbol tELEL tELEH
Parameter (all times nanoseconds) Chip Enable Compare Cycle Time Chip Enable Pulse Width Short Cycle: Medium Cycle: Long Cycle:
tEHEL tCVEL tELCX tELQX tELQV tEHQZ tDVEL tELDX tFIVEL tFIVFFV tELFFV tMIVEL tEHMFX tMIVMFV tEHMFV tEHMXV tRLRH
Chip Enable HIGH Pulse Width Control Input Chip Enable Setup Time Control Input from Chip Enable Hold Time Chip Enable Outputs Active Chip Enable Outputs Valid Chip Enable HIGH Outputs HIGH-Z Data Chip Enable Setup Time Data from Chip Enable Hold Time Full Valid Chip Enable Setup Time Full Valid Full Flag Valid Chip Enable Full Flag Valid Match Valid Chip Enable Setup Time Chip Enable HIGH /MF, /MA, Invalid Match Valid Valid, /MA, Chip Enable HIGH Valid Chip Enable HIGH Valid Reset Pulse Width
Notes: -1.0 Volts duration measured amplitude points Input-only lines (see Figure Common lines clamped, that signal transients cannot fall below -0.5 Volts. Over ambient operating temperature range Vcc(min) Vcc(max). Table page Control signals /CM, /EC. With load specified Figure Test Load With load specified Figure Test Load must HIGH during this period ensure accurate default values configuration registers. With output pins unloaded. TEST1 and/or TEST2 implemented versions these products.
Rev.
MU9C5480A/L
TIMING DIAGRAMS
READ CYCLE WRITE CYCLE
COMPARE CYCLE
Rev.
MU9C5480A/L
PACKAGE OUTLINE
Dimensions inches
Dim. 44-Pin PLCC .170 .180 Dim. .017 Dim. .018 .032 Dim. .100 Dim. .650 .656 Dim. .685 .695 Dim. .590 .630 Dim. Dim. Dim.
Rev.
MU9C5480A/L
ORDERING INFORMATION
Part Number MU9C5480A 70DC MU9C5480A 90DC MU9C5480A 12DC MU9C5480L 70DC MU9C5480L 90DC MU9C5480L 12DC MU9C5480A 70DI MU9C5480A 90DI MU9C5480A 12DI MU9C5480L 70DI MU9C5480L 90DI MU9C5480L 12DI Cycle Time 70ns 90ns 120ns 70ns 90ns 120ns 70ns 90ns 120ns 70ns 90ns 120ns Package 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC 44-PIN PLCC Temperature 0-70° 0-70° 0-70° 0-70° 0-70° 0-70° -40-85° -40-85° -40-85° -40-85° -40-85° -40-85° Voltage 0.25 0.25 0.25 0.25 0.25 0.25
factory availability
MUSIC Semiconductors Agent Distributor:
MUSIC Semiconductors reserves right make changes products specifications time order improve performance, manufacturability, reliability. Information furnished MUSIC believed accurate, responsibility assumed MUSIC Semiconductors said information, infringement patents other third party rights which result from said use. license granted implication otherwise under patent patent rights MUSIC company. ©Copyright 1998, MUSIC Semiconductors Asian Headquarters European Headquarters MUSIC Semiconductors MUSIC Semiconductors Special Export Processing Zone Torenstraat Carmelray Industrial Park 6471 Eygelshoven Canlubang, Calamba, Laguna Netherlands Philippines Tel: 5462177 Tel: 1480 Fax: 5463663 Fax: 1023 Sales Tel/Fax: +632
Headquarters MUSIC Semiconductors Mountain Avenue Hackettstown, Jersey 07840 Tel: 908/979-1010 http://www.music-ic.com Fax: 908/979-1035 email: info@music-ic.com Only: 800/933-1550 Tech. Support 888/226-6874 Product Info.
Rev.

APPLICATION BENEFITS 64-bit LANCAM facilitates numerous operation

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