Data Data Parity Control HOST Data Parity Control Data Control TQ9502

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Data Data Parity Control HOST Data Parity Control Data Control TQ9502

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Data Data Parity Control HOST Data Parity Control Data Control TQ9502 Receiver Optical Copper Interface TQ9303 ENDEC Fiber Optic Cable Control TQ9501 Transmitter Optical Copper Interface
TQ9501/9502
531/1063 Mbaud Fibre Channel Transmitter Receiver
TriQuint's Fibre Channel transmitter (TQ9501) receiver (TQ9502) part FC531/FC1063 (Fibre Channel 1063 Megabaud) chip set. addition transmitter receiver, TriQuint offers ENcoder/ DECoder (TQ9303 ENDEC). TQ9501, TQ9502, TQ9303 gigabit fiber optic module provide complete solution Fibre Channel's layers well partial support layer. TQ9501 TQ9502 designed TriQuint's proprietary 0.7-micron GaAs process, enabling transmitter receiver higher speeds lower power than with conventional processes. transmitter receiver data interface been selected bits order conserve input/output power reduce count package size. transmitter performs parallel-to-serial conversion generates internal high-speed clock serial output. receiver performs serial-toparallel conversion, recovers clock data from serial input, detects K28.5 character (Fibre Channel standard "SYNC" transmission character). TQ9303 ENDEC implements 8b/10b encoding decoding, ordered encoding decoding, parity checking generation, 32-bit checking generation, word synchronization defined Fibre Channel Physical Signaling Interface Standard (FC-PH). Fibre Channel provides high-speed physical layer Intelligent Peripheral Interface (IPI) Small Computer System Interface (SCSI) upper-layer command sets, High-Performance Parallel Interface (HIPPI) data link layer, other user-defined command sets. Fibre Channel replaces SCSI, HIPPI physical interfaces with higherspeed interface capable driving longer distances.
Features
Compliant with ANSI X3T11 Fibre Channel Standard Operates 531.125 Mbaud 1.0625 Gigabaud (1.25 Gigabaud max) power dissipation (2.25 typical) jitter external components 10-bit TTL-compatible data Synchronous Data Interface Direct interface TQ9303 ENDEC Single supply 48-pin MQuad package
DATACOM PRODUCTS
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TQ9501/TQ9502
Fibre Channel optimized predictable transfers large blocks data, such those used file transfers between processors (super computer, mainframe, super-mini, etc.), storage systems (disk tape), output-only devices such laser printers raster scan graphics terminals. Fibre Channel protocol implemented hardware, making simple, efficient robust. lower-level physical interface decoupled from higher-level protocol allowing Fibre Channel configured with various topologies, including point-topoint, multi-drop bus, ring, cross point switch. Fibre Channel supports distances baud rates 132.8125 Mbaud 1.0625 Gbaud. Copper media such Coax (Shielded Twisted Pair) used shorter distances while fiber optic cables used longer distances. Applications TQ9501 TQ9502 include serial SCSI, IPI, HIPPI, point-to-point serial communication, Aand other networking applications.
TriQuint offers chip sets Fibre Channel: TQ9501 TQ9502 chip 531.125 Mbaud 1.0625 Gbaud, GA9101 GA9102 chip 265.625 Mbaud rate.
Functional Description TQ9501 Transmitter
TQ9501 serializes 10-bit input into differential PECL output. TQ9501 composed input register, parallel-to-serial converter, clock generator, differential output buffer PECLto-TTL translator, illustrated Figure self-contained (Phase-Locked Loop) clock generator requires external components. generates internal high-speed clock serial output, internal byte clock parallel-to-serial converter BYTECLK, based REFCLK (REFerence CLocK). BYTECLK used TQ9303 ENDEC generate TXCLK. TXD0.9 latched into input register rising edge TXCLK. parallel-to-serial converter serializes data into differential PECL buffer. TXD9 sent first TXD0 sent last.
Figure TQ9501 Transmitter
RATESEL REFCLK (25-31.25 BYTECLK (50-62.5 100-125
LOOPEN
Clock Generator
Clock
Byte Clock
Parallelto-Serial Converter
Register
TXD0.9
SIGN PECL-to-TTL Converter
TXCLK SIGDE
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TQ9501/TQ9502
Figure TQ9502 Receiver
SYNCEN RLX, Data Clock/Data Recovery (500-625 MBaud Clock 1.0-1.25 GBaud) Serial-toParallel Converter
Register
RXD0.9
SYNC LOOPEN RATESEL REFCLK (25-31.25 MHz) Clock Generate RXCLK (50-62.5 100-125 CLKPOL
LOOPEN (LOOP ENable) selects between differential output pairs, TLY, LOOPEN selects differential output TLY, setting Conversely, LOOPEN selects setting This relationship shown Table
PECL-to-TTL translator block differential PECLto-TTL translator. normally used translating PECL signals generated optical receivers signals drive control circuitry.
Table LOOPEN Configuration
LOOPEN
Input
RLX,
Output
TX,TY TLX,
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DATACOM PRODUCTS
TQ9501/TQ9502
Functional Description TQ9502 Receiver
TQ9502 consists clock data recovery circuit, multiplexer, serial-to-parallel converter block, shown Figure multiplexer selects between inputs inputs. Outputs RTX, RTY, RLTX RLTY, shown Figure provided Fly-Bytermination, which allows termination resistors placed away from chip. multiplexer output selected LOOPEN shown Table selected data goes (Clock/Data Recovery) block. clock data recovery block modes: clock recovery frequency acquisition. clock input, automatically switches frequency acquisition mode which causes lock onto REFCLK signal. This prevents from drifting away from serial data rate ensures that will properly lock onto input serial data when reapplied. receiver synchronizes after applying power, REFCLK data. receiver synchronizes after applying valid data power REFCLK already been applied. output this block latched into output register. When SYNCEN high (SYNCronization ENable), serial-to-parallel converter monitors serial data K28.5 character. When sees K28.5, realigns 10-bit register K28.5 character drives SYNC high. clock generate block also detects SYNC going high, delays phase output RXCLK coincide with alignment. Some bits lost during realignment. When SYNCEN low, SYNC driven serial-to-parallel converter ignores K28.5 character. output register takes 10-bit-wide output from Serial-to-Parallel Converter drives RXD0.9 outputs. RXD0.9 strobed rising edge RXCLK. CLKPOL results longer setup time shorter hold time than CLKPOL first serial placed RXD9 tenth placed RXD0. Fibre Channel Interface Figure illustrates typical Fibre Channel physical layer block diagram using TQ9501, TQ9502 TQ9303 chip set. interface between host ENDEC operates 26.5625 with data width 32-bits transmit path separate 32-bits receive path. ENDEC performs 8b/10b encoding decoding; ordered encoding decoding; parity checking generation; 32-bit checking generation; word synchronization. interface between TQ9303 TQ9501/ TQ9502 operates 531.25 106.250 with encoded data width 10-bits. serial interface operates from 531.125 Mbaud 1.0625 Gbaud respectively, which connected optical, coaxial twisted pair interface. additional information ENDEC, please refer TQ9303 data sheet.
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TQ9501/TQ9502
Figure System Block Diagram Fibre Channel
TQ9501
SIGDE
Host TQ9303 ENDEC
RATESEL REFCLK LOOPEN
BTXD0.9 TXD0.9 CTXD0.31 TXCLK CTXC0,1 BTXCKOUT CTXP0.3 BYTECLK BTXCKIN CTXRAWA,B CTXRAW CTXPENN SIG, SIGN CTXPMODE CTXPERR RATESEL CTXCERR CTXCLK REFCLK CTXWREF LOOPEN RESETN CRXD0.31 CRXP0.3 BRXD0.9 CRXS0.5 BRXCLK RAWRX RXPMODE BRXSYNC WRDSYNCN RXCKPH0,1 CRXCLK
TLX,
Optical, Coaxial, Twisted Pair Interface
RXD0.9 RXCLK SYNC
RLX,
Termination Network
SYNCEN CLKPOL
RLTX RLTY
TQ9303
Note that fast edge rates TQ9303 outputs affect stability TQ9501 PLL. These edge rates effectively "slowed" adding some series resistance from ohms data lines (TXD0.9) shown Figure Resistance should also added TXCLK maintain correct timing relationship with data lines. resistors should placed near TQ9303. cases where line capacitance traces less than also necessary from capacitance each trace near TQ9501. purpose slow edge rates enough prevent potential undershoot from disturbing power supplies circuitry TQ9501.
Figure Adding resistance capacitance data bus.
TQ9301
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DATACOM PRODUCTS
TQ9502
Optical, Coaxial, Twisted Pair Interface
TQ9501/TQ9502
Table Transmitter Descriptions
Symbol
TLX, LOOPEN REFCLK
Type
Description
Differential Transmitter Outputs connect optical transmitter, coaxial interface shielded twisted pair interface. LOOPEN selects outputs. LOOPEN high drives high. Loopback Differential Transmitter Outputs connect Receiver inputs. LOOPEN high selects outputs. LOOPEN drives high. Loopback Enable high selects outputs. LOOPEN selects outputs. multiplies Reference Clock generates high speed clock transmitting serial data. REFCLK shall equal 1/40 baud rate. REFCLK shall have frequency tolerance guarantee clock data recovery receiver. REFCLK operating range 31.25 MHz. ENDEC uses Byte Clock synchronize Transmitter. ENDEC generates TXCLK from BYTECLK simplifying synchronization between Transmitter ENDEC, shown Figure Transmitter latches Encoded Data Bits rising edge TXCLK. Transmitter serially sends TXD9 first TXD0 last. Transmitter Data Clock strobes TXD0.9 into Transmitter. ENDEC generates TXCLK from BYTECLK simplifying synchronization between Transmitter ENDEC. Differential Signal Present inputs PECL translator. translator typically used convert differential signals from differential optical receiver output TTL. equivalent SIGN SIGDET. Signal Detect output PECL translator. translator typically used convert differential signals from differential optical receiver output TTL. SIGDET useful when implementing Open Fibre Control protocol where link activity optical receiver outputs monitored continuously. Rate Select used select between Mbaud (RATESEL=VDD) 1063 Mbaud (RATESEL=GND) operation.
BYTECLK TXD0.9 TXCLK SIG, SIGN
SIGDE
RATESEL
Figure Fly-By Termination Schematic
RLTX
TQ9502
RLTY
Figure Transmitter Synchronization Ciruit Block Diagram
TQ9303 ENDEC TQ9501
BTXD0.9 TXD0.9 BTXCKOURTY
TXCLK BTXCKIN BYTECLK
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TQ9501/TQ9502
Table Receiver Descriptions
Symbol
RTX,
Type
Description
Receiver Differential Inputs connects optical, coaxial shielded twisted pair interface. LOOPEN selects inputs. LOOPEN high selects inputs. Receiver Differential Termination used Fly-Bytermination. internally connected internally connected RTY. termination circuit connects instead With Fly-Bytermination, termination circuit located away from Receiver instead requiring termination directly Both must terminated with chip resistor series with reference Thevenin equivalent shown Figure Looped Receiver Differential Inputs connect Transmitters outputs providing loop back path. LOOPEN high selects inputs. LOOPEN selects inputs. Receiver Differential Termination used Fly-Bytermination. internally connected RLTX internally connected RLTY. termination circuit connects RLTX RLTY instead RLY. With Fly-BYtermination, termination circuit located away from Receiver instead requiring termination directly RLY. Both RLTX RLTY must terminated with chip resistor series with reference Thevenin equivalent shown Figure Loopback Enable high selects inputs. LOOPEN selects inputs. Reference Clock provides clock needed clock recovery circuit. REFCLK frequency shall chosen equal 1/40 baud rate. REFCLK shall have frequency tolerance guarantee clock data recovery receiver. receiver automatically locks onto REFCLK during power-up and/or when input signals applied. This prevents from drifting away from input data rate. automatically locks onto input data stream when applied. frequency range REFCLK 31.25 MHz. When Sync Enable high, receiver searches K28.5 character from input data stream byte aligns parallel register this character defined Fibre Channel standard. SYNCEN disables byte alignment K28.5 character drives SYNC low. K28.5 character pattern RXD9.0 001111 1010 110000 0101. Whenever receiver detects K28.5 pattern byte aligns this character drives SYNC high that byte cycle. SYNC high only byte cycle where K28.5 character present. These Encoded Data Bits where first received from serial data stream RXD9 last received RXD0. receiver generates RXCLK strobe RXD0.9. SYNCEN high, Synchronization K28.5 goes high byte clock cycle which K28.5 character present RXD0.9 output. SYNCEN then SYNC always low. Receiver Data Clock strobe RXD0.9 SYNC. phase RXCLK with respect RXD0.9 SYNC changes depending CLKPOL. CLKPOL high provides longer setup time shorter hold time while CLKPOL provides shorter setup time longer hold time. frequency range RXCLK 62.5 FC531 mode FC1063 mode. Clock Phase Polarity controls phase RXCLK with respect RXD0.9 SYNC. CLKPOL high provides longer setup time shorter hold time while CLKPOL provides shorter setup time longer hold time. Rate Select used select between Mbaud (RATESEL=VDD) 1063 Mbaud (RATESEL=GND) operation.
RLX,
RLTX, RLTY
LOOPEN REFCLK
SYNCEN
RXDO.9 SYNC RXCLK
CLKPOL
RATESEL
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DATACOM PRODUCTS
TQ9501/TQ9502
Layout Guidelines
Multiple ground power pins TQ9501/02 reduce ground bounce. Good layout techniques, however, necessary guarantee proper operation meet specifications across full operating range. TriQuint recommends bypassing each supply pins nearest ground pin, close chip possible. Figure shows recommended power layout TQ9501/02. bypass capacitors should located same side board TQ9501/02. traces connect inner-layer plane. ground pins (GND) connected small ground plane surface beneath chip. Multiple through-holes connect this small surface plane inner-layer ground plane. capacitors TriQuint's test board uses temperature-stable capacitors 1206 cases.
Figure Example Layer Layout Power Pins (Not scale)
Ground Plane
Only
Note:
Series resistors small capacitors needed data clock lines. previous "Fibre Channel Interface" section this datasheet details.
Table Absolute Maximum Ratings
Parameter
Storage temperature Case temperature Supply voltage ground input voltage input current Package Thermal Resistance Junction Temperature Note:
Table Operating Conditions
Parameter
Supply voltage Ambient temperature Note:
Range
+150 +125 -0.5 +7.0 -0.5 (VDD +0.5
°C/W; °C/W
Range
5V±5
Proper functionality guaranteed under these operating conditions.
Stresses above those listed Absolute Maximum Rating cause permanent damage device. This stress-only rating operation device these other conditions above those indicated operational section this specification implied.
Table Test Loads
Symbol
Description
Input capacitance Output capacitance
Test Conditions
VOUT
Min.
Typ.
Max.
Unit
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TQ9501/TQ9502
Table Characteristics-TQ9501 Transmitter Signals (TXDO.9, TXCLK, BYTECLK, LOOPEN, SIGDET, REFCLK, RATESEL) (Over operating range unless otherwise specified)
Symbol
ISC4 VIH5 VIL5
Description
Output HIGH voltage Output voltage Output short-circuit current Input current Input HIGH current Input HIGH current Input HIGH level Input level Input clamp voltage Power supply current
Test Conditions
VIN2 VIN2 -1.6 -3.2 VOUT
Min.
Limits Typ.
Max.
Unit
-120
Guaranteed input logical HIGH voltage inputs, Guaranteed input logical voltage inputs Max, static
-1.2
Table Characteristics-TQ9501 Transmitter PECL Signals (TX, TLX, TLY, SIG, SIGN)
Limits Typ.
Symbol
VCMO DVOUT VIHS VILS VDIF VICM
Description
Output HIGH voltage Output voltage Output common mode voltage Output differential voltage Input current Input HIGH current Highest input HIGH voltage Lowest input voltage Differential input voltage Input common mode voltage
Test Conditions
PECL load PECL load
Min.
1.200 2.00 1.60 0.60
Max.
0.50 1.60 -1.10
Unit
=2.4
Notes: Typical limits are: inputs could HIGH LOW. specifications valid only BYTECLK. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
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TQ9501/TQ9502
Table Characteristics-TQ9502 Receiver Signals (RXD0.9, RXCLK, SYNCEN, REFCLK, LOOPEN, SYNC, CLKPOL, RATESEL) (Over operating range unless otherwise specified)
Symbol
ISC5 VIH4 VIL4
Description
Output HIGH voltage Output voltage VIN2 Output short-circuit current Input current Input HIGH current Input HIGH current Input HIGH level voltage inputs Input level voltage inputs Input clamp voltage Power supply current
Test Conditions
VIN2 -1.6 -3.2
Min.
Limits Typ.
Max.
Unit
VOUT 0.40
-120 -400 -1.2
Guaranteed input logical HIGH Guaranteed input logical Max, static
Table Characteristics-TQ9502 Receiver PECL Signals (RX, RTX, RTY, RLX, RLY, RLTX, RLTY)
Limits Typ.
Symbol
VIHS VILS VDIF VICM
Description
Input current Input HIGH current Highest input HIGH voltage Lowest input voltage Differential input voltage Input common mode voltage
Test Conditions
-0.5
Min.
Max.
0.50
Unit
Notes:
Typical limits are: inputs could HIGH LOW. specifications valid only RXCLK. These absolute values with respect device ground. more than output should tested time. Duration short circuit should exceed second.
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TQ9501/TQ9502
Table Specifications-TQ9501 Transmitter Parameters with dual values refer 531Mbaud/1063Mbaud operation respectively.
Parameter
T123
Description
REFCLK pulse width HIGH REFCLK pulse width REFCLK period setup time hold time BYTECLK, TXCLK pulse width HIGH BYTECLK, TXCLK pulse width BYTECLK, TXCLK period TLX, rise time TLX, fall time skew
Min.
10.0 10.0 32.0 6.0/3.0 6.0/3.0 16.0/8.0
Typ.
Max.
Units
40.0
20.0/10.0 400/300 400/300 100/60 100/75 200/150
output jitter deterministic jitter (DJ) random jitter (RJ)
Notes: REFCLK Tolerance (20/baud rate) ±0.01%, baud rate 500Mbaud 625Mbaud (40/baud rate) 0.01%, baud rate Gbaud 1.25 Gbaud. baud time 1/baud rate jitter numbers 10-12.
Figure Timing TQ9501 Transmitter
REFCLK TXD0.9 TXCLK BYTECLK
Figure 9.Serial Output Timing TQ9501
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DATACOM PRODUCTS
TQ9501/TQ9502
Table Specifications-TQ9502 Receiver Parameters with dual values refer 531Mbaud/1063Mbaud operation respectively.
Parameter
T231 T261 T271 T281
Description
REFCLK pulse width REFCLK pulse width HIGH REFCLK period Setup Time SYNC Hold Time SYNC RXCLK period RXCLK pulse width HIGH RXCLK pulse width RLX, rise time RLX, fall time skew RLX, peak-to-peak input jitter 32.0 CLKPOL=0 CLKPOL=1 CLKPOL=0 CLKPOL=1
Min.
10.0 10.0
Typ.
Max.
Units
40.0 4.0/2.0 12.0/6.0 8.0/4.0 16.0/8.0 6.0/4.0 6.0/4.0
20.0/10.0 baud time baud time baud time baud time
Notes:
REFCLK Tolerance (20/baud rate) ±0.01%, baud rate 500Mbaud 625Mbaud (40/baud rate) 0.01%, baud rate Gbaud 1.25 Gbaud. baud time 1/baud Rate jitter numbers 10-12.
Table Synchronization Times
Description
Power application REFCLK receiver synchronization Application valid data receiver synchronization Receiver resynchronization after phase shift data
Min.
Typ.
Max.
2500
Units
time
Figure Timing TQ9502 Receiver
REFCLK RXD0.9 SYNC RXCLK
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TQ9501/TQ9502
Figure Serial Input Timing TQ9502
RTX, RLX, RLTX
RTY, RLY, RLTY
Figure 12a. Test Load,RXCLK
DATACOM PRODUCTS
1000
Figure 12b. Test Load, Other Outputs
2000
1370
Figure 12c. PECL Test Load
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TQ9501/TQ9502
Figure Pinout Transmitter
TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9
TXD2 TXD1 TXD0 SIGN
SIGDET BYTECLK RATESEL TXCLK REFCLK LOOPEN
TQ9501
Table Definitions TQ9501 Transmitter
Symbol
TLX, SIG, SIGN TXCLK LOOPEN SIGDET REFCLK BYTECLK RATESEL
7,18, 3,11,
Output Output Input Input Input Input Output Input Output Input
Pins
Logic Type
PECL PECL PECL
Active
HIGH HIGH HIGH HIGH HIGH HIGH HIGH
Description
Differential serial data output Loopback differential serial data output Differential optical signal present Transmit clock Transmit data input Enable loopback Signal detect Oscillator clock 31.25 MHz) Byte clock Volt Supply Ground Connect 531Mbaud operation Ground 1063Mbaud operation
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TQ9501/TQ9502
Figure Pinout Receiver
RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
RXDO RXCLK RATESEL SYNCEN REFCLK LOOPEN
RXD8 RXD9 SYNC CLKPOL
TQ9502
Table Definitions TQ9502 Receiver
Symbol
RLX, RTX, RLTX, RLTY RXCLK REFCLK SYNC SYNCEN LOOPEN CLKPOL RATESEL
Pins
Logic Type
PECL PECL PECL PECL
Active
HIGH HIGH HIGH HIGH HIGH HIGH
Description
Differential serial data input Differential serial data input, loopback fly-by termination fly-by termination Receive output data Receive clock Oscillator clock 31.25 MHz) Receive byte sync Sync Enable Align K28.5 Enable loopback RXCLK Clock Phase supply Ground connect VDD(1) 531Mbaud operation Ground(0) 1063 Mbaud operation
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DATACOM PRODUCTS
RLTY
RLTX
TQ9501/TQ9502
Figure 44-Pin MQuad J-leaded Package
.690 .005 .045 .645
.172 .0125 .104 .030
.018 .004
0.125 VENT PLUG
.645 .690 .005 .028
.050
.610 .015
.015 .050 .132
Ordering Information
TQ9501-MC TQ9502-MC
Additional Information
FC531/1063 Transmitter FC531/1063 Receiver
latest specifications, additional product information, worldwide sales distribution locations, information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
technical questions additional information specific applications: Email: applications@tqs.com
information provided herein believed reliable; TriQuint assumes liability inaccuracies omissions. TriQuint assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. TriQuint does authorize warrant TriQuint product life-support devices and/or systems. Copyright 1997 TriQuint Semiconductor, Inc. rights reserved. Revision 1.1.A November 1997
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Data Data Parity Control HOST Data Parity Control Data Control TQ9502

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